target/riscv/cpu_helper.c

   1 /*
   2  * RISC-V CPU helpers for qemu.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/main-loop.h"
  23 #include "cpu.h"
  24 #include "exec/exec-all.h"
  25 #include "tcg/tcg-op.h"
  26 #include "trace.h"
  27
  28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
  29 {
  30 #ifdef CONFIG_USER_ONLY
  31     return 0;
  32 #else
  33     return env->priv;
  34 #endif
  35 }
  36
  37 #ifndef CONFIG_USER_ONLY
  38 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
  39 {
  40     target_ulong irqs;
  41
  42     target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
  43     target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
  44     target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
  45
  46     target_ulong pending = env->mip & env->mie &
  47                                ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
  48     target_ulong vspending = (env->mip & env->mie &
  49                               (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
  50
  51     target_ulong mie    = env->priv < PRV_M ||
  52                           (env->priv == PRV_M && mstatus_mie);
  53     target_ulong sie    = env->priv < PRV_S ||
  54                           (env->priv == PRV_S && mstatus_sie);
  55     target_ulong hs_sie = env->priv < PRV_S ||
  56                           (env->priv == PRV_S && hs_mstatus_sie);
  57
  58     if (riscv_cpu_virt_enabled(env)) {
  59         target_ulong pending_hs_irq = pending & -hs_sie;
  60
  61         if (pending_hs_irq) {
  62             riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
  63             return ctz64(pending_hs_irq);
  64         }
  65
  66         pending = vspending;
  67     }
  68
  69     irqs = (pending & ~env->mideleg & -mie) | (pending &  env->mideleg & -sie);
  70
  71     if (irqs) {
  72         return ctz64(irqs); /* since non-zero */
  73     } else {
  74         return EXCP_NONE; /* indicates no pending interrupt */
  75     }
  76 }
  77 #endif
  78
  79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  80 {
  81 #if !defined(CONFIG_USER_ONLY)
  82     if (interrupt_request & CPU_INTERRUPT_HARD) {
  83         RISCVCPU *cpu = RISCV_CPU(cs);
  84         CPURISCVState *env = &cpu->env;
  85         int interruptno = riscv_cpu_local_irq_pending(env);
  86         if (interruptno >= 0) {
  87             cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
  88             riscv_cpu_do_interrupt(cs);
  89             return true;
  90         }
  91     }
  92 #endif
  93     return false;
  94 }
  95
  96 #if !defined(CONFIG_USER_ONLY)
  97
  98 /* Return true is floating point support is currently enabled */
  99 bool riscv_cpu_fp_enabled(CPURISCVState *env)
 100 {
 101     if (env->mstatus & MSTATUS_FS) {
 102         if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
 103             return false;
 104         }
 105         return true;
 106     }
 107
 108     return false;
 109 }
 110
 111 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 112 {
 113     target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
 114                                 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
 115     bool current_virt = riscv_cpu_virt_enabled(env);
 116
 117     g_assert(riscv_has_ext(env, RVH));
 118
 119 #if defined(TARGET_RISCV64)
 120     mstatus_mask |= MSTATUS64_UXL;
 121 #endif
 122
 123     if (current_virt) {
 124         /* Current V=1 and we are about to change to V=0 */
 125         env->vsstatus = env->mstatus & mstatus_mask;
 126         env->mstatus &= ~mstatus_mask;
 127         env->mstatus |= env->mstatus_hs;
 128
 129 #if defined(TARGET_RISCV32)
 130         env->vsstatush = env->mstatush;
 131         env->mstatush |= env->mstatush_hs;
 132 #endif
 133
 134         env->vstvec = env->stvec;
 135         env->stvec = env->stvec_hs;
 136
 137         env->vsscratch = env->sscratch;
 138         env->sscratch = env->sscratch_hs;
 139
 140         env->vsepc = env->sepc;
 141         env->sepc = env->sepc_hs;
 142
 143         env->vscause = env->scause;
 144         env->scause = env->scause_hs;
 145
 146         env->vstval = env->sbadaddr;
 147         env->sbadaddr = env->stval_hs;
 148
 149         env->vsatp = env->satp;
 150         env->satp = env->satp_hs;
 151     } else {
 152         /* Current V=0 and we are about to change to V=1 */
 153         env->mstatus_hs = env->mstatus & mstatus_mask;
 154         env->mstatus &= ~mstatus_mask;
 155         env->mstatus |= env->vsstatus;
 156
 157 #if defined(TARGET_RISCV32)
 158         env->mstatush_hs = env->mstatush;
 159         env->mstatush |= env->vsstatush;
 160 #endif
 161
 162         env->stvec_hs = env->stvec;
 163         env->stvec = env->vstvec;
 164
 165         env->sscratch_hs = env->sscratch;
 166         env->sscratch = env->vsscratch;
 167
 168         env->sepc_hs = env->sepc;
 169         env->sepc = env->vsepc;
 170
 171         env->scause_hs = env->scause;
 172         env->scause = env->vscause;
 173
 174         env->stval_hs = env->sbadaddr;
 175         env->sbadaddr = env->vstval;
 176
 177         env->satp_hs = env->satp;
 178         env->satp = env->vsatp;
 179     }
 180 }
 181
 182 bool riscv_cpu_virt_enabled(CPURISCVState *env)
 183 {
 184     if (!riscv_has_ext(env, RVH)) {
 185         return false;
 186     }
 187
 188     return get_field(env->virt, VIRT_ONOFF);
 189 }
 190
 191 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
 192 {
 193     if (!riscv_has_ext(env, RVH)) {
 194         return;
 195     }
 196
 197     /* Flush the TLB on all virt mode changes. */
 198     if (get_field(env->virt, VIRT_ONOFF) != enable) {
 199         tlb_flush(env_cpu(env));
 200     }
 201
 202     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
 203 }
 204
 205 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
 206 {
 207     if (!riscv_has_ext(env, RVH)) {
 208         return false;
 209     }
 210
 211     return get_field(env->virt, FORCE_HS_EXCEP);
 212 }
 213
 214 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
 215 {
 216     if (!riscv_has_ext(env, RVH)) {
 217         return;
 218     }
 219
 220     env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
 221 }
 222
 223 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
 224 {
 225     CPURISCVState *env = &cpu->env;
 226     if (env->miclaim & interrupts) {
 227         return -1;
 228     } else {
 229         env->miclaim |= interrupts;
 230         return 0;
 231     }
 232 }
 233
 234 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
 235 {
 236     CPURISCVState *env = &cpu->env;
 237     CPUState *cs = CPU(cpu);
 238     uint32_t old = env->mip;
 239     bool locked = false;
 240
 241     if (!qemu_mutex_iothread_locked()) {
 242         locked = true;
 243         qemu_mutex_lock_iothread();
 244     }
 245
 246     env->mip = (env->mip & ~mask) | (value & mask);
 247
 248     if (env->mip) {
 249         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 250     } else {
 251         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 252     }
 253
 254     if (locked) {
 255         qemu_mutex_unlock_iothread();
 256     }
 257
 258     return old;
 259 }
 260
 261 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
 262 {
 263     env->rdtime_fn = fn;
 264 }
 265
 266 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
 267 {
 268     if (newpriv > PRV_M) {
 269         g_assert_not_reached();
 270     }
 271     if (newpriv == PRV_H) {
 272         newpriv = PRV_U;
 273     }
 274     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
 275     env->priv = newpriv;
 276
 277     /*
 278      * Clear the load reservation - otherwise a reservation placed in one
 279      * context/process can be used by another, resulting in an SC succeeding
 280      * incorrectly. Version 2.2 of the ISA specification explicitly requires
 281      * this behaviour, while later revisions say that the kernel "should" use
 282      * an SC instruction to force the yielding of a load reservation on a
 283      * preemptive context switch. As a result, do both.
 284      */
 285     env->load_res = -1;
 286 }
 287
 288 /* get_physical_address - get the physical address for this virtual address
 289  *
 290  * Do a page table walk to obtain the physical address corresponding to a
 291  * virtual address. Returns 0 if the translation was successful
 292  *
 293  * Adapted from Spike's mmu_t::translate and mmu_t::walk
 294  *
 295  * @env: CPURISCVState
 296  * @physical: This will be set to the calculated physical address
 297  * @prot: The returned protection attributes
 298  * @addr: The virtual address to be translated
 299  * @access_type: The type of MMU access
 300  * @mmu_idx: Indicates current privilege level
 301  * @first_stage: Are we in first stage translation?
 302  *               Second stage is used for hypervisor guest translation
 303  * @two_stage: Are we going to perform two stage translation
 304  */
 305 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 306                                 int *prot, target_ulong addr,
 307                                 int access_type, int mmu_idx,
 308                                 bool first_stage, bool two_stage)
 309 {
 310     /* NOTE: the env->pc value visible here will not be
 311      * correct, but the value visible to the exception handler
 312      * (riscv_cpu_do_interrupt) is correct */
 313     MemTxResult res;
 314     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
 315     int mode = mmu_idx;
 316     bool use_background = false;
 317
 318     /*
 319      * Check if we should use the background registers for the two
 320      * stage translation. We don't need to check if we actually need
 321      * two stage translation as that happened before this function
 322      * was called. Background registers will be used if the guest has
 323      * forced a two stage translation to be on (in HS or M mode).
 324      */
 325     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 326         if (get_field(env->mstatus, MSTATUS_MPRV)) {
 327             mode = get_field(env->mstatus, MSTATUS_MPP);
 328
 329             if (riscv_has_ext(env, RVH) &&
 330                 MSTATUS_MPV_ISSET(env)) {
 331                 use_background = true;
 332             }
 333         }
 334     }
 335
 336     if (mode == PRV_S && access_type != MMU_INST_FETCH &&
 337         riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
 338         if (get_field(env->hstatus, HSTATUS_SPRV)) {
 339             mode = get_field(env->mstatus, SSTATUS_SPP);
 340             use_background = true;
 341         }
 342     }
 343
 344     if (first_stage == false) {
 345         /* We are in stage 2 translation, this is similar to stage 1. */
 346         /* Stage 2 is always taken as U-mode */
 347         mode = PRV_U;
 348     }
 349
 350     if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
 351         *physical = addr;
 352         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 353         return TRANSLATE_SUCCESS;
 354     }
 355
 356     *prot = 0;
 357
 358     hwaddr base;
 359     int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
 360
 361     if (first_stage == true) {
 362         mxr = get_field(env->mstatus, MSTATUS_MXR);
 363     } else {
 364         mxr = get_field(env->vsstatus, MSTATUS_MXR);
 365     }
 366
 367     if (first_stage == true) {
 368         if (use_background) {
 369             base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
 370             vm = get_field(env->vsatp, SATP_MODE);
 371         } else {
 372             base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
 373             vm = get_field(env->satp, SATP_MODE);
 374         }
 375         widened = 0;
 376     } else {
 377         base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
 378         vm = get_field(env->hgatp, HGATP_MODE);
 379         widened = 2;
 380     }
 381     sum = get_field(env->mstatus, MSTATUS_SUM);
 382     switch (vm) {
 383     case VM_1_10_SV32:
 384       levels = 2; ptidxbits = 10; ptesize = 4; break;
 385     case VM_1_10_SV39:
 386       levels = 3; ptidxbits = 9; ptesize = 8; break;
 387     case VM_1_10_SV48:
 388       levels = 4; ptidxbits = 9; ptesize = 8; break;
 389     case VM_1_10_SV57:
 390       levels = 5; ptidxbits = 9; ptesize = 8; break;
 391     case VM_1_10_MBARE:
 392         *physical = addr;
 393         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 394         return TRANSLATE_SUCCESS;
 395     default:
 396       g_assert_not_reached();
 397     }
 398
 399     CPUState *cs = env_cpu(env);
 400     int va_bits = PGSHIFT + levels * ptidxbits + widened;
 401     target_ulong mask, masked_msbs;
 402
 403     if (TARGET_LONG_BITS > (va_bits - 1)) {
 404         mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
 405     } else {
 406         mask = 0;
 407     }
 408     masked_msbs = (addr >> (va_bits - 1)) & mask;
 409
 410     if (masked_msbs != 0 && masked_msbs != mask) {
 411         return TRANSLATE_FAIL;
 412     }
 413
 414     int ptshift = (levels - 1) * ptidxbits;
 415     int i;
 416
 417 #if !TCG_OVERSIZED_GUEST
 418 restart:
 419 #endif
 420     for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
 421         target_ulong idx;
 422         if (i == 0) {
 423             idx = (addr >> (PGSHIFT + ptshift)) &
 424                            ((1 << (ptidxbits + widened)) - 1);
 425         } else {
 426             idx = (addr >> (PGSHIFT + ptshift)) &
 427                            ((1 << ptidxbits) - 1);
 428         }
 429
 430         /* check that physical address of PTE is legal */
 431         hwaddr pte_addr;
 432
 433         if (two_stage && first_stage) {
 434             int vbase_prot;
 435             hwaddr vbase;
 436
 437             /* Do the second stage translation on the base PTE address. */
 438             int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
 439                                                  base, MMU_DATA_LOAD,
 440                                                  mmu_idx, false, true);
 441
 442             if (vbase_ret != TRANSLATE_SUCCESS) {
 443                 return vbase_ret;
 444             }
 445
 446             pte_addr = vbase + idx * ptesize;
 447         } else {
 448             pte_addr = base + idx * ptesize;
 449         }
 450
 451         if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 452             !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
 453             1 << MMU_DATA_LOAD, PRV_S)) {
 454             return TRANSLATE_PMP_FAIL;
 455         }
 456
 457 #if defined(TARGET_RISCV32)
 458         target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
 459 #elif defined(TARGET_RISCV64)
 460         target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
 461 #endif
 462         if (res != MEMTX_OK) {
 463             return TRANSLATE_FAIL;
 464         }
 465
 466         hwaddr ppn = pte >> PTE_PPN_SHIFT;
 467
 468         if (!(pte & PTE_V)) {
 469             /* Invalid PTE */
 470             return TRANSLATE_FAIL;
 471         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
 472             /* Inner PTE, continue walking */
 473             base = ppn << PGSHIFT;
 474         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
 475             /* Reserved leaf PTE flags: PTE_W */
 476             return TRANSLATE_FAIL;
 477         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
 478             /* Reserved leaf PTE flags: PTE_W + PTE_X */
 479             return TRANSLATE_FAIL;
 480         } else if ((pte & PTE_U) && ((mode != PRV_U) &&
 481                    (!sum || access_type == MMU_INST_FETCH))) {
 482             /* User PTE flags when not U mode and mstatus.SUM is not set,
 483                or the access type is an instruction fetch */
 484             return TRANSLATE_FAIL;
 485         } else if (!(pte & PTE_U) && (mode != PRV_S)) {
 486             /* Supervisor PTE flags when not S mode */
 487             return TRANSLATE_FAIL;
 488         } else if (ppn & ((1ULL << ptshift) - 1)) {
 489             /* Misaligned PPN */
 490             return TRANSLATE_FAIL;
 491         } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
 492                    ((pte & PTE_X) && mxr))) {
 493             /* Read access check failed */
 494             return TRANSLATE_FAIL;
 495         } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
 496             /* Write access check failed */
 497             return TRANSLATE_FAIL;
 498         } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
 499             /* Fetch access check failed */
 500             return TRANSLATE_FAIL;
 501         } else {
 502             /* if necessary, set accessed and dirty bits. */
 503             target_ulong updated_pte = pte | PTE_A |
 504                 (access_type == MMU_DATA_STORE ? PTE_D : 0);
 505
 506             /* Page table updates need to be atomic with MTTCG enabled */
 507             if (updated_pte != pte) {
 508                 /*
 509                  * - if accessed or dirty bits need updating, and the PTE is
 510                  *   in RAM, then we do so atomically with a compare and swap.
 511                  * - if the PTE is in IO space or ROM, then it can't be updated
 512                  *   and we return TRANSLATE_FAIL.
 513                  * - if the PTE changed by the time we went to update it, then
 514                  *   it is no longer valid and we must re-walk the page table.
 515                  */
 516                 MemoryRegion *mr;
 517                 hwaddr l = sizeof(target_ulong), addr1;
 518                 mr = address_space_translate(cs->as, pte_addr,
 519                     &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
 520                 if (memory_region_is_ram(mr)) {
 521                     target_ulong *pte_pa =
 522                         qemu_map_ram_ptr(mr->ram_block, addr1);
 523 #if TCG_OVERSIZED_GUEST
 524                     /* MTTCG is not enabled on oversized TCG guests so
 525                      * page table updates do not need to be atomic */
 526                     *pte_pa = pte = updated_pte;
 527 #else
 528                     target_ulong old_pte =
 529                         atomic_cmpxchg(pte_pa, pte, updated_pte);
 530                     if (old_pte != pte) {
 531                         goto restart;
 532                     } else {
 533                         pte = updated_pte;
 534                     }
 535 #endif
 536                 } else {
 537                     /* misconfigured PTE in ROM (AD bits are not preset) or
 538                      * PTE is in IO space and can't be updated atomically */
 539                     return TRANSLATE_FAIL;
 540                 }
 541             }
 542
 543             /* for superpage mappings, make a fake leaf PTE for the TLB's
 544                benefit. */
 545             target_ulong vpn = addr >> PGSHIFT;
 546             *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
 547
 548             /* set permissions on the TLB entry */
 549             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
 550                 *prot |= PAGE_READ;
 551             }
 552             if ((pte & PTE_X)) {
 553                 *prot |= PAGE_EXEC;
 554             }
 555             /* add write permission on stores or if the page is already dirty,
 556                so that we TLB miss on later writes to update the dirty bit */
 557             if ((pte & PTE_W) &&
 558                     (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
 559                 *prot |= PAGE_WRITE;
 560             }
 561             return TRANSLATE_SUCCESS;
 562         }
 563     }
 564     return TRANSLATE_FAIL;
 565 }
 566
 567 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 568                                 MMUAccessType access_type, bool pmp_violation,
 569                                 bool first_stage)
 570 {
 571     CPUState *cs = env_cpu(env);
 572     int page_fault_exceptions;
 573     if (first_stage) {
 574         page_fault_exceptions =
 575             get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
 576             !pmp_violation;
 577     } else {
 578         page_fault_exceptions =
 579             get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
 580             !pmp_violation;
 581     }
 582     switch (access_type) {
 583     case MMU_INST_FETCH:
 584         if (riscv_cpu_virt_enabled(env) && !first_stage) {
 585             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
 586         } else {
 587             cs->exception_index = page_fault_exceptions ?
 588                 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
 589         }
 590         break;
 591     case MMU_DATA_LOAD:
 592         if (riscv_cpu_virt_enabled(env) && !first_stage) {
 593             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
 594         } else {
 595             cs->exception_index = page_fault_exceptions ?
 596                 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
 597         }
 598         break;
 599     case MMU_DATA_STORE:
 600         if (riscv_cpu_virt_enabled(env) && !first_stage) {
 601             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
 602         } else {
 603             cs->exception_index = page_fault_exceptions ?
 604                 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 605         }
 606         break;
 607     default:
 608         g_assert_not_reached();
 609     }
 610     env->badaddr = address;
 611 }
 612
 613 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 614 {
 615     RISCVCPU *cpu = RISCV_CPU(cs);
 616     CPURISCVState *env = &cpu->env;
 617     hwaddr phys_addr;
 618     int prot;
 619     int mmu_idx = cpu_mmu_index(&cpu->env, false);
 620
 621     if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx,
 622                              true, riscv_cpu_virt_enabled(env))) {
 623         return -1;
 624     }
 625
 626     if (riscv_cpu_virt_enabled(env)) {
 627         if (get_physical_address(env, &phys_addr, &prot, phys_addr,
 628                                  0, mmu_idx, false, true)) {
 629             return -1;
 630         }
 631     }
 632
 633     return phys_addr;
 634 }
 635
 636 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 637                                      vaddr addr, unsigned size,
 638                                      MMUAccessType access_type,
 639                                      int mmu_idx, MemTxAttrs attrs,
 640                                      MemTxResult response, uintptr_t retaddr)
 641 {
 642     RISCVCPU *cpu = RISCV_CPU(cs);
 643     CPURISCVState *env = &cpu->env;
 644
 645     if (access_type == MMU_DATA_STORE) {
 646         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 647     } else {
 648         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 649     }
 650
 651     env->badaddr = addr;
 652     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 653 }
 654
 655 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 656                                    MMUAccessType access_type, int mmu_idx,
 657                                    uintptr_t retaddr)
 658 {
 659     RISCVCPU *cpu = RISCV_CPU(cs);
 660     CPURISCVState *env = &cpu->env;
 661     switch (access_type) {
 662     case MMU_INST_FETCH:
 663         cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
 664         break;
 665     case MMU_DATA_LOAD:
 666         cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
 667         break;
 668     case MMU_DATA_STORE:
 669         cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
 670         break;
 671     default:
 672         g_assert_not_reached();
 673     }
 674     env->badaddr = addr;
 675     riscv_raise_exception(env, cs->exception_index, retaddr);
 676 }
 677 #endif
 678
 679 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 680                         MMUAccessType access_type, int mmu_idx,
 681                         bool probe, uintptr_t retaddr)
 682 {
 683     RISCVCPU *cpu = RISCV_CPU(cs);
 684     CPURISCVState *env = &cpu->env;
 685 #ifndef CONFIG_USER_ONLY
 686     vaddr im_address;
 687     hwaddr pa = 0;
 688     int prot, prot2;
 689     bool pmp_violation = false;
 690     bool m_mode_two_stage = false;
 691     bool hs_mode_two_stage = false;
 692     bool first_stage_error = true;
 693     int ret = TRANSLATE_FAIL;
 694     int mode = mmu_idx;
 695
 696     env->guest_phys_fault_addr = 0;
 697
 698     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 699                   __func__, address, access_type, mmu_idx);
 700
 701     /*
 702      * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
 703      * set and we want to access a virtulisation address.
 704      */
 705     if (riscv_has_ext(env, RVH)) {
 706         m_mode_two_stage = env->priv == PRV_M &&
 707                            access_type != MMU_INST_FETCH &&
 708                            get_field(env->mstatus, MSTATUS_MPRV) &&
 709                            MSTATUS_MPV_ISSET(env);
 710
 711         hs_mode_two_stage = env->priv == PRV_S &&
 712                             !riscv_cpu_virt_enabled(env) &&
 713                             access_type != MMU_INST_FETCH &&
 714                             get_field(env->hstatus, HSTATUS_SPRV) &&
 715                             get_field(env->hstatus, HSTATUS_SPV);
 716     }
 717
 718     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 719         if (get_field(env->mstatus, MSTATUS_MPRV)) {
 720             mode = get_field(env->mstatus, MSTATUS_MPP);
 721         }
 722     }
 723
 724     if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
 725         /* Two stage lookup */
 726         ret = get_physical_address(env, &pa, &prot, address, access_type,
 727                                    mmu_idx, true, true);
 728
 729         qemu_log_mask(CPU_LOG_MMU,
 730                       "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
 731                       TARGET_FMT_plx " prot %d\n",
 732                       __func__, address, ret, pa, prot);
 733
 734         if (ret != TRANSLATE_FAIL) {
 735             /* Second stage lookup */
 736             im_address = pa;
 737
 738             ret = get_physical_address(env, &pa, &prot2, im_address,
 739                                        access_type, mmu_idx, false, true);
 740
 741             qemu_log_mask(CPU_LOG_MMU,
 742                     "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
 743                     TARGET_FMT_plx " prot %d\n",
 744                     __func__, im_address, ret, pa, prot2);
 745
 746             prot &= prot2;
 747
 748             if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 749                 (ret == TRANSLATE_SUCCESS) &&
 750                 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 751                 ret = TRANSLATE_PMP_FAIL;
 752             }
 753
 754             if (ret != TRANSLATE_SUCCESS) {
 755                 /*
 756                  * Guest physical address translation failed, this is a HS
 757                  * level exception
 758                  */
 759                 first_stage_error = false;
 760                 env->guest_phys_fault_addr = (im_address |
 761                                               (address &
 762                                                (TARGET_PAGE_SIZE - 1))) >> 2;
 763             }
 764         }
 765     } else {
 766         /* Single stage lookup */
 767         ret = get_physical_address(env, &pa, &prot, address, access_type,
 768                                    mmu_idx, true, false);
 769
 770         qemu_log_mask(CPU_LOG_MMU,
 771                       "%s address=%" VADDR_PRIx " ret %d physical "
 772                       TARGET_FMT_plx " prot %d\n",
 773                       __func__, address, ret, pa, prot);
 774     }
 775
 776     if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 777         (ret == TRANSLATE_SUCCESS) &&
 778         !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 779         ret = TRANSLATE_PMP_FAIL;
 780     }
 781     if (ret == TRANSLATE_PMP_FAIL) {
 782         pmp_violation = true;
 783     }
 784
 785     if (ret == TRANSLATE_SUCCESS) {
 786         tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 787                      prot, mmu_idx, TARGET_PAGE_SIZE);
 788         return true;
 789     } else if (probe) {
 790         return false;
 791     } else {
 792         raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error);
 793         riscv_raise_exception(env, cs->exception_index, retaddr);
 794     }
 795
 796     return true;
 797
 798 #else
 799     switch (access_type) {
 800     case MMU_INST_FETCH:
 801         cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
 802         break;
 803     case MMU_DATA_LOAD:
 804         cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
 805         break;
 806     case MMU_DATA_STORE:
 807         cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
 808         break;
 809     default:
 810         g_assert_not_reached();
 811     }
 812     env->badaddr = address;
 813     cpu_loop_exit_restore(cs, retaddr);
 814 #endif
 815 }
 816
 817 /*
 818  * Handle Traps
 819  *
 820  * Adapted from Spike's processor_t::take_trap.
 821  *
 822  */
 823 void riscv_cpu_do_interrupt(CPUState *cs)
 824 {
 825 #if !defined(CONFIG_USER_ONLY)
 826
 827     RISCVCPU *cpu = RISCV_CPU(cs);
 828     CPURISCVState *env = &cpu->env;
 829     bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
 830     target_ulong s;
 831
 832     /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
 833      * so we mask off the MSB and separate into trap type and cause.
 834      */
 835     bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
 836     target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
 837     target_ulong deleg = async ? env->mideleg : env->medeleg;
 838     target_ulong tval = 0;
 839     target_ulong htval = 0;
 840     target_ulong mtval2 = 0;
 841
 842     if (!async) {
 843         /* set tval to badaddr for traps with address information */
 844         switch (cause) {
 845         case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
 846         case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
 847         case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
 848             force_hs_execp = true;
 849             /* fallthrough */
 850         case RISCV_EXCP_INST_ADDR_MIS:
 851         case RISCV_EXCP_INST_ACCESS_FAULT:
 852         case RISCV_EXCP_LOAD_ADDR_MIS:
 853         case RISCV_EXCP_STORE_AMO_ADDR_MIS:
 854         case RISCV_EXCP_LOAD_ACCESS_FAULT:
 855         case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
 856         case RISCV_EXCP_INST_PAGE_FAULT:
 857         case RISCV_EXCP_LOAD_PAGE_FAULT:
 858         case RISCV_EXCP_STORE_PAGE_FAULT:
 859             tval = env->badaddr;
 860             break;
 861         default:
 862             break;
 863         }
 864         /* ecall is dispatched as one cause so translate based on mode */
 865         if (cause == RISCV_EXCP_U_ECALL) {
 866             assert(env->priv <= 3);
 867
 868             if (env->priv == PRV_M) {
 869                 cause = RISCV_EXCP_M_ECALL;
 870             } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
 871                 cause = RISCV_EXCP_VS_ECALL;
 872             } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
 873                 cause = RISCV_EXCP_S_ECALL;
 874             } else if (env->priv == PRV_U) {
 875                 cause = RISCV_EXCP_U_ECALL;
 876             }
 877         }
 878     }
 879
 880     trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
 881         (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
 882
 883     if (env->priv <= PRV_S &&
 884             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
 885         /* handle the trap in S-mode */
 886         if (riscv_has_ext(env, RVH)) {
 887             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 888
 889             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
 890                 !force_hs_execp) {
 891                 /*
 892                  * See if we need to adjust cause. Yes if its VS mode interrupt
 893                  * no if hypervisor has delegated one of hs mode's interrupt
 894                  */
 895                 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
 896                     cause == IRQ_VS_EXT)
 897                     cause = cause - 1;
 898                 /* Trap to VS mode */
 899             } else if (riscv_cpu_virt_enabled(env)) {
 900                 /* Trap into HS mode, from virt */
 901                 riscv_cpu_swap_hypervisor_regs(env);
 902                 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
 903                                          get_field(env->hstatus, HSTATUS_SPV));
 904                 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
 905                                          get_field(env->mstatus, SSTATUS_SPP));
 906                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 907                                          riscv_cpu_virt_enabled(env));
 908
 909                 htval = env->guest_phys_fault_addr;
 910
 911                 riscv_cpu_set_virt_enabled(env, 0);
 912                 riscv_cpu_set_force_hs_excep(env, 0);
 913             } else {
 914                 /* Trap into HS mode */
 915                 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
 916                                          get_field(env->hstatus, HSTATUS_SPV));
 917                 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
 918                                          get_field(env->mstatus, SSTATUS_SPP));
 919                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 920                                          riscv_cpu_virt_enabled(env));
 921
 922                 htval = env->guest_phys_fault_addr;
 923             }
 924         }
 925
 926         s = env->mstatus;
 927         s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 928         s = set_field(s, MSTATUS_SPP, env->priv);
 929         s = set_field(s, MSTATUS_SIE, 0);
 930         env->mstatus = s;
 931         env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
 932         env->sepc = env->pc;
 933         env->sbadaddr = tval;
 934         env->htval = htval;
 935         env->pc = (env->stvec >> 2 << 2) +
 936             ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
 937         riscv_cpu_set_mode(env, PRV_S);
 938     } else {
 939         /* handle the trap in M-mode */
 940         if (riscv_has_ext(env, RVH)) {
 941             if (riscv_cpu_virt_enabled(env)) {
 942                 riscv_cpu_swap_hypervisor_regs(env);
 943             }
 944 #ifdef TARGET_RISCV32
 945             env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
 946                                        riscv_cpu_virt_enabled(env));
 947             env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
 948                                        riscv_cpu_force_hs_excep_enabled(env));
 949 #else
 950             env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
 951                                       riscv_cpu_virt_enabled(env));
 952             env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
 953                                       riscv_cpu_force_hs_excep_enabled(env));
 954 #endif
 955
 956             mtval2 = env->guest_phys_fault_addr;
 957
 958             /* Trapping to M mode, virt is disabled */
 959             riscv_cpu_set_virt_enabled(env, 0);
 960             riscv_cpu_set_force_hs_excep(env, 0);
 961         }
 962
 963         s = env->mstatus;
 964         s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 965         s = set_field(s, MSTATUS_MPP, env->priv);
 966         s = set_field(s, MSTATUS_MIE, 0);
 967         env->mstatus = s;
 968         env->mcause = cause | ~(((target_ulong)-1) >> async);
 969         env->mepc = env->pc;
 970         env->mbadaddr = tval;
 971         env->mtval2 = mtval2;
 972         env->pc = (env->mtvec >> 2 << 2) +
 973             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
 974         riscv_cpu_set_mode(env, PRV_M);
 975     }
 976
 977     /* NOTE: it is not necessary to yield load reservations here. It is only
 978      * necessary for an SC from "another hart" to cause a load reservation
 979      * to be yielded. Refer to the memory consistency model section of the
 980      * RISC-V ISA Specification.
 981      */
 982
 983 #endif
 984     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 985 }