4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "hw/core/cpu.h"
24 #include "exec/cpu-defs.h"
25 #include "fpu/softfloat-types.h"
27 #define TCG_GUEST_DEFAULT_MO 0
29 #define TYPE_RISCV_CPU "riscv-cpu"
31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
38 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
39 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
40 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
41 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
42 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
43 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
45 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
46 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
48 #if defined(TARGET_RISCV32)
50 #elif defined(TARGET_RISCV64)
54 #define RV(x) ((target_ulong)1 << (x - 'A'))
57 #define RVE RV('E') /* E and I are mutually exclusive */
67 /* S extension denotes that Supervisor mode exists, however it is possible
68 to have a core that support S mode but does not have an MMU and there
69 is currently no bit in misa to indicate whether an MMU exists or not
70 so a cpu features bitfield is required, likewise for optional PMP support */
77 #define PRIV_VERSION_1_10_0 0x00011000
78 #define PRIV_VERSION_1_11_0 0x00011100
80 #define TRANSLATE_PMP_FAIL 2
81 #define TRANSLATE_FAIL 1
82 #define TRANSLATE_SUCCESS 0
83 #define MMU_USER_IDX 3
85 #define MAX_RISCV_PMPS (16)
87 typedef struct CPURISCVState CPURISCVState
;
91 struct CPURISCVState
{
93 uint64_t fpr
[32]; /* assume both F and D extensions */
95 target_ulong load_res
;
96 target_ulong load_val
;
100 target_ulong badaddr
;
101 target_ulong guest_phys_fault_addr
;
103 target_ulong priv_ver
;
105 target_ulong misa_mask
;
109 #ifdef CONFIG_USER_ONLY
113 #ifndef CONFIG_USER_ONLY
115 /* This contains QEMU specific information about the virt state. */
117 target_ulong resetvec
;
119 target_ulong mhartid
;
120 target_ulong mstatus
;
124 #ifdef TARGET_RISCV32
125 target_ulong mstatush
;
131 target_ulong mideleg
;
133 target_ulong sptbr
; /* until: priv-1.9.1 */
134 target_ulong satp
; /* since: priv-1.10.0 */
135 target_ulong sbadaddr
;
136 target_ulong mbadaddr
;
137 target_ulong medeleg
;
146 target_ulong mtval
; /* since: priv-1.10.0 */
148 /* Hypervisor CSRs */
149 target_ulong hstatus
;
150 target_ulong hedeleg
;
151 target_ulong hideleg
;
152 target_ulong hcounteren
;
159 target_ulong vsstatus
;
161 target_ulong vsscratch
;
163 target_ulong vscause
;
166 #ifdef TARGET_RISCV32
167 target_ulong vsstatush
;
174 target_ulong stvec_hs
;
175 target_ulong sscratch_hs
;
176 target_ulong sepc_hs
;
177 target_ulong scause_hs
;
178 target_ulong stval_hs
;
179 target_ulong satp_hs
;
180 target_ulong mstatus_hs
;
181 #ifdef TARGET_RISCV32
182 target_ulong mstatush_hs
;
185 target_ulong scounteren
;
186 target_ulong mcounteren
;
188 target_ulong sscratch
;
189 target_ulong mscratch
;
191 /* temporary htif regs */
196 /* physical memory protection */
197 pmp_table_t pmp_state
;
199 /* machine specific rdtime callback */
200 uint64_t (*rdtime_fn
)(void);
202 /* True if in debugger mode. */
206 float_status fp_status
;
208 /* Fields from here on are preserved across CPU reset. */
209 QEMUTimer
*timer
; /* Internal timer */
212 #define RISCV_CPU_CLASS(klass) \
213 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
214 #define RISCV_CPU(obj) \
215 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
216 #define RISCV_CPU_GET_CLASS(obj) \
217 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
221 * @parent_realize: The parent class' realize handler.
222 * @parent_reset: The parent class' reset handler.
226 typedef struct RISCVCPUClass
{
228 CPUClass parent_class
;
230 DeviceRealize parent_realize
;
231 DeviceReset parent_reset
;
236 * @env: #CPURISCVState
240 typedef struct RISCVCPU
{
244 CPUNegativeOffsetState neg
;
247 /* Configuration Settings */
271 static inline int riscv_has_ext(CPURISCVState
*env
, target_ulong ext
)
273 return (env
->misa
& ext
) != 0;
276 static inline bool riscv_feature(CPURISCVState
*env
, int feature
)
278 return env
->features
& (1ULL << feature
);
281 #include "cpu_user.h"
282 #include "cpu_bits.h"
284 extern const char * const riscv_int_regnames
[];
285 extern const char * const riscv_fpr_regnames
[];
286 extern const char * const riscv_excp_names
[];
287 extern const char * const riscv_intr_names
[];
289 void riscv_cpu_do_interrupt(CPUState
*cpu
);
290 int riscv_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
291 int riscv_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
292 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
);
293 bool riscv_cpu_fp_enabled(CPURISCVState
*env
);
294 bool riscv_cpu_virt_enabled(CPURISCVState
*env
);
295 void riscv_cpu_set_virt_enabled(CPURISCVState
*env
, bool enable
);
296 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState
*env
);
297 void riscv_cpu_set_force_hs_excep(CPURISCVState
*env
, bool enable
);
298 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
);
299 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
300 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
301 MMUAccessType access_type
, int mmu_idx
,
303 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
304 MMUAccessType access_type
, int mmu_idx
,
305 bool probe
, uintptr_t retaddr
);
306 void riscv_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
307 vaddr addr
, unsigned size
,
308 MMUAccessType access_type
,
309 int mmu_idx
, MemTxAttrs attrs
,
310 MemTxResult response
, uintptr_t retaddr
);
311 char *riscv_isa_string(RISCVCPU
*cpu
);
312 void riscv_cpu_list(void);
314 #define cpu_signal_handler riscv_cpu_signal_handler
315 #define cpu_list riscv_cpu_list
316 #define cpu_mmu_index riscv_cpu_mmu_index
318 #ifndef CONFIG_USER_ONLY
319 void riscv_cpu_swap_hypervisor_regs(CPURISCVState
*env
);
320 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint32_t interrupts
);
321 uint32_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint32_t mask
, uint32_t value
);
322 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
323 void riscv_cpu_set_rdtime_fn(CPURISCVState
*env
, uint64_t (*fn
)(void));
325 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
);
327 void riscv_translate_init(void);
328 int riscv_cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
);
329 void QEMU_NORETURN
riscv_raise_exception(CPURISCVState
*env
,
330 uint32_t exception
, uintptr_t pc
);
332 target_ulong
riscv_cpu_get_fflags(CPURISCVState
*env
);
333 void riscv_cpu_set_fflags(CPURISCVState
*env
, target_ulong
);
335 #define TB_FLAGS_MMU_MASK 3
336 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
338 static inline void cpu_get_tb_cpu_state(CPURISCVState
*env
, target_ulong
*pc
,
339 target_ulong
*cs_base
, uint32_t *flags
)
343 #ifdef CONFIG_USER_ONLY
344 *flags
= TB_FLAGS_MSTATUS_FS
;
346 *flags
= cpu_mmu_index(env
, 0);
347 if (riscv_cpu_fp_enabled(env
)) {
348 *flags
|= env
->mstatus
& MSTATUS_FS
;
353 int riscv_csrrw(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
354 target_ulong new_value
, target_ulong write_mask
);
355 int riscv_csrrw_debug(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
356 target_ulong new_value
, target_ulong write_mask
);
358 static inline void riscv_csr_write(CPURISCVState
*env
, int csrno
,
361 riscv_csrrw(env
, csrno
, NULL
, val
, MAKE_64BIT_MASK(0, TARGET_LONG_BITS
));
364 static inline target_ulong
riscv_csr_read(CPURISCVState
*env
, int csrno
)
366 target_ulong val
= 0;
367 riscv_csrrw(env
, csrno
, &val
, 0, 0);
371 typedef int (*riscv_csr_predicate_fn
)(CPURISCVState
*env
, int csrno
);
372 typedef int (*riscv_csr_read_fn
)(CPURISCVState
*env
, int csrno
,
373 target_ulong
*ret_value
);
374 typedef int (*riscv_csr_write_fn
)(CPURISCVState
*env
, int csrno
,
375 target_ulong new_value
);
376 typedef int (*riscv_csr_op_fn
)(CPURISCVState
*env
, int csrno
,
377 target_ulong
*ret_value
, target_ulong new_value
, target_ulong write_mask
);
380 riscv_csr_predicate_fn predicate
;
381 riscv_csr_read_fn read
;
382 riscv_csr_write_fn write
;
384 } riscv_csr_operations
;
386 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
);
387 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
);
389 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
);
391 typedef CPURISCVState CPUArchState
;
392 typedef RISCVCPU ArchCPU
;
394 #include "exec/cpu-all.h"
396 #endif /* RISCV_CPU_H */