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arm/acpi: Add the TPM2.0 device under the DSDT
[qemu/ar7.git] / hw / arm / virt-acpi-build.c
blob1384a2cf2ab4323d0f799b3f8a35f2e1e1030103
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "trace.h"
33 #include "hw/core/cpu.h"
34 #include "target/arm/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/generic_event_device.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/pci/pcie_host.h"
46 #include "hw/pci/pci.h"
47 #include "hw/arm/virt.h"
48 #include "hw/mem/nvdimm.h"
49 #include "hw/platform-bus.h"
50 #include "sysemu/numa.h"
51 #include "sysemu/reset.h"
52 #include "sysemu/tpm.h"
53 #include "kvm_arm.h"
54 #include "migration/vmstate.h"
55 #include "hw/acpi/ghes.h"
56
57 #define ARM_SPI_BASE 32
58
59 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
60 {
61 uint16_t i;
62
63 for (i = 0; i < smp_cpus; i++) {
64 Aml *dev = aml_device("C%.03X", i);
65 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
66 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
67 aml_append(scope, dev);
68 }
69 }
70
71 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
72 uint32_t uart_irq)
73 {
74 Aml *dev = aml_device("COM0");
75 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
76 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
77
78 Aml *crs = aml_resource_template();
79 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
80 uart_memmap->size, AML_READ_WRITE));
81 aml_append(crs,
82 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
83 AML_EXCLUSIVE, &uart_irq, 1));
84 aml_append(dev, aml_name_decl("_CRS", crs));
85
86 aml_append(scope, dev);
87 }
88
89 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
90 {
91 Aml *dev = aml_device("FWCF");
92 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
93 /* device present, functioning, decoding, not shown in UI */
94 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
95 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
96
97 Aml *crs = aml_resource_template();
98 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
99 fw_cfg_memmap->size, AML_READ_WRITE));
100 aml_append(dev, aml_name_decl("_CRS", crs));
101 aml_append(scope, dev);
102 }
103
104 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
105 {
106 Aml *dev, *crs;
107 hwaddr base = flash_memmap->base;
108 hwaddr size = flash_memmap->size / 2;
109
110 dev = aml_device("FLS0");
111 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
112 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
113
114 crs = aml_resource_template();
115 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
116 aml_append(dev, aml_name_decl("_CRS", crs));
117 aml_append(scope, dev);
118
119 dev = aml_device("FLS1");
120 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
121 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
122 crs = aml_resource_template();
123 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
124 aml_append(dev, aml_name_decl("_CRS", crs));
125 aml_append(scope, dev);
126 }
127
128 static void acpi_dsdt_add_virtio(Aml *scope,
129 const MemMapEntry *virtio_mmio_memmap,
130 uint32_t mmio_irq, int num)
131 {
132 hwaddr base = virtio_mmio_memmap->base;
133 hwaddr size = virtio_mmio_memmap->size;
134 int i;
135
136 for (i = 0; i < num; i++) {
137 uint32_t irq = mmio_irq + i;
138 Aml *dev = aml_device("VR%02u", i);
139 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
140 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
141 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
142
143 Aml *crs = aml_resource_template();
144 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
145 aml_append(crs,
146 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
147 AML_EXCLUSIVE, &irq, 1));
148 aml_append(dev, aml_name_decl("_CRS", crs));
149 aml_append(scope, dev);
150 base += size;
151 }
152 }
153
154 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
155 uint32_t irq, bool use_highmem, bool highmem_ecam)
156 {
157 int ecam_id = VIRT_ECAM_ID(highmem_ecam);
158 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
159 int i, slot_no;
160 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
161 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
162 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
163 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
164 hwaddr base_ecam = memmap[ecam_id].base;
165 hwaddr size_ecam = memmap[ecam_id].size;
166 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
167
168 Aml *dev = aml_device("%s", "PCI0");
169 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
170 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
171 aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
172 aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
173 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
174 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
175 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
176
177 /* Declare the PCI Routing Table. */
178 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
179 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
180 for (i = 0; i < PCI_NUM_PINS; i++) {
181 int gsi = (i + slot_no) % PCI_NUM_PINS;
182 Aml *pkg = aml_package(4);
183 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
184 aml_append(pkg, aml_int(i));
185 aml_append(pkg, aml_name("GSI%d", gsi));
186 aml_append(pkg, aml_int(0));
187 aml_append(rt_pkg, pkg);
188 }
189 }
190 aml_append(dev, aml_name_decl("_PRT", rt_pkg));
191
192 /* Create GSI link device */
193 for (i = 0; i < PCI_NUM_PINS; i++) {
194 uint32_t irqs = irq + i;
195 Aml *dev_gsi = aml_device("GSI%d", i);
196 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
197 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
198 crs = aml_resource_template();
199 aml_append(crs,
200 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
201 AML_EXCLUSIVE, &irqs, 1));
202 aml_append(dev_gsi, aml_name_decl("_PRS", crs));
203 crs = aml_resource_template();
204 aml_append(crs,
205 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
206 AML_EXCLUSIVE, &irqs, 1));
207 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
208 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
209 aml_append(dev_gsi, method);
210 aml_append(dev, dev_gsi);
211 }
212
213 method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
214 aml_append(method, aml_return(aml_int(base_ecam)));
215 aml_append(dev, method);
216
217 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
218 Aml *rbuf = aml_resource_template();
219 aml_append(rbuf,
220 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
221 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
222 nr_pcie_buses));
223 aml_append(rbuf,
224 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
225 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
226 base_mmio + size_mmio - 1, 0x0000, size_mmio));
227 aml_append(rbuf,
228 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
229 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
230 size_pio));
231
232 if (use_highmem) {
233 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
234 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
235
236 aml_append(rbuf,
237 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
238 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
239 base_mmio_high,
240 base_mmio_high + size_mmio_high - 1, 0x0000,
241 size_mmio_high));
242 }
243
244 aml_append(method, aml_return(rbuf));
245 aml_append(dev, method);
246
247 /* Declare an _OSC (OS Control Handoff) method */
248 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
249 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
250 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
251 aml_append(method,
252 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
253
254 /* PCI Firmware Specification 3.0
255 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
256 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
257 * identified by the Universal Unique IDentifier (UUID)
258 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
259 */
260 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
261 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
262 aml_append(ifctx,
263 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
264 aml_append(ifctx,
265 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
266 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
267 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
268
269 /*
270 * Allow OS control for all 5 features:
271 * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
272 */
273 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
274 aml_name("CTRL")));
275
276 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
277 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
278 aml_name("CDW1")));
279 aml_append(ifctx, ifctx1);
280
281 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
282 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
283 aml_name("CDW1")));
284 aml_append(ifctx, ifctx1);
285
286 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
287 aml_append(ifctx, aml_return(aml_arg(3)));
288 aml_append(method, ifctx);
289
290 elsectx = aml_else();
291 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
292 aml_name("CDW1")));
293 aml_append(elsectx, aml_return(aml_arg(3)));
294 aml_append(method, elsectx);
295 aml_append(dev, method);
296
297 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
298
299 /* PCI Firmware Specification 3.0
300 * 4.6.1. _DSM for PCI Express Slot Information
301 * The UUID in _DSM in this context is
302 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
303 */
304 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
305 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
306 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
307 uint8_t byte_list[1] = {1};
308 buf = aml_buffer(1, byte_list);
309 aml_append(ifctx1, aml_return(buf));
310 aml_append(ifctx, ifctx1);
311 aml_append(method, ifctx);
312
313 byte_list[0] = 0;
314 buf = aml_buffer(1, byte_list);
315 aml_append(method, aml_return(buf));
316 aml_append(dev, method);
317
318 Aml *dev_res0 = aml_device("%s", "RES0");
319 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
320 crs = aml_resource_template();
321 aml_append(crs,
322 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
323 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
324 base_ecam + size_ecam - 1, 0x0000, size_ecam));
325 aml_append(dev_res0, aml_name_decl("_CRS", crs));
326 aml_append(dev, dev_res0);
327 aml_append(scope, dev);
328 }
329
330 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
331 uint32_t gpio_irq)
332 {
333 Aml *dev = aml_device("GPO0");
334 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
335 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
336
337 Aml *crs = aml_resource_template();
338 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
339 AML_READ_WRITE));
340 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
341 AML_EXCLUSIVE, &gpio_irq, 1));
342 aml_append(dev, aml_name_decl("_CRS", crs));
343
344 Aml *aei = aml_resource_template();
345 /* Pin 3 for power button */
346 const uint32_t pin_list[1] = {3};
347 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
348 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
349 "GPO0", NULL, 0));
350 aml_append(dev, aml_name_decl("_AEI", aei));
351
352 /* _E03 is handle for power button */
353 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
354 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
355 aml_int(0x80)));
356 aml_append(dev, method);
357 aml_append(scope, dev);
358 }
359
360 static void acpi_dsdt_add_power_button(Aml *scope)
361 {
362 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
363 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
364 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
365 aml_append(scope, dev);
366 }
367
368 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
369 {
370 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
371 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
372 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
373 MemoryRegion *sbdev_mr;
374 hwaddr tpm_base;
375
376 if (!sbdev) {
377 return;
378 }
379
380 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
381 assert(tpm_base != -1);
382
383 tpm_base += pbus_base;
384
385 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
386
387 Aml *dev = aml_device("TPM0");
388 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
389 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
390
391 Aml *crs = aml_resource_template();
392 aml_append(crs,
393 aml_memory32_fixed(tpm_base,
394 (uint32_t)memory_region_size(sbdev_mr),
395 AML_READ_WRITE));
396 aml_append(dev, aml_name_decl("_CRS", crs));
397 aml_append(scope, dev);
398 }
399
400 static void
401 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
402 {
403 int nb_nodes, iort_start = table_data->len;
404 AcpiIortIdMapping *idmap;
405 AcpiIortItsGroup *its;
406 AcpiIortTable *iort;
407 AcpiIortSmmu3 *smmu;
408 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
409 AcpiIortRC *rc;
410
411 iort = acpi_data_push(table_data, sizeof(*iort));
412
413 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
414 nb_nodes = 3; /* RC, ITS, SMMUv3 */
415 } else {
416 nb_nodes = 2; /* RC, ITS */
417 }
418
419 iort_length = sizeof(*iort);
420 iort->node_count = cpu_to_le32(nb_nodes);
421 /*
422 * Use a copy in case table_data->data moves during acpi_data_push
423 * operations.
424 */
425 iort_node_offset = sizeof(*iort);
426 iort->node_offset = cpu_to_le32(iort_node_offset);
427
428 /* ITS group node */
429 node_size = sizeof(*its) + sizeof(uint32_t);
430 iort_length += node_size;
431 its = acpi_data_push(table_data, node_size);
432
433 its->type = ACPI_IORT_NODE_ITS_GROUP;
434 its->length = cpu_to_le16(node_size);
435 its->its_count = cpu_to_le32(1);
436 its->identifiers[0] = 0; /* MADT translation_id */
437
438 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
439 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
440
441 /* SMMUv3 node */
442 smmu_offset = iort_node_offset + node_size;
443 node_size = sizeof(*smmu) + sizeof(*idmap);
444 iort_length += node_size;
445 smmu = acpi_data_push(table_data, node_size);
446
447 smmu->type = ACPI_IORT_NODE_SMMU_V3;
448 smmu->length = cpu_to_le16(node_size);
449 smmu->mapping_count = cpu_to_le32(1);
450 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
451 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
452 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
453 smmu->event_gsiv = cpu_to_le32(irq);
454 smmu->pri_gsiv = cpu_to_le32(irq + 1);
455 smmu->gerr_gsiv = cpu_to_le32(irq + 2);
456 smmu->sync_gsiv = cpu_to_le32(irq + 3);
457
458 /* Identity RID mapping covering the whole input RID range */
459 idmap = &smmu->id_mapping_array[0];
460 idmap->input_base = 0;
461 idmap->id_count = cpu_to_le32(0xFFFF);
462 idmap->output_base = 0;
463 /* output IORT node is the ITS group node (the first node) */
464 idmap->output_reference = cpu_to_le32(iort_node_offset);
465 }
466
467 /* Root Complex Node */
468 node_size = sizeof(*rc) + sizeof(*idmap);
469 iort_length += node_size;
470 rc = acpi_data_push(table_data, node_size);
471
472 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
473 rc->length = cpu_to_le16(node_size);
474 rc->mapping_count = cpu_to_le32(1);
475 rc->mapping_offset = cpu_to_le32(sizeof(*rc));
476
477 /* fully coherent device */
478 rc->memory_properties.cache_coherency = cpu_to_le32(1);
479 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
480 rc->pci_segment_number = 0; /* MCFG pci_segment */
481
482 /* Identity RID mapping covering the whole input RID range */
483 idmap = &rc->id_mapping_array[0];
484 idmap->input_base = 0;
485 idmap->id_count = cpu_to_le32(0xFFFF);
486 idmap->output_base = 0;
487
488 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
489 /* output IORT node is the smmuv3 node */
490 idmap->output_reference = cpu_to_le32(smmu_offset);
491 } else {
492 /* output IORT node is the ITS group node (the first node) */
493 idmap->output_reference = cpu_to_le32(iort_node_offset);
494 }
495
496 /*
497 * Update the pointer address in case table_data->data moves during above
498 * acpi_data_push operations.
499 */
500 iort = (AcpiIortTable *)(table_data->data + iort_start);
501 iort->length = cpu_to_le32(iort_length);
502
503 build_header(linker, table_data, (void *)(table_data->data + iort_start),
504 "IORT", table_data->len - iort_start, 0, NULL, NULL);
505 }
506
507 static void
508 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
509 {
510 AcpiSerialPortConsoleRedirection *spcr;
511 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
512 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
513 int spcr_start = table_data->len;
514
515 spcr = acpi_data_push(table_data, sizeof(*spcr));
516
517 spcr->interface_type = 0x3; /* ARM PL011 UART */
518
519 spcr->base_address.space_id = AML_SYSTEM_MEMORY;
520 spcr->base_address.bit_width = 8;
521 spcr->base_address.bit_offset = 0;
522 spcr->base_address.access_width = 1;
523 spcr->base_address.address = cpu_to_le64(uart_memmap->base);
524
525 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
526 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
527
528 spcr->baud = 3; /* Baud Rate: 3 = 9600 */
529 spcr->parity = 0; /* No Parity */
530 spcr->stopbits = 1; /* 1 Stop bit */
531 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
532 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
533
534 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
535 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
536
537 build_header(linker, table_data, (void *)(table_data->data + spcr_start),
538 "SPCR", table_data->len - spcr_start, 2, NULL, NULL);
539 }
540
541 static void
542 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
543 {
544 AcpiSystemResourceAffinityTable *srat;
545 AcpiSratProcessorGiccAffinity *core;
546 AcpiSratMemoryAffinity *numamem;
547 int i, srat_start;
548 uint64_t mem_base;
549 MachineClass *mc = MACHINE_GET_CLASS(vms);
550 MachineState *ms = MACHINE(vms);
551 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
552
553 srat_start = table_data->len;
554 srat = acpi_data_push(table_data, sizeof(*srat));
555 srat->reserved1 = cpu_to_le32(1);
556
557 for (i = 0; i < cpu_list->len; ++i) {
558 core = acpi_data_push(table_data, sizeof(*core));
559 core->type = ACPI_SRAT_PROCESSOR_GICC;
560 core->length = sizeof(*core);
561 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
562 core->acpi_processor_uid = cpu_to_le32(i);
563 core->flags = cpu_to_le32(1);
564 }
565
566 mem_base = vms->memmap[VIRT_MEM].base;
567 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
568 if (ms->numa_state->nodes[i].node_mem > 0) {
569 numamem = acpi_data_push(table_data, sizeof(*numamem));
570 build_srat_memory(numamem, mem_base,
571 ms->numa_state->nodes[i].node_mem, i,
572 MEM_AFFINITY_ENABLED);
573 mem_base += ms->numa_state->nodes[i].node_mem;
574 }
575 }
576
577 if (ms->nvdimms_state->is_enabled) {
578 nvdimm_build_srat(table_data);
579 }
580
581 if (ms->device_memory) {
582 numamem = acpi_data_push(table_data, sizeof *numamem);
583 build_srat_memory(numamem, ms->device_memory->base,
584 memory_region_size(&ms->device_memory->mr),
585 ms->numa_state->num_nodes - 1,
586 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
587 }
588
589 build_header(linker, table_data, (void *)(table_data->data + srat_start),
590 "SRAT", table_data->len - srat_start, 3, NULL, NULL);
591 }
592
593 /* GTDT */
594 static void
595 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
596 {
597 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
598 int gtdt_start = table_data->len;
599 AcpiGenericTimerTable *gtdt;
600 uint32_t irqflags;
601
602 if (vmc->claim_edge_triggered_timers) {
603 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
604 } else {
605 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
606 }
607
608 gtdt = acpi_data_push(table_data, sizeof *gtdt);
609 /* The interrupt values are the same with the device tree when adding 16 */
610 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
611 gtdt->secure_el1_flags = cpu_to_le32(irqflags);
612
613 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
614 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
615 ACPI_GTDT_CAP_ALWAYS_ON);
616
617 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
618 gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
619
620 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
621 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
622
623 build_header(linker, table_data,
624 (void *)(table_data->data + gtdt_start), "GTDT",
625 table_data->len - gtdt_start, 2, NULL, NULL);
626 }
627
628 /* MADT */
629 static void
630 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
631 {
632 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
633 int madt_start = table_data->len;
634 const MemMapEntry *memmap = vms->memmap;
635 const int *irqmap = vms->irqmap;
636 AcpiMultipleApicTable *madt;
637 AcpiMadtGenericDistributor *gicd;
638 AcpiMadtGenericMsiFrame *gic_msi;
639 int i;
640
641 madt = acpi_data_push(table_data, sizeof *madt);
642
643 gicd = acpi_data_push(table_data, sizeof *gicd);
644 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
645 gicd->length = sizeof(*gicd);
646 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
647 gicd->version = vms->gic_version;
648
649 for (i = 0; i < vms->smp_cpus; i++) {
650 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
651 sizeof(*gicc));
652 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
653
654 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
655 gicc->length = sizeof(*gicc);
656 if (vms->gic_version == 2) {
657 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
658 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
659 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
660 }
661 gicc->cpu_interface_number = cpu_to_le32(i);
662 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
663 gicc->uid = cpu_to_le32(i);
664 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
665
666 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
667 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
668 }
669 if (vms->virt) {
670 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
671 }
672 }
673
674 if (vms->gic_version == 3) {
675 AcpiMadtGenericTranslator *gic_its;
676 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
677 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
678 sizeof *gicr);
679
680 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
681 gicr->length = sizeof(*gicr);
682 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
683 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
684
685 if (nb_redist_regions == 2) {
686 gicr = acpi_data_push(table_data, sizeof(*gicr));
687 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
688 gicr->length = sizeof(*gicr);
689 gicr->base_address =
690 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
691 gicr->range_length =
692 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
693 }
694
695 if (its_class_name() && !vmc->no_its) {
696 gic_its = acpi_data_push(table_data, sizeof *gic_its);
697 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
698 gic_its->length = sizeof(*gic_its);
699 gic_its->translation_id = 0;
700 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
701 }
702 } else {
703 gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
704 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
705 gic_msi->length = sizeof(*gic_msi);
706 gic_msi->gic_msi_frame_id = 0;
707 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
708 gic_msi->flags = cpu_to_le32(1);
709 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
710 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
711 }
712
713 build_header(linker, table_data,
714 (void *)(table_data->data + madt_start), "APIC",
715 table_data->len - madt_start, 3, NULL, NULL);
716 }
717
718 /* FADT */
719 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
720 VirtMachineState *vms, unsigned dsdt_tbl_offset)
721 {
722 /* ACPI v5.1 */
723 AcpiFadtData fadt = {
724 .rev = 5,
725 .minor_ver = 1,
726 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
727 .xdsdt_tbl_offset = &dsdt_tbl_offset,
728 };
729
730 switch (vms->psci_conduit) {
731 case QEMU_PSCI_CONDUIT_DISABLED:
732 fadt.arm_boot_arch = 0;
733 break;
734 case QEMU_PSCI_CONDUIT_HVC:
735 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
736 ACPI_FADT_ARM_PSCI_USE_HVC;
737 break;
738 case QEMU_PSCI_CONDUIT_SMC:
739 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
740 break;
741 default:
742 g_assert_not_reached();
743 }
744
745 build_fadt(table_data, linker, &fadt, NULL, NULL);
746 }
747
748 /* DSDT */
749 static void
750 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
751 {
752 Aml *scope, *dsdt;
753 MachineState *ms = MACHINE(vms);
754 const MemMapEntry *memmap = vms->memmap;
755 const int *irqmap = vms->irqmap;
756
757 dsdt = init_aml_allocator();
758 /* Reserve space for header */
759 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
760
761 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
762 * While UEFI can use libfdt to disable the RTC device node in the DTB that
763 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
764 * the RTC ACPI device at all when using UEFI.
765 */
766 scope = aml_scope("\\_SB");
767 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
768 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
769 (irqmap[VIRT_UART] + ARM_SPI_BASE));
770 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
771 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
772 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
773 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
774 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
775 vms->highmem, vms->highmem_ecam);
776 if (vms->acpi_dev) {
777 build_ged_aml(scope, "\\_SB."GED_DEVICE,
778 HOTPLUG_HANDLER(vms->acpi_dev),
779 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
780 memmap[VIRT_ACPI_GED].base);
781 } else {
782 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
783 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
784 }
785
786 if (vms->acpi_dev) {
787 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
788 "ged-event", &error_abort);
789
790 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
791 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
792 AML_SYSTEM_MEMORY,
793 memmap[VIRT_PCDIMM_ACPI].base);
794 }
795 }
796
797 acpi_dsdt_add_power_button(scope);
798 acpi_dsdt_add_tpm(scope, vms);
799
800 aml_append(dsdt, scope);
801
802 /* copy AML table into ACPI tables blob and patch header there */
803 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
804 build_header(linker, table_data,
805 (void *)(table_data->data + table_data->len - dsdt->buf->len),
806 "DSDT", dsdt->buf->len, 2, NULL, NULL);
807 free_aml_allocator();
808 }
809
810 typedef
811 struct AcpiBuildState {
812 /* Copy of table in RAM (for patching). */
813 MemoryRegion *table_mr;
814 MemoryRegion *rsdp_mr;
815 MemoryRegion *linker_mr;
816 /* Is table patched? */
817 bool patched;
818 } AcpiBuildState;
819
820 static
821 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
822 {
823 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
824 GArray *table_offsets;
825 unsigned dsdt, xsdt;
826 GArray *tables_blob = tables->table_data;
827 MachineState *ms = MACHINE(vms);
828
829 table_offsets = g_array_new(false, true /* clear */,
830 sizeof(uint32_t));
831
832 bios_linker_loader_alloc(tables->linker,
833 ACPI_BUILD_TABLE_FILE, tables_blob,
834 64, false /* high memory */);
835
836 /* DSDT is pointed to by FADT */
837 dsdt = tables_blob->len;
838 build_dsdt(tables_blob, tables->linker, vms);
839
840 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
841 acpi_add_table(table_offsets, tables_blob);
842 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
843
844 acpi_add_table(table_offsets, tables_blob);
845 build_madt(tables_blob, tables->linker, vms);
846
847 acpi_add_table(table_offsets, tables_blob);
848 build_gtdt(tables_blob, tables->linker, vms);
849
850 acpi_add_table(table_offsets, tables_blob);
851 {
852 AcpiMcfgInfo mcfg = {
853 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
854 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
855 };
856 build_mcfg(tables_blob, tables->linker, &mcfg);
857 }
858
859 acpi_add_table(table_offsets, tables_blob);
860 build_spcr(tables_blob, tables->linker, vms);
861
862 if (vms->ras) {
863 build_ghes_error_table(tables->hardware_errors, tables->linker);
864 acpi_add_table(table_offsets, tables_blob);
865 acpi_build_hest(tables_blob, tables->linker);
866 }
867
868 if (ms->numa_state->num_nodes > 0) {
869 acpi_add_table(table_offsets, tables_blob);
870 build_srat(tables_blob, tables->linker, vms);
871 if (ms->numa_state->have_numa_distance) {
872 acpi_add_table(table_offsets, tables_blob);
873 build_slit(tables_blob, tables->linker, ms);
874 }
875 }
876
877 if (ms->nvdimms_state->is_enabled) {
878 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
879 ms->nvdimms_state, ms->ram_slots);
880 }
881
882 if (its_class_name() && !vmc->no_its) {
883 acpi_add_table(table_offsets, tables_blob);
884 build_iort(tables_blob, tables->linker, vms);
885 }
886
887 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
888 acpi_add_table(table_offsets, tables_blob);
889 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
890 }
891
892 /* XSDT is pointed to by RSDP */
893 xsdt = tables_blob->len;
894 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
895
896 /* RSDP is in FSEG memory, so allocate it separately */
897 {
898 AcpiRsdpData rsdp_data = {
899 .revision = 2,
900 .oem_id = ACPI_BUILD_APPNAME6,
901 .xsdt_tbl_offset = &xsdt,
902 .rsdt_tbl_offset = NULL,
903 };
904 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
905 }
906
907 /* Cleanup memory that's no longer used. */
908 g_array_free(table_offsets, true);
909 }
910
911 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
912 {
913 uint32_t size = acpi_data_len(data);
914
915 /* Make sure RAM size is correct - in case it got changed
916 * e.g. by migration */
917 memory_region_ram_resize(mr, size, &error_abort);
918
919 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
920 memory_region_set_dirty(mr, 0, size);
921 }
922
923 static void virt_acpi_build_update(void *build_opaque)
924 {
925 AcpiBuildState *build_state = build_opaque;
926 AcpiBuildTables tables;
927
928 /* No state to update or already patched? Nothing to do. */
929 if (!build_state || build_state->patched) {
930 return;
931 }
932 build_state->patched = true;
933
934 acpi_build_tables_init(&tables);
935
936 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
937
938 acpi_ram_update(build_state->table_mr, tables.table_data);
939 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
940 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
941
942 acpi_build_tables_cleanup(&tables, true);
943 }
944
945 static void virt_acpi_build_reset(void *build_opaque)
946 {
947 AcpiBuildState *build_state = build_opaque;
948 build_state->patched = false;
949 }
950
951 static const VMStateDescription vmstate_virt_acpi_build = {
952 .name = "virt_acpi_build",
953 .version_id = 1,
954 .minimum_version_id = 1,
955 .fields = (VMStateField[]) {
956 VMSTATE_BOOL(patched, AcpiBuildState),
957 VMSTATE_END_OF_LIST()
958 },
959 };
960
961 void virt_acpi_setup(VirtMachineState *vms)
962 {
963 AcpiBuildTables tables;
964 AcpiBuildState *build_state;
965 AcpiGedState *acpi_ged_state;
966
967 if (!vms->fw_cfg) {
968 trace_virt_acpi_setup();
969 return;
970 }
971
972 if (!virt_is_acpi_enabled(vms)) {
973 trace_virt_acpi_setup();
974 return;
975 }
976
977 build_state = g_malloc0(sizeof *build_state);
978
979 acpi_build_tables_init(&tables);
980 virt_acpi_build(vms, &tables);
981
982 /* Now expose it all to Guest */
983 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
984 build_state, tables.table_data,
985 ACPI_BUILD_TABLE_FILE,
986 ACPI_BUILD_TABLE_MAX_SIZE);
987 assert(build_state->table_mr != NULL);
988
989 build_state->linker_mr =
990 acpi_add_rom_blob(virt_acpi_build_update, build_state,
991 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
992
993 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
994 acpi_data_len(tables.tcpalog));
995
996 if (vms->ras) {
997 assert(vms->acpi_dev);
998 acpi_ged_state = ACPI_GED(vms->acpi_dev);
999 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1000 vms->fw_cfg, tables.hardware_errors);
1001 }
1002
1003 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1004 build_state, tables.rsdp,
1005 ACPI_BUILD_RSDP_FILE, 0);
1006
1007 qemu_register_reset(virt_acpi_build_reset, build_state);
1008 virt_acpi_build_reset(build_state);
1009 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1010
1011 /* Cleanup tables but don't free the memory: we track it
1012 * in build_state.
1013 */
1014 acpi_build_tables_cleanup(&tables, false);
1015 }
AR7 emulation for QEMU