target/mips/tx79_translate.c

   1 /*
   2  * Toshiba TX79-specific instructions translation routines
   3  *
   4  *  Copyright (c) 2018 Fredrik Noring
   5  *
   6  * SPDX-License-Identifier: GPL-2.0-or-later
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "tcg/tcg-op.h"
  11 #include "exec/helper-gen.h"
  12 #include "translate.h"
  13
  14 /* Include the auto-generated decoder.  */
  15 #include "decode-tx79.c.inc"
  16
  17 bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
  18 {
  19     if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
  20         return true;
  21     }
  22     return false;
  23 }
  24
  25 static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
  26 {
  27     gen_store_gpr(cpu_HI[1], a->rd);
  28
  29     return true;
  30 }
  31
  32 static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
  33 {
  34     gen_store_gpr(cpu_LO[1], a->rd);
  35
  36     return true;
  37 }
  38
  39 static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
  40 {
  41     gen_load_gpr(cpu_HI[1], a->rs);
  42
  43     return true;
  44 }
  45
  46 static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
  47 {
  48     gen_load_gpr(cpu_LO[1], a->rs);
  49
  50     return true;
  51 }
  52
  53 /* Parallel Copy Halfword */
  54 static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
  55 {
  56     if (a->rd == 0) {
  57         /* nop */
  58         return true;
  59     }
  60
  61     if (a->rt == 0) {
  62         tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
  63         tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
  64         return true;
  65     }
  66
  67     tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16);
  68     tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32);
  69     tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16);
  70     tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32);
  71
  72     return true;
  73 }