4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "sysemu/reset.h"
28 #include "qapi/error.h"
29 #include "hw/display/vga.h"
30 #include "hw/pci/pci.h"
33 #include "ui/pixel_ops.h"
34 #include "qemu/timer.h"
35 #include "hw/xen/xen.h"
36 #include "migration/vmstate.h"
39 //#define DEBUG_VGA_MEM
40 //#define DEBUG_VGA_REG
44 /* 16 state changes per vertical frame @60 Hz */
45 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
48 * Video Graphics Array (VGA)
50 * Chipset docs for original IBM VGA:
51 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
54 * http://www.osdever.net/FreeVGA/home.htm
56 * Standard VGA features and Bochs VBE extensions are implemented.
59 /* force some bits to zero */
60 const uint8_t sr_mask
[8] = {
71 const uint8_t gr_mask
[16] = {
90 #define cbswap_32(__x) \
92 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
93 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
94 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
95 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
97 #ifdef HOST_WORDS_BIGENDIAN
98 #define PAT(x) cbswap_32(x)
103 #ifdef HOST_WORDS_BIGENDIAN
109 #ifdef HOST_WORDS_BIGENDIAN
110 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
112 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
115 static const uint32_t mask16
[16] = {
136 #ifdef HOST_WORDS_BIGENDIAN
139 #define PAT(x) cbswap_32(x)
142 static uint32_t expand4
[256];
143 static uint16_t expand2
[256];
144 static uint8_t expand4to8
[16];
146 static void vbe_update_vgaregs(VGACommonState
*s
);
148 static inline bool vbe_enabled(VGACommonState
*s
)
150 return s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
;
153 static inline uint8_t sr(VGACommonState
*s
, int idx
)
155 return vbe_enabled(s
) ? s
->sr_vbe
[idx
] : s
->sr
[idx
];
158 static void vga_update_memory_access(VGACommonState
*s
)
160 hwaddr base
, offset
, size
;
162 if (s
->legacy_address_space
== NULL
) {
166 if (s
->has_chain4_alias
) {
167 memory_region_del_subregion(s
->legacy_address_space
, &s
->chain4_alias
);
168 object_unparent(OBJECT(&s
->chain4_alias
));
169 s
->has_chain4_alias
= false;
170 s
->plane_updated
= 0xf;
172 if ((sr(s
, VGA_SEQ_PLANE_WRITE
) & VGA_SR02_ALL_PLANES
) ==
173 VGA_SR02_ALL_PLANES
&& sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
175 switch ((s
->gr
[VGA_GFX_MISC
] >> 2) & 3) {
183 offset
= s
->bank_offset
;
195 assert(offset
+ size
<= s
->vram_size
);
196 memory_region_init_alias(&s
->chain4_alias
, memory_region_owner(&s
->vram
),
197 "vga.chain4", &s
->vram
, offset
, size
);
198 memory_region_add_subregion_overlap(s
->legacy_address_space
, base
,
199 &s
->chain4_alias
, 2);
200 s
->has_chain4_alias
= true;
204 static void vga_dumb_update_retrace_info(VGACommonState
*s
)
209 static void vga_precise_update_retrace_info(VGACommonState
*s
)
212 int hretr_start_char
;
213 int hretr_skew_chars
;
217 int vretr_start_line
;
226 const int clk_hz
[] = {25175000, 28322000, 25175000, 25175000};
227 int64_t chars_per_sec
;
228 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
230 htotal_chars
= s
->cr
[VGA_CRTC_H_TOTAL
] + 5;
231 hretr_start_char
= s
->cr
[VGA_CRTC_H_SYNC_START
];
232 hretr_skew_chars
= (s
->cr
[VGA_CRTC_H_SYNC_END
] >> 5) & 3;
233 hretr_end_char
= s
->cr
[VGA_CRTC_H_SYNC_END
] & 0x1f;
235 vtotal_lines
= (s
->cr
[VGA_CRTC_V_TOTAL
] |
236 (((s
->cr
[VGA_CRTC_OVERFLOW
] & 1) |
237 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 4) & 2)) << 8)) + 2;
238 vretr_start_line
= s
->cr
[VGA_CRTC_V_SYNC_START
] |
239 ((((s
->cr
[VGA_CRTC_OVERFLOW
] >> 2) & 1) |
240 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 6) & 2)) << 8);
241 vretr_end_line
= s
->cr
[VGA_CRTC_V_SYNC_END
] & 0xf;
243 clocking_mode
= (sr(s
, VGA_SEQ_CLOCK_MODE
) >> 3) & 1;
244 clock_sel
= (s
->msr
>> 2) & 3;
245 dots
= (s
->msr
& 1) ? 8 : 9;
247 chars_per_sec
= clk_hz
[clock_sel
] / dots
;
249 htotal_chars
<<= clocking_mode
;
251 r
->total_chars
= vtotal_lines
* htotal_chars
;
253 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ (r
->total_chars
* r
->freq
);
255 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ chars_per_sec
;
258 r
->vstart
= vretr_start_line
;
259 r
->vend
= r
->vstart
+ vretr_end_line
+ 1;
261 r
->hstart
= hretr_start_char
+ hretr_skew_chars
;
262 r
->hend
= r
->hstart
+ hretr_end_char
+ 1;
263 r
->htotal
= htotal_chars
;
266 div2
= (s
->cr
[VGA_CRTC_MODE
] >> 2) & 1;
267 sldiv2
= (s
->cr
[VGA_CRTC_MODE
] >> 3) & 1;
277 "div2 = %d sldiv2 = %d\n"
278 "clocking_mode = %d\n"
279 "clock_sel = %d %d\n"
281 "ticks/char = %" PRId64
"\n"
283 (double) NANOSECONDS_PER_SECOND
/ (r
->ticks_per_char
* r
->total_chars
),
301 static uint8_t vga_precise_retrace(VGACommonState
*s
)
303 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
304 uint8_t val
= s
->st01
& ~(ST01_V_RETRACE
| ST01_DISP_ENABLE
);
306 if (r
->total_chars
) {
307 int cur_line
, cur_line_char
, cur_char
;
310 cur_tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
312 cur_char
= (cur_tick
/ r
->ticks_per_char
) % r
->total_chars
;
313 cur_line
= cur_char
/ r
->htotal
;
315 if (cur_line
>= r
->vstart
&& cur_line
<= r
->vend
) {
316 val
|= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
318 cur_line_char
= cur_char
% r
->htotal
;
319 if (cur_line_char
>= r
->hstart
&& cur_line_char
<= r
->hend
) {
320 val
|= ST01_DISP_ENABLE
;
326 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
330 static uint8_t vga_dumb_retrace(VGACommonState
*s
)
332 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
335 int vga_ioport_invalid(VGACommonState
*s
, uint32_t addr
)
337 if (s
->msr
& VGA_MIS_COLOR
) {
339 return (addr
>= 0x3b0 && addr
<= 0x3bf);
342 return (addr
>= 0x3d0 && addr
<= 0x3df);
346 uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
348 VGACommonState
*s
= opaque
;
351 if (vga_ioport_invalid(s
, addr
)) {
356 if (s
->ar_flip_flop
== 0) {
363 index
= s
->ar_index
& 0x1f;
364 if (index
< VGA_ATT_C
) {
377 val
= s
->sr
[s
->sr_index
];
379 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
386 val
= s
->dac_write_index
;
389 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
390 if (++s
->dac_sub_index
== 3) {
391 s
->dac_sub_index
= 0;
405 val
= s
->gr
[s
->gr_index
];
407 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
416 val
= s
->cr
[s
->cr_index
];
418 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
423 /* just toggle to fool polling */
424 val
= s
->st01
= s
->retrace(s
);
432 trace_vga_std_read_io(addr
, val
);
436 void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
438 VGACommonState
*s
= opaque
;
441 /* check port range access depending on color/monochrome mode */
442 if (vga_ioport_invalid(s
, addr
)) {
445 trace_vga_std_write_io(addr
, val
);
449 if (s
->ar_flip_flop
== 0) {
453 index
= s
->ar_index
& 0x1f;
455 case VGA_ATC_PALETTE0
... VGA_ATC_PALETTEF
:
456 s
->ar
[index
] = val
& 0x3f;
459 s
->ar
[index
] = val
& ~0x10;
461 case VGA_ATC_OVERSCAN
:
464 case VGA_ATC_PLANE_ENABLE
:
465 s
->ar
[index
] = val
& ~0xc0;
468 s
->ar
[index
] = val
& ~0xf0;
470 case VGA_ATC_COLOR_PAGE
:
471 s
->ar
[index
] = val
& ~0xf0;
477 s
->ar_flip_flop
^= 1;
480 s
->msr
= val
& ~0x10;
481 s
->update_retrace_info(s
);
484 s
->sr_index
= val
& 7;
488 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
490 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
491 if (s
->sr_index
== VGA_SEQ_CLOCK_MODE
) {
492 s
->update_retrace_info(s
);
494 vga_update_memory_access(s
);
497 s
->dac_read_index
= val
;
498 s
->dac_sub_index
= 0;
502 s
->dac_write_index
= val
;
503 s
->dac_sub_index
= 0;
507 s
->dac_cache
[s
->dac_sub_index
] = val
;
508 if (++s
->dac_sub_index
== 3) {
509 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
510 s
->dac_sub_index
= 0;
511 s
->dac_write_index
++;
515 s
->gr_index
= val
& 0x0f;
519 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
521 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
522 vbe_update_vgaregs(s
);
523 vga_update_memory_access(s
);
532 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
534 /* handle CR0-7 protection */
535 if ((s
->cr
[VGA_CRTC_V_SYNC_END
] & VGA_CR11_LOCK_CR0_CR7
) &&
536 s
->cr_index
<= VGA_CRTC_OVERFLOW
) {
537 /* can always write bit 4 of CR7 */
538 if (s
->cr_index
== VGA_CRTC_OVERFLOW
) {
539 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x10) |
541 vbe_update_vgaregs(s
);
545 s
->cr
[s
->cr_index
] = val
;
546 vbe_update_vgaregs(s
);
548 switch(s
->cr_index
) {
549 case VGA_CRTC_H_TOTAL
:
550 case VGA_CRTC_H_SYNC_START
:
551 case VGA_CRTC_H_SYNC_END
:
552 case VGA_CRTC_V_TOTAL
:
553 case VGA_CRTC_OVERFLOW
:
554 case VGA_CRTC_V_SYNC_END
:
556 s
->update_retrace_info(s
);
568 * Sanity check vbe register writes.
570 * As we don't have a way to signal errors to the guest in the bochs
571 * dispi interface we'll go adjust the registers to the closest valid
574 static void vbe_fixup_regs(VGACommonState
*s
)
576 uint16_t *r
= s
->vbe_regs
;
577 uint32_t bits
, linelength
, maxy
, offset
;
579 if (!vbe_enabled(s
)) {
580 /* vbe is turned off -- nothing to do */
585 switch (r
[VBE_DISPI_INDEX_BPP
]) {
591 bits
= r
[VBE_DISPI_INDEX_BPP
];
597 bits
= r
[VBE_DISPI_INDEX_BPP
] = 8;
602 r
[VBE_DISPI_INDEX_XRES
] &= ~7u;
603 if (r
[VBE_DISPI_INDEX_XRES
] == 0) {
604 r
[VBE_DISPI_INDEX_XRES
] = 8;
606 if (r
[VBE_DISPI_INDEX_XRES
] > VBE_DISPI_MAX_XRES
) {
607 r
[VBE_DISPI_INDEX_XRES
] = VBE_DISPI_MAX_XRES
;
609 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] &= ~7u;
610 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] > VBE_DISPI_MAX_XRES
) {
611 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = VBE_DISPI_MAX_XRES
;
613 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] < r
[VBE_DISPI_INDEX_XRES
]) {
614 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = r
[VBE_DISPI_INDEX_XRES
];
618 linelength
= r
[VBE_DISPI_INDEX_VIRT_WIDTH
] * bits
/ 8;
619 maxy
= s
->vbe_size
/ linelength
;
620 if (r
[VBE_DISPI_INDEX_YRES
] == 0) {
621 r
[VBE_DISPI_INDEX_YRES
] = 1;
623 if (r
[VBE_DISPI_INDEX_YRES
] > VBE_DISPI_MAX_YRES
) {
624 r
[VBE_DISPI_INDEX_YRES
] = VBE_DISPI_MAX_YRES
;
626 if (r
[VBE_DISPI_INDEX_YRES
] > maxy
) {
627 r
[VBE_DISPI_INDEX_YRES
] = maxy
;
631 if (r
[VBE_DISPI_INDEX_X_OFFSET
] > VBE_DISPI_MAX_XRES
) {
632 r
[VBE_DISPI_INDEX_X_OFFSET
] = VBE_DISPI_MAX_XRES
;
634 if (r
[VBE_DISPI_INDEX_Y_OFFSET
] > VBE_DISPI_MAX_YRES
) {
635 r
[VBE_DISPI_INDEX_Y_OFFSET
] = VBE_DISPI_MAX_YRES
;
637 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
638 offset
+= r
[VBE_DISPI_INDEX_Y_OFFSET
] * linelength
;
639 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
640 r
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
641 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
642 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
643 r
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
648 /* update vga state */
649 r
[VBE_DISPI_INDEX_VIRT_HEIGHT
] = maxy
;
650 s
->vbe_line_offset
= linelength
;
651 s
->vbe_start_addr
= offset
/ 4;
654 /* we initialize the VGA graphic mode */
655 static void vbe_update_vgaregs(VGACommonState
*s
)
657 int h
, shift_control
;
659 if (!vbe_enabled(s
)) {
660 /* vbe is turned off -- nothing to do */
664 /* graphic mode + memory map 1 */
665 s
->gr
[VGA_GFX_MISC
] = (s
->gr
[VGA_GFX_MISC
] & ~0x0c) | 0x04 |
666 VGA_GR06_GRAPHICS_MODE
;
667 s
->cr
[VGA_CRTC_MODE
] |= 3; /* no CGA modes */
668 s
->cr
[VGA_CRTC_OFFSET
] = s
->vbe_line_offset
>> 3;
670 s
->cr
[VGA_CRTC_H_DISP
] =
671 (s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 3) - 1;
672 /* height (only meaningful if < 1024) */
673 h
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] - 1;
674 s
->cr
[VGA_CRTC_V_DISP_END
] = h
;
675 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x42) |
676 ((h
>> 7) & 0x02) | ((h
>> 3) & 0x40);
677 /* line compare to 1023 */
678 s
->cr
[VGA_CRTC_LINE_COMPARE
] = 0xff;
679 s
->cr
[VGA_CRTC_OVERFLOW
] |= 0x10;
680 s
->cr
[VGA_CRTC_MAX_SCAN
] |= 0x40;
682 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
684 s
->sr_vbe
[VGA_SEQ_CLOCK_MODE
] &= ~8; /* no double line */
687 /* set chain 4 mode */
688 s
->sr_vbe
[VGA_SEQ_MEMORY_MODE
] |= VGA_SR04_CHN_4M
;
689 /* activate all planes */
690 s
->sr_vbe
[VGA_SEQ_PLANE_WRITE
] |= VGA_SR02_ALL_PLANES
;
692 s
->gr
[VGA_GFX_MODE
] = (s
->gr
[VGA_GFX_MODE
] & ~0x60) |
693 (shift_control
<< 5);
694 s
->cr
[VGA_CRTC_MAX_SCAN
] &= ~0x9f; /* no double scan */
697 static uint32_t vbe_ioport_read_index(void *opaque
, uint32_t addr
)
699 VGACommonState
*s
= opaque
;
703 uint32_t vbe_ioport_read_data(void *opaque
, uint32_t addr
)
705 VGACommonState
*s
= opaque
;
708 if (s
->vbe_index
< VBE_DISPI_INDEX_NB
) {
709 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_GETCAPS
) {
710 switch(s
->vbe_index
) {
711 /* XXX: do not hardcode ? */
712 case VBE_DISPI_INDEX_XRES
:
713 val
= VBE_DISPI_MAX_XRES
;
715 case VBE_DISPI_INDEX_YRES
:
716 val
= VBE_DISPI_MAX_YRES
;
718 case VBE_DISPI_INDEX_BPP
:
719 val
= VBE_DISPI_MAX_BPP
;
722 val
= s
->vbe_regs
[s
->vbe_index
];
726 val
= s
->vbe_regs
[s
->vbe_index
];
728 } else if (s
->vbe_index
== VBE_DISPI_INDEX_VIDEO_MEMORY_64K
) {
729 val
= s
->vbe_size
/ (64 * KiB
);
733 trace_vga_vbe_read(s
->vbe_index
, val
);
737 void vbe_ioport_write_index(void *opaque
, uint32_t addr
, uint32_t val
)
739 VGACommonState
*s
= opaque
;
743 void vbe_ioport_write_data(void *opaque
, uint32_t addr
, uint32_t val
)
745 VGACommonState
*s
= opaque
;
747 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
748 trace_vga_vbe_write(s
->vbe_index
, val
);
749 switch(s
->vbe_index
) {
750 case VBE_DISPI_INDEX_ID
:
751 if (val
== VBE_DISPI_ID0
||
752 val
== VBE_DISPI_ID1
||
753 val
== VBE_DISPI_ID2
||
754 val
== VBE_DISPI_ID3
||
755 val
== VBE_DISPI_ID4
) {
756 s
->vbe_regs
[s
->vbe_index
] = val
;
759 case VBE_DISPI_INDEX_XRES
:
760 case VBE_DISPI_INDEX_YRES
:
761 case VBE_DISPI_INDEX_BPP
:
762 case VBE_DISPI_INDEX_VIRT_WIDTH
:
763 case VBE_DISPI_INDEX_X_OFFSET
:
764 case VBE_DISPI_INDEX_Y_OFFSET
:
765 s
->vbe_regs
[s
->vbe_index
] = val
;
767 vbe_update_vgaregs(s
);
769 case VBE_DISPI_INDEX_BANK
:
770 val
&= s
->vbe_bank_mask
;
771 s
->vbe_regs
[s
->vbe_index
] = val
;
772 s
->bank_offset
= (val
<< 16);
773 vga_update_memory_access(s
);
775 case VBE_DISPI_INDEX_ENABLE
:
776 if ((val
& VBE_DISPI_ENABLED
) &&
777 !(s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
779 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] = 0;
780 s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
781 s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
782 s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] |= VBE_DISPI_ENABLED
;
784 vbe_update_vgaregs(s
);
786 /* clear the screen */
787 if (!(val
& VBE_DISPI_NOCLEARMEM
)) {
788 memset(s
->vram_ptr
, 0,
789 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] * s
->vbe_line_offset
);
794 s
->dac_8bit
= (val
& VBE_DISPI_8BIT_DAC
) > 0;
795 s
->vbe_regs
[s
->vbe_index
] = val
;
796 vga_update_memory_access(s
);
804 /* called for accesses between 0xa0000 and 0xc0000 */
805 uint32_t vga_mem_readb(VGACommonState
*s
, hwaddr addr
)
807 int memory_map_mode
, plane
;
810 /* convert to VGA memory offset */
811 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
813 switch(memory_map_mode
) {
819 addr
+= s
->bank_offset
;
834 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
835 /* chain 4 mode : simplest access */
836 assert(addr
< s
->vram_size
);
837 ret
= s
->vram_ptr
[addr
];
838 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
839 /* odd/even mode (aka text mode mapping) */
840 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
841 addr
= ((addr
& ~1) << 1) | plane
;
842 if (addr
>= s
->vram_size
) {
845 ret
= s
->vram_ptr
[addr
];
847 /* standard VGA latched access */
848 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
851 s
->latch
= ((uint32_t *)s
->vram_ptr
)[addr
];
853 if (!(s
->gr
[VGA_GFX_MODE
] & 0x08)) {
855 plane
= s
->gr
[VGA_GFX_PLANE_READ
];
856 ret
= GET_PLANE(s
->latch
, plane
);
859 ret
= (s
->latch
^ mask16
[s
->gr
[VGA_GFX_COMPARE_VALUE
]]) &
860 mask16
[s
->gr
[VGA_GFX_COMPARE_MASK
]];
869 /* called for accesses between 0xa0000 and 0xc0000 */
870 void vga_mem_writeb(VGACommonState
*s
, hwaddr addr
, uint32_t val
)
872 int memory_map_mode
, plane
, write_mode
, b
, func_select
, mask
;
873 uint32_t write_mask
, bit_mask
, set_mask
;
876 printf("vga: [0x" TARGET_FMT_plx
"] = 0x%02x\n", addr
, val
);
878 /* convert to VGA memory offset */
879 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
881 switch(memory_map_mode
) {
887 addr
+= s
->bank_offset
;
902 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
903 /* chain 4 mode : simplest access */
906 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
907 assert(addr
< s
->vram_size
);
908 s
->vram_ptr
[addr
] = val
;
910 printf("vga: chain4: [0x" TARGET_FMT_plx
"]\n", addr
);
912 s
->plane_updated
|= mask
; /* only used to detect font change */
913 memory_region_set_dirty(&s
->vram
, addr
, 1);
915 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
916 /* odd/even mode (aka text mode mapping) */
917 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
919 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
920 addr
= ((addr
& ~1) << 1) | plane
;
921 if (addr
>= s
->vram_size
) {
924 s
->vram_ptr
[addr
] = val
;
926 printf("vga: odd/even: [0x" TARGET_FMT_plx
"]\n", addr
);
928 s
->plane_updated
|= mask
; /* only used to detect font change */
929 memory_region_set_dirty(&s
->vram
, addr
, 1);
932 /* standard VGA latched access */
933 write_mode
= s
->gr
[VGA_GFX_MODE
] & 3;
938 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
939 val
= ((val
>> b
) | (val
<< (8 - b
))) & 0xff;
943 /* apply set/reset mask */
944 set_mask
= mask16
[s
->gr
[VGA_GFX_SR_ENABLE
]];
945 val
= (val
& ~set_mask
) |
946 (mask16
[s
->gr
[VGA_GFX_SR_VALUE
]] & set_mask
);
947 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
953 val
= mask16
[val
& 0x0f];
954 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
958 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
959 val
= (val
>> b
) | (val
<< (8 - b
));
961 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
] & val
;
962 val
= mask16
[s
->gr
[VGA_GFX_SR_VALUE
]];
966 /* apply logical operation */
967 func_select
= s
->gr
[VGA_GFX_DATA_ROTATE
] >> 3;
968 switch(func_select
) {
988 bit_mask
|= bit_mask
<< 8;
989 bit_mask
|= bit_mask
<< 16;
990 val
= (val
& bit_mask
) | (s
->latch
& ~bit_mask
);
993 /* mask data according to sr[2] */
994 mask
= sr(s
, VGA_SEQ_PLANE_WRITE
);
995 s
->plane_updated
|= mask
; /* only used to detect font change */
996 write_mask
= mask16
[mask
];
997 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
1000 ((uint32_t *)s
->vram_ptr
)[addr
] =
1001 (((uint32_t *)s
->vram_ptr
)[addr
] & ~write_mask
) |
1003 #ifdef DEBUG_VGA_MEM
1004 printf("vga: latch: [0x" TARGET_FMT_plx
"] mask=0x%08x val=0x%08x\n",
1005 addr
* 4, write_mask
, val
);
1007 memory_region_set_dirty(&s
->vram
, addr
<< 2, sizeof(uint32_t));
1011 typedef void vga_draw_line_func(VGACommonState
*s1
, uint8_t *d
,
1012 uint32_t srcaddr
, int width
);
1014 #include "vga-access.h"
1015 #include "vga-helpers.h"
1017 /* return true if the palette was modified */
1018 static int update_palette16(VGACommonState
*s
)
1021 uint32_t v
, col
, *palette
;
1024 palette
= s
->last_palette
;
1025 for(i
= 0; i
< 16; i
++) {
1027 if (s
->ar
[VGA_ATC_MODE
] & 0x80) {
1028 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xf) << 4) | (v
& 0xf);
1030 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xc) << 4) | (v
& 0x3f);
1033 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1034 c6_to_8(s
->palette
[v
+ 1]),
1035 c6_to_8(s
->palette
[v
+ 2]));
1036 if (col
!= palette
[i
]) {
1044 /* return true if the palette was modified */
1045 static int update_palette256(VGACommonState
*s
)
1048 uint32_t v
, col
, *palette
;
1051 palette
= s
->last_palette
;
1053 for(i
= 0; i
< 256; i
++) {
1055 col
= rgb_to_pixel32(s
->palette
[v
],
1059 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1060 c6_to_8(s
->palette
[v
+ 1]),
1061 c6_to_8(s
->palette
[v
+ 2]));
1063 if (col
!= palette
[i
]) {
1072 static void vga_get_offsets(VGACommonState
*s
,
1073 uint32_t *pline_offset
,
1074 uint32_t *pstart_addr
,
1075 uint32_t *pline_compare
)
1077 uint32_t start_addr
, line_offset
, line_compare
;
1079 if (vbe_enabled(s
)) {
1080 line_offset
= s
->vbe_line_offset
;
1081 start_addr
= s
->vbe_start_addr
;
1082 line_compare
= 65535;
1084 /* compute line_offset in bytes */
1085 line_offset
= s
->cr
[VGA_CRTC_OFFSET
];
1088 /* starting address */
1089 start_addr
= s
->cr
[VGA_CRTC_START_LO
] |
1090 (s
->cr
[VGA_CRTC_START_HI
] << 8);
1093 line_compare
= s
->cr
[VGA_CRTC_LINE_COMPARE
] |
1094 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x10) << 4) |
1095 ((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x40) << 3);
1097 *pline_offset
= line_offset
;
1098 *pstart_addr
= start_addr
;
1099 *pline_compare
= line_compare
;
1102 /* update start_addr and line_offset. Return TRUE if modified */
1103 static int update_basic_params(VGACommonState
*s
)
1106 uint32_t start_addr
, line_offset
, line_compare
;
1110 s
->get_offsets(s
, &line_offset
, &start_addr
, &line_compare
);
1112 if (line_offset
!= s
->line_offset
||
1113 start_addr
!= s
->start_addr
||
1114 line_compare
!= s
->line_compare
) {
1115 s
->line_offset
= line_offset
;
1116 s
->start_addr
= start_addr
;
1117 s
->line_compare
= line_compare
;
1124 static const uint8_t cursor_glyph
[32 * 4] = {
1125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1138 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1139 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1140 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1143 static void vga_get_text_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
,
1144 int *pcwidth
, int *pcheight
)
1146 int width
, cwidth
, height
, cheight
;
1148 /* total width & height */
1149 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1151 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1154 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1155 cwidth
= 16; /* NOTE: no 18 pixel wide */
1157 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1158 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1159 /* ugly hack for CGA 160x100x16 - explain me the logic */
1162 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1163 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1164 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1165 height
= (height
+ 1) / cheight
;
1171 *pcheight
= cheight
;
1182 static void vga_draw_text(VGACommonState
*s
, int full_update
)
1184 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1185 int cx
, cy
, cheight
, cw
, ch
, cattr
, height
, width
, ch_attr
;
1186 int cx_min
, cx_max
, linesize
, x_incr
, line
, line1
;
1187 uint32_t offset
, fgcol
, bgcol
, v
, cursor_offset
;
1188 uint8_t *d1
, *d
, *src
, *dest
, *cursor_ptr
;
1189 const uint8_t *font_ptr
, *font_base
[2];
1190 int dup9
, line_offset
;
1192 uint32_t *ch_attr_ptr
;
1193 int64_t now
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1195 /* compute font data address (in plane 2) */
1196 v
= sr(s
, VGA_SEQ_CHARACTER_MAP
);
1197 offset
= (((v
>> 4) & 1) | ((v
<< 1) & 6)) * 8192 * 4 + 2;
1198 if (offset
!= s
->font_offsets
[0]) {
1199 s
->font_offsets
[0] = offset
;
1202 font_base
[0] = s
->vram_ptr
+ offset
;
1204 offset
= (((v
>> 5) & 1) | ((v
>> 1) & 6)) * 8192 * 4 + 2;
1205 font_base
[1] = s
->vram_ptr
+ offset
;
1206 if (offset
!= s
->font_offsets
[1]) {
1207 s
->font_offsets
[1] = offset
;
1210 if (s
->plane_updated
& (1 << 2) || s
->has_chain4_alias
) {
1211 /* if the plane 2 was modified since the last display, it
1212 indicates the font may have been modified */
1213 s
->plane_updated
= 0;
1216 full_update
|= update_basic_params(s
);
1218 line_offset
= s
->line_offset
;
1220 vga_get_text_resolution(s
, &width
, &height
, &cw
, &cheight
);
1221 if ((height
* width
) <= 1) {
1222 /* better than nothing: exit if transient size is too small */
1225 if ((height
* width
) > CH_ATTR_SIZE
) {
1226 /* better than nothing: exit if transient size is too big */
1230 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1231 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
|| s
->last_depth
) {
1232 s
->last_scr_width
= width
* cw
;
1233 s
->last_scr_height
= height
* cheight
;
1234 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1235 surface
= qemu_console_surface(s
->con
);
1236 dpy_text_resize(s
->con
, width
, height
);
1238 s
->last_width
= width
;
1239 s
->last_height
= height
;
1240 s
->last_ch
= cheight
;
1244 full_update
|= update_palette16(s
);
1245 palette
= s
->last_palette
;
1246 x_incr
= cw
* surface_bytes_per_pixel(surface
);
1249 s
->full_update_text
= 1;
1251 if (s
->full_update_gfx
) {
1252 s
->full_update_gfx
= 0;
1256 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1257 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1258 if (cursor_offset
!= s
->cursor_offset
||
1259 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1260 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
) {
1261 /* if the cursor position changed, we update the old and new
1263 if (s
->cursor_offset
< CH_ATTR_SIZE
)
1264 s
->last_ch_attr
[s
->cursor_offset
] = -1;
1265 if (cursor_offset
< CH_ATTR_SIZE
)
1266 s
->last_ch_attr
[cursor_offset
] = -1;
1267 s
->cursor_offset
= cursor_offset
;
1268 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1269 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1271 cursor_ptr
= s
->vram_ptr
+ (s
->start_addr
+ cursor_offset
) * 4;
1272 if (now
>= s
->cursor_blink_time
) {
1273 s
->cursor_blink_time
= now
+ VGA_TEXT_CURSOR_PERIOD_MS
/ 2;
1274 s
->cursor_visible_phase
= !s
->cursor_visible_phase
;
1277 dest
= surface_data(surface
);
1278 linesize
= surface_stride(surface
);
1279 ch_attr_ptr
= s
->last_ch_attr
;
1281 offset
= s
->start_addr
* 4;
1282 for(cy
= 0; cy
< height
; cy
++) {
1284 src
= s
->vram_ptr
+ offset
;
1287 for(cx
= 0; cx
< width
; cx
++) {
1288 if (src
+ sizeof(uint16_t) > s
->vram_ptr
+ s
->vram_size
) {
1291 ch_attr
= *(uint16_t *)src
;
1292 if (full_update
|| ch_attr
!= *ch_attr_ptr
|| src
== cursor_ptr
) {
1297 *ch_attr_ptr
= ch_attr
;
1298 #ifdef HOST_WORDS_BIGENDIAN
1300 cattr
= ch_attr
& 0xff;
1302 ch
= ch_attr
& 0xff;
1303 cattr
= ch_attr
>> 8;
1305 font_ptr
= font_base
[(cattr
>> 3) & 1];
1306 font_ptr
+= 32 * 4 * ch
;
1307 bgcol
= palette
[cattr
>> 4];
1308 fgcol
= palette
[cattr
& 0x0f];
1310 vga_draw_glyph16(d1
, linesize
,
1311 font_ptr
, cheight
, fgcol
, bgcol
);
1312 } else if (cw
!= 9) {
1313 vga_draw_glyph8(d1
, linesize
,
1314 font_ptr
, cheight
, fgcol
, bgcol
);
1317 if (ch
>= 0xb0 && ch
<= 0xdf &&
1318 (s
->ar
[VGA_ATC_MODE
] & 0x04)) {
1321 vga_draw_glyph9(d1
, linesize
,
1322 font_ptr
, cheight
, fgcol
, bgcol
, dup9
);
1324 if (src
== cursor_ptr
&&
1325 !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20) &&
1326 s
->cursor_visible_phase
) {
1327 int line_start
, line_last
, h
;
1328 /* draw the cursor */
1329 line_start
= s
->cr
[VGA_CRTC_CURSOR_START
] & 0x1f;
1330 line_last
= s
->cr
[VGA_CRTC_CURSOR_END
] & 0x1f;
1331 /* XXX: check that */
1332 if (line_last
> cheight
- 1)
1333 line_last
= cheight
- 1;
1334 if (line_last
>= line_start
&& line_start
< cheight
) {
1335 h
= line_last
- line_start
+ 1;
1336 d
= d1
+ linesize
* line_start
;
1338 vga_draw_glyph16(d
, linesize
,
1339 cursor_glyph
, h
, fgcol
, bgcol
);
1340 } else if (cw
!= 9) {
1341 vga_draw_glyph8(d
, linesize
,
1342 cursor_glyph
, h
, fgcol
, bgcol
);
1344 vga_draw_glyph9(d
, linesize
,
1345 cursor_glyph
, h
, fgcol
, bgcol
, 1);
1355 dpy_gfx_update(s
->con
, cx_min
* cw
, cy
* cheight
,
1356 (cx_max
- cx_min
+ 1) * cw
, cheight
);
1358 dest
+= linesize
* cheight
;
1359 line1
= line
+ cheight
;
1360 offset
+= line_offset
;
1361 if (line
< s
->line_compare
&& line1
>= s
->line_compare
) {
1386 static vga_draw_line_func
* const vga_draw_line_table
[VGA_DRAW_LINE_NB
] = {
1403 static int vga_get_bpp(VGACommonState
*s
)
1407 if (vbe_enabled(s
)) {
1408 ret
= s
->vbe_regs
[VBE_DISPI_INDEX_BPP
];
1415 static void vga_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1419 if (vbe_enabled(s
)) {
1420 width
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
1421 height
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
1423 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1) * 8;
1424 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1425 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1426 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1427 height
= (height
+ 1);
1433 void vga_invalidate_scanlines(VGACommonState
*s
, int y1
, int y2
)
1436 if (y1
>= VGA_MAX_HEIGHT
)
1438 if (y2
>= VGA_MAX_HEIGHT
)
1439 y2
= VGA_MAX_HEIGHT
;
1440 for(y
= y1
; y
< y2
; y
++) {
1441 s
->invalidated_y_table
[y
>> 5] |= 1 << (y
& 0x1f);
1445 static bool vga_scanline_invalidated(VGACommonState
*s
, int y
)
1447 if (y
>= VGA_MAX_HEIGHT
) {
1450 return s
->invalidated_y_table
[y
>> 5] & (1 << (y
& 0x1f));
1453 void vga_dirty_log_start(VGACommonState
*s
)
1455 memory_region_set_log(&s
->vram
, true, DIRTY_MEMORY_VGA
);
1458 void vga_dirty_log_stop(VGACommonState
*s
)
1460 memory_region_set_log(&s
->vram
, false, DIRTY_MEMORY_VGA
);
1466 static void vga_draw_graphic(VGACommonState
*s
, int full_update
)
1468 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1469 int y1
, y
, update
, linesize
, y_start
, double_scan
, mask
, depth
;
1470 int width
, height
, shift_control
, bwidth
, bits
;
1471 ram_addr_t page0
, page1
, region_start
, region_end
;
1472 DirtyBitmapSnapshot
*snap
= NULL
;
1473 int disp_width
, multi_scan
, multi_run
;
1475 uint32_t v
, addr1
, addr
;
1476 vga_draw_line_func
*vga_draw_line
= NULL
;
1477 bool share_surface
, force_shadow
= false;
1478 pixman_format_code_t format
;
1479 #ifdef HOST_WORDS_BIGENDIAN
1480 bool byteswap
= !s
->big_endian_fb
;
1482 bool byteswap
= s
->big_endian_fb
;
1485 full_update
|= update_basic_params(s
);
1487 s
->get_resolution(s
, &width
, &height
);
1489 depth
= s
->get_bpp(s
);
1491 region_start
= (s
->start_addr
* 4);
1492 region_end
= region_start
+ (ram_addr_t
)s
->line_offset
* height
;
1493 region_end
+= width
* depth
/ 8; /* scanline length */
1494 region_end
-= s
->line_offset
;
1495 if (region_end
> s
->vbe_size
|| depth
== 0 || depth
== 15) {
1498 * - wraps around (can happen with cirrus vbe modes)
1499 * - depth == 0 (256 color palette video mode)
1502 * Take the safe and slow route:
1503 * - create a dirty bitmap snapshot for all vga memory.
1504 * - force shadowing (so all vga memory access goes
1505 * through vga_read_*() helpers).
1507 * Given this affects only vga features which are pretty much
1508 * unused by modern guests there should be no performance
1512 region_end
= s
->vbe_size
;
1513 force_shadow
= true;
1516 shift_control
= (s
->gr
[VGA_GFX_MODE
] >> 5) & 3;
1517 double_scan
= (s
->cr
[VGA_CRTC_MAX_SCAN
] >> 7);
1518 if (shift_control
!= 1) {
1519 multi_scan
= (((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1) << double_scan
)
1522 /* in CGA modes, multi_scan is ignored */
1523 /* XXX: is it correct ? */
1524 multi_scan
= double_scan
;
1526 multi_run
= multi_scan
;
1527 if (shift_control
!= s
->shift_control
||
1528 double_scan
!= s
->double_scan
) {
1530 s
->shift_control
= shift_control
;
1531 s
->double_scan
= double_scan
;
1534 if (shift_control
== 0) {
1535 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1538 } else if (shift_control
== 1) {
1539 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1545 * Check whether we can share the surface with the backend
1546 * or whether we need a shadow surface. We share native
1547 * endian surfaces for 15bpp and above and byteswapped
1548 * surfaces for 24bpp and above.
1550 format
= qemu_default_pixman_format(depth
, !byteswap
);
1552 share_surface
= dpy_gfx_check_format(s
->con
, format
)
1553 && !s
->force_shadow
&& !force_shadow
;
1555 share_surface
= false;
1558 if (s
->line_offset
!= s
->last_line_offset
||
1559 disp_width
!= s
->last_width
||
1560 height
!= s
->last_height
||
1561 s
->last_depth
!= depth
||
1562 s
->last_byteswap
!= byteswap
||
1563 share_surface
!= is_buffer_shared(surface
)) {
1564 /* display parameters changed -> need new display surface */
1565 s
->last_scr_width
= disp_width
;
1566 s
->last_scr_height
= height
;
1567 s
->last_width
= disp_width
;
1568 s
->last_height
= height
;
1569 s
->last_line_offset
= s
->line_offset
;
1570 s
->last_depth
= depth
;
1571 s
->last_byteswap
= byteswap
;
1574 if (surface_data(surface
) != s
->vram_ptr
+ (s
->start_addr
* 4)
1575 && is_buffer_shared(surface
)) {
1576 /* base address changed (page flip) -> shared display surfaces
1577 * must be updated with the new base address */
1582 if (share_surface
) {
1583 surface
= qemu_create_displaysurface_from(disp_width
,
1584 height
, format
, s
->line_offset
,
1585 s
->vram_ptr
+ (s
->start_addr
* 4));
1586 dpy_gfx_replace_surface(s
->con
, surface
);
1588 qemu_console_resize(s
->con
, disp_width
, height
);
1589 surface
= qemu_console_surface(s
->con
);
1593 if (shift_control
== 0) {
1594 full_update
|= update_palette16(s
);
1595 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1596 v
= VGA_DRAW_LINE4D2
;
1601 } else if (shift_control
== 1) {
1602 full_update
|= update_palette16(s
);
1603 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1604 v
= VGA_DRAW_LINE2D2
;
1610 switch(s
->get_bpp(s
)) {
1613 full_update
|= update_palette256(s
);
1614 v
= VGA_DRAW_LINE8D2
;
1618 full_update
|= update_palette256(s
);
1623 v
= s
->big_endian_fb
? VGA_DRAW_LINE15_BE
: VGA_DRAW_LINE15_LE
;
1627 v
= s
->big_endian_fb
? VGA_DRAW_LINE16_BE
: VGA_DRAW_LINE16_LE
;
1631 v
= s
->big_endian_fb
? VGA_DRAW_LINE24_BE
: VGA_DRAW_LINE24_LE
;
1635 v
= s
->big_endian_fb
? VGA_DRAW_LINE32_BE
: VGA_DRAW_LINE32_LE
;
1640 vga_draw_line
= vga_draw_line_table
[v
];
1642 if (!is_buffer_shared(surface
) && s
->cursor_invalidate
) {
1643 s
->cursor_invalidate(s
);
1647 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1648 width
, height
, v
, line_offset
, s
->cr
[9], s
->cr
[VGA_CRTC_MODE
],
1649 s
->line_compare
, sr(s
, VGA_SEQ_CLOCK_MODE
));
1651 addr1
= (s
->start_addr
* 4);
1652 bwidth
= DIV_ROUND_UP(width
* bits
, 8);
1654 d
= surface_data(surface
);
1655 linesize
= surface_stride(surface
);
1659 if (s
->line_compare
< height
) {
1660 /* split screen mode */
1663 snap
= memory_region_snapshot_and_clear_dirty(&s
->vram
, region_start
,
1664 region_end
- region_start
,
1668 for(y
= 0; y
< height
; y
++) {
1670 if (!(s
->cr
[VGA_CRTC_MODE
] & 1)) {
1672 /* CGA compatibility handling */
1673 shift
= 14 + ((s
->cr
[VGA_CRTC_MODE
] >> 6) & 1);
1674 addr
= (addr
& ~(1 << shift
)) | ((y1
& 1) << shift
);
1676 if (!(s
->cr
[VGA_CRTC_MODE
] & 2)) {
1677 addr
= (addr
& ~0x8000) | ((y1
& 2) << 14);
1679 page0
= addr
& s
->vbe_size_mask
;
1680 page1
= (addr
+ bwidth
- 1) & s
->vbe_size_mask
;
1683 } else if (page1
< page0
) {
1684 /* scanline wraps from end of video memory to the start */
1685 assert(force_shadow
);
1686 update
= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1687 page0
, s
->vbe_size
- page0
);
1688 update
|= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1691 update
= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1692 page0
, page1
- page0
);
1694 /* explicit invalidation for the hardware cursor (cirrus only) */
1695 update
|= vga_scanline_invalidated(s
, y
);
1699 if (!(is_buffer_shared(surface
))) {
1700 vga_draw_line(s
, d
, addr
, width
);
1701 if (s
->cursor_draw_line
)
1702 s
->cursor_draw_line(s
, d
, y
);
1706 /* flush to display */
1707 dpy_gfx_update(s
->con
, 0, y_start
,
1708 disp_width
, y
- y_start
);
1713 mask
= (s
->cr
[VGA_CRTC_MODE
] & 3) ^ 3;
1714 if ((y1
& mask
) == mask
)
1715 addr1
+= s
->line_offset
;
1717 multi_run
= multi_scan
;
1721 /* line compare acts on the displayed lines */
1722 if (y
== s
->line_compare
)
1727 /* flush to display */
1728 dpy_gfx_update(s
->con
, 0, y_start
,
1729 disp_width
, y
- y_start
);
1732 memset(s
->invalidated_y_table
, 0, sizeof(s
->invalidated_y_table
));
1735 static void vga_draw_blank(VGACommonState
*s
, int full_update
)
1737 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1743 if (s
->last_scr_width
<= 0 || s
->last_scr_height
<= 0)
1746 w
= s
->last_scr_width
* surface_bytes_per_pixel(surface
);
1747 d
= surface_data(surface
);
1748 for(i
= 0; i
< s
->last_scr_height
; i
++) {
1750 d
+= surface_stride(surface
);
1752 dpy_gfx_update_full(s
->con
);
1755 #define GMODE_TEXT 0
1756 #define GMODE_GRAPH 1
1757 #define GMODE_BLANK 2
1759 static void vga_update_display(void *opaque
)
1761 VGACommonState
*s
= opaque
;
1762 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1763 int full_update
, graphic_mode
;
1765 qemu_flush_coalesced_mmio_buffer();
1767 if (surface_bits_per_pixel(surface
) == 0) {
1771 if (!(s
->ar_index
& 0x20)) {
1772 graphic_mode
= GMODE_BLANK
;
1774 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1776 if (graphic_mode
!= s
->graphic_mode
) {
1777 s
->graphic_mode
= graphic_mode
;
1778 s
->cursor_blink_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1781 switch(graphic_mode
) {
1783 vga_draw_text(s
, full_update
);
1786 vga_draw_graphic(s
, full_update
);
1790 vga_draw_blank(s
, full_update
);
1796 /* force a full display refresh */
1797 static void vga_invalidate_display(void *opaque
)
1799 VGACommonState
*s
= opaque
;
1802 s
->last_height
= -1;
1805 void vga_common_reset(VGACommonState
*s
)
1808 memset(s
->sr
, '\0', sizeof(s
->sr
));
1809 memset(s
->sr_vbe
, '\0', sizeof(s
->sr_vbe
));
1811 memset(s
->gr
, '\0', sizeof(s
->gr
));
1813 memset(s
->ar
, '\0', sizeof(s
->ar
));
1814 s
->ar_flip_flop
= 0;
1816 memset(s
->cr
, '\0', sizeof(s
->cr
));
1822 s
->dac_sub_index
= 0;
1823 s
->dac_read_index
= 0;
1824 s
->dac_write_index
= 0;
1825 memset(s
->dac_cache
, '\0', sizeof(s
->dac_cache
));
1827 memset(s
->palette
, '\0', sizeof(s
->palette
));
1830 memset(s
->vbe_regs
, '\0', sizeof(s
->vbe_regs
));
1831 s
->vbe_regs
[VBE_DISPI_INDEX_ID
] = VBE_DISPI_ID5
;
1832 s
->vbe_start_addr
= 0;
1833 s
->vbe_line_offset
= 0;
1834 s
->vbe_bank_mask
= (s
->vram_size
>> 16) - 1;
1835 memset(s
->font_offsets
, '\0', sizeof(s
->font_offsets
));
1836 s
->graphic_mode
= -1; /* force full update */
1837 s
->shift_control
= 0;
1840 s
->line_compare
= 0;
1842 s
->plane_updated
= 0;
1847 s
->last_scr_width
= 0;
1848 s
->last_scr_height
= 0;
1849 s
->cursor_start
= 0;
1851 s
->cursor_offset
= 0;
1852 s
->big_endian_fb
= s
->default_endian_fb
;
1853 memset(s
->invalidated_y_table
, '\0', sizeof(s
->invalidated_y_table
));
1854 memset(s
->last_palette
, '\0', sizeof(s
->last_palette
));
1855 memset(s
->last_ch_attr
, '\0', sizeof(s
->last_ch_attr
));
1856 switch (vga_retrace_method
) {
1857 case VGA_RETRACE_DUMB
:
1859 case VGA_RETRACE_PRECISE
:
1860 memset(&s
->retrace_info
, 0, sizeof (s
->retrace_info
));
1863 vga_update_memory_access(s
);
1866 static void vga_reset(void *opaque
)
1868 VGACommonState
*s
= opaque
;
1869 vga_common_reset(s
);
1872 #define TEXTMODE_X(x) ((x) % width)
1873 #define TEXTMODE_Y(x) ((x) / width)
1874 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1875 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1876 /* relay text rendering to the display driver
1877 * instead of doing a full vga_update_display() */
1878 static void vga_update_text(void *opaque
, console_ch_t
*chardata
)
1880 VGACommonState
*s
= opaque
;
1881 int graphic_mode
, i
, cursor_offset
, cursor_visible
;
1882 int cw
, cheight
, width
, height
, size
, c_min
, c_max
;
1884 console_ch_t
*dst
, val
;
1885 char msg_buffer
[80];
1886 int full_update
= 0;
1888 qemu_flush_coalesced_mmio_buffer();
1890 if (!(s
->ar_index
& 0x20)) {
1891 graphic_mode
= GMODE_BLANK
;
1893 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1895 if (graphic_mode
!= s
->graphic_mode
) {
1896 s
->graphic_mode
= graphic_mode
;
1899 if (s
->last_width
== -1) {
1904 switch (graphic_mode
) {
1906 /* TODO: update palette */
1907 full_update
|= update_basic_params(s
);
1909 /* total width & height */
1910 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1912 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1915 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1916 cw
= 16; /* NOTE: no 18 pixel wide */
1918 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1919 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1920 /* ugly hack for CGA 160x100x16 - explain me the logic */
1923 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1924 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1925 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1926 height
= (height
+ 1) / cheight
;
1929 size
= (height
* width
);
1930 if (size
> CH_ATTR_SIZE
) {
1934 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Text mode",
1939 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1940 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
) {
1941 s
->last_scr_width
= width
* cw
;
1942 s
->last_scr_height
= height
* cheight
;
1943 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1944 dpy_text_resize(s
->con
, width
, height
);
1946 s
->last_width
= width
;
1947 s
->last_height
= height
;
1948 s
->last_ch
= cheight
;
1954 s
->full_update_gfx
= 1;
1956 if (s
->full_update_text
) {
1957 s
->full_update_text
= 0;
1961 /* Update "hardware" cursor */
1962 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1963 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1964 if (cursor_offset
!= s
->cursor_offset
||
1965 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1966 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
|| full_update
) {
1967 cursor_visible
= !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20);
1968 if (cursor_visible
&& cursor_offset
< size
&& cursor_offset
>= 0)
1969 dpy_text_cursor(s
->con
,
1970 TEXTMODE_X(cursor_offset
),
1971 TEXTMODE_Y(cursor_offset
));
1973 dpy_text_cursor(s
->con
, -1, -1);
1974 s
->cursor_offset
= cursor_offset
;
1975 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1976 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1979 src
= (uint32_t *) s
->vram_ptr
+ s
->start_addr
;
1983 for (i
= 0; i
< size
; src
++, dst
++, i
++)
1984 console_write_ch(dst
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1986 dpy_text_update(s
->con
, 0, 0, width
, height
);
1990 for (i
= 0; i
< size
; src
++, dst
++, i
++) {
1991 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1999 for (; i
< size
; src
++, dst
++, i
++) {
2000 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
2007 if (c_min
<= c_max
) {
2008 i
= TEXTMODE_Y(c_min
);
2009 dpy_text_update(s
->con
, 0, i
, width
, TEXTMODE_Y(c_max
) - i
+ 1);
2018 s
->get_resolution(s
, &width
, &height
);
2019 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Graphic mode",
2027 snprintf(msg_buffer
, sizeof(msg_buffer
), "VGA Blank mode");
2031 /* Display a message */
2033 s
->last_height
= height
= 3;
2034 dpy_text_cursor(s
->con
, -1, -1);
2035 dpy_text_resize(s
->con
, s
->last_width
, height
);
2037 for (dst
= chardata
, i
= 0; i
< s
->last_width
* height
; i
++)
2038 console_write_ch(dst
++, ' ');
2040 size
= strlen(msg_buffer
);
2041 width
= (s
->last_width
- size
) / 2;
2042 dst
= chardata
+ s
->last_width
+ width
;
2043 for (i
= 0; i
< size
; i
++)
2044 console_write_ch(dst
++, ATTR2CHTYPE(msg_buffer
[i
], QEMU_COLOR_BLUE
,
2045 QEMU_COLOR_BLACK
, 1));
2047 dpy_text_update(s
->con
, 0, 0, s
->last_width
, height
);
2050 static uint64_t vga_mem_read(void *opaque
, hwaddr addr
,
2053 VGACommonState
*s
= opaque
;
2055 return vga_mem_readb(s
, addr
);
2058 static void vga_mem_write(void *opaque
, hwaddr addr
,
2059 uint64_t data
, unsigned size
)
2061 VGACommonState
*s
= opaque
;
2063 vga_mem_writeb(s
, addr
, data
);
2066 const MemoryRegionOps vga_mem_ops
= {
2067 .read
= vga_mem_read
,
2068 .write
= vga_mem_write
,
2069 .endianness
= DEVICE_LITTLE_ENDIAN
,
2071 .min_access_size
= 1,
2072 .max_access_size
= 1,
2076 static int vga_common_post_load(void *opaque
, int version_id
)
2078 VGACommonState
*s
= opaque
;
2081 s
->graphic_mode
= -1;
2082 vbe_update_vgaregs(s
);
2083 vga_update_memory_access(s
);
2087 static bool vga_endian_state_needed(void *opaque
)
2089 VGACommonState
*s
= opaque
;
2092 * Only send the endian state if it's different from the
2093 * default one, thus ensuring backward compatibility for
2094 * migration of the common case
2096 return s
->default_endian_fb
!= s
->big_endian_fb
;
2099 static const VMStateDescription vmstate_vga_endian
= {
2100 .name
= "vga.endian",
2102 .minimum_version_id
= 1,
2103 .needed
= vga_endian_state_needed
,
2104 .fields
= (VMStateField
[]) {
2105 VMSTATE_BOOL(big_endian_fb
, VGACommonState
),
2106 VMSTATE_END_OF_LIST()
2110 const VMStateDescription vmstate_vga_common
= {
2113 .minimum_version_id
= 2,
2114 .post_load
= vga_common_post_load
,
2115 .fields
= (VMStateField
[]) {
2116 VMSTATE_UINT32(latch
, VGACommonState
),
2117 VMSTATE_UINT8(sr_index
, VGACommonState
),
2118 VMSTATE_PARTIAL_BUFFER(sr
, VGACommonState
, 8),
2119 VMSTATE_UINT8(gr_index
, VGACommonState
),
2120 VMSTATE_PARTIAL_BUFFER(gr
, VGACommonState
, 16),
2121 VMSTATE_UINT8(ar_index
, VGACommonState
),
2122 VMSTATE_BUFFER(ar
, VGACommonState
),
2123 VMSTATE_INT32(ar_flip_flop
, VGACommonState
),
2124 VMSTATE_UINT8(cr_index
, VGACommonState
),
2125 VMSTATE_BUFFER(cr
, VGACommonState
),
2126 VMSTATE_UINT8(msr
, VGACommonState
),
2127 VMSTATE_UINT8(fcr
, VGACommonState
),
2128 VMSTATE_UINT8(st00
, VGACommonState
),
2129 VMSTATE_UINT8(st01
, VGACommonState
),
2131 VMSTATE_UINT8(dac_state
, VGACommonState
),
2132 VMSTATE_UINT8(dac_sub_index
, VGACommonState
),
2133 VMSTATE_UINT8(dac_read_index
, VGACommonState
),
2134 VMSTATE_UINT8(dac_write_index
, VGACommonState
),
2135 VMSTATE_BUFFER(dac_cache
, VGACommonState
),
2136 VMSTATE_BUFFER(palette
, VGACommonState
),
2138 VMSTATE_INT32(bank_offset
, VGACommonState
),
2139 VMSTATE_UINT8_EQUAL(is_vbe_vmstate
, VGACommonState
, NULL
),
2140 VMSTATE_UINT16(vbe_index
, VGACommonState
),
2141 VMSTATE_UINT16_ARRAY(vbe_regs
, VGACommonState
, VBE_DISPI_INDEX_NB
),
2142 VMSTATE_UINT32(vbe_start_addr
, VGACommonState
),
2143 VMSTATE_UINT32(vbe_line_offset
, VGACommonState
),
2144 VMSTATE_UINT32(vbe_bank_mask
, VGACommonState
),
2145 VMSTATE_END_OF_LIST()
2147 .subsections
= (const VMStateDescription
*[]) {
2148 &vmstate_vga_endian
,
2153 static const GraphicHwOps vga_ops
= {
2154 .invalidate
= vga_invalidate_display
,
2155 .gfx_update
= vga_update_display
,
2156 .text_update
= vga_update_text
,
2159 static inline uint32_t uint_clamp(uint32_t val
, uint32_t vmin
, uint32_t vmax
)
2170 void vga_common_init(VGACommonState
*s
, Object
*obj
)
2174 for(i
= 0;i
< 256; i
++) {
2176 for(j
= 0; j
< 8; j
++) {
2177 v
|= ((i
>> j
) & 1) << (j
* 4);
2182 for(j
= 0; j
< 4; j
++) {
2183 v
|= ((i
>> (2 * j
)) & 3) << (j
* 4);
2187 for(i
= 0; i
< 16; i
++) {
2189 for(j
= 0; j
< 4; j
++) {
2192 v
|= b
<< (2 * j
+ 1);
2197 s
->vram_size_mb
= uint_clamp(s
->vram_size_mb
, 1, 512);
2198 s
->vram_size_mb
= pow2ceil(s
->vram_size_mb
);
2199 s
->vram_size
= s
->vram_size_mb
* MiB
;
2202 s
->vbe_size
= s
->vram_size
;
2204 s
->vbe_size_mask
= s
->vbe_size
- 1;
2206 s
->is_vbe_vmstate
= 1;
2207 memory_region_init_ram_nomigrate(&s
->vram
, obj
, "vga.vram", s
->vram_size
,
2209 vmstate_register_ram(&s
->vram
, s
->global_vmstate
? NULL
: DEVICE(obj
));
2210 xen_register_framebuffer(&s
->vram
);
2211 s
->vram_ptr
= memory_region_get_ram_ptr(&s
->vram
);
2212 s
->get_bpp
= vga_get_bpp
;
2213 s
->get_offsets
= vga_get_offsets
;
2214 s
->get_resolution
= vga_get_resolution
;
2215 s
->hw_ops
= &vga_ops
;
2216 switch (vga_retrace_method
) {
2217 case VGA_RETRACE_DUMB
:
2218 s
->retrace
= vga_dumb_retrace
;
2219 s
->update_retrace_info
= vga_dumb_update_retrace_info
;
2222 case VGA_RETRACE_PRECISE
:
2223 s
->retrace
= vga_precise_retrace
;
2224 s
->update_retrace_info
= vga_precise_update_retrace_info
;
2229 * Set default fb endian based on target, could probably be turned
2230 * into a device attribute set by the machine/platform to remove
2231 * all target endian dependencies from this file.
2233 #ifdef TARGET_WORDS_BIGENDIAN
2234 s
->default_endian_fb
= true;
2236 s
->default_endian_fb
= false;
2238 vga_dirty_log_start(s
);
2241 static const MemoryRegionPortio vga_portio_list
[] = {
2242 { 0x04, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3b4 */
2243 { 0x0a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3ba */
2244 { 0x10, 16, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3c0 */
2245 { 0x24, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3d4 */
2246 { 0x2a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3da */
2247 PORTIO_END_OF_LIST(),
2250 static const MemoryRegionPortio vbe_portio_list
[] = {
2251 { 0, 1, 2, .read
= vbe_ioport_read_index
, .write
= vbe_ioport_write_index
},
2253 { 1, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2255 { 2, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2256 PORTIO_END_OF_LIST(),
2259 /* Used by both ISA and PCI */
2260 MemoryRegion
*vga_init_io(VGACommonState
*s
, Object
*obj
,
2261 const MemoryRegionPortio
**vga_ports
,
2262 const MemoryRegionPortio
**vbe_ports
)
2264 MemoryRegion
*vga_mem
;
2266 *vga_ports
= vga_portio_list
;
2267 *vbe_ports
= vbe_portio_list
;
2269 vga_mem
= g_malloc(sizeof(*vga_mem
));
2270 memory_region_init_io(vga_mem
, obj
, &vga_mem_ops
, s
,
2271 "vga-lowmem", 0x20000);
2272 memory_region_set_flush_coalesced(vga_mem
);
2277 void vga_init(VGACommonState
*s
, Object
*obj
, MemoryRegion
*address_space
,
2278 MemoryRegion
*address_space_io
, bool init_vga_ports
)
2280 MemoryRegion
*vga_io_memory
;
2281 const MemoryRegionPortio
*vga_ports
, *vbe_ports
;
2283 qemu_register_reset(vga_reset
, s
);
2287 s
->legacy_address_space
= address_space
;
2289 vga_io_memory
= vga_init_io(s
, obj
, &vga_ports
, &vbe_ports
);
2290 memory_region_add_subregion_overlap(address_space
,
2294 memory_region_set_coalescing(vga_io_memory
);
2295 if (init_vga_ports
) {
2296 portio_list_init(&s
->vga_port_list
, obj
, vga_ports
, s
, "vga");
2297 portio_list_set_flush_coalesced(&s
->vga_port_list
);
2298 portio_list_add(&s
->vga_port_list
, address_space_io
, 0x3b0);
2301 portio_list_init(&s
->vbe_port_list
, obj
, vbe_ports
, s
, "vbe");
2302 portio_list_add(&s
->vbe_port_list
, address_space_io
, 0x1ce);