| blob | 73d5d1b045bfa48c368022396261e4ccdf756134 |
1 #
2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 #
4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5 # Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6 #
7 # This program is free software; you can redistribute it and/or modify it
8 # under the terms and conditions of the GNU General Public License,
9 # version 2 or later, as published by the Free Software Foundation.
10 #
11 # This program is distributed in the hope it will be useful, but WITHOUT
12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 # more details.
15 #
16 # You should have received a copy of the GNU General Public License along with
17 # this program. If not, see <http://www.gnu.org/licenses/>.
19 # Fields:
20 %rs3 27:5
21 %rs2 20:5
22 %rs1 15:5
23 %rd 7:5
24 %sh5 20:5
25 %sh6 20:6
27 %sh7 20:7
28 %csr 20:12
29 %rm 12:3
30 %nf 29:3 !function=ex_plus_1
32 # immediates:
33 %imm_i 20:s12
34 %imm_s 25:s7 7:5
35 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
36 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
37 %imm_u 12:s20 !function=ex_shift_12
38 %imm_bs 30:2 !function=ex_shift_3
39 %imm_rnum 20:4
41 # Argument sets:
42 &empty
43 &b imm rs2 rs1
44 &i imm rs1 rd
45 &j imm rd
46 &r rd rs1 rs2
47 &r2 rd rs1
48 &r2_s rs1 rs2
49 &s imm rs1 rs2
50 &u imm rd
51 &shift shamt rs1 rd
52 &atomic aq rl rs2 rs1 rd
53 &rmrr vm rd rs1 rs2
54 &rmr vm rd rs2
55 &r2nfvm vm rd rs1 nf
56 &rnfvm vm rd rs1 rs2 nf
57 &k_aes shamt rs2 rs1 rd
59 # Formats 32:
60 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
61 @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
62 @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
63 @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
64 @u .................... ..... ....... &u imm=%imm_u %rd
65 @j .................... ..... ....... &j imm=%imm_j %rd
67 @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
68 @csr ............ ..... ... ..... ....... %csr %rs1 %rd
70 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
71 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
73 @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
74 @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
75 @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
76 @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
77 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
78 @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
79 @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
80 @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
81 @r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
82 @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
83 @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
84 @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
85 @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
86 @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
87 @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
89 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
90 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
92 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
93 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
95 @k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
96 @i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
98 # Formats 64:
99 @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
101 # Formats 128:
102 @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
104 # *** Privileged Instructions ***
105 ecall 000000000000 00000 000 00000 1110011
106 ebreak 000000000001 00000 000 00000 1110011
107 uret 0000000 00010 00000 000 00000 1110011
108 sret 0001000 00010 00000 000 00000 1110011
109 mret 0011000 00010 00000 000 00000 1110011
110 wfi 0001000 00101 00000 000 00000 1110011
111 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
112 sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
114 # *** RV32I Base Instruction Set ***
115 lui .................... ..... 0110111 @u
116 auipc .................... ..... 0010111 @u
117 jal .................... ..... 1101111 @j
118 jalr ............ ..... 000 ..... 1100111 @i
119 beq ....... ..... ..... 000 ..... 1100011 @b
120 bne ....... ..... ..... 001 ..... 1100011 @b
121 blt ....... ..... ..... 100 ..... 1100011 @b
122 bge ....... ..... ..... 101 ..... 1100011 @b
123 bltu ....... ..... ..... 110 ..... 1100011 @b
124 bgeu ....... ..... ..... 111 ..... 1100011 @b
125 lb ............ ..... 000 ..... 0000011 @i
126 lh ............ ..... 001 ..... 0000011 @i
127 lw ............ ..... 010 ..... 0000011 @i
128 lbu ............ ..... 100 ..... 0000011 @i
129 lhu ............ ..... 101 ..... 0000011 @i
130 sb ....... ..... ..... 000 ..... 0100011 @s
131 sh ....... ..... ..... 001 ..... 0100011 @s
132 sw ....... ..... ..... 010 ..... 0100011 @s
133 addi ............ ..... 000 ..... 0010011 @i
134 slti ............ ..... 010 ..... 0010011 @i
135 sltiu ............ ..... 011 ..... 0010011 @i
136 xori ............ ..... 100 ..... 0010011 @i
137 # cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
138 ori ............ ..... 110 ..... 0010011 @i
139 andi ............ ..... 111 ..... 0010011 @i
140 slli 00000. ...... ..... 001 ..... 0010011 @sh
141 srli 00000. ...... ..... 101 ..... 0010011 @sh
142 srai 01000. ...... ..... 101 ..... 0010011 @sh
143 add 0000000 ..... ..... 000 ..... 0110011 @r
144 sub 0100000 ..... ..... 000 ..... 0110011 @r
145 sll 0000000 ..... ..... 001 ..... 0110011 @r
146 slt 0000000 ..... ..... 010 ..... 0110011 @r
147 sltu 0000000 ..... ..... 011 ..... 0110011 @r
148 xor 0000000 ..... ..... 100 ..... 0110011 @r
149 srl 0000000 ..... ..... 101 ..... 0110011 @r
150 sra 0100000 ..... ..... 101 ..... 0110011 @r
151 or 0000000 ..... ..... 110 ..... 0110011 @r
152 and 0000000 ..... ..... 111 ..... 0110011 @r
154 {
155 pause 0000 0001 0000 00000 000 00000 0001111
156 fence ---- pred:4 succ:4 ----- 000 ----- 0001111
157 }
159 fence_i ---- ---- ---- ----- 001 ----- 0001111
160 csrrw ............ ..... 001 ..... 1110011 @csr
161 csrrs ............ ..... 010 ..... 1110011 @csr
162 csrrc ............ ..... 011 ..... 1110011 @csr
163 csrrwi ............ ..... 101 ..... 1110011 @csr
164 csrrsi ............ ..... 110 ..... 1110011 @csr
165 csrrci ............ ..... 111 ..... 1110011 @csr
167 # *** RV64I Base Instruction Set (in addition to RV32I) ***
168 lwu ............ ..... 110 ..... 0000011 @i
169 ld ............ ..... 011 ..... 0000011 @i
170 sd ....... ..... ..... 011 ..... 0100011 @s
171 addiw ............ ..... 000 ..... 0011011 @i
172 slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
173 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
174 sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
175 addw 0000000 ..... ..... 000 ..... 0111011 @r
176 subw 0100000 ..... ..... 000 ..... 0111011 @r
177 sllw 0000000 ..... ..... 001 ..... 0111011 @r
178 srlw 0000000 ..... ..... 101 ..... 0111011 @r
179 sraw 0100000 ..... ..... 101 ..... 0111011 @r
181 # *** RV128I Base Instruction Set (in addition to RV64I) ***
182 ldu ............ ..... 111 ..... 0000011 @i
183 {
184 [
185 # *** RV32 Zicbom Standard Extension ***
186 cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm
187 cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm
188 cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
190 # *** RV32 Zicboz Standard Extension ***
191 cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm
192 ]
194 # *** RVI128 lq ***
195 lq ............ ..... 010 ..... 0001111 @i
196 }
197 sq ............ ..... 100 ..... 0100011 @s
198 addid ............ ..... 000 ..... 1011011 @i
199 sllid 000000 ...... ..... 001 ..... 1011011 @sh6
200 srlid 000000 ...... ..... 101 ..... 1011011 @sh6
201 sraid 010000 ...... ..... 101 ..... 1011011 @sh6
202 addd 0000000 ..... ..... 000 ..... 1111011 @r
203 subd 0100000 ..... ..... 000 ..... 1111011 @r
204 slld 0000000 ..... ..... 001 ..... 1111011 @r
205 srld 0000000 ..... ..... 101 ..... 1111011 @r
206 srad 0100000 ..... ..... 101 ..... 1111011 @r
208 # *** RV32M Standard Extension ***
209 mul 0000001 ..... ..... 000 ..... 0110011 @r
210 mulh 0000001 ..... ..... 001 ..... 0110011 @r
211 mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
212 mulhu 0000001 ..... ..... 011 ..... 0110011 @r
213 div 0000001 ..... ..... 100 ..... 0110011 @r
214 divu 0000001 ..... ..... 101 ..... 0110011 @r
215 rem 0000001 ..... ..... 110 ..... 0110011 @r
216 remu 0000001 ..... ..... 111 ..... 0110011 @r
218 # *** RV64M Standard Extension (in addition to RV32M) ***
219 mulw 0000001 ..... ..... 000 ..... 0111011 @r
220 divw 0000001 ..... ..... 100 ..... 0111011 @r
221 divuw 0000001 ..... ..... 101 ..... 0111011 @r
222 remw 0000001 ..... ..... 110 ..... 0111011 @r
223 remuw 0000001 ..... ..... 111 ..... 0111011 @r
225 # *** RV128M Standard Extension (in addition to RV64M) ***
226 muld 0000001 ..... ..... 000 ..... 1111011 @r
227 divd 0000001 ..... ..... 100 ..... 1111011 @r
228 divud 0000001 ..... ..... 101 ..... 1111011 @r
229 remd 0000001 ..... ..... 110 ..... 1111011 @r
230 remud 0000001 ..... ..... 111 ..... 1111011 @r
232 # *** RV32A Standard Extension ***
233 lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
234 sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
235 amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
236 amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
237 amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
238 amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
239 amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
240 amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
241 amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
242 amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
243 amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
245 # *** RV64A Standard Extension (in addition to RV32A) ***
246 lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
247 sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
248 amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
249 amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
250 amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
251 amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
252 amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
253 amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
254 amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
255 amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
256 amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
258 # *** RV32F Standard Extension ***
259 flw ............ ..... 010 ..... 0000111 @i
260 fsw ....... ..... ..... 010 ..... 0100111 @s
261 fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
262 fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
263 fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
264 fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
265 fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
266 fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
267 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
268 fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
269 fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
270 fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
271 fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
272 fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
273 fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
274 fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
275 fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
276 fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
277 fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
278 feq_s 1010000 ..... ..... 010 ..... 1010011 @r
279 flt_s 1010000 ..... ..... 001 ..... 1010011 @r
280 fle_s 1010000 ..... ..... 000 ..... 1010011 @r
281 fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
282 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
283 fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
284 fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
286 # *** RV64F Standard Extension (in addition to RV32F) ***
287 fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
288 fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
289 fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
290 fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
292 # *** RV32D Standard Extension ***
293 fld ............ ..... 011 ..... 0000111 @i
294 fsd ....... ..... ..... 011 ..... 0100111 @s
295 fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
296 fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
297 fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
298 fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
299 fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
300 fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
301 fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
302 fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
303 fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
304 fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
305 fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
306 fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
307 fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
308 fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
309 fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
310 fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
311 feq_d 1010001 ..... ..... 010 ..... 1010011 @r
312 flt_d 1010001 ..... ..... 001 ..... 1010011 @r
313 fle_d 1010001 ..... ..... 000 ..... 1010011 @r
314 fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
315 fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
316 fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
317 fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
318 fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
320 # *** RV64D Standard Extension (in addition to RV32D) ***
321 fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
322 fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
323 fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
324 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
325 fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
326 fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
328 # *** RV32H Base Instruction Set ***
329 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
330 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
331 hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
332 hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
333 hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
334 hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
335 hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
336 hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
337 hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
338 hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
339 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
340 hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
342 # *** RV64H Base Instruction Set ***
343 hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
344 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
345 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
347 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
348 # Vector unit-stride load/store insns.
349 vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
350 vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
351 vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
352 vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
353 vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
354 vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
355 vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
356 vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
358 # Vector unit-stride mask load/store insns.
359 vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
360 vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
362 # Vector strided insns.
363 vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
364 vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
365 vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
366 vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
367 vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
368 vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
369 vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
370 vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
372 # Vector ordered-indexed and unordered-indexed load insns.
373 vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
374 vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
375 vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
376 vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
378 # Vector ordered-indexed and unordered-indexed store insns.
379 vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
380 vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
381 vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
382 vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
384 # Vector unit-stride fault-only-first load insns.
385 vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
386 vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
387 vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
388 vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
390 # Vector whole register insns
391 vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
392 vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
393 vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
394 vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
395 vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
396 vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
397 vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
398 vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
399 vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
400 vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
401 vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
402 vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
403 vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
404 vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
405 vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
406 vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
407 vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
408 vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
409 vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
410 vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
412 # *** new major opcode OP-V ***
413 vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
414 vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
415 vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
416 vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
417 vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
418 vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
419 vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
420 vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
421 vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
422 vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
423 vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
424 vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
425 vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
426 vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
427 vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
428 vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
429 vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
430 vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
431 vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
432 vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
433 vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
434 vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
435 vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
436 vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
437 vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
438 vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
439 vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
440 vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
441 vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
442 vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
443 vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
444 vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
445 vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
446 vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
447 vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
448 vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
449 vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
450 vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
451 vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
452 vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
453 vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
454 vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
455 vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
456 vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
457 vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
458 vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
459 vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
460 vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
461 vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
462 vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
463 vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
464 vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
465 vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
466 vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
467 vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
468 vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
469 vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
470 vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
471 vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
472 vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
473 vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
474 vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
475 vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
476 vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
477 vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
478 vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
479 vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
480 vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
481 vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
482 vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
483 vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
484 vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
485 vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
486 vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
487 vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
488 vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
489 vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
490 vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
491 vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
492 vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
493 vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
494 vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
495 vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
496 vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
497 vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
498 vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
499 vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
500 vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
501 vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
502 vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
503 vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
504 vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
505 vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
506 vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
507 vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
508 vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
509 vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
510 vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
511 vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
512 vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
513 vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
514 vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
515 vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
516 vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
517 vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
518 vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
519 vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
520 vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
521 vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
522 vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
523 vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
524 vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
525 vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
526 vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
527 vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
528 vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
529 vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
530 vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
531 vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
532 vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
533 vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
534 vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
535 vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
536 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
537 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
538 vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
539 vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
540 vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
541 vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
542 vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
543 vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
544 vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
545 vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
546 vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
547 vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
548 vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
549 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
550 vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
551 vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
552 vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
553 vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
554 vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
555 vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
556 vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
557 vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
558 vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
559 vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
560 vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
561 vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
562 vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
563 vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
564 vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
565 vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
566 vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
567 vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
568 vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
569 vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
570 vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
571 vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
572 vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
573 vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
574 vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
575 vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
576 vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
577 vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
578 vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
579 vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
580 vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
581 vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
582 vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
583 vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
584 vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
585 vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
586 vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
587 vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
588 vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
589 vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
590 vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
591 vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
592 vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
593 vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
594 vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
595 vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
596 vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
597 vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
598 vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
599 vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
600 vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
601 vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
602 vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
603 vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
604 vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
605 vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
606 vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
607 vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
608 vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
609 vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
610 vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
611 vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
612 vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
613 vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
614 vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
615 vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
616 vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
617 vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
618 vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
619 vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
620 vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
621 vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
622 vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
623 vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
624 vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
625 vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
626 vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
627 vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
628 vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
629 vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
630 vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
631 vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
632 vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
633 vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
634 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
635 vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
636 vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
637 vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
638 vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
639 vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
640 vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
641 vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
642 vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
643 vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
644 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
646 vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
647 vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
648 vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
649 vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
650 vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
651 vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
653 vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
654 vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
655 vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
656 vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
657 vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
658 vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
659 vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
661 vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
662 vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
663 vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
664 vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
665 vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
666 vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
667 vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
668 vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
670 vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
671 vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
672 vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
673 vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
674 vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
675 vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
676 vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
677 vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
678 vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
679 vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
680 # Vector ordered and unordered reduction sum
681 vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
682 vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
683 vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
684 vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
685 # Vector widening ordered and unordered float reduction sum
686 vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
687 vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
688 vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
689 vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
690 vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r
691 vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
692 vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
693 vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
694 vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r
695 vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
696 vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
697 vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
698 vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
699 vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
700 vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
701 viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
702 vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
703 vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
704 vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
705 vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
706 vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
707 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
708 vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
709 vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
710 vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
711 vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
712 vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
713 vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
714 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
715 vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
716 vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
717 vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
718 vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
719 vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
720 vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
721 vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
723 # Vector Integer Extension
724 vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
725 vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
726 vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
727 vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
728 vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
729 vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
731 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
732 vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
733 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
735 # *** Zawrs Standard Extension ***
736 wrs_nto 000000001101 00000 000 00000 1110011
737 wrs_sto 000000011101 00000 000 00000 1110011
739 # *** RV32 Zba Standard Extension ***
740 sh1add 0010000 .......... 010 ..... 0110011 @r
741 sh2add 0010000 .......... 100 ..... 0110011 @r
742 sh3add 0010000 .......... 110 ..... 0110011 @r
744 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
745 add_uw 0000100 .......... 000 ..... 0111011 @r
746 sh1add_uw 0010000 .......... 010 ..... 0111011 @r
747 sh2add_uw 0010000 .......... 100 ..... 0111011 @r
748 sh3add_uw 0010000 .......... 110 ..... 0111011 @r
749 slli_uw 00001 ............ 001 ..... 0011011 @sh
751 # *** RV32 Zbb/Zbkb Standard Extension ***
752 andn 0100000 .......... 111 ..... 0110011 @r
753 rol 0110000 .......... 001 ..... 0110011 @r
754 ror 0110000 .......... 101 ..... 0110011 @r
755 rori 01100 ............ 101 ..... 0010011 @sh
756 # The encoding for rev8 differs between RV32 and RV64.
757 # rev8_32 denotes the RV32 variant.
758 rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
759 # The encoding for zext.h differs between RV32 and RV64.
760 # zext_h_32 denotes the RV32 variant.
761 {
762 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
763 pack 0000100 ..... ..... 100 ..... 0110011 @r
764 }
765 xnor 0100000 .......... 100 ..... 0110011 @r
766 # *** RV32 extra Zbb Standard Extension ***
767 clz 011000 000000 ..... 001 ..... 0010011 @r2
768 cpop 011000 000010 ..... 001 ..... 0010011 @r2
769 ctz 011000 000001 ..... 001 ..... 0010011 @r2
770 max 0000101 .......... 110 ..... 0110011 @r
771 maxu 0000101 .......... 111 ..... 0110011 @r
772 min 0000101 .......... 100 ..... 0110011 @r
773 minu 0000101 .......... 101 ..... 0110011 @r
774 orc_b 001010 000111 ..... 101 ..... 0010011 @r2
775 orn 0100000 .......... 110 ..... 0110011 @r
776 sext_b 011000 000100 ..... 001 ..... 0010011 @r2
777 sext_h 011000 000101 ..... 001 ..... 0010011 @r2
778 # *** RV32 extra Zbkb Standard Extension ***
779 brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
780 packh 0000100 .......... 111 ..... 0110011 @r
781 unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
782 zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
784 # *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
785 # The encoding for rev8 differs between RV32 and RV64.
786 # When executing on RV64, the encoding used in RV32 is an illegal
787 # instruction, so we use different handler functions to differentiate.
788 rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
789 rolw 0110000 .......... 001 ..... 0111011 @r
790 roriw 0110000 .......... 101 ..... 0011011 @sh5
791 rorw 0110000 .......... 101 ..... 0111011 @r
792 # The encoding for zext.h differs between RV32 and RV64.
793 # When executing on RV64, the encoding used in RV32 is an illegal
794 # instruction, so we use different handler functions to differentiate.
795 {
796 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
797 packw 0000100 ..... ..... 100 ..... 0111011 @r
798 }
799 # *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
800 clzw 0110000 00000 ..... 001 ..... 0011011 @r2
801 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
802 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
804 # *** RV32 Zbc/Zbkc Standard Extension ***
805 clmul 0000101 .......... 001 ..... 0110011 @r
806 clmulh 0000101 .......... 011 ..... 0110011 @r
807 # *** RV32 extra Zbc Standard Extension ***
808 clmulr 0000101 .......... 010 ..... 0110011 @r
810 # *** RV32 Zbkx Standard Extension ***
811 xperm4 0010100 .......... 010 ..... 0110011 @r
812 xperm8 0010100 .......... 100 ..... 0110011 @r
814 # *** RV32 Zbs Standard Extension ***
815 bclr 0100100 .......... 001 ..... 0110011 @r
816 bclri 01001. ........... 001 ..... 0010011 @sh
817 bext 0100100 .......... 101 ..... 0110011 @r
818 bexti 01001. ........... 101 ..... 0010011 @sh
819 binv 0110100 .......... 001 ..... 0110011 @r
820 binvi 01101. ........... 001 ..... 0010011 @sh
821 bset 0010100 .......... 001 ..... 0110011 @r
822 bseti 00101. ........... 001 ..... 0010011 @sh
824 # *** RV32 Zfh Extension ***
825 flh ............ ..... 001 ..... 0000111 @i
826 fsh ....... ..... ..... 001 ..... 0100111 @s
827 fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
828 fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
829 fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
830 fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
831 fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
832 fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
833 fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
834 fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
835 fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
836 fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
837 fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
838 fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
839 fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
840 fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
841 fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
842 fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
843 fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
844 fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
845 fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
846 fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
847 fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
848 feq_h 1010010 ..... ..... 010 ..... 1010011 @r
849 flt_h 1010010 ..... ..... 001 ..... 1010011 @r
850 fle_h 1010010 ..... ..... 000 ..... 1010011 @r
851 fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
852 fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
853 fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
854 fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
856 # *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
857 fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
858 fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
859 fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
860 fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
862 # *** Svinval Standard Extension ***
863 sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
864 sfence_w_inval 0001100 00000 00000 000 00000 1110011
865 sfence_inval_ir 0001100 00001 00000 000 00000 1110011
866 hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
867 hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
869 # *** RV32 Zknd Standard Extension ***
870 aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
871 aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
872 # *** RV64 Zknd Standard Extension ***
873 aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
874 aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
875 aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
876 # *** RV32 Zkne Standard Extension ***
877 aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
878 aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
879 # *** RV64 Zkne Standard Extension ***
880 aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
881 aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
882 # *** RV64 Zkne/zknd Standard Extension ***
883 aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
884 aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
885 # *** RV32 Zknh Standard Extension ***
886 sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
887 sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
888 sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
889 sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
890 sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
891 sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
892 sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
893 sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
894 sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
895 sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
896 # *** RV64 Zknh Standard Extension ***
897 sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
898 sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
899 sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
900 sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
901 # *** RV32 Zksh Standard Extension ***
902 sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
903 sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
904 # *** RV32 Zksed Standard Extension ***
905 sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
906 sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
908 # *** RV32 Zicond Standard Extension ***
909 czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r
910 czero_nez 0000111 ..... ..... 111 ..... 0110011 @r