hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 #ifdef DEBUG_PIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 //#define DEBUG_IRQ_LATENCY
  41 //#define DEBUG_IRQ_COUNT
  42
  43 typedef struct PicState {
  44     uint8_t last_irr; /* edge detection */
  45     uint8_t irr; /* interrupt request register */
  46     uint8_t imr; /* interrupt mask register */
  47     uint8_t isr; /* interrupt service register */
  48     uint8_t priority_add; /* highest irq priority */
  49     uint8_t irq_base;
  50     uint8_t read_reg_select;
  51     uint8_t poll;
  52     uint8_t special_mask;
  53     uint8_t init_state;
  54     uint8_t auto_eoi;
  55     uint8_t rotate_on_auto_eoi;
  56     uint8_t special_fully_nested_mode;
  57     uint8_t init4; /* true if 4 byte init */
  58     uint8_t single_mode; /* true if slave pic is not initialized */
  59     uint8_t elcr; /* PIIX edge/trigger selection*/
  60     uint8_t elcr_mask;
  61     PicState2 *pics_state;
  62 } PicState;
  63
  64 struct PicState2 {
  65     /* 0 is master pic, 1 is slave pic */
  66     /* XXX: better separation between the two pics */
  67     PicState pics[2];
  68     qemu_irq parent_irq;
  69     void *irq_request_opaque;
  70 };
  71
  72 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  73 static int irq_level[16];
  74 #endif
  75 #ifdef DEBUG_IRQ_COUNT
  76 static uint64_t irq_count[16];
  77 #endif
  78 PicState2 *isa_pic;
  79
  80 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  81 static inline void pic_set_irq1(PicState *s, int irq, int level)
  82 {
  83     int mask;
  84     mask = 1 << irq;
  85     if (s->elcr & mask) {
  86         /* level triggered */
  87         if (level) {
  88             s->irr |= mask;
  89             s->last_irr |= mask;
  90         } else {
  91             s->irr &= ~mask;
  92             s->last_irr &= ~mask;
  93         }
  94     } else {
  95         /* edge triggered */
  96         if (level) {
  97             if ((s->last_irr & mask) == 0)
  98                 s->irr |= mask;
  99             s->last_irr |= mask;
 100         } else {
 101             s->last_irr &= ~mask;
 102         }
 103     }
 104 }
 105
 106 /* return the highest priority found in mask (highest = smallest
 107    number). Return 8 if no irq */
 108 static inline int get_priority(PicState *s, int mask)
 109 {
 110     int priority;
 111     if (mask == 0)
 112         return 8;
 113     priority = 0;
 114     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 115         priority++;
 116     return priority;
 117 }
 118
 119 /* return the pic wanted interrupt. return -1 if none */
 120 static int pic_get_irq(PicState *s)
 121 {
 122     int mask, cur_priority, priority;
 123
 124     mask = s->irr & ~s->imr;
 125     priority = get_priority(s, mask);
 126     if (priority == 8)
 127         return -1;
 128     /* compute current priority. If special fully nested mode on the
 129        master, the IRQ coming from the slave is not taken into account
 130        for the priority computation. */
 131     mask = s->isr;
 132     if (s->special_mask)
 133         mask &= ~s->imr;
 134     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 135         mask &= ~(1 << 2);
 136     cur_priority = get_priority(s, mask);
 137     if (priority < cur_priority) {
 138         /* higher priority found: an irq should be generated */
 139         return (priority + s->priority_add) & 7;
 140     } else {
 141         return -1;
 142     }
 143 }
 144
 145 /* raise irq to CPU if necessary. must be called every time the active
 146    irq may change */
 147 /* XXX: should not export it, but it is needed for an APIC kludge */
 148 void pic_update_irq(PicState2 *s)
 149 {
 150     int irq2, irq;
 151
 152     /* first look at slave pic */
 153     irq2 = pic_get_irq(&s->pics[1]);
 154     if (irq2 >= 0) {
 155         /* if irq request by slave pic, signal master PIC */
 156         pic_set_irq1(&s->pics[0], 2, 1);
 157         pic_set_irq1(&s->pics[0], 2, 0);
 158     }
 159     /* look at requested irq */
 160     irq = pic_get_irq(&s->pics[0]);
 161     if (irq >= 0) {
 162 #if defined(DEBUG_PIC)
 163         {
 164             int i;
 165             for(i = 0; i < 2; i++) {
 166                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 167                        i, s->pics[i].imr, s->pics[i].irr,
 168                        s->pics[i].priority_add);
 169
 170             }
 171         }
 172         printf("pic: cpu_interrupt\n");
 173 #endif
 174         qemu_irq_raise(s->parent_irq);
 175     }
 176
 177 /* all targets should do this rather than acking the IRQ in the cpu */
 178 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 179     else {
 180         qemu_irq_lower(s->parent_irq);
 181     }
 182 #endif
 183 }
 184
 185 #ifdef DEBUG_IRQ_LATENCY
 186 int64_t irq_time[16];
 187 #endif
 188
 189 static void i8259_set_irq(void *opaque, int irq, int level)
 190 {
 191     PicState2 *s = opaque;
 192
 193 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 194     if (level != irq_level[irq]) {
 195         DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
 196         irq_level[irq] = level;
 197 #ifdef DEBUG_IRQ_COUNT
 198         if (level == 1)
 199             irq_count[irq]++;
 200 #endif
 201     }
 202 #endif
 203 #ifdef DEBUG_IRQ_LATENCY
 204     if (level) {
 205         irq_time[irq] = qemu_get_clock_ns(vm_clock);
 206     }
 207 #endif
 208     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 209     pic_update_irq(s);
 210 }
 211
 212 /* acknowledge interrupt 'irq' */
 213 static inline void pic_intack(PicState *s, int irq)
 214 {
 215     if (s->auto_eoi) {
 216         if (s->rotate_on_auto_eoi)
 217             s->priority_add = (irq + 1) & 7;
 218     } else {
 219         s->isr |= (1 << irq);
 220     }
 221     /* We don't clear a level sensitive interrupt here */
 222     if (!(s->elcr & (1 << irq)))
 223         s->irr &= ~(1 << irq);
 224 }
 225
 226 int pic_read_irq(PicState2 *s)
 227 {
 228     int irq, irq2, intno;
 229
 230     irq = pic_get_irq(&s->pics[0]);
 231     if (irq >= 0) {
 232         pic_intack(&s->pics[0], irq);
 233         if (irq == 2) {
 234             irq2 = pic_get_irq(&s->pics[1]);
 235             if (irq2 >= 0) {
 236                 pic_intack(&s->pics[1], irq2);
 237             } else {
 238                 /* spurious IRQ on slave controller */
 239                 irq2 = 7;
 240             }
 241             intno = s->pics[1].irq_base + irq2;
 242 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 243             irq = irq2 + 8;
 244 #endif
 245         } else {
 246             intno = s->pics[0].irq_base + irq;
 247         }
 248     } else {
 249         /* spurious IRQ on host controller */
 250         irq = 7;
 251         intno = s->pics[0].irq_base + irq;
 252     }
 253     pic_update_irq(s);
 254
 255 #ifdef DEBUG_IRQ_LATENCY
 256     printf("IRQ%d latency=%0.3fus\n",
 257            irq,
 258            (double)(qemu_get_clock_ns(vm_clock) -
 259                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 260 #endif
 261     DPRINTF("pic_interrupt: irq=%d\n", irq);
 262     return intno;
 263 }
 264
 265 static void pic_reset(void *opaque)
 266 {
 267     PicState *s = opaque;
 268
 269     s->last_irr = 0;
 270     s->irr = 0;
 271     s->imr = 0;
 272     s->isr = 0;
 273     s->priority_add = 0;
 274     s->irq_base = 0;
 275     s->read_reg_select = 0;
 276     s->poll = 0;
 277     s->special_mask = 0;
 278     s->init_state = 0;
 279     s->auto_eoi = 0;
 280     s->rotate_on_auto_eoi = 0;
 281     s->special_fully_nested_mode = 0;
 282     s->init4 = 0;
 283     s->single_mode = 0;
 284     /* Note: ELCR is not reset */
 285 }
 286
 287 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 288 {
 289     PicState *s = opaque;
 290     int priority, cmd, irq;
 291
 292     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 293     addr &= 1;
 294     if (addr == 0) {
 295         if (val & 0x10) {
 296             /* init */
 297             pic_reset(s);
 298             /* deassert a pending interrupt */
 299             qemu_irq_lower(s->pics_state->parent_irq);
 300             s->init_state = 1;
 301             s->init4 = val & 1;
 302             s->single_mode = val & 2;
 303             if (val & 0x08)
 304                 hw_error("level sensitive irq not supported");
 305         } else if (val & 0x08) {
 306             if (val & 0x04)
 307                 s->poll = 1;
 308             if (val & 0x02)
 309                 s->read_reg_select = val & 1;
 310             if (val & 0x40)
 311                 s->special_mask = (val >> 5) & 1;
 312         } else {
 313             cmd = val >> 5;
 314             switch(cmd) {
 315             case 0:
 316             case 4:
 317                 s->rotate_on_auto_eoi = cmd >> 2;
 318                 break;
 319             case 1: /* end of interrupt */
 320             case 5:
 321                 priority = get_priority(s, s->isr);
 322                 if (priority != 8) {
 323                     irq = (priority + s->priority_add) & 7;
 324                     s->isr &= ~(1 << irq);
 325                     if (cmd == 5)
 326                         s->priority_add = (irq + 1) & 7;
 327                     pic_update_irq(s->pics_state);
 328                 }
 329                 break;
 330             case 3:
 331                 irq = val & 7;
 332                 s->isr &= ~(1 << irq);
 333                 pic_update_irq(s->pics_state);
 334                 break;
 335             case 6:
 336                 s->priority_add = (val + 1) & 7;
 337                 pic_update_irq(s->pics_state);
 338                 break;
 339             case 7:
 340                 irq = val & 7;
 341                 s->isr &= ~(1 << irq);
 342                 s->priority_add = (irq + 1) & 7;
 343                 pic_update_irq(s->pics_state);
 344                 break;
 345             default:
 346                 /* no operation */
 347                 break;
 348             }
 349         }
 350     } else {
 351         switch(s->init_state) {
 352         case 0:
 353             /* normal mode */
 354             s->imr = val;
 355             pic_update_irq(s->pics_state);
 356             break;
 357         case 1:
 358             s->irq_base = val & 0xf8;
 359             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 360             break;
 361         case 2:
 362             if (s->init4) {
 363                 s->init_state = 3;
 364             } else {
 365                 s->init_state = 0;
 366             }
 367             break;
 368         case 3:
 369             s->special_fully_nested_mode = (val >> 4) & 1;
 370             s->auto_eoi = (val >> 1) & 1;
 371             s->init_state = 0;
 372             break;
 373         }
 374     }
 375 }
 376
 377 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 378 {
 379     int ret;
 380
 381     ret = pic_get_irq(s);
 382     if (ret >= 0) {
 383         if (addr1 >> 7) {
 384             s->pics_state->pics[0].isr &= ~(1 << 2);
 385             s->pics_state->pics[0].irr &= ~(1 << 2);
 386         }
 387         s->irr &= ~(1 << ret);
 388         s->isr &= ~(1 << ret);
 389         if (addr1 >> 7 || ret != 2)
 390             pic_update_irq(s->pics_state);
 391     } else {
 392         ret = 0x07;
 393         pic_update_irq(s->pics_state);
 394     }
 395
 396     return ret;
 397 }
 398
 399 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 400 {
 401     PicState *s = opaque;
 402     unsigned int addr;
 403     int ret;
 404
 405     addr = addr1;
 406     addr &= 1;
 407     if (s->poll) {
 408         ret = pic_poll_read(s, addr1);
 409         s->poll = 0;
 410     } else {
 411         if (addr == 0) {
 412             if (s->read_reg_select)
 413                 ret = s->isr;
 414             else
 415                 ret = s->irr;
 416         } else {
 417             ret = s->imr;
 418         }
 419     }
 420     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
 421     return ret;
 422 }
 423
 424 /* memory mapped interrupt status */
 425 /* XXX: may be the same than pic_read_irq() */
 426 uint32_t pic_intack_read(PicState2 *s)
 427 {
 428     int ret;
 429
 430     ret = pic_poll_read(&s->pics[0], 0x00);
 431     if (ret == 2)
 432         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 433     /* Prepare for ISR read */
 434     s->pics[0].read_reg_select = 1;
 435
 436     return ret;
 437 }
 438
 439 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 440 {
 441     PicState *s = opaque;
 442     s->elcr = val & s->elcr_mask;
 443 }
 444
 445 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 446 {
 447     PicState *s = opaque;
 448     return s->elcr;
 449 }
 450
 451 static const VMStateDescription vmstate_pic = {
 452     .name = "i8259",
 453     .version_id = 1,
 454     .minimum_version_id = 1,
 455     .minimum_version_id_old = 1,
 456     .fields      = (VMStateField []) {
 457         VMSTATE_UINT8(last_irr, PicState),
 458         VMSTATE_UINT8(irr, PicState),
 459         VMSTATE_UINT8(imr, PicState),
 460         VMSTATE_UINT8(isr, PicState),
 461         VMSTATE_UINT8(priority_add, PicState),
 462         VMSTATE_UINT8(irq_base, PicState),
 463         VMSTATE_UINT8(read_reg_select, PicState),
 464         VMSTATE_UINT8(poll, PicState),
 465         VMSTATE_UINT8(special_mask, PicState),
 466         VMSTATE_UINT8(init_state, PicState),
 467         VMSTATE_UINT8(auto_eoi, PicState),
 468         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 469         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 470         VMSTATE_UINT8(init4, PicState),
 471         VMSTATE_UINT8(single_mode, PicState),
 472         VMSTATE_UINT8(elcr, PicState),
 473         VMSTATE_END_OF_LIST()
 474     }
 475 };
 476
 477 /* XXX: add generic master/slave system */
 478 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 479 {
 480     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 481     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 482     if (elcr_addr >= 0) {
 483         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 484         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 485     }
 486     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 487     qemu_register_reset(pic_reset, s);
 488 }
 489
 490 void pic_info(Monitor *mon)
 491 {
 492     int i;
 493     PicState *s;
 494
 495     if (!isa_pic)
 496         return;
 497
 498     for(i=0;i<2;i++) {
 499         s = &isa_pic->pics[i];
 500         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 501                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 502                        i, s->irr, s->imr, s->isr, s->priority_add,
 503                        s->irq_base, s->read_reg_select, s->elcr,
 504                        s->special_fully_nested_mode);
 505     }
 506 }
 507
 508 void irq_info(Monitor *mon)
 509 {
 510 #ifndef DEBUG_IRQ_COUNT
 511     monitor_printf(mon, "irq statistic code not compiled.\n");
 512 #else
 513     int i;
 514     int64_t count;
 515
 516     monitor_printf(mon, "IRQ statistics:\n");
 517     for (i = 0; i < 16; i++) {
 518         count = irq_count[i];
 519         if (count > 0)
 520             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 521     }
 522 #endif
 523 }
 524
 525 qemu_irq *i8259_init(qemu_irq parent_irq)
 526 {
 527     PicState2 *s;
 528
 529     s = g_malloc0(sizeof(PicState2));
 530     pic_init1(0x20, 0x4d0, &s->pics[0]);
 531     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 532     s->pics[0].elcr_mask = 0xf8;
 533     s->pics[1].elcr_mask = 0xde;
 534     s->parent_irq = parent_irq;
 535     s->pics[0].pics_state = s;
 536     s->pics[1].pics_state = s;
 537     isa_pic = s;
 538     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 539 }