hw/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "scsi.h"
  27 #include "esp.h"
  28
  29 /* debug ESP card */
  30 //#define DEBUG_ESP
  31
  32 /*
  33  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  34  * also produced as NCR89C100. See
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  36  * and
  37  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  38  */
  39
  40 #ifdef DEBUG_ESP
  41 #define DPRINTF(fmt, ...)                                       \
  42     do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
  43 #else
  44 #define DPRINTF(fmt, ...) do {} while (0)
  45 #endif
  46
  47 #define ESP_ERROR(fmt, ...)                                             \
  48     do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  49
  50 #define ESP_REGS 16
  51 #define TI_BUFSZ 16
  52
  53 typedef struct ESPState ESPState;
  54
  55 struct ESPState {
  56     SysBusDevice busdev;
  57     uint8_t rregs[ESP_REGS];
  58     uint8_t wregs[ESP_REGS];
  59     qemu_irq irq;
  60     uint32_t it_shift;
  61     int32_t ti_size;
  62     uint32_t ti_rptr, ti_wptr;
  63     uint32_t status;
  64     uint32_t dma;
  65     uint8_t ti_buf[TI_BUFSZ];
  66     SCSIBus bus;
  67     SCSIDevice *current_dev;
  68     SCSIRequest *current_req;
  69     uint8_t cmdbuf[TI_BUFSZ];
  70     uint32_t cmdlen;
  71     uint32_t do_cmd;
  72
  73     /* The amount of data left in the current DMA transfer.  */
  74     uint32_t dma_left;
  75     /* The size of the current DMA transfer.  Zero if no transfer is in
  76        progress.  */
  77     uint32_t dma_counter;
  78     int dma_enabled;
  79
  80     uint32_t async_len;
  81     uint8_t *async_buf;
  82
  83     ESPDMAMemoryReadWriteFunc dma_memory_read;
  84     ESPDMAMemoryReadWriteFunc dma_memory_write;
  85     void *dma_opaque;
  86     void (*dma_cb)(ESPState *s);
  87 };
  88
  89 #define ESP_TCLO   0x0
  90 #define ESP_TCMID  0x1
  91 #define ESP_FIFO   0x2
  92 #define ESP_CMD    0x3
  93 #define ESP_RSTAT  0x4
  94 #define ESP_WBUSID 0x4
  95 #define ESP_RINTR  0x5
  96 #define ESP_WSEL   0x5
  97 #define ESP_RSEQ   0x6
  98 #define ESP_WSYNTP 0x6
  99 #define ESP_RFLAGS 0x7
 100 #define ESP_WSYNO  0x7
 101 #define ESP_CFG1   0x8
 102 #define ESP_RRES1  0x9
 103 #define ESP_WCCF   0x9
 104 #define ESP_RRES2  0xa
 105 #define ESP_WTEST  0xa
 106 #define ESP_CFG2   0xb
 107 #define ESP_CFG3   0xc
 108 #define ESP_RES3   0xd
 109 #define ESP_TCHI   0xe
 110 #define ESP_RES4   0xf
 111
 112 #define CMD_DMA 0x80
 113 #define CMD_CMD 0x7f
 114
 115 #define CMD_NOP      0x00
 116 #define CMD_FLUSH    0x01
 117 #define CMD_RESET    0x02
 118 #define CMD_BUSRESET 0x03
 119 #define CMD_TI       0x10
 120 #define CMD_ICCS     0x11
 121 #define CMD_MSGACC   0x12
 122 #define CMD_PAD      0x18
 123 #define CMD_SATN     0x1a
 124 #define CMD_SEL      0x41
 125 #define CMD_SELATN   0x42
 126 #define CMD_SELATNS  0x43
 127 #define CMD_ENSEL    0x44
 128
 129 #define STAT_DO 0x00
 130 #define STAT_DI 0x01
 131 #define STAT_CD 0x02
 132 #define STAT_ST 0x03
 133 #define STAT_MO 0x06
 134 #define STAT_MI 0x07
 135 #define STAT_PIO_MASK 0x06
 136
 137 #define STAT_TC 0x10
 138 #define STAT_PE 0x20
 139 #define STAT_GE 0x40
 140 #define STAT_INT 0x80
 141
 142 #define BUSID_DID 0x07
 143
 144 #define INTR_FC 0x08
 145 #define INTR_BS 0x10
 146 #define INTR_DC 0x20
 147 #define INTR_RST 0x80
 148
 149 #define SEQ_0 0x0
 150 #define SEQ_CD 0x4
 151
 152 #define CFG1_RESREPT 0x40
 153
 154 #define TCHI_FAS100A 0x4
 155
 156 static void esp_raise_irq(ESPState *s)
 157 {
 158     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
 159         s->rregs[ESP_RSTAT] |= STAT_INT;
 160         qemu_irq_raise(s->irq);
 161         DPRINTF("Raise IRQ\n");
 162     }
 163 }
 164
 165 static void esp_lower_irq(ESPState *s)
 166 {
 167     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 168         s->rregs[ESP_RSTAT] &= ~STAT_INT;
 169         qemu_irq_lower(s->irq);
 170         DPRINTF("Lower IRQ\n");
 171     }
 172 }
 173
 174 static void esp_dma_enable(void *opaque, int irq, int level)
 175 {
 176     DeviceState *d = opaque;
 177     ESPState *s = container_of(d, ESPState, busdev.qdev);
 178
 179     if (level) {
 180         s->dma_enabled = 1;
 181         DPRINTF("Raise enable\n");
 182         if (s->dma_cb) {
 183             s->dma_cb(s);
 184             s->dma_cb = NULL;
 185         }
 186     } else {
 187         DPRINTF("Lower enable\n");
 188         s->dma_enabled = 0;
 189     }
 190 }
 191
 192 static void esp_request_cancelled(SCSIRequest *req)
 193 {
 194     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 195
 196     if (req == s->current_req) {
 197         scsi_req_unref(s->current_req);
 198         s->current_req = NULL;
 199         s->current_dev = NULL;
 200     }
 201 }
 202
 203 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
 204 {
 205     uint32_t dmalen;
 206     int target;
 207
 208     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 209     if (s->dma) {
 210         dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 211         s->dma_memory_read(s->dma_opaque, buf, dmalen);
 212     } else {
 213         dmalen = s->ti_size;
 214         memcpy(buf, s->ti_buf, dmalen);
 215         buf[0] = buf[2] >> 5;
 216     }
 217     DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
 218
 219     s->ti_size = 0;
 220     s->ti_rptr = 0;
 221     s->ti_wptr = 0;
 222
 223     if (s->current_req) {
 224         /* Started a new command before the old one finished.  Cancel it.  */
 225         scsi_req_cancel(s->current_req);
 226         s->async_len = 0;
 227     }
 228
 229     if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) {
 230         // No such drive
 231         s->rregs[ESP_RSTAT] = 0;
 232         s->rregs[ESP_RINTR] = INTR_DC;
 233         s->rregs[ESP_RSEQ] = SEQ_0;
 234         esp_raise_irq(s);
 235         return 0;
 236     }
 237     s->current_dev = s->bus.devs[target];
 238     return dmalen;
 239 }
 240
 241 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 242 {
 243     int32_t datalen;
 244     int lun;
 245
 246     DPRINTF("do_busid_cmd: busid 0x%x\n", busid);
 247     lun = busid & 7;
 248     s->current_req = scsi_req_new(s->current_dev, 0, lun, buf, NULL);
 249     datalen = scsi_req_enqueue(s->current_req);
 250     s->ti_size = datalen;
 251     if (datalen != 0) {
 252         s->rregs[ESP_RSTAT] = STAT_TC;
 253         s->dma_left = 0;
 254         s->dma_counter = 0;
 255         if (datalen > 0) {
 256             s->rregs[ESP_RSTAT] |= STAT_DI;
 257         } else {
 258             s->rregs[ESP_RSTAT] |= STAT_DO;
 259         }
 260         scsi_req_continue(s->current_req);
 261     }
 262     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 263     s->rregs[ESP_RSEQ] = SEQ_CD;
 264     esp_raise_irq(s);
 265 }
 266
 267 static void do_cmd(ESPState *s, uint8_t *buf)
 268 {
 269     uint8_t busid = buf[0];
 270
 271     do_busid_cmd(s, &buf[1], busid);
 272 }
 273
 274 static void handle_satn(ESPState *s)
 275 {
 276     uint8_t buf[32];
 277     int len;
 278
 279     if (!s->dma_enabled) {
 280         s->dma_cb = handle_satn;
 281         return;
 282     }
 283     len = get_cmd(s, buf);
 284     if (len)
 285         do_cmd(s, buf);
 286 }
 287
 288 static void handle_s_without_atn(ESPState *s)
 289 {
 290     uint8_t buf[32];
 291     int len;
 292
 293     if (!s->dma_enabled) {
 294         s->dma_cb = handle_s_without_atn;
 295         return;
 296     }
 297     len = get_cmd(s, buf);
 298     if (len) {
 299         do_busid_cmd(s, buf, 0);
 300     }
 301 }
 302
 303 static void handle_satn_stop(ESPState *s)
 304 {
 305     if (!s->dma_enabled) {
 306         s->dma_cb = handle_satn_stop;
 307         return;
 308     }
 309     s->cmdlen = get_cmd(s, s->cmdbuf);
 310     if (s->cmdlen) {
 311         DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
 312         s->do_cmd = 1;
 313         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 314         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 315         s->rregs[ESP_RSEQ] = SEQ_CD;
 316         esp_raise_irq(s);
 317     }
 318 }
 319
 320 static void write_response(ESPState *s)
 321 {
 322     DPRINTF("Transfer status (status=%d)\n", s->status);
 323     s->ti_buf[0] = s->status;
 324     s->ti_buf[1] = 0;
 325     if (s->dma) {
 326         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 327         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 328         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 329         s->rregs[ESP_RSEQ] = SEQ_CD;
 330     } else {
 331         s->ti_size = 2;
 332         s->ti_rptr = 0;
 333         s->ti_wptr = 0;
 334         s->rregs[ESP_RFLAGS] = 2;
 335     }
 336     esp_raise_irq(s);
 337 }
 338
 339 static void esp_dma_done(ESPState *s)
 340 {
 341     s->rregs[ESP_RSTAT] |= STAT_TC;
 342     s->rregs[ESP_RINTR] = INTR_BS;
 343     s->rregs[ESP_RSEQ] = 0;
 344     s->rregs[ESP_RFLAGS] = 0;
 345     s->rregs[ESP_TCLO] = 0;
 346     s->rregs[ESP_TCMID] = 0;
 347     esp_raise_irq(s);
 348 }
 349
 350 static void esp_do_dma(ESPState *s)
 351 {
 352     uint32_t len;
 353     int to_device;
 354
 355     to_device = (s->ti_size < 0);
 356     len = s->dma_left;
 357     if (s->do_cmd) {
 358         DPRINTF("command len %d + %d\n", s->cmdlen, len);
 359         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 360         s->ti_size = 0;
 361         s->cmdlen = 0;
 362         s->do_cmd = 0;
 363         do_cmd(s, s->cmdbuf);
 364         return;
 365     }
 366     if (s->async_len == 0) {
 367         /* Defer until data is available.  */
 368         return;
 369     }
 370     if (len > s->async_len) {
 371         len = s->async_len;
 372     }
 373     if (to_device) {
 374         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 375     } else {
 376         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 377     }
 378     s->dma_left -= len;
 379     s->async_buf += len;
 380     s->async_len -= len;
 381     if (to_device)
 382         s->ti_size += len;
 383     else
 384         s->ti_size -= len;
 385     if (s->async_len == 0) {
 386         scsi_req_continue(s->current_req);
 387         /* If there is still data to be read from the device then
 388            complete the DMA operation immediately.  Otherwise defer
 389            until the scsi layer has completed.  */
 390         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 391             return;
 392         }
 393     }
 394
 395     /* Partially filled a scsi buffer. Complete immediately.  */
 396     esp_dma_done(s);
 397 }
 398
 399 static void esp_command_complete(SCSIRequest *req, uint32_t status)
 400 {
 401     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 402
 403     DPRINTF("SCSI Command complete\n");
 404     if (s->ti_size != 0) {
 405         DPRINTF("SCSI command completed unexpectedly\n");
 406     }
 407     s->ti_size = 0;
 408     s->dma_left = 0;
 409     s->async_len = 0;
 410     if (status) {
 411         DPRINTF("Command failed\n");
 412     }
 413     s->status = status;
 414     s->rregs[ESP_RSTAT] = STAT_ST;
 415     esp_dma_done(s);
 416     if (s->current_req) {
 417         scsi_req_unref(s->current_req);
 418         s->current_req = NULL;
 419         s->current_dev = NULL;
 420     }
 421 }
 422
 423 static void esp_transfer_data(SCSIRequest *req, uint32_t len)
 424 {
 425     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 426
 427     DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
 428     s->async_len = len;
 429     s->async_buf = scsi_req_get_buf(req);
 430     if (s->dma_left) {
 431         esp_do_dma(s);
 432     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 433         /* If this was the last part of a DMA transfer then the
 434            completion interrupt is deferred to here.  */
 435         esp_dma_done(s);
 436     }
 437 }
 438
 439 static void handle_ti(ESPState *s)
 440 {
 441     uint32_t dmalen, minlen;
 442
 443     dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 444     if (dmalen==0) {
 445       dmalen=0x10000;
 446     }
 447     s->dma_counter = dmalen;
 448
 449     if (s->do_cmd)
 450         minlen = (dmalen < 32) ? dmalen : 32;
 451     else if (s->ti_size < 0)
 452         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 453     else
 454         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 455     DPRINTF("Transfer Information len %d\n", minlen);
 456     if (s->dma) {
 457         s->dma_left = minlen;
 458         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 459         esp_do_dma(s);
 460     } else if (s->do_cmd) {
 461         DPRINTF("command len %d\n", s->cmdlen);
 462         s->ti_size = 0;
 463         s->cmdlen = 0;
 464         s->do_cmd = 0;
 465         do_cmd(s, s->cmdbuf);
 466         return;
 467     }
 468 }
 469
 470 static void esp_hard_reset(DeviceState *d)
 471 {
 472     ESPState *s = container_of(d, ESPState, busdev.qdev);
 473
 474     memset(s->rregs, 0, ESP_REGS);
 475     memset(s->wregs, 0, ESP_REGS);
 476     s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
 477     s->ti_size = 0;
 478     s->ti_rptr = 0;
 479     s->ti_wptr = 0;
 480     s->dma = 0;
 481     s->do_cmd = 0;
 482     s->dma_cb = NULL;
 483
 484     s->rregs[ESP_CFG1] = 7;
 485 }
 486
 487 static void esp_soft_reset(DeviceState *d)
 488 {
 489     ESPState *s = container_of(d, ESPState, busdev.qdev);
 490
 491     qemu_irq_lower(s->irq);
 492     esp_hard_reset(d);
 493 }
 494
 495 static void parent_esp_reset(void *opaque, int irq, int level)
 496 {
 497     if (level) {
 498         esp_soft_reset(opaque);
 499     }
 500 }
 501
 502 static void esp_gpio_demux(void *opaque, int irq, int level)
 503 {
 504     switch (irq) {
 505     case 0:
 506         parent_esp_reset(opaque, irq, level);
 507         break;
 508     case 1:
 509         esp_dma_enable(opaque, irq, level);
 510         break;
 511     }
 512 }
 513
 514 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
 515 {
 516     ESPState *s = opaque;
 517     uint32_t saddr, old_val;
 518
 519     saddr = addr >> s->it_shift;
 520     DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
 521     switch (saddr) {
 522     case ESP_FIFO:
 523         if (s->ti_size > 0) {
 524             s->ti_size--;
 525             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 526                 /* Data out.  */
 527                 ESP_ERROR("PIO data read not implemented\n");
 528                 s->rregs[ESP_FIFO] = 0;
 529             } else {
 530                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 531             }
 532             esp_raise_irq(s);
 533         }
 534         if (s->ti_size == 0) {
 535             s->ti_rptr = 0;
 536             s->ti_wptr = 0;
 537         }
 538         break;
 539     case ESP_RINTR:
 540         /* Clear sequence step, interrupt register and all status bits
 541            except TC */
 542         old_val = s->rregs[ESP_RINTR];
 543         s->rregs[ESP_RINTR] = 0;
 544         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 545         s->rregs[ESP_RSEQ] = SEQ_CD;
 546         esp_lower_irq(s);
 547
 548         return old_val;
 549     default:
 550         break;
 551     }
 552     return s->rregs[saddr];
 553 }
 554
 555 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 556 {
 557     ESPState *s = opaque;
 558     uint32_t saddr;
 559
 560     saddr = addr >> s->it_shift;
 561     DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
 562             val);
 563     switch (saddr) {
 564     case ESP_TCLO:
 565     case ESP_TCMID:
 566         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 567         break;
 568     case ESP_FIFO:
 569         if (s->do_cmd) {
 570             s->cmdbuf[s->cmdlen++] = val & 0xff;
 571         } else if (s->ti_size == TI_BUFSZ - 1) {
 572             ESP_ERROR("fifo overrun\n");
 573         } else {
 574             s->ti_size++;
 575             s->ti_buf[s->ti_wptr++] = val & 0xff;
 576         }
 577         break;
 578     case ESP_CMD:
 579         s->rregs[saddr] = val;
 580         if (val & CMD_DMA) {
 581             s->dma = 1;
 582             /* Reload DMA counter.  */
 583             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 584             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 585         } else {
 586             s->dma = 0;
 587         }
 588         switch(val & CMD_CMD) {
 589         case CMD_NOP:
 590             DPRINTF("NOP (%2.2x)\n", val);
 591             break;
 592         case CMD_FLUSH:
 593             DPRINTF("Flush FIFO (%2.2x)\n", val);
 594             //s->ti_size = 0;
 595             s->rregs[ESP_RINTR] = INTR_FC;
 596             s->rregs[ESP_RSEQ] = 0;
 597             s->rregs[ESP_RFLAGS] = 0;
 598             break;
 599         case CMD_RESET:
 600             DPRINTF("Chip reset (%2.2x)\n", val);
 601             esp_soft_reset(&s->busdev.qdev);
 602             break;
 603         case CMD_BUSRESET:
 604             DPRINTF("Bus reset (%2.2x)\n", val);
 605             s->rregs[ESP_RINTR] = INTR_RST;
 606             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 607                 esp_raise_irq(s);
 608             }
 609             break;
 610         case CMD_TI:
 611             handle_ti(s);
 612             break;
 613         case CMD_ICCS:
 614             DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
 615             write_response(s);
 616             s->rregs[ESP_RINTR] = INTR_FC;
 617             s->rregs[ESP_RSTAT] |= STAT_MI;
 618             break;
 619         case CMD_MSGACC:
 620             DPRINTF("Message Accepted (%2.2x)\n", val);
 621             s->rregs[ESP_RINTR] = INTR_DC;
 622             s->rregs[ESP_RSEQ] = 0;
 623             s->rregs[ESP_RFLAGS] = 0;
 624             esp_raise_irq(s);
 625             break;
 626         case CMD_PAD:
 627             DPRINTF("Transfer padding (%2.2x)\n", val);
 628             s->rregs[ESP_RSTAT] = STAT_TC;
 629             s->rregs[ESP_RINTR] = INTR_FC;
 630             s->rregs[ESP_RSEQ] = 0;
 631             break;
 632         case CMD_SATN:
 633             DPRINTF("Set ATN (%2.2x)\n", val);
 634             break;
 635         case CMD_SEL:
 636             DPRINTF("Select without ATN (%2.2x)\n", val);
 637             handle_s_without_atn(s);
 638             break;
 639         case CMD_SELATN:
 640             DPRINTF("Select with ATN (%2.2x)\n", val);
 641             handle_satn(s);
 642             break;
 643         case CMD_SELATNS:
 644             DPRINTF("Select with ATN & stop (%2.2x)\n", val);
 645             handle_satn_stop(s);
 646             break;
 647         case CMD_ENSEL:
 648             DPRINTF("Enable selection (%2.2x)\n", val);
 649             s->rregs[ESP_RINTR] = 0;
 650             break;
 651         default:
 652             ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
 653             break;
 654         }
 655         break;
 656     case ESP_WBUSID ... ESP_WSYNO:
 657         break;
 658     case ESP_CFG1:
 659         s->rregs[saddr] = val;
 660         break;
 661     case ESP_WCCF ... ESP_WTEST:
 662         break;
 663     case ESP_CFG2 ... ESP_RES4:
 664         s->rregs[saddr] = val;
 665         break;
 666     default:
 667         ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
 668         return;
 669     }
 670     s->wregs[saddr] = val;
 671 }
 672
 673 static CPUReadMemoryFunc * const esp_mem_read[3] = {
 674     esp_mem_readb,
 675     NULL,
 676     NULL,
 677 };
 678
 679 static CPUWriteMemoryFunc * const esp_mem_write[3] = {
 680     esp_mem_writeb,
 681     NULL,
 682     esp_mem_writeb,
 683 };
 684
 685 static const VMStateDescription vmstate_esp = {
 686     .name ="esp",
 687     .version_id = 3,
 688     .minimum_version_id = 3,
 689     .minimum_version_id_old = 3,
 690     .fields      = (VMStateField []) {
 691         VMSTATE_BUFFER(rregs, ESPState),
 692         VMSTATE_BUFFER(wregs, ESPState),
 693         VMSTATE_INT32(ti_size, ESPState),
 694         VMSTATE_UINT32(ti_rptr, ESPState),
 695         VMSTATE_UINT32(ti_wptr, ESPState),
 696         VMSTATE_BUFFER(ti_buf, ESPState),
 697         VMSTATE_UINT32(status, ESPState),
 698         VMSTATE_UINT32(dma, ESPState),
 699         VMSTATE_BUFFER(cmdbuf, ESPState),
 700         VMSTATE_UINT32(cmdlen, ESPState),
 701         VMSTATE_UINT32(do_cmd, ESPState),
 702         VMSTATE_UINT32(dma_left, ESPState),
 703         VMSTATE_END_OF_LIST()
 704     }
 705 };
 706
 707 void esp_init(target_phys_addr_t espaddr, int it_shift,
 708               ESPDMAMemoryReadWriteFunc dma_memory_read,
 709               ESPDMAMemoryReadWriteFunc dma_memory_write,
 710               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
 711               qemu_irq *dma_enable)
 712 {
 713     DeviceState *dev;
 714     SysBusDevice *s;
 715     ESPState *esp;
 716
 717     dev = qdev_create(NULL, "esp");
 718     esp = DO_UPCAST(ESPState, busdev.qdev, dev);
 719     esp->dma_memory_read = dma_memory_read;
 720     esp->dma_memory_write = dma_memory_write;
 721     esp->dma_opaque = dma_opaque;
 722     esp->it_shift = it_shift;
 723     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 724     esp->dma_enabled = 1;
 725     qdev_init_nofail(dev);
 726     s = sysbus_from_qdev(dev);
 727     sysbus_connect_irq(s, 0, irq);
 728     sysbus_mmio_map(s, 0, espaddr);
 729     *reset = qdev_get_gpio_in(dev, 0);
 730     *dma_enable = qdev_get_gpio_in(dev, 1);
 731 }
 732
 733 static const struct SCSIBusOps esp_scsi_ops = {
 734     .transfer_data = esp_transfer_data,
 735     .complete = esp_command_complete,
 736     .cancel = esp_request_cancelled
 737 };
 738
 739 static int esp_init1(SysBusDevice *dev)
 740 {
 741     ESPState *s = FROM_SYSBUS(ESPState, dev);
 742     int esp_io_memory;
 743
 744     sysbus_init_irq(dev, &s->irq);
 745     assert(s->it_shift != -1);
 746
 747     esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
 748                                            DEVICE_NATIVE_ENDIAN);
 749     sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
 750
 751     qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
 752
 753     scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, &esp_scsi_ops);
 754     return scsi_bus_legacy_handle_cmdline(&s->bus);
 755 }
 756
 757 static SysBusDeviceInfo esp_info = {
 758     .init = esp_init1,
 759     .qdev.name  = "esp",
 760     .qdev.size  = sizeof(ESPState),
 761     .qdev.vmsd  = &vmstate_esp,
 762     .qdev.reset = esp_hard_reset,
 763     .qdev.props = (Property[]) {
 764         {.name = NULL}
 765     }
 766 };
 767
 768 static void esp_register_devices(void)
 769 {
 770     sysbus_register_withprop(&esp_info);
 771 }
 772
 773 device_init(esp_register_devices)