2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_LIVENESS_ANALYSIS
27 #define USE_TCG_OPTIMIZATIONS
29 #include "qemu/osdep.h"
31 /* Define to jump the ELF file used to communicate with GDB. */
34 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
35 /* define it to suppress various consistency checks (faster) */
39 #include "qemu-common.h"
40 #include "qemu/host-utils.h"
41 #include "qemu/timer.h"
43 /* Note: the long term plan is to reduce the dependencies on the QEMU
44 CPU definitions. Currently they are used for qemu_ld/st
46 #define NO_CPU_IO_DEFS
51 #if UINTPTR_MAX == UINT32_MAX
52 # define ELF_CLASS ELFCLASS32
54 # define ELF_CLASS ELFCLASS64
56 #ifdef HOST_WORDS_BIGENDIAN
57 # define ELF_DATA ELFDATA2MSB
59 # define ELF_DATA ELFDATA2LSB
65 /* Forward declarations for functions declared in tcg-target.c and used here. */
66 static void tcg_target_init(TCGContext
*s
);
67 static void tcg_target_qemu_prologue(TCGContext
*s
);
68 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
69 intptr_t value
, intptr_t addend
);
71 /* The CIE and FDE header definitions will be common to all hosts. */
73 uint32_t len
__attribute__((aligned((sizeof(void *)))));
79 uint8_t return_column
;
82 typedef struct QEMU_PACKED
{
83 uint32_t len
__attribute__((aligned((sizeof(void *)))));
87 } DebugFrameFDEHeader
;
89 typedef struct QEMU_PACKED
{
91 DebugFrameFDEHeader fde
;
94 static void tcg_register_jit_int(void *buf
, size_t size
,
95 const void *debug_frame
,
96 size_t debug_frame_size
)
97 __attribute__((unused
));
99 /* Forward declarations for functions declared and used in tcg-target.c. */
100 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
);
101 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
103 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
104 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
105 TCGReg ret
, tcg_target_long arg
);
106 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
107 const int *const_args
);
108 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
110 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
);
111 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
112 const TCGArgConstraint
*arg_ct
);
113 static void tcg_out_tb_init(TCGContext
*s
);
114 static void tcg_out_tb_finalize(TCGContext
*s
);
118 static TCGRegSet tcg_target_available_regs
[2];
119 static TCGRegSet tcg_target_call_clobber_regs
;
121 #if TCG_TARGET_INSN_UNIT_SIZE == 1
122 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
127 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
134 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
135 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
137 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
140 tcg_insn_unit
*p
= s
->code_ptr
;
141 memcpy(p
, &v
, sizeof(v
));
142 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
146 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
149 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
152 memcpy(p
, &v
, sizeof(v
));
157 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
158 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
160 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
163 tcg_insn_unit
*p
= s
->code_ptr
;
164 memcpy(p
, &v
, sizeof(v
));
165 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
169 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
172 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
175 memcpy(p
, &v
, sizeof(v
));
180 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
181 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
183 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
186 tcg_insn_unit
*p
= s
->code_ptr
;
187 memcpy(p
, &v
, sizeof(v
));
188 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
192 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
195 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
198 memcpy(p
, &v
, sizeof(v
));
203 /* label relocation processing */
205 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
206 TCGLabel
*l
, intptr_t addend
)
211 /* FIXME: This may break relocations on RISC targets that
212 modify instruction fields in place. The caller may not have
213 written the initial value. */
214 patch_reloc(code_ptr
, type
, l
->u
.value
, addend
);
216 /* add a new relocation entry */
217 r
= tcg_malloc(sizeof(TCGRelocation
));
221 r
->next
= l
->u
.first_reloc
;
222 l
->u
.first_reloc
= r
;
226 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
, tcg_insn_unit
*ptr
)
228 intptr_t value
= (intptr_t)ptr
;
231 assert(!l
->has_value
);
233 for (r
= l
->u
.first_reloc
; r
!= NULL
; r
= r
->next
) {
234 patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
);
238 l
->u
.value_ptr
= ptr
;
241 TCGLabel
*gen_new_label(void)
243 TCGContext
*s
= &tcg_ctx
;
244 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
253 #include "tcg-target.c"
255 /* pool based memory allocation */
256 void *tcg_malloc_internal(TCGContext
*s
, int size
)
261 if (size
> TCG_POOL_CHUNK_SIZE
) {
262 /* big malloc: insert a new pool (XXX: could optimize) */
263 p
= g_malloc(sizeof(TCGPool
) + size
);
265 p
->next
= s
->pool_first_large
;
266 s
->pool_first_large
= p
;
277 pool_size
= TCG_POOL_CHUNK_SIZE
;
278 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
282 s
->pool_current
->next
= p
;
291 s
->pool_cur
= p
->data
+ size
;
292 s
->pool_end
= p
->data
+ p
->size
;
296 void tcg_pool_reset(TCGContext
*s
)
299 for (p
= s
->pool_first_large
; p
; p
= t
) {
303 s
->pool_first_large
= NULL
;
304 s
->pool_cur
= s
->pool_end
= NULL
;
305 s
->pool_current
= NULL
;
308 typedef struct TCGHelperInfo
{
315 #include "exec/helper-proto.h"
317 static const TCGHelperInfo all_helpers
[] = {
318 #include "exec/helper-tcg.h"
321 void tcg_context_init(TCGContext
*s
)
323 int op
, total_args
, n
, i
;
325 TCGArgConstraint
*args_ct
;
327 GHashTable
*helper_table
;
329 memset(s
, 0, sizeof(*s
));
332 /* Count total number of arguments and allocate the corresponding
335 for(op
= 0; op
< NB_OPS
; op
++) {
336 def
= &tcg_op_defs
[op
];
337 n
= def
->nb_iargs
+ def
->nb_oargs
;
341 args_ct
= g_malloc(sizeof(TCGArgConstraint
) * total_args
);
342 sorted_args
= g_malloc(sizeof(int) * total_args
);
344 for(op
= 0; op
< NB_OPS
; op
++) {
345 def
= &tcg_op_defs
[op
];
346 def
->args_ct
= args_ct
;
347 def
->sorted_args
= sorted_args
;
348 n
= def
->nb_iargs
+ def
->nb_oargs
;
353 /* Register helpers. */
354 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
355 s
->helpers
= helper_table
= g_hash_table_new(NULL
, NULL
);
357 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
358 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
359 (gpointer
)&all_helpers
[i
]);
365 void tcg_prologue_init(TCGContext
*s
)
367 size_t prologue_size
, total_size
;
370 /* Put the prologue at the beginning of code_gen_buffer. */
371 buf0
= s
->code_gen_buffer
;
374 s
->code_gen_prologue
= buf0
;
376 /* Generate the prologue. */
377 tcg_target_qemu_prologue(s
);
379 flush_icache_range((uintptr_t)buf0
, (uintptr_t)buf1
);
381 /* Deduct the prologue from the buffer. */
382 prologue_size
= tcg_current_code_size(s
);
383 s
->code_gen_ptr
= buf1
;
384 s
->code_gen_buffer
= buf1
;
386 total_size
= s
->code_gen_buffer_size
- prologue_size
;
387 s
->code_gen_buffer_size
= total_size
;
389 /* Compute a high-water mark, at which we voluntarily flush the buffer
390 and start over. The size here is arbitrary, significantly larger
391 than we expect the code generation for any one opcode to require. */
392 /* ??? We currently have no good estimate for, or checks in,
393 tcg_out_tb_finalize. If there are quite a lot of guest memory ops,
394 the number of out-of-line fragments could be quite high. In the
395 short-term, increase the highwater buffer. */
396 s
->code_gen_highwater
= s
->code_gen_buffer
+ (total_size
- 64*1024);
398 tcg_register_jit(s
->code_gen_buffer
, total_size
);
401 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
402 qemu_log("PROLOGUE: [size=%zu]\n", prologue_size
);
403 log_disas(buf0
, prologue_size
);
410 void tcg_set_frame(TCGContext
*s
, int reg
, intptr_t start
, intptr_t size
)
412 s
->frame_start
= start
;
413 s
->frame_end
= start
+ size
;
417 void tcg_func_start(TCGContext
*s
)
420 s
->nb_temps
= s
->nb_globals
;
422 /* No temps have been previously allocated for size or locality. */
423 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
426 s
->current_frame_offset
= s
->frame_start
;
428 #ifdef CONFIG_DEBUG_TCG
429 s
->goto_tb_issue_mask
= 0;
432 s
->gen_first_op_idx
= 0;
433 s
->gen_last_op_idx
= -1;
434 s
->gen_next_op_idx
= 0;
435 s
->gen_next_parm_idx
= 0;
437 s
->be
= tcg_malloc(sizeof(TCGBackendData
));
440 static inline void tcg_temp_alloc(TCGContext
*s
, int n
)
442 if (n
> TCG_MAX_TEMPS
)
446 static inline int tcg_global_reg_new_internal(TCGType type
, int reg
,
449 TCGContext
*s
= &tcg_ctx
;
453 #if TCG_TARGET_REG_BITS == 32
454 if (type
!= TCG_TYPE_I32
)
457 if (tcg_regset_test_reg(s
->reserved_regs
, reg
))
460 tcg_temp_alloc(s
, s
->nb_globals
+ 1);
461 ts
= &s
->temps
[s
->nb_globals
];
462 ts
->base_type
= type
;
468 tcg_regset_set_reg(s
->reserved_regs
, reg
);
472 TCGv_i32
tcg_global_reg_new_i32(int reg
, const char *name
)
476 idx
= tcg_global_reg_new_internal(TCG_TYPE_I32
, reg
, name
);
477 return MAKE_TCGV_I32(idx
);
480 TCGv_i64
tcg_global_reg_new_i64(int reg
, const char *name
)
484 idx
= tcg_global_reg_new_internal(TCG_TYPE_I64
, reg
, name
);
485 return MAKE_TCGV_I64(idx
);
488 static inline int tcg_global_mem_new_internal(TCGType type
, int reg
,
492 TCGContext
*s
= &tcg_ctx
;
497 #if TCG_TARGET_REG_BITS == 32
498 if (type
== TCG_TYPE_I64
) {
500 tcg_temp_alloc(s
, s
->nb_globals
+ 2);
501 ts
= &s
->temps
[s
->nb_globals
];
502 ts
->base_type
= type
;
503 ts
->type
= TCG_TYPE_I32
;
505 ts
->mem_allocated
= 1;
507 #ifdef HOST_WORDS_BIGENDIAN
508 ts
->mem_offset
= offset
+ 4;
510 ts
->mem_offset
= offset
;
512 pstrcpy(buf
, sizeof(buf
), name
);
513 pstrcat(buf
, sizeof(buf
), "_0");
514 ts
->name
= strdup(buf
);
517 ts
->base_type
= type
;
518 ts
->type
= TCG_TYPE_I32
;
520 ts
->mem_allocated
= 1;
522 #ifdef HOST_WORDS_BIGENDIAN
523 ts
->mem_offset
= offset
;
525 ts
->mem_offset
= offset
+ 4;
527 pstrcpy(buf
, sizeof(buf
), name
);
528 pstrcat(buf
, sizeof(buf
), "_1");
529 ts
->name
= strdup(buf
);
535 tcg_temp_alloc(s
, s
->nb_globals
+ 1);
536 ts
= &s
->temps
[s
->nb_globals
];
537 ts
->base_type
= type
;
540 ts
->mem_allocated
= 1;
542 ts
->mem_offset
= offset
;
549 TCGv_i32
tcg_global_mem_new_i32(int reg
, intptr_t offset
, const char *name
)
551 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
552 return MAKE_TCGV_I32(idx
);
555 TCGv_i64
tcg_global_mem_new_i64(int reg
, intptr_t offset
, const char *name
)
557 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
558 return MAKE_TCGV_I64(idx
);
561 static inline int tcg_temp_new_internal(TCGType type
, int temp_local
)
563 TCGContext
*s
= &tcg_ctx
;
567 k
= type
+ (temp_local
? TCG_TYPE_COUNT
: 0);
568 idx
= find_first_bit(s
->free_temps
[k
].l
, TCG_MAX_TEMPS
);
569 if (idx
< TCG_MAX_TEMPS
) {
570 /* There is already an available temp with the right type. */
571 clear_bit(idx
, s
->free_temps
[k
].l
);
574 ts
->temp_allocated
= 1;
575 assert(ts
->base_type
== type
);
576 assert(ts
->temp_local
== temp_local
);
579 #if TCG_TARGET_REG_BITS == 32
580 if (type
== TCG_TYPE_I64
) {
581 tcg_temp_alloc(s
, s
->nb_temps
+ 2);
582 ts
= &s
->temps
[s
->nb_temps
];
583 ts
->base_type
= type
;
584 ts
->type
= TCG_TYPE_I32
;
585 ts
->temp_allocated
= 1;
586 ts
->temp_local
= temp_local
;
589 ts
->base_type
= type
;
590 ts
->type
= TCG_TYPE_I32
;
591 ts
->temp_allocated
= 1;
592 ts
->temp_local
= temp_local
;
598 tcg_temp_alloc(s
, s
->nb_temps
+ 1);
599 ts
= &s
->temps
[s
->nb_temps
];
600 ts
->base_type
= type
;
602 ts
->temp_allocated
= 1;
603 ts
->temp_local
= temp_local
;
609 #if defined(CONFIG_DEBUG_TCG)
615 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
)
619 idx
= tcg_temp_new_internal(TCG_TYPE_I32
, temp_local
);
620 return MAKE_TCGV_I32(idx
);
623 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
)
627 idx
= tcg_temp_new_internal(TCG_TYPE_I64
, temp_local
);
628 return MAKE_TCGV_I64(idx
);
631 static void tcg_temp_free_internal(int idx
)
633 TCGContext
*s
= &tcg_ctx
;
637 #if defined(CONFIG_DEBUG_TCG)
639 if (s
->temps_in_use
< 0) {
640 fprintf(stderr
, "More temporaries freed than allocated!\n");
644 assert(idx
>= s
->nb_globals
&& idx
< s
->nb_temps
);
646 assert(ts
->temp_allocated
!= 0);
647 ts
->temp_allocated
= 0;
649 k
= ts
->base_type
+ (ts
->temp_local
? TCG_TYPE_COUNT
: 0);
650 set_bit(idx
, s
->free_temps
[k
].l
);
653 void tcg_temp_free_i32(TCGv_i32 arg
)
655 tcg_temp_free_internal(GET_TCGV_I32(arg
));
658 void tcg_temp_free_i64(TCGv_i64 arg
)
660 tcg_temp_free_internal(GET_TCGV_I64(arg
));
663 TCGv_i32
tcg_const_i32(int32_t val
)
666 t0
= tcg_temp_new_i32();
667 tcg_gen_movi_i32(t0
, val
);
671 TCGv_i64
tcg_const_i64(int64_t val
)
674 t0
= tcg_temp_new_i64();
675 tcg_gen_movi_i64(t0
, val
);
679 TCGv_i32
tcg_const_local_i32(int32_t val
)
682 t0
= tcg_temp_local_new_i32();
683 tcg_gen_movi_i32(t0
, val
);
687 TCGv_i64
tcg_const_local_i64(int64_t val
)
690 t0
= tcg_temp_local_new_i64();
691 tcg_gen_movi_i64(t0
, val
);
695 #if defined(CONFIG_DEBUG_TCG)
696 void tcg_clear_temp_count(void)
698 TCGContext
*s
= &tcg_ctx
;
702 int tcg_check_temp_count(void)
704 TCGContext
*s
= &tcg_ctx
;
705 if (s
->temps_in_use
) {
706 /* Clear the count so that we don't give another
707 * warning immediately next time around.
716 /* Note: we convert the 64 bit args to 32 bit and do some alignment
717 and endian swap. Maybe it would be better to do the alignment
718 and endian swap in tcg_reg_alloc_call(). */
719 void tcg_gen_callN(TCGContext
*s
, void *func
, TCGArg ret
,
720 int nargs
, TCGArg
*args
)
722 int i
, real_args
, nb_rets
, pi
, pi_first
;
723 unsigned sizemask
, flags
;
726 info
= g_hash_table_lookup(s
->helpers
, (gpointer
)func
);
728 sizemask
= info
->sizemask
;
730 #if defined(__sparc__) && !defined(__arch64__) \
731 && !defined(CONFIG_TCG_INTERPRETER)
732 /* We have 64-bit values in one register, but need to pass as two
733 separate parameters. Split them. */
734 int orig_sizemask
= sizemask
;
735 int orig_nargs
= nargs
;
738 TCGV_UNUSED_I64(retl
);
739 TCGV_UNUSED_I64(reth
);
741 TCGArg
*split_args
= __builtin_alloca(sizeof(TCGArg
) * nargs
* 2);
742 for (i
= real_args
= 0; i
< nargs
; ++i
) {
743 int is_64bit
= sizemask
& (1 << (i
+1)*2);
745 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
746 TCGv_i32 h
= tcg_temp_new_i32();
747 TCGv_i32 l
= tcg_temp_new_i32();
748 tcg_gen_extr_i64_i32(l
, h
, orig
);
749 split_args
[real_args
++] = GET_TCGV_I32(h
);
750 split_args
[real_args
++] = GET_TCGV_I32(l
);
752 split_args
[real_args
++] = args
[i
];
759 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
760 for (i
= 0; i
< nargs
; ++i
) {
761 int is_64bit
= sizemask
& (1 << (i
+1)*2);
762 int is_signed
= sizemask
& (2 << (i
+1)*2);
764 TCGv_i64 temp
= tcg_temp_new_i64();
765 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
767 tcg_gen_ext32s_i64(temp
, orig
);
769 tcg_gen_ext32u_i64(temp
, orig
);
771 args
[i
] = GET_TCGV_I64(temp
);
774 #endif /* TCG_TARGET_EXTEND_ARGS */
776 pi_first
= pi
= s
->gen_next_parm_idx
;
777 if (ret
!= TCG_CALL_DUMMY_ARG
) {
778 #if defined(__sparc__) && !defined(__arch64__) \
779 && !defined(CONFIG_TCG_INTERPRETER)
780 if (orig_sizemask
& 1) {
781 /* The 32-bit ABI is going to return the 64-bit value in
782 the %o0/%o1 register pair. Prepare for this by using
783 two return temporaries, and reassemble below. */
784 retl
= tcg_temp_new_i64();
785 reth
= tcg_temp_new_i64();
786 s
->gen_opparam_buf
[pi
++] = GET_TCGV_I64(reth
);
787 s
->gen_opparam_buf
[pi
++] = GET_TCGV_I64(retl
);
790 s
->gen_opparam_buf
[pi
++] = ret
;
794 if (TCG_TARGET_REG_BITS
< 64 && (sizemask
& 1)) {
795 #ifdef HOST_WORDS_BIGENDIAN
796 s
->gen_opparam_buf
[pi
++] = ret
+ 1;
797 s
->gen_opparam_buf
[pi
++] = ret
;
799 s
->gen_opparam_buf
[pi
++] = ret
;
800 s
->gen_opparam_buf
[pi
++] = ret
+ 1;
804 s
->gen_opparam_buf
[pi
++] = ret
;
812 for (i
= 0; i
< nargs
; i
++) {
813 int is_64bit
= sizemask
& (1 << (i
+1)*2);
814 if (TCG_TARGET_REG_BITS
< 64 && is_64bit
) {
815 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
816 /* some targets want aligned 64 bit args */
818 s
->gen_opparam_buf
[pi
++] = TCG_CALL_DUMMY_ARG
;
822 /* If stack grows up, then we will be placing successive
823 arguments at lower addresses, which means we need to
824 reverse the order compared to how we would normally
825 treat either big or little-endian. For those arguments
826 that will wind up in registers, this still works for
827 HPPA (the only current STACK_GROWSUP target) since the
828 argument registers are *also* allocated in decreasing
829 order. If another such target is added, this logic may
830 have to get more complicated to differentiate between
831 stack arguments and register arguments. */
832 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
833 s
->gen_opparam_buf
[pi
++] = args
[i
] + 1;
834 s
->gen_opparam_buf
[pi
++] = args
[i
];
836 s
->gen_opparam_buf
[pi
++] = args
[i
];
837 s
->gen_opparam_buf
[pi
++] = args
[i
] + 1;
843 s
->gen_opparam_buf
[pi
++] = args
[i
];
846 s
->gen_opparam_buf
[pi
++] = (uintptr_t)func
;
847 s
->gen_opparam_buf
[pi
++] = flags
;
849 i
= s
->gen_next_op_idx
;
850 tcg_debug_assert(i
< OPC_BUF_SIZE
);
851 tcg_debug_assert(pi
<= OPPARAM_BUF_SIZE
);
853 /* Set links for sequential allocation during translation. */
854 s
->gen_op_buf
[i
] = (TCGOp
){
855 .opc
= INDEX_op_call
,
863 /* Make sure the calli field didn't overflow. */
864 tcg_debug_assert(s
->gen_op_buf
[i
].calli
== real_args
);
866 s
->gen_last_op_idx
= i
;
867 s
->gen_next_op_idx
= i
+ 1;
868 s
->gen_next_parm_idx
= pi
;
870 #if defined(__sparc__) && !defined(__arch64__) \
871 && !defined(CONFIG_TCG_INTERPRETER)
872 /* Free all of the parts we allocated above. */
873 for (i
= real_args
= 0; i
< orig_nargs
; ++i
) {
874 int is_64bit
= orig_sizemask
& (1 << (i
+1)*2);
876 TCGv_i32 h
= MAKE_TCGV_I32(args
[real_args
++]);
877 TCGv_i32 l
= MAKE_TCGV_I32(args
[real_args
++]);
878 tcg_temp_free_i32(h
);
879 tcg_temp_free_i32(l
);
884 if (orig_sizemask
& 1) {
885 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
886 Note that describing these as TCGv_i64 eliminates an unnecessary
887 zero-extension that tcg_gen_concat_i32_i64 would create. */
888 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret
), retl
, reth
);
889 tcg_temp_free_i64(retl
);
890 tcg_temp_free_i64(reth
);
892 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
893 for (i
= 0; i
< nargs
; ++i
) {
894 int is_64bit
= sizemask
& (1 << (i
+1)*2);
896 TCGv_i64 temp
= MAKE_TCGV_I64(args
[i
]);
897 tcg_temp_free_i64(temp
);
900 #endif /* TCG_TARGET_EXTEND_ARGS */
903 static void tcg_reg_alloc_start(TCGContext
*s
)
907 for(i
= 0; i
< s
->nb_globals
; i
++) {
910 ts
->val_type
= TEMP_VAL_REG
;
912 ts
->val_type
= TEMP_VAL_MEM
;
915 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
917 if (ts
->temp_local
) {
918 ts
->val_type
= TEMP_VAL_MEM
;
920 ts
->val_type
= TEMP_VAL_DEAD
;
922 ts
->mem_allocated
= 0;
925 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
926 s
->reg_to_temp
[i
] = -1;
930 static char *tcg_get_arg_str_idx(TCGContext
*s
, char *buf
, int buf_size
,
935 assert(idx
>= 0 && idx
< s
->nb_temps
);
937 if (idx
< s
->nb_globals
) {
938 pstrcpy(buf
, buf_size
, ts
->name
);
941 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
943 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
948 char *tcg_get_arg_str_i32(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i32 arg
)
950 return tcg_get_arg_str_idx(s
, buf
, buf_size
, GET_TCGV_I32(arg
));
953 char *tcg_get_arg_str_i64(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i64 arg
)
955 return tcg_get_arg_str_idx(s
, buf
, buf_size
, GET_TCGV_I64(arg
));
958 /* Find helper name. */
959 static inline const char *tcg_find_helper(TCGContext
*s
, uintptr_t val
)
961 const char *ret
= NULL
;
963 TCGHelperInfo
*info
= g_hash_table_lookup(s
->helpers
, (gpointer
)val
);
971 static const char * const cond_name
[] =
973 [TCG_COND_NEVER
] = "never",
974 [TCG_COND_ALWAYS
] = "always",
975 [TCG_COND_EQ
] = "eq",
976 [TCG_COND_NE
] = "ne",
977 [TCG_COND_LT
] = "lt",
978 [TCG_COND_GE
] = "ge",
979 [TCG_COND_LE
] = "le",
980 [TCG_COND_GT
] = "gt",
981 [TCG_COND_LTU
] = "ltu",
982 [TCG_COND_GEU
] = "geu",
983 [TCG_COND_LEU
] = "leu",
984 [TCG_COND_GTU
] = "gtu"
987 static const char * const ldst_name
[] =
1003 void tcg_dump_ops(TCGContext
*s
)
1009 for (oi
= s
->gen_first_op_idx
; oi
>= 0; oi
= op
->next
) {
1010 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
1011 const TCGOpDef
*def
;
1015 op
= &s
->gen_op_buf
[oi
];
1017 def
= &tcg_op_defs
[c
];
1018 args
= &s
->gen_opparam_buf
[op
->args
];
1020 if (c
== INDEX_op_insn_start
) {
1021 qemu_log("%s ----", oi
!= s
->gen_first_op_idx
? "\n" : "");
1023 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
1025 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1026 a
= ((target_ulong
)args
[i
* 2 + 1] << 32) | args
[i
* 2];
1030 qemu_log(" " TARGET_FMT_lx
, a
);
1032 } else if (c
== INDEX_op_call
) {
1033 /* variable number of arguments */
1034 nb_oargs
= op
->callo
;
1035 nb_iargs
= op
->calli
;
1036 nb_cargs
= def
->nb_cargs
;
1038 /* function name, flags, out args */
1039 qemu_log(" %s %s,$0x%" TCG_PRIlx
",$%d", def
->name
,
1040 tcg_find_helper(s
, args
[nb_oargs
+ nb_iargs
]),
1041 args
[nb_oargs
+ nb_iargs
+ 1], nb_oargs
);
1042 for (i
= 0; i
< nb_oargs
; i
++) {
1043 qemu_log(",%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1046 for (i
= 0; i
< nb_iargs
; i
++) {
1047 TCGArg arg
= args
[nb_oargs
+ i
];
1048 const char *t
= "<dummy>";
1049 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1050 t
= tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), arg
);
1055 qemu_log(" %s ", def
->name
);
1057 nb_oargs
= def
->nb_oargs
;
1058 nb_iargs
= def
->nb_iargs
;
1059 nb_cargs
= def
->nb_cargs
;
1062 for (i
= 0; i
< nb_oargs
; i
++) {
1066 qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1069 for (i
= 0; i
< nb_iargs
; i
++) {
1073 qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1077 case INDEX_op_brcond_i32
:
1078 case INDEX_op_setcond_i32
:
1079 case INDEX_op_movcond_i32
:
1080 case INDEX_op_brcond2_i32
:
1081 case INDEX_op_setcond2_i32
:
1082 case INDEX_op_brcond_i64
:
1083 case INDEX_op_setcond_i64
:
1084 case INDEX_op_movcond_i64
:
1085 if (args
[k
] < ARRAY_SIZE(cond_name
) && cond_name
[args
[k
]]) {
1086 qemu_log(",%s", cond_name
[args
[k
++]]);
1088 qemu_log(",$0x%" TCG_PRIlx
, args
[k
++]);
1092 case INDEX_op_qemu_ld_i32
:
1093 case INDEX_op_qemu_st_i32
:
1094 case INDEX_op_qemu_ld_i64
:
1095 case INDEX_op_qemu_st_i64
:
1097 TCGMemOpIdx oi
= args
[k
++];
1098 TCGMemOp op
= get_memop(oi
);
1099 unsigned ix
= get_mmuidx(oi
);
1101 if (op
& ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
)) {
1102 qemu_log(",$0x%x,%u", op
, ix
);
1104 const char *s_al
= "", *s_op
;
1105 if (op
& MO_AMASK
) {
1106 if ((op
& MO_AMASK
) == MO_ALIGN
) {
1112 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
1113 qemu_log(",%s%s,%u", s_al
, s_op
, ix
);
1123 case INDEX_op_set_label
:
1125 case INDEX_op_brcond_i32
:
1126 case INDEX_op_brcond_i64
:
1127 case INDEX_op_brcond2_i32
:
1128 qemu_log("%s$L%d", k
? "," : "", arg_label(args
[k
])->id
);
1134 for (; i
< nb_cargs
; i
++, k
++) {
1135 qemu_log("%s$0x%" TCG_PRIlx
, k
? "," : "", args
[k
]);
1142 /* we give more priority to constraints with less registers */
1143 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
1145 const TCGArgConstraint
*arg_ct
;
1148 arg_ct
= &def
->args_ct
[k
];
1149 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
1150 /* an alias is equivalent to a single register */
1153 if (!(arg_ct
->ct
& TCG_CT_REG
))
1156 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1157 if (tcg_regset_test_reg(arg_ct
->u
.regs
, i
))
1161 return TCG_TARGET_NB_REGS
- n
+ 1;
1164 /* sort from highest priority to lowest */
1165 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
1167 int i
, j
, p1
, p2
, tmp
;
1169 for(i
= 0; i
< n
; i
++)
1170 def
->sorted_args
[start
+ i
] = start
+ i
;
1173 for(i
= 0; i
< n
- 1; i
++) {
1174 for(j
= i
+ 1; j
< n
; j
++) {
1175 p1
= get_constraint_priority(def
, def
->sorted_args
[start
+ i
]);
1176 p2
= get_constraint_priority(def
, def
->sorted_args
[start
+ j
]);
1178 tmp
= def
->sorted_args
[start
+ i
];
1179 def
->sorted_args
[start
+ i
] = def
->sorted_args
[start
+ j
];
1180 def
->sorted_args
[start
+ j
] = tmp
;
1186 void tcg_add_target_add_op_defs(const TCGTargetOpDef
*tdefs
)
1194 if (tdefs
->op
== (TCGOpcode
)-1)
1197 assert((unsigned)op
< NB_OPS
);
1198 def
= &tcg_op_defs
[op
];
1199 #if defined(CONFIG_DEBUG_TCG)
1200 /* Duplicate entry in op definitions? */
1204 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
1205 for(i
= 0; i
< nb_args
; i
++) {
1206 ct_str
= tdefs
->args_ct_str
[i
];
1207 /* Incomplete TCGTargetOpDef entry? */
1208 assert(ct_str
!= NULL
);
1209 tcg_regset_clear(def
->args_ct
[i
].u
.regs
);
1210 def
->args_ct
[i
].ct
= 0;
1211 if (ct_str
[0] >= '0' && ct_str
[0] <= '9') {
1213 oarg
= ct_str
[0] - '0';
1214 assert(oarg
< def
->nb_oargs
);
1215 assert(def
->args_ct
[oarg
].ct
& TCG_CT_REG
);
1216 /* TCG_CT_ALIAS is for the output arguments. The input
1217 argument is tagged with TCG_CT_IALIAS. */
1218 def
->args_ct
[i
] = def
->args_ct
[oarg
];
1219 def
->args_ct
[oarg
].ct
= TCG_CT_ALIAS
;
1220 def
->args_ct
[oarg
].alias_index
= i
;
1221 def
->args_ct
[i
].ct
|= TCG_CT_IALIAS
;
1222 def
->args_ct
[i
].alias_index
= oarg
;
1225 if (*ct_str
== '\0')
1229 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
1233 if (target_parse_constraint(&def
->args_ct
[i
], &ct_str
) < 0) {
1234 fprintf(stderr
, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1235 ct_str
, i
, def
->name
);
1243 /* TCGTargetOpDef entry with too much information? */
1244 assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
1246 /* sort the constraints (XXX: this is just an heuristic) */
1247 sort_constraints(def
, 0, def
->nb_oargs
);
1248 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
1254 printf("%s: sorted=", def
->name
);
1255 for(i
= 0; i
< def
->nb_oargs
+ def
->nb_iargs
; i
++)
1256 printf(" %d", def
->sorted_args
[i
]);
1263 #if defined(CONFIG_DEBUG_TCG)
1265 for (op
= 0; op
< tcg_op_defs_max
; op
++) {
1266 const TCGOpDef
*def
= &tcg_op_defs
[op
];
1267 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
1268 /* Wrong entry in op definitions? */
1270 fprintf(stderr
, "Invalid op definition for %s\n", def
->name
);
1274 /* Missing entry in op definitions? */
1276 fprintf(stderr
, "Missing op definition for %s\n", def
->name
);
1287 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
1289 int next
= op
->next
;
1290 int prev
= op
->prev
;
1293 s
->gen_op_buf
[next
].prev
= prev
;
1295 s
->gen_last_op_idx
= prev
;
1298 s
->gen_op_buf
[prev
].next
= next
;
1300 s
->gen_first_op_idx
= next
;
1303 memset(op
, -1, sizeof(*op
));
1305 #ifdef CONFIG_PROFILER
1310 #ifdef USE_LIVENESS_ANALYSIS
1311 /* liveness analysis: end of function: all temps are dead, and globals
1312 should be in memory. */
1313 static inline void tcg_la_func_end(TCGContext
*s
, uint8_t *dead_temps
,
1316 memset(dead_temps
, 1, s
->nb_temps
);
1317 memset(mem_temps
, 1, s
->nb_globals
);
1318 memset(mem_temps
+ s
->nb_globals
, 0, s
->nb_temps
- s
->nb_globals
);
1321 /* liveness analysis: end of basic block: all temps are dead, globals
1322 and local temps should be in memory. */
1323 static inline void tcg_la_bb_end(TCGContext
*s
, uint8_t *dead_temps
,
1328 memset(dead_temps
, 1, s
->nb_temps
);
1329 memset(mem_temps
, 1, s
->nb_globals
);
1330 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1331 mem_temps
[i
] = s
->temps
[i
].temp_local
;
1335 /* Liveness analysis : update the opc_dead_args array to tell if a
1336 given input arguments is dead. Instructions updating dead
1337 temporaries are removed. */
1338 static void tcg_liveness_analysis(TCGContext
*s
)
1340 uint8_t *dead_temps
, *mem_temps
;
1341 int oi
, oi_prev
, nb_ops
;
1343 nb_ops
= s
->gen_next_op_idx
;
1344 s
->op_dead_args
= tcg_malloc(nb_ops
* sizeof(uint16_t));
1345 s
->op_sync_args
= tcg_malloc(nb_ops
* sizeof(uint8_t));
1347 dead_temps
= tcg_malloc(s
->nb_temps
);
1348 mem_temps
= tcg_malloc(s
->nb_temps
);
1349 tcg_la_func_end(s
, dead_temps
, mem_temps
);
1351 for (oi
= s
->gen_last_op_idx
; oi
>= 0; oi
= oi_prev
) {
1352 int i
, nb_iargs
, nb_oargs
;
1353 TCGOpcode opc_new
, opc_new2
;
1359 TCGOp
* const op
= &s
->gen_op_buf
[oi
];
1360 TCGArg
* const args
= &s
->gen_opparam_buf
[op
->args
];
1361 TCGOpcode opc
= op
->opc
;
1362 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
1371 nb_oargs
= op
->callo
;
1372 nb_iargs
= op
->calli
;
1373 call_flags
= args
[nb_oargs
+ nb_iargs
+ 1];
1375 /* pure functions can be removed if their result is unused */
1376 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
1377 for (i
= 0; i
< nb_oargs
; i
++) {
1379 if (!dead_temps
[arg
] || mem_temps
[arg
]) {
1380 goto do_not_remove_call
;
1387 /* output args are dead */
1390 for (i
= 0; i
< nb_oargs
; i
++) {
1392 if (dead_temps
[arg
]) {
1393 dead_args
|= (1 << i
);
1395 if (mem_temps
[arg
]) {
1396 sync_args
|= (1 << i
);
1398 dead_temps
[arg
] = 1;
1402 if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
1403 /* globals should be synced to memory */
1404 memset(mem_temps
, 1, s
->nb_globals
);
1406 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
1407 TCG_CALL_NO_READ_GLOBALS
))) {
1408 /* globals should go back to memory */
1409 memset(dead_temps
, 1, s
->nb_globals
);
1412 /* record arguments that die in this helper */
1413 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1415 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1416 if (dead_temps
[arg
]) {
1417 dead_args
|= (1 << i
);
1421 /* input arguments are live for preceding opcodes */
1422 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1424 dead_temps
[arg
] = 0;
1426 s
->op_dead_args
[oi
] = dead_args
;
1427 s
->op_sync_args
[oi
] = sync_args
;
1431 case INDEX_op_insn_start
:
1433 case INDEX_op_discard
:
1434 /* mark the temporary as dead */
1435 dead_temps
[args
[0]] = 1;
1436 mem_temps
[args
[0]] = 0;
1439 case INDEX_op_add2_i32
:
1440 opc_new
= INDEX_op_add_i32
;
1442 case INDEX_op_sub2_i32
:
1443 opc_new
= INDEX_op_sub_i32
;
1445 case INDEX_op_add2_i64
:
1446 opc_new
= INDEX_op_add_i64
;
1448 case INDEX_op_sub2_i64
:
1449 opc_new
= INDEX_op_sub_i64
;
1453 /* Test if the high part of the operation is dead, but not
1454 the low part. The result can be optimized to a simple
1455 add or sub. This happens often for x86_64 guest when the
1456 cpu mode is set to 32 bit. */
1457 if (dead_temps
[args
[1]] && !mem_temps
[args
[1]]) {
1458 if (dead_temps
[args
[0]] && !mem_temps
[args
[0]]) {
1461 /* Replace the opcode and adjust the args in place,
1462 leaving 3 unused args at the end. */
1463 op
->opc
= opc
= opc_new
;
1466 /* Fall through and mark the single-word operation live. */
1472 case INDEX_op_mulu2_i32
:
1473 opc_new
= INDEX_op_mul_i32
;
1474 opc_new2
= INDEX_op_muluh_i32
;
1475 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
1477 case INDEX_op_muls2_i32
:
1478 opc_new
= INDEX_op_mul_i32
;
1479 opc_new2
= INDEX_op_mulsh_i32
;
1480 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
1482 case INDEX_op_mulu2_i64
:
1483 opc_new
= INDEX_op_mul_i64
;
1484 opc_new2
= INDEX_op_muluh_i64
;
1485 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
1487 case INDEX_op_muls2_i64
:
1488 opc_new
= INDEX_op_mul_i64
;
1489 opc_new2
= INDEX_op_mulsh_i64
;
1490 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
1495 if (dead_temps
[args
[1]] && !mem_temps
[args
[1]]) {
1496 if (dead_temps
[args
[0]] && !mem_temps
[args
[0]]) {
1497 /* Both parts of the operation are dead. */
1500 /* The high part of the operation is dead; generate the low. */
1501 op
->opc
= opc
= opc_new
;
1504 } else if (have_opc_new2
&& dead_temps
[args
[0]]
1505 && !mem_temps
[args
[0]]) {
1506 /* The low part of the operation is dead; generate the high. */
1507 op
->opc
= opc
= opc_new2
;
1514 /* Mark the single-word operation live. */
1519 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
1520 nb_iargs
= def
->nb_iargs
;
1521 nb_oargs
= def
->nb_oargs
;
1523 /* Test if the operation can be removed because all
1524 its outputs are dead. We assume that nb_oargs == 0
1525 implies side effects */
1526 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
1527 for (i
= 0; i
< nb_oargs
; i
++) {
1529 if (!dead_temps
[arg
] || mem_temps
[arg
]) {
1534 tcg_op_remove(s
, op
);
1537 /* output args are dead */
1540 for (i
= 0; i
< nb_oargs
; i
++) {
1542 if (dead_temps
[arg
]) {
1543 dead_args
|= (1 << i
);
1545 if (mem_temps
[arg
]) {
1546 sync_args
|= (1 << i
);
1548 dead_temps
[arg
] = 1;
1552 /* if end of basic block, update */
1553 if (def
->flags
& TCG_OPF_BB_END
) {
1554 tcg_la_bb_end(s
, dead_temps
, mem_temps
);
1555 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
1556 /* globals should be synced to memory */
1557 memset(mem_temps
, 1, s
->nb_globals
);
1560 /* record arguments that die in this opcode */
1561 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1563 if (dead_temps
[arg
]) {
1564 dead_args
|= (1 << i
);
1567 /* input arguments are live for preceding opcodes */
1568 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1570 dead_temps
[arg
] = 0;
1572 s
->op_dead_args
[oi
] = dead_args
;
1573 s
->op_sync_args
[oi
] = sync_args
;
1580 /* dummy liveness analysis */
1581 static void tcg_liveness_analysis(TCGContext
*s
)
1584 nb_ops
= s
->gen_opc_ptr
- s
->gen_opc_buf
;
1586 s
->op_dead_args
= tcg_malloc(nb_ops
* sizeof(uint16_t));
1587 memset(s
->op_dead_args
, 0, nb_ops
* sizeof(uint16_t));
1588 s
->op_sync_args
= tcg_malloc(nb_ops
* sizeof(uint8_t));
1589 memset(s
->op_sync_args
, 0, nb_ops
* sizeof(uint8_t));
1594 static void dump_regs(TCGContext
*s
)
1600 for(i
= 0; i
< s
->nb_temps
; i
++) {
1602 printf(" %10s: ", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), i
));
1603 switch(ts
->val_type
) {
1605 printf("%s", tcg_target_reg_names
[ts
->reg
]);
1608 printf("%d(%s)", (int)ts
->mem_offset
, tcg_target_reg_names
[ts
->mem_reg
]);
1610 case TEMP_VAL_CONST
:
1611 printf("$0x%" TCG_PRIlx
, ts
->val
);
1623 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1624 if (s
->reg_to_temp
[i
] >= 0) {
1626 tcg_target_reg_names
[i
],
1627 tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), s
->reg_to_temp
[i
]));
1632 static void check_regs(TCGContext
*s
)
1638 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
1639 k
= s
->reg_to_temp
[reg
];
1642 if (ts
->val_type
!= TEMP_VAL_REG
||
1644 printf("Inconsistency for register %s:\n",
1645 tcg_target_reg_names
[reg
]);
1650 for(k
= 0; k
< s
->nb_temps
; k
++) {
1652 if (ts
->val_type
== TEMP_VAL_REG
&&
1654 s
->reg_to_temp
[ts
->reg
] != k
) {
1655 printf("Inconsistency for temp %s:\n",
1656 tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), k
));
1658 printf("reg state:\n");
1666 static void temp_allocate_frame(TCGContext
*s
, int temp
)
1669 ts
= &s
->temps
[temp
];
1670 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1671 /* Sparc64 stack is accessed with offset of 2047 */
1672 s
->current_frame_offset
= (s
->current_frame_offset
+
1673 (tcg_target_long
)sizeof(tcg_target_long
) - 1) &
1674 ~(sizeof(tcg_target_long
) - 1);
1676 if (s
->current_frame_offset
+ (tcg_target_long
)sizeof(tcg_target_long
) >
1680 ts
->mem_offset
= s
->current_frame_offset
;
1681 ts
->mem_reg
= s
->frame_reg
;
1682 ts
->mem_allocated
= 1;
1683 s
->current_frame_offset
+= sizeof(tcg_target_long
);
1686 /* sync register 'reg' by saving it to the corresponding temporary */
1687 static inline void tcg_reg_sync(TCGContext
*s
, int reg
)
1692 temp
= s
->reg_to_temp
[reg
];
1693 ts
= &s
->temps
[temp
];
1694 assert(ts
->val_type
== TEMP_VAL_REG
);
1695 if (!ts
->mem_coherent
&& !ts
->fixed_reg
) {
1696 if (!ts
->mem_allocated
) {
1697 temp_allocate_frame(s
, temp
);
1699 tcg_out_st(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
1701 ts
->mem_coherent
= 1;
1704 /* free register 'reg' by spilling the corresponding temporary if necessary */
1705 static void tcg_reg_free(TCGContext
*s
, int reg
)
1709 temp
= s
->reg_to_temp
[reg
];
1711 tcg_reg_sync(s
, reg
);
1712 s
->temps
[temp
].val_type
= TEMP_VAL_MEM
;
1713 s
->reg_to_temp
[reg
] = -1;
1717 /* Allocate a register belonging to reg1 & ~reg2 */
1718 static int tcg_reg_alloc(TCGContext
*s
, TCGRegSet reg1
, TCGRegSet reg2
)
1723 tcg_regset_andnot(reg_ct
, reg1
, reg2
);
1725 /* first try free registers */
1726 for(i
= 0; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); i
++) {
1727 reg
= tcg_target_reg_alloc_order
[i
];
1728 if (tcg_regset_test_reg(reg_ct
, reg
) && s
->reg_to_temp
[reg
] == -1)
1732 /* XXX: do better spill choice */
1733 for(i
= 0; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); i
++) {
1734 reg
= tcg_target_reg_alloc_order
[i
];
1735 if (tcg_regset_test_reg(reg_ct
, reg
)) {
1736 tcg_reg_free(s
, reg
);
1744 /* mark a temporary as dead. */
1745 static inline void temp_dead(TCGContext
*s
, int temp
)
1749 ts
= &s
->temps
[temp
];
1750 if (!ts
->fixed_reg
) {
1751 if (ts
->val_type
== TEMP_VAL_REG
) {
1752 s
->reg_to_temp
[ts
->reg
] = -1;
1754 if (temp
< s
->nb_globals
|| ts
->temp_local
) {
1755 ts
->val_type
= TEMP_VAL_MEM
;
1757 ts
->val_type
= TEMP_VAL_DEAD
;
1762 /* sync a temporary to memory. 'allocated_regs' is used in case a
1763 temporary registers needs to be allocated to store a constant. */
1764 static inline void temp_sync(TCGContext
*s
, int temp
, TCGRegSet allocated_regs
)
1768 ts
= &s
->temps
[temp
];
1769 if (!ts
->fixed_reg
) {
1770 switch(ts
->val_type
) {
1771 case TEMP_VAL_CONST
:
1772 ts
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
1774 ts
->val_type
= TEMP_VAL_REG
;
1775 s
->reg_to_temp
[ts
->reg
] = temp
;
1776 ts
->mem_coherent
= 0;
1777 tcg_out_movi(s
, ts
->type
, ts
->reg
, ts
->val
);
1780 tcg_reg_sync(s
, ts
->reg
);
1791 /* save a temporary to memory. 'allocated_regs' is used in case a
1792 temporary registers needs to be allocated to store a constant. */
1793 static inline void temp_save(TCGContext
*s
, int temp
, TCGRegSet allocated_regs
)
1795 #ifdef USE_LIVENESS_ANALYSIS
1796 /* The liveness analysis already ensures that globals are back
1797 in memory. Keep an assert for safety. */
1798 assert(s
->temps
[temp
].val_type
== TEMP_VAL_MEM
|| s
->temps
[temp
].fixed_reg
);
1800 temp_sync(s
, temp
, allocated_regs
);
1805 /* save globals to their canonical location and assume they can be
1806 modified be the following code. 'allocated_regs' is used in case a
1807 temporary registers needs to be allocated to store a constant. */
1808 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
1812 for(i
= 0; i
< s
->nb_globals
; i
++) {
1813 temp_save(s
, i
, allocated_regs
);
1817 /* sync globals to their canonical location and assume they can be
1818 read by the following code. 'allocated_regs' is used in case a
1819 temporary registers needs to be allocated to store a constant. */
1820 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
1824 for (i
= 0; i
< s
->nb_globals
; i
++) {
1825 #ifdef USE_LIVENESS_ANALYSIS
1826 assert(s
->temps
[i
].val_type
!= TEMP_VAL_REG
|| s
->temps
[i
].fixed_reg
||
1827 s
->temps
[i
].mem_coherent
);
1829 temp_sync(s
, i
, allocated_regs
);
1834 /* at the end of a basic block, we assume all temporaries are dead and
1835 all globals are stored at their canonical location. */
1836 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
1841 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1843 if (ts
->temp_local
) {
1844 temp_save(s
, i
, allocated_regs
);
1846 #ifdef USE_LIVENESS_ANALYSIS
1847 /* The liveness analysis already ensures that temps are dead.
1848 Keep an assert for safety. */
1849 assert(ts
->val_type
== TEMP_VAL_DEAD
);
1856 save_globals(s
, allocated_regs
);
1859 #define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
1860 #define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
1862 static void tcg_reg_alloc_movi(TCGContext
*s
, const TCGArg
*args
,
1863 uint16_t dead_args
, uint8_t sync_args
)
1866 tcg_target_ulong val
;
1868 ots
= &s
->temps
[args
[0]];
1871 if (ots
->fixed_reg
) {
1872 /* for fixed registers, we do not do any constant
1874 tcg_out_movi(s
, ots
->type
, ots
->reg
, val
);
1876 /* The movi is not explicitly generated here */
1877 if (ots
->val_type
== TEMP_VAL_REG
)
1878 s
->reg_to_temp
[ots
->reg
] = -1;
1879 ots
->val_type
= TEMP_VAL_CONST
;
1882 if (NEED_SYNC_ARG(0)) {
1883 temp_sync(s
, args
[0], s
->reserved_regs
);
1885 if (IS_DEAD_ARG(0)) {
1886 temp_dead(s
, args
[0]);
1890 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOpDef
*def
,
1891 const TCGArg
*args
, uint16_t dead_args
,
1894 TCGRegSet allocated_regs
;
1896 TCGType otype
, itype
;
1898 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
1899 ots
= &s
->temps
[args
[0]];
1900 ts
= &s
->temps
[args
[1]];
1902 /* Note that otype != itype for no-op truncation. */
1906 /* If the source value is not in a register, and we're going to be
1907 forced to have it in a register in order to perform the copy,
1908 then copy the SOURCE value into its own register first. That way
1909 we don't have to reload SOURCE the next time it is used. */
1910 if (((NEED_SYNC_ARG(0) || ots
->fixed_reg
) && ts
->val_type
!= TEMP_VAL_REG
)
1911 || ts
->val_type
== TEMP_VAL_MEM
) {
1912 ts
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[itype
],
1914 if (ts
->val_type
== TEMP_VAL_MEM
) {
1915 tcg_out_ld(s
, itype
, ts
->reg
, ts
->mem_reg
, ts
->mem_offset
);
1916 ts
->mem_coherent
= 1;
1917 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
1918 tcg_out_movi(s
, itype
, ts
->reg
, ts
->val
);
1919 ts
->mem_coherent
= 0;
1921 s
->reg_to_temp
[ts
->reg
] = args
[1];
1922 ts
->val_type
= TEMP_VAL_REG
;
1925 if (IS_DEAD_ARG(0) && !ots
->fixed_reg
) {
1926 /* mov to a non-saved dead register makes no sense (even with
1927 liveness analysis disabled). */
1928 assert(NEED_SYNC_ARG(0));
1929 /* The code above should have moved the temp to a register. */
1930 assert(ts
->val_type
== TEMP_VAL_REG
);
1931 if (!ots
->mem_allocated
) {
1932 temp_allocate_frame(s
, args
[0]);
1934 tcg_out_st(s
, otype
, ts
->reg
, ots
->mem_reg
, ots
->mem_offset
);
1935 if (IS_DEAD_ARG(1)) {
1936 temp_dead(s
, args
[1]);
1938 temp_dead(s
, args
[0]);
1939 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
1940 /* propagate constant */
1941 if (ots
->val_type
== TEMP_VAL_REG
) {
1942 s
->reg_to_temp
[ots
->reg
] = -1;
1944 ots
->val_type
= TEMP_VAL_CONST
;
1946 if (IS_DEAD_ARG(1)) {
1947 temp_dead(s
, args
[1]);
1950 /* The code in the first if block should have moved the
1951 temp to a register. */
1952 assert(ts
->val_type
== TEMP_VAL_REG
);
1953 if (IS_DEAD_ARG(1) && !ts
->fixed_reg
&& !ots
->fixed_reg
) {
1954 /* the mov can be suppressed */
1955 if (ots
->val_type
== TEMP_VAL_REG
) {
1956 s
->reg_to_temp
[ots
->reg
] = -1;
1959 temp_dead(s
, args
[1]);
1961 if (ots
->val_type
!= TEMP_VAL_REG
) {
1962 /* When allocating a new register, make sure to not spill the
1964 tcg_regset_set_reg(allocated_regs
, ts
->reg
);
1965 ots
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
1968 tcg_out_mov(s
, otype
, ots
->reg
, ts
->reg
);
1970 ots
->val_type
= TEMP_VAL_REG
;
1971 ots
->mem_coherent
= 0;
1972 s
->reg_to_temp
[ots
->reg
] = args
[0];
1973 if (NEED_SYNC_ARG(0)) {
1974 tcg_reg_sync(s
, ots
->reg
);
1979 static void tcg_reg_alloc_op(TCGContext
*s
,
1980 const TCGOpDef
*def
, TCGOpcode opc
,
1981 const TCGArg
*args
, uint16_t dead_args
,
1984 TCGRegSet allocated_regs
;
1985 int i
, k
, nb_iargs
, nb_oargs
, reg
;
1987 const TCGArgConstraint
*arg_ct
;
1989 TCGArg new_args
[TCG_MAX_OP_ARGS
];
1990 int const_args
[TCG_MAX_OP_ARGS
];
1992 nb_oargs
= def
->nb_oargs
;
1993 nb_iargs
= def
->nb_iargs
;
1995 /* copy constants */
1996 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
1997 args
+ nb_oargs
+ nb_iargs
,
1998 sizeof(TCGArg
) * def
->nb_cargs
);
2000 /* satisfy input constraints */
2001 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2002 for(k
= 0; k
< nb_iargs
; k
++) {
2003 i
= def
->sorted_args
[nb_oargs
+ k
];
2005 arg_ct
= &def
->args_ct
[i
];
2006 ts
= &s
->temps
[arg
];
2007 if (ts
->val_type
== TEMP_VAL_MEM
) {
2008 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2009 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2010 ts
->val_type
= TEMP_VAL_REG
;
2012 ts
->mem_coherent
= 1;
2013 s
->reg_to_temp
[reg
] = arg
;
2014 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2015 if (tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
)) {
2016 /* constant is OK for instruction */
2018 new_args
[i
] = ts
->val
;
2021 /* need to move to a register */
2022 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2023 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2024 ts
->val_type
= TEMP_VAL_REG
;
2026 ts
->mem_coherent
= 0;
2027 s
->reg_to_temp
[reg
] = arg
;
2030 assert(ts
->val_type
== TEMP_VAL_REG
);
2031 if (arg_ct
->ct
& TCG_CT_IALIAS
) {
2032 if (ts
->fixed_reg
) {
2033 /* if fixed register, we must allocate a new register
2034 if the alias is not the same register */
2035 if (arg
!= args
[arg_ct
->alias_index
])
2036 goto allocate_in_reg
;
2038 /* if the input is aliased to an output and if it is
2039 not dead after the instruction, we must allocate
2040 a new register and move it */
2041 if (!IS_DEAD_ARG(i
)) {
2042 goto allocate_in_reg
;
2044 /* check if the current register has already been allocated
2045 for another input aliased to an output */
2047 for (k2
= 0 ; k2
< k
; k2
++) {
2048 i2
= def
->sorted_args
[nb_oargs
+ k2
];
2049 if ((def
->args_ct
[i2
].ct
& TCG_CT_IALIAS
) &&
2050 (new_args
[i2
] == ts
->reg
)) {
2051 goto allocate_in_reg
;
2057 if (tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2058 /* nothing to do : the constraint is satisfied */
2061 /* allocate a new register matching the constraint
2062 and move the temporary register into it */
2063 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2064 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2068 tcg_regset_set_reg(allocated_regs
, reg
);
2072 /* mark dead temporaries and free the associated registers */
2073 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
2074 if (IS_DEAD_ARG(i
)) {
2075 temp_dead(s
, args
[i
]);
2079 if (def
->flags
& TCG_OPF_BB_END
) {
2080 tcg_reg_alloc_bb_end(s
, allocated_regs
);
2082 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
2083 /* XXX: permit generic clobber register list ? */
2084 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
2085 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, reg
)) {
2086 tcg_reg_free(s
, reg
);
2090 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
2091 /* sync globals if the op has side effects and might trigger
2093 sync_globals(s
, allocated_regs
);
2096 /* satisfy the output constraints */
2097 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2098 for(k
= 0; k
< nb_oargs
; k
++) {
2099 i
= def
->sorted_args
[k
];
2101 arg_ct
= &def
->args_ct
[i
];
2102 ts
= &s
->temps
[arg
];
2103 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
2104 reg
= new_args
[arg_ct
->alias_index
];
2106 /* if fixed register, we try to use it */
2108 if (ts
->fixed_reg
&&
2109 tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2112 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2114 tcg_regset_set_reg(allocated_regs
, reg
);
2115 /* if a fixed register is used, then a move will be done afterwards */
2116 if (!ts
->fixed_reg
) {
2117 if (ts
->val_type
== TEMP_VAL_REG
) {
2118 s
->reg_to_temp
[ts
->reg
] = -1;
2120 ts
->val_type
= TEMP_VAL_REG
;
2122 /* temp value is modified, so the value kept in memory is
2123 potentially not the same */
2124 ts
->mem_coherent
= 0;
2125 s
->reg_to_temp
[reg
] = arg
;
2132 /* emit instruction */
2133 tcg_out_op(s
, opc
, new_args
, const_args
);
2135 /* move the outputs in the correct register if needed */
2136 for(i
= 0; i
< nb_oargs
; i
++) {
2137 ts
= &s
->temps
[args
[i
]];
2139 if (ts
->fixed_reg
&& ts
->reg
!= reg
) {
2140 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2142 if (NEED_SYNC_ARG(i
)) {
2143 tcg_reg_sync(s
, reg
);
2145 if (IS_DEAD_ARG(i
)) {
2146 temp_dead(s
, args
[i
]);
2151 #ifdef TCG_TARGET_STACK_GROWSUP
2152 #define STACK_DIR(x) (-(x))
2154 #define STACK_DIR(x) (x)
2157 static void tcg_reg_alloc_call(TCGContext
*s
, int nb_oargs
, int nb_iargs
,
2158 const TCGArg
* const args
, uint16_t dead_args
,
2161 int flags
, nb_regs
, i
, reg
;
2164 intptr_t stack_offset
;
2165 size_t call_stack_size
;
2166 tcg_insn_unit
*func_addr
;
2168 TCGRegSet allocated_regs
;
2170 func_addr
= (tcg_insn_unit
*)(intptr_t)args
[nb_oargs
+ nb_iargs
];
2171 flags
= args
[nb_oargs
+ nb_iargs
+ 1];
2173 nb_regs
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
2174 if (nb_regs
> nb_iargs
) {
2178 /* assign stack slots first */
2179 call_stack_size
= (nb_iargs
- nb_regs
) * sizeof(tcg_target_long
);
2180 call_stack_size
= (call_stack_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
2181 ~(TCG_TARGET_STACK_ALIGN
- 1);
2182 allocate_args
= (call_stack_size
> TCG_STATIC_CALL_ARGS_SIZE
);
2183 if (allocate_args
) {
2184 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2185 preallocate call stack */
2189 stack_offset
= TCG_TARGET_CALL_STACK_OFFSET
;
2190 for(i
= nb_regs
; i
< nb_iargs
; i
++) {
2191 arg
= args
[nb_oargs
+ i
];
2192 #ifdef TCG_TARGET_STACK_GROWSUP
2193 stack_offset
-= sizeof(tcg_target_long
);
2195 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2196 ts
= &s
->temps
[arg
];
2197 if (ts
->val_type
== TEMP_VAL_REG
) {
2198 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
, stack_offset
);
2199 } else if (ts
->val_type
== TEMP_VAL_MEM
) {
2200 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
2202 /* XXX: not correct if reading values from the stack */
2203 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2204 tcg_out_st(s
, ts
->type
, reg
, TCG_REG_CALL_STACK
, stack_offset
);
2205 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2206 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
2208 /* XXX: sign extend may be needed on some targets */
2209 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2210 tcg_out_st(s
, ts
->type
, reg
, TCG_REG_CALL_STACK
, stack_offset
);
2215 #ifndef TCG_TARGET_STACK_GROWSUP
2216 stack_offset
+= sizeof(tcg_target_long
);
2220 /* assign input registers */
2221 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2222 for(i
= 0; i
< nb_regs
; i
++) {
2223 arg
= args
[nb_oargs
+ i
];
2224 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2225 ts
= &s
->temps
[arg
];
2226 reg
= tcg_target_call_iarg_regs
[i
];
2227 tcg_reg_free(s
, reg
);
2228 if (ts
->val_type
== TEMP_VAL_REG
) {
2229 if (ts
->reg
!= reg
) {
2230 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2232 } else if (ts
->val_type
== TEMP_VAL_MEM
) {
2233 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2234 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2235 /* XXX: sign extend ? */
2236 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2240 tcg_regset_set_reg(allocated_regs
, reg
);
2244 /* mark dead temporaries and free the associated registers */
2245 for(i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
2246 if (IS_DEAD_ARG(i
)) {
2247 temp_dead(s
, args
[i
]);
2251 /* clobber call registers */
2252 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
2253 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, reg
)) {
2254 tcg_reg_free(s
, reg
);
2258 /* Save globals if they might be written by the helper, sync them if
2259 they might be read. */
2260 if (flags
& TCG_CALL_NO_READ_GLOBALS
) {
2262 } else if (flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
2263 sync_globals(s
, allocated_regs
);
2265 save_globals(s
, allocated_regs
);
2268 tcg_out_call(s
, func_addr
);
2270 /* assign output registers and emit moves if needed */
2271 for(i
= 0; i
< nb_oargs
; i
++) {
2273 ts
= &s
->temps
[arg
];
2274 reg
= tcg_target_call_oarg_regs
[i
];
2275 assert(s
->reg_to_temp
[reg
] == -1);
2277 if (ts
->fixed_reg
) {
2278 if (ts
->reg
!= reg
) {
2279 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2282 if (ts
->val_type
== TEMP_VAL_REG
) {
2283 s
->reg_to_temp
[ts
->reg
] = -1;
2285 ts
->val_type
= TEMP_VAL_REG
;
2287 ts
->mem_coherent
= 0;
2288 s
->reg_to_temp
[reg
] = arg
;
2289 if (NEED_SYNC_ARG(i
)) {
2290 tcg_reg_sync(s
, reg
);
2292 if (IS_DEAD_ARG(i
)) {
2293 temp_dead(s
, args
[i
]);
2299 #ifdef CONFIG_PROFILER
2301 static int64_t tcg_table_op_count
[NB_OPS
];
2303 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
)
2307 for (i
= 0; i
< NB_OPS
; i
++) {
2308 cpu_fprintf(f
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
2309 tcg_table_op_count
[i
]);
2313 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
)
2315 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2320 int tcg_gen_code(TCGContext
*s
, tcg_insn_unit
*gen_code_buf
)
2322 int i
, oi
, oi_next
, num_insns
;
2324 #ifdef CONFIG_PROFILER
2328 n
= s
->gen_last_op_idx
+ 1;
2330 if (n
> s
->op_count_max
) {
2331 s
->op_count_max
= n
;
2336 if (n
> s
->temp_count_max
) {
2337 s
->temp_count_max
= n
;
2343 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2350 #ifdef CONFIG_PROFILER
2351 s
->opt_time
-= profile_getclock();
2354 #ifdef USE_TCG_OPTIMIZATIONS
2358 #ifdef CONFIG_PROFILER
2359 s
->opt_time
+= profile_getclock();
2360 s
->la_time
-= profile_getclock();
2363 tcg_liveness_analysis(s
);
2365 #ifdef CONFIG_PROFILER
2366 s
->la_time
+= profile_getclock();
2370 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
))) {
2371 qemu_log("OP after optimization and liveness analysis:\n");
2377 tcg_reg_alloc_start(s
);
2379 s
->code_buf
= gen_code_buf
;
2380 s
->code_ptr
= gen_code_buf
;
2385 for (oi
= s
->gen_first_op_idx
; oi
>= 0; oi
= oi_next
) {
2386 TCGOp
* const op
= &s
->gen_op_buf
[oi
];
2387 TCGArg
* const args
= &s
->gen_opparam_buf
[op
->args
];
2388 TCGOpcode opc
= op
->opc
;
2389 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
2390 uint16_t dead_args
= s
->op_dead_args
[oi
];
2391 uint8_t sync_args
= s
->op_sync_args
[oi
];
2394 #ifdef CONFIG_PROFILER
2395 tcg_table_op_count
[opc
]++;
2399 case INDEX_op_mov_i32
:
2400 case INDEX_op_mov_i64
:
2401 tcg_reg_alloc_mov(s
, def
, args
, dead_args
, sync_args
);
2403 case INDEX_op_movi_i32
:
2404 case INDEX_op_movi_i64
:
2405 tcg_reg_alloc_movi(s
, args
, dead_args
, sync_args
);
2407 case INDEX_op_insn_start
:
2408 if (num_insns
>= 0) {
2409 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
2412 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
2414 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2415 a
= ((target_ulong
)args
[i
* 2 + 1] << 32) | args
[i
* 2];
2419 s
->gen_insn_data
[num_insns
][i
] = a
;
2422 case INDEX_op_discard
:
2423 temp_dead(s
, args
[0]);
2425 case INDEX_op_set_label
:
2426 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
2427 tcg_out_label(s
, arg_label(args
[0]), s
->code_ptr
);
2430 tcg_reg_alloc_call(s
, op
->callo
, op
->calli
, args
,
2431 dead_args
, sync_args
);
2434 /* Sanity check that we've not introduced any unhandled opcodes. */
2435 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2438 /* Note: in order to speed up the code, it would be much
2439 faster to have specialized register allocator functions for
2440 some common argument patterns */
2441 tcg_reg_alloc_op(s
, def
, opc
, args
, dead_args
, sync_args
);
2447 /* Test for (pending) buffer overflow. The assumption is that any
2448 one operation beginning below the high water mark cannot overrun
2449 the buffer completely. Thus we can test for overflow after
2450 generating code without having to check during generation. */
2451 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
2455 tcg_debug_assert(num_insns
>= 0);
2456 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
2458 /* Generate TB finalization at the end of block */
2459 tcg_out_tb_finalize(s
);
2461 /* flush instruction cache */
2462 flush_icache_range((uintptr_t)s
->code_buf
, (uintptr_t)s
->code_ptr
);
2464 return tcg_current_code_size(s
);
2467 #ifdef CONFIG_PROFILER
2468 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2470 TCGContext
*s
= &tcg_ctx
;
2471 int64_t tb_count
= s
->tb_count
;
2472 int64_t tb_div_count
= tb_count
? tb_count
: 1;
2473 int64_t tot
= s
->interm_time
+ s
->code_time
;
2475 cpu_fprintf(f
, "JIT cycles %" PRId64
" (%0.3f s at 2.4 GHz)\n",
2477 cpu_fprintf(f
, "translated TBs %" PRId64
" (aborted=%" PRId64
" %0.1f%%)\n",
2478 tb_count
, s
->tb_count1
- tb_count
,
2479 (double)(s
->tb_count1
- s
->tb_count
)
2480 / (s
->tb_count1
? s
->tb_count1
: 1) * 100.0);
2481 cpu_fprintf(f
, "avg ops/TB %0.1f max=%d\n",
2482 (double)s
->op_count
/ tb_div_count
, s
->op_count_max
);
2483 cpu_fprintf(f
, "deleted ops/TB %0.2f\n",
2484 (double)s
->del_op_count
/ tb_div_count
);
2485 cpu_fprintf(f
, "avg temps/TB %0.2f max=%d\n",
2486 (double)s
->temp_count
/ tb_div_count
, s
->temp_count_max
);
2487 cpu_fprintf(f
, "avg host code/TB %0.1f\n",
2488 (double)s
->code_out_len
/ tb_div_count
);
2489 cpu_fprintf(f
, "avg search data/TB %0.1f\n",
2490 (double)s
->search_out_len
/ tb_div_count
);
2492 cpu_fprintf(f
, "cycles/op %0.1f\n",
2493 s
->op_count
? (double)tot
/ s
->op_count
: 0);
2494 cpu_fprintf(f
, "cycles/in byte %0.1f\n",
2495 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
2496 cpu_fprintf(f
, "cycles/out byte %0.1f\n",
2497 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
2498 cpu_fprintf(f
, "cycles/search byte %0.1f\n",
2499 s
->search_out_len
? (double)tot
/ s
->search_out_len
: 0);
2503 cpu_fprintf(f
, " gen_interm time %0.1f%%\n",
2504 (double)s
->interm_time
/ tot
* 100.0);
2505 cpu_fprintf(f
, " gen_code time %0.1f%%\n",
2506 (double)s
->code_time
/ tot
* 100.0);
2507 cpu_fprintf(f
, "optim./code time %0.1f%%\n",
2508 (double)s
->opt_time
/ (s
->code_time
? s
->code_time
: 1)
2510 cpu_fprintf(f
, "liveness/code time %0.1f%%\n",
2511 (double)s
->la_time
/ (s
->code_time
? s
->code_time
: 1) * 100.0);
2512 cpu_fprintf(f
, "cpu_restore count %" PRId64
"\n",
2514 cpu_fprintf(f
, " avg cycles %0.1f\n",
2515 s
->restore_count
? (double)s
->restore_time
/ s
->restore_count
: 0);
2518 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2520 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2524 #ifdef ELF_HOST_MACHINE
2525 /* In order to use this feature, the backend needs to do three things:
2527 (1) Define ELF_HOST_MACHINE to indicate both what value to
2528 put into the ELF image and to indicate support for the feature.
2530 (2) Define tcg_register_jit. This should create a buffer containing
2531 the contents of a .debug_frame section that describes the post-
2532 prologue unwind info for the tcg machine.
2534 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2537 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2544 struct jit_code_entry
{
2545 struct jit_code_entry
*next_entry
;
2546 struct jit_code_entry
*prev_entry
;
2547 const void *symfile_addr
;
2548 uint64_t symfile_size
;
2551 struct jit_descriptor
{
2553 uint32_t action_flag
;
2554 struct jit_code_entry
*relevant_entry
;
2555 struct jit_code_entry
*first_entry
;
2558 void __jit_debug_register_code(void) __attribute__((noinline
));
2559 void __jit_debug_register_code(void)
2564 /* Must statically initialize the version, because GDB may check
2565 the version before we can set it. */
2566 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
2568 /* End GDB interface. */
2570 static int find_string(const char *strtab
, const char *str
)
2572 const char *p
= strtab
+ 1;
2575 if (strcmp(p
, str
) == 0) {
2582 static void tcg_register_jit_int(void *buf_ptr
, size_t buf_size
,
2583 const void *debug_frame
,
2584 size_t debug_frame_size
)
2586 struct __attribute__((packed
)) DebugInfo
{
2593 uintptr_t cu_low_pc
;
2594 uintptr_t cu_high_pc
;
2597 uintptr_t fn_low_pc
;
2598 uintptr_t fn_high_pc
;
2607 struct DebugInfo di
;
2612 struct ElfImage
*img
;
2614 static const struct ElfImage img_template
= {
2616 .e_ident
[EI_MAG0
] = ELFMAG0
,
2617 .e_ident
[EI_MAG1
] = ELFMAG1
,
2618 .e_ident
[EI_MAG2
] = ELFMAG2
,
2619 .e_ident
[EI_MAG3
] = ELFMAG3
,
2620 .e_ident
[EI_CLASS
] = ELF_CLASS
,
2621 .e_ident
[EI_DATA
] = ELF_DATA
,
2622 .e_ident
[EI_VERSION
] = EV_CURRENT
,
2624 .e_machine
= ELF_HOST_MACHINE
,
2625 .e_version
= EV_CURRENT
,
2626 .e_phoff
= offsetof(struct ElfImage
, phdr
),
2627 .e_shoff
= offsetof(struct ElfImage
, shdr
),
2628 .e_ehsize
= sizeof(ElfW(Shdr
)),
2629 .e_phentsize
= sizeof(ElfW(Phdr
)),
2631 .e_shentsize
= sizeof(ElfW(Shdr
)),
2632 .e_shnum
= ARRAY_SIZE(img
->shdr
),
2633 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
2634 #ifdef ELF_HOST_FLAGS
2635 .e_flags
= ELF_HOST_FLAGS
,
2638 .e_ident
[EI_OSABI
] = ELF_OSABI
,
2646 [0] = { .sh_type
= SHT_NULL
},
2647 /* Trick: The contents of code_gen_buffer are not present in
2648 this fake ELF file; that got allocated elsewhere. Therefore
2649 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2650 will not look for contents. We can record any address. */
2652 .sh_type
= SHT_NOBITS
,
2653 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
2655 [2] = { /* .debug_info */
2656 .sh_type
= SHT_PROGBITS
,
2657 .sh_offset
= offsetof(struct ElfImage
, di
),
2658 .sh_size
= sizeof(struct DebugInfo
),
2660 [3] = { /* .debug_abbrev */
2661 .sh_type
= SHT_PROGBITS
,
2662 .sh_offset
= offsetof(struct ElfImage
, da
),
2663 .sh_size
= sizeof(img
->da
),
2665 [4] = { /* .debug_frame */
2666 .sh_type
= SHT_PROGBITS
,
2667 .sh_offset
= sizeof(struct ElfImage
),
2669 [5] = { /* .symtab */
2670 .sh_type
= SHT_SYMTAB
,
2671 .sh_offset
= offsetof(struct ElfImage
, sym
),
2672 .sh_size
= sizeof(img
->sym
),
2674 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
2675 .sh_entsize
= sizeof(ElfW(Sym
)),
2677 [6] = { /* .strtab */
2678 .sh_type
= SHT_STRTAB
,
2679 .sh_offset
= offsetof(struct ElfImage
, str
),
2680 .sh_size
= sizeof(img
->str
),
2684 [1] = { /* code_gen_buffer */
2685 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
2690 .len
= sizeof(struct DebugInfo
) - 4,
2692 .ptr_size
= sizeof(void *),
2694 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
2696 .fn_name
= "code_gen_buffer"
2699 1, /* abbrev number (the cu) */
2700 0x11, 1, /* DW_TAG_compile_unit, has children */
2701 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2702 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2703 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2704 0, 0, /* end of abbrev */
2705 2, /* abbrev number (the fn) */
2706 0x2e, 0, /* DW_TAG_subprogram, no children */
2707 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2708 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2709 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2710 0, 0, /* end of abbrev */
2711 0 /* no more abbrev */
2713 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2714 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
2717 /* We only need a single jit entry; statically allocate it. */
2718 static struct jit_code_entry one_entry
;
2720 uintptr_t buf
= (uintptr_t)buf_ptr
;
2721 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
2722 DebugFrameHeader
*dfh
;
2724 img
= g_malloc(img_size
);
2725 *img
= img_template
;
2727 img
->phdr
.p_vaddr
= buf
;
2728 img
->phdr
.p_paddr
= buf
;
2729 img
->phdr
.p_memsz
= buf_size
;
2731 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
2732 img
->shdr
[1].sh_addr
= buf
;
2733 img
->shdr
[1].sh_size
= buf_size
;
2735 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
2736 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
2738 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
2739 img
->shdr
[4].sh_size
= debug_frame_size
;
2741 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
2742 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
2744 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
2745 img
->sym
[1].st_value
= buf
;
2746 img
->sym
[1].st_size
= buf_size
;
2748 img
->di
.cu_low_pc
= buf
;
2749 img
->di
.cu_high_pc
= buf
+ buf_size
;
2750 img
->di
.fn_low_pc
= buf
;
2751 img
->di
.fn_high_pc
= buf
+ buf_size
;
2753 dfh
= (DebugFrameHeader
*)(img
+ 1);
2754 memcpy(dfh
, debug_frame
, debug_frame_size
);
2755 dfh
->fde
.func_start
= buf
;
2756 dfh
->fde
.func_len
= buf_size
;
2759 /* Enable this block to be able to debug the ELF image file creation.
2760 One can use readelf, objdump, or other inspection utilities. */
2762 FILE *f
= fopen("/tmp/qemu.jit", "w+b");
2764 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
2765 /* Avoid stupid unused return value warning for fwrite. */
2772 one_entry
.symfile_addr
= img
;
2773 one_entry
.symfile_size
= img_size
;
2775 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
2776 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
2777 __jit_debug_descriptor
.first_entry
= &one_entry
;
2778 __jit_debug_register_code();
2781 /* No support for the feature. Provide the entry point expected by exec.c,
2782 and implement the internal function we declared earlier. */
2784 static void tcg_register_jit_int(void *buf
, size_t size
,
2785 const void *debug_frame
,
2786 size_t debug_frame_size
)
2790 void tcg_register_jit(void *buf
, size_t buf_size
)
2793 #endif /* ELF_HOST_MACHINE */