4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "sysemu/runstate.h"
30 #include "hyperv-proto.h"
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/main-loop.h"
35 #include "qemu/config-file.h"
36 #include "qemu/error-report.h"
37 #include "hw/i386/x86.h"
38 #include "hw/i386/apic.h"
39 #include "hw/i386/apic_internal.h"
40 #include "hw/i386/apic-msidef.h"
41 #include "hw/i386/intel_iommu.h"
42 #include "hw/i386/x86-iommu.h"
43 #include "hw/i386/e820_memory_layout.h"
45 #include "hw/pci/pci.h"
46 #include "hw/pci/msi.h"
47 #include "hw/pci/msix.h"
48 #include "migration/blocker.h"
49 #include "exec/memattrs.h"
55 #define DPRINTF(fmt, ...) \
56 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58 #define DPRINTF(fmt, ...) \
62 #define MSR_KVM_WALL_CLOCK 0x11
63 #define MSR_KVM_SYSTEM_TIME 0x12
65 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
66 * 255 kvm_msr_entry structs */
67 #define MSR_BUF_SIZE 4096
69 static void kvm_init_msrs(X86CPU
*cpu
);
71 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
72 KVM_CAP_INFO(SET_TSS_ADDR
),
73 KVM_CAP_INFO(EXT_CPUID
),
74 KVM_CAP_INFO(MP_STATE
),
78 static bool has_msr_star
;
79 static bool has_msr_hsave_pa
;
80 static bool has_msr_tsc_aux
;
81 static bool has_msr_tsc_adjust
;
82 static bool has_msr_tsc_deadline
;
83 static bool has_msr_feature_control
;
84 static bool has_msr_misc_enable
;
85 static bool has_msr_smbase
;
86 static bool has_msr_bndcfgs
;
87 static int lm_capable_kernel
;
88 static bool has_msr_hv_hypercall
;
89 static bool has_msr_hv_crash
;
90 static bool has_msr_hv_reset
;
91 static bool has_msr_hv_vpindex
;
92 static bool hv_vpindex_settable
;
93 static bool has_msr_hv_runtime
;
94 static bool has_msr_hv_synic
;
95 static bool has_msr_hv_stimer
;
96 static bool has_msr_hv_frequencies
;
97 static bool has_msr_hv_reenlightenment
;
98 static bool has_msr_xss
;
99 static bool has_msr_umwait
;
100 static bool has_msr_spec_ctrl
;
101 static bool has_msr_tsx_ctrl
;
102 static bool has_msr_virt_ssbd
;
103 static bool has_msr_smi_count
;
104 static bool has_msr_arch_capabs
;
105 static bool has_msr_core_capabs
;
106 static bool has_msr_vmx_vmfunc
;
107 static bool has_msr_ucode_rev
;
108 static bool has_msr_vmx_procbased_ctls2
;
110 static uint32_t has_architectural_pmu_version
;
111 static uint32_t num_architectural_pmu_gp_counters
;
112 static uint32_t num_architectural_pmu_fixed_counters
;
114 static int has_xsave
;
116 static int has_pit_state2
;
117 static int has_exception_payload
;
119 static bool has_msr_mcg_ext_ctl
;
121 static struct kvm_cpuid2
*cpuid_cache
;
122 static struct kvm_msr_list
*kvm_feature_msrs
;
124 int kvm_has_pit_state2(void)
126 return has_pit_state2
;
129 bool kvm_has_smm(void)
131 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
134 bool kvm_has_adjust_clock_stable(void)
136 int ret
= kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
);
138 return (ret
== KVM_CLOCK_TSC_STABLE
);
141 bool kvm_has_exception_payload(void)
143 return has_exception_payload
;
146 bool kvm_allows_irq0_override(void)
148 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
151 static bool kvm_x2apic_api_set_flags(uint64_t flags
)
153 KVMState
*s
= KVM_STATE(current_accel());
155 return !kvm_vm_enable_cap(s
, KVM_CAP_X2APIC_API
, 0, flags
);
158 #define MEMORIZE(fn, _result) \
160 static bool _memorized; \
169 static bool has_x2apic_api
;
171 bool kvm_has_x2apic_api(void)
173 return has_x2apic_api
;
176 bool kvm_enable_x2apic(void)
179 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS
|
180 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK
),
184 bool kvm_hv_vpindex_settable(void)
186 return hv_vpindex_settable
;
189 static int kvm_get_tsc(CPUState
*cs
)
191 X86CPU
*cpu
= X86_CPU(cs
);
192 CPUX86State
*env
= &cpu
->env
;
194 struct kvm_msrs info
;
195 struct kvm_msr_entry entries
[1];
199 if (env
->tsc_valid
) {
203 memset(&msr_data
, 0, sizeof(msr_data
));
204 msr_data
.info
.nmsrs
= 1;
205 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
206 env
->tsc_valid
= !runstate_is_running();
208 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
214 env
->tsc
= msr_data
.entries
[0].data
;
218 static inline void do_kvm_synchronize_tsc(CPUState
*cpu
, run_on_cpu_data arg
)
223 void kvm_synchronize_all_tsc(void)
229 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, RUN_ON_CPU_NULL
);
234 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
236 struct kvm_cpuid2
*cpuid
;
239 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
240 cpuid
= g_malloc0(size
);
242 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
243 if (r
== 0 && cpuid
->nent
>= max
) {
251 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
259 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
262 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
264 struct kvm_cpuid2
*cpuid
;
267 if (cpuid_cache
!= NULL
) {
270 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
277 static const struct kvm_para_features
{
280 } para_features
[] = {
281 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
282 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
283 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
284 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
287 static int get_para_features(KVMState
*s
)
291 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
292 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
293 features
|= (1 << para_features
[i
].feature
);
300 static bool host_tsx_blacklisted(void)
302 int family
, model
, stepping
;\
303 char vendor
[CPUID_VENDOR_SZ
+ 1];
305 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
307 /* Check if we are running on a Haswell host known to have broken TSX */
308 return !strcmp(vendor
, CPUID_VENDOR_INTEL
) &&
310 ((model
== 63 && stepping
< 4) ||
311 model
== 60 || model
== 69 || model
== 70);
314 /* Returns the value for a specific register on the cpuid entry
316 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
336 /* Find matching entry for function/index on kvm_cpuid2 struct
338 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
343 for (i
= 0; i
< cpuid
->nent
; ++i
) {
344 if (cpuid
->entries
[i
].function
== function
&&
345 cpuid
->entries
[i
].index
== index
) {
346 return &cpuid
->entries
[i
];
353 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
354 uint32_t index
, int reg
)
356 struct kvm_cpuid2
*cpuid
;
358 uint32_t cpuid_1_edx
;
361 cpuid
= get_supported_cpuid(s
);
363 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
366 ret
= cpuid_entry_get_reg(entry
, reg
);
369 /* Fixups for the data returned by KVM, below */
371 if (function
== 1 && reg
== R_EDX
) {
372 /* KVM before 2.6.30 misreports the following features */
373 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
374 } else if (function
== 1 && reg
== R_ECX
) {
375 /* We can set the hypervisor flag, even if KVM does not return it on
376 * GET_SUPPORTED_CPUID
378 ret
|= CPUID_EXT_HYPERVISOR
;
379 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
380 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
381 * and the irqchip is in the kernel.
383 if (kvm_irqchip_in_kernel() &&
384 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
385 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
388 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
389 * without the in-kernel irqchip
391 if (!kvm_irqchip_in_kernel()) {
392 ret
&= ~CPUID_EXT_X2APIC
;
396 int disable_exits
= kvm_check_extension(s
,
397 KVM_CAP_X86_DISABLE_EXITS
);
399 if (disable_exits
& KVM_X86_DISABLE_EXITS_MWAIT
) {
400 ret
|= CPUID_EXT_MONITOR
;
403 } else if (function
== 6 && reg
== R_EAX
) {
404 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
405 } else if (function
== 7 && index
== 0 && reg
== R_EBX
) {
406 if (host_tsx_blacklisted()) {
407 ret
&= ~(CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_HLE
);
409 } else if (function
== 7 && index
== 0 && reg
== R_ECX
) {
411 ret
|= CPUID_7_0_ECX_WAITPKG
;
413 ret
&= ~CPUID_7_0_ECX_WAITPKG
;
415 } else if (function
== 7 && index
== 0 && reg
== R_EDX
) {
417 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
418 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
419 * returned by KVM_GET_MSR_INDEX_LIST.
421 if (!has_msr_arch_capabs
) {
422 ret
&= ~CPUID_7_0_EDX_ARCH_CAPABILITIES
;
424 } else if (function
== 0x80000001 && reg
== R_ECX
) {
426 * It's safe to enable TOPOEXT even if it's not returned by
427 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
428 * us to keep CPU models including TOPOEXT runnable on older kernels.
430 ret
|= CPUID_EXT3_TOPOEXT
;
431 } else if (function
== 0x80000001 && reg
== R_EDX
) {
432 /* On Intel, kvm returns cpuid according to the Intel spec,
433 * so add missing bits according to the AMD spec:
435 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
436 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
437 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EAX
) {
438 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
439 * be enabled without the in-kernel irqchip
441 if (!kvm_irqchip_in_kernel()) {
442 ret
&= ~(1U << KVM_FEATURE_PV_UNHALT
);
444 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EDX
) {
445 ret
|= 1U << KVM_HINTS_REALTIME
;
449 /* fallback for older kernels */
450 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
451 ret
= get_para_features(s
);
457 uint64_t kvm_arch_get_supported_msr_feature(KVMState
*s
, uint32_t index
)
460 struct kvm_msrs info
;
461 struct kvm_msr_entry entries
[1];
464 uint32_t ret
, can_be_one
, must_be_one
;
466 if (kvm_feature_msrs
== NULL
) { /* Host doesn't support feature MSRs */
470 /* Check if requested MSR is supported feature MSR */
472 for (i
= 0; i
< kvm_feature_msrs
->nmsrs
; i
++)
473 if (kvm_feature_msrs
->indices
[i
] == index
) {
476 if (i
== kvm_feature_msrs
->nmsrs
) {
477 return 0; /* if the feature MSR is not supported, simply return 0 */
480 msr_data
.info
.nmsrs
= 1;
481 msr_data
.entries
[0].index
= index
;
483 ret
= kvm_ioctl(s
, KVM_GET_MSRS
, &msr_data
);
485 error_report("KVM get MSR (index=0x%x) feature failed, %s",
486 index
, strerror(-ret
));
490 value
= msr_data
.entries
[0].data
;
492 case MSR_IA32_VMX_PROCBASED_CTLS2
:
493 if (!has_msr_vmx_procbased_ctls2
) {
494 /* KVM forgot to add these bits for some time, do this ourselves. */
495 if (kvm_arch_get_supported_cpuid(s
, 0xD, 1, R_ECX
) &
496 CPUID_XSAVE_XSAVES
) {
497 value
|= (uint64_t)VMX_SECONDARY_EXEC_XSAVES
<< 32;
499 if (kvm_arch_get_supported_cpuid(s
, 1, 0, R_ECX
) &
501 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING
<< 32;
503 if (kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
) &
504 CPUID_7_0_EBX_INVPCID
) {
505 value
|= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID
<< 32;
507 if (kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
) &
508 CPUID_7_0_EBX_RDSEED
) {
509 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING
<< 32;
511 if (kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
) &
513 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP
<< 32;
517 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
518 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
519 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
520 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
522 * Return true for bits that can be one, but do not have to be one.
523 * The SDM tells us which bits could have a "must be one" setting,
524 * so we can do the opposite transformation in make_vmx_msr_value.
526 must_be_one
= (uint32_t)value
;
527 can_be_one
= (uint32_t)(value
>> 32);
528 return can_be_one
& ~must_be_one
;
535 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
540 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
543 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
548 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
550 CPUState
*cs
= CPU(cpu
);
551 CPUX86State
*env
= &cpu
->env
;
552 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
553 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
554 uint64_t mcg_status
= MCG_STATUS_MCIP
;
557 if (code
== BUS_MCEERR_AR
) {
558 status
|= MCI_STATUS_AR
| 0x134;
559 mcg_status
|= MCG_STATUS_EIPV
;
562 mcg_status
|= MCG_STATUS_RIPV
;
565 flags
= cpu_x86_support_mca_broadcast(env
) ? MCE_INJECT_BROADCAST
: 0;
566 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
567 * guest kernel back into env->mcg_ext_ctl.
569 cpu_synchronize_state(cs
);
570 if (env
->mcg_ext_ctl
& MCG_EXT_CTL_LMCE_EN
) {
571 mcg_status
|= MCG_STATUS_LMCE
;
575 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
576 (MCM_ADDR_PHYS
<< 6) | 0xc, flags
);
579 static void hardware_memory_error(void *host_addr
)
581 error_report("QEMU got Hardware memory error at addr %p", host_addr
);
585 void kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
587 X86CPU
*cpu
= X86_CPU(c
);
588 CPUX86State
*env
= &cpu
->env
;
592 /* If we get an action required MCE, it has been injected by KVM
593 * while the VM was running. An action optional MCE instead should
594 * be coming from the main thread, which qemu_init_sigbus identifies
595 * as the "early kill" thread.
597 assert(code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
);
599 if ((env
->mcg_cap
& MCG_SER_P
) && addr
) {
600 ram_addr
= qemu_ram_addr_from_host(addr
);
601 if (ram_addr
!= RAM_ADDR_INVALID
&&
602 kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
603 kvm_hwpoison_page_add(ram_addr
);
604 kvm_mce_inject(cpu
, paddr
, code
);
607 * Use different logging severity based on error type.
608 * If there is additional MCE reporting on the hypervisor, QEMU VA
609 * could be another source to identify the PA and MCE details.
611 if (code
== BUS_MCEERR_AR
) {
612 error_report("Guest MCE Memory Error at QEMU addr %p and "
613 "GUEST addr 0x%" HWADDR_PRIx
" of type %s injected",
614 addr
, paddr
, "BUS_MCEERR_AR");
616 warn_report("Guest MCE Memory Error at QEMU addr %p and "
617 "GUEST addr 0x%" HWADDR_PRIx
" of type %s injected",
618 addr
, paddr
, "BUS_MCEERR_AO");
624 if (code
== BUS_MCEERR_AO
) {
625 warn_report("Hardware memory error at addr %p of type %s "
626 "for memory used by QEMU itself instead of guest system!",
627 addr
, "BUS_MCEERR_AO");
631 if (code
== BUS_MCEERR_AR
) {
632 hardware_memory_error(addr
);
635 /* Hope we are lucky for AO MCE */
638 static void kvm_reset_exception(CPUX86State
*env
)
640 env
->exception_nr
= -1;
641 env
->exception_pending
= 0;
642 env
->exception_injected
= 0;
643 env
->exception_has_payload
= false;
644 env
->exception_payload
= 0;
647 static void kvm_queue_exception(CPUX86State
*env
,
648 int32_t exception_nr
,
649 uint8_t exception_has_payload
,
650 uint64_t exception_payload
)
652 assert(env
->exception_nr
== -1);
653 assert(!env
->exception_pending
);
654 assert(!env
->exception_injected
);
655 assert(!env
->exception_has_payload
);
657 env
->exception_nr
= exception_nr
;
659 if (has_exception_payload
) {
660 env
->exception_pending
= 1;
662 env
->exception_has_payload
= exception_has_payload
;
663 env
->exception_payload
= exception_payload
;
665 env
->exception_injected
= 1;
667 if (exception_nr
== EXCP01_DB
) {
668 assert(exception_has_payload
);
669 env
->dr
[6] = exception_payload
;
670 } else if (exception_nr
== EXCP0E_PAGE
) {
671 assert(exception_has_payload
);
672 env
->cr
[2] = exception_payload
;
674 assert(!exception_has_payload
);
679 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
681 CPUX86State
*env
= &cpu
->env
;
683 if (!kvm_has_vcpu_events() && env
->exception_nr
== EXCP12_MCHK
) {
684 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
685 struct kvm_x86_mce mce
;
687 kvm_reset_exception(env
);
690 * There must be at least one bank in use if an MCE is pending.
691 * Find it and use its values for the event injection.
693 for (bank
= 0; bank
< bank_num
; bank
++) {
694 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
698 assert(bank
< bank_num
);
701 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
702 mce
.mcg_status
= env
->mcg_status
;
703 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
704 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
706 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
711 static void cpu_update_state(void *opaque
, int running
, RunState state
)
713 CPUX86State
*env
= opaque
;
716 env
->tsc_valid
= false;
720 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
722 X86CPU
*cpu
= X86_CPU(cs
);
726 #ifndef KVM_CPUID_SIGNATURE_NEXT
727 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
730 static bool hyperv_enabled(X86CPU
*cpu
)
732 CPUState
*cs
= CPU(cpu
);
733 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
734 ((cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
) ||
735 cpu
->hyperv_features
|| cpu
->hyperv_passthrough
);
738 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
740 X86CPU
*cpu
= X86_CPU(cs
);
741 CPUX86State
*env
= &cpu
->env
;
748 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
749 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
752 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
753 * TSC frequency doesn't match the one we want.
755 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
756 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
758 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
759 warn_report("TSC frequency mismatch between "
760 "VM (%" PRId64
" kHz) and host (%d kHz), "
761 "and TSC scaling unavailable",
762 env
->tsc_khz
, cur_freq
);
770 static bool tsc_is_stable_and_known(CPUX86State
*env
)
775 return (env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
)
776 || env
->user_tsc_khz
;
785 uint64_t dependencies
;
786 } kvm_hyperv_properties
[] = {
787 [HYPERV_FEAT_RELAXED
] = {
788 .desc
= "relaxed timing (hv-relaxed)",
790 {.fw
= FEAT_HYPERV_EAX
,
791 .bits
= HV_HYPERCALL_AVAILABLE
},
792 {.fw
= FEAT_HV_RECOMM_EAX
,
793 .bits
= HV_RELAXED_TIMING_RECOMMENDED
}
796 [HYPERV_FEAT_VAPIC
] = {
797 .desc
= "virtual APIC (hv-vapic)",
799 {.fw
= FEAT_HYPERV_EAX
,
800 .bits
= HV_HYPERCALL_AVAILABLE
| HV_APIC_ACCESS_AVAILABLE
},
801 {.fw
= FEAT_HV_RECOMM_EAX
,
802 .bits
= HV_APIC_ACCESS_RECOMMENDED
}
805 [HYPERV_FEAT_TIME
] = {
806 .desc
= "clocksources (hv-time)",
808 {.fw
= FEAT_HYPERV_EAX
,
809 .bits
= HV_HYPERCALL_AVAILABLE
| HV_TIME_REF_COUNT_AVAILABLE
|
810 HV_REFERENCE_TSC_AVAILABLE
}
813 [HYPERV_FEAT_CRASH
] = {
814 .desc
= "crash MSRs (hv-crash)",
816 {.fw
= FEAT_HYPERV_EDX
,
817 .bits
= HV_GUEST_CRASH_MSR_AVAILABLE
}
820 [HYPERV_FEAT_RESET
] = {
821 .desc
= "reset MSR (hv-reset)",
823 {.fw
= FEAT_HYPERV_EAX
,
824 .bits
= HV_RESET_AVAILABLE
}
827 [HYPERV_FEAT_VPINDEX
] = {
828 .desc
= "VP_INDEX MSR (hv-vpindex)",
830 {.fw
= FEAT_HYPERV_EAX
,
831 .bits
= HV_VP_INDEX_AVAILABLE
}
834 [HYPERV_FEAT_RUNTIME
] = {
835 .desc
= "VP_RUNTIME MSR (hv-runtime)",
837 {.fw
= FEAT_HYPERV_EAX
,
838 .bits
= HV_VP_RUNTIME_AVAILABLE
}
841 [HYPERV_FEAT_SYNIC
] = {
842 .desc
= "synthetic interrupt controller (hv-synic)",
844 {.fw
= FEAT_HYPERV_EAX
,
845 .bits
= HV_SYNIC_AVAILABLE
}
848 [HYPERV_FEAT_STIMER
] = {
849 .desc
= "synthetic timers (hv-stimer)",
851 {.fw
= FEAT_HYPERV_EAX
,
852 .bits
= HV_SYNTIMERS_AVAILABLE
}
854 .dependencies
= BIT(HYPERV_FEAT_SYNIC
) | BIT(HYPERV_FEAT_TIME
)
856 [HYPERV_FEAT_FREQUENCIES
] = {
857 .desc
= "frequency MSRs (hv-frequencies)",
859 {.fw
= FEAT_HYPERV_EAX
,
860 .bits
= HV_ACCESS_FREQUENCY_MSRS
},
861 {.fw
= FEAT_HYPERV_EDX
,
862 .bits
= HV_FREQUENCY_MSRS_AVAILABLE
}
865 [HYPERV_FEAT_REENLIGHTENMENT
] = {
866 .desc
= "reenlightenment MSRs (hv-reenlightenment)",
868 {.fw
= FEAT_HYPERV_EAX
,
869 .bits
= HV_ACCESS_REENLIGHTENMENTS_CONTROL
}
872 [HYPERV_FEAT_TLBFLUSH
] = {
873 .desc
= "paravirtualized TLB flush (hv-tlbflush)",
875 {.fw
= FEAT_HV_RECOMM_EAX
,
876 .bits
= HV_REMOTE_TLB_FLUSH_RECOMMENDED
|
877 HV_EX_PROCESSOR_MASKS_RECOMMENDED
}
879 .dependencies
= BIT(HYPERV_FEAT_VPINDEX
)
881 [HYPERV_FEAT_EVMCS
] = {
882 .desc
= "enlightened VMCS (hv-evmcs)",
884 {.fw
= FEAT_HV_RECOMM_EAX
,
885 .bits
= HV_ENLIGHTENED_VMCS_RECOMMENDED
}
887 .dependencies
= BIT(HYPERV_FEAT_VAPIC
)
889 [HYPERV_FEAT_IPI
] = {
890 .desc
= "paravirtualized IPI (hv-ipi)",
892 {.fw
= FEAT_HV_RECOMM_EAX
,
893 .bits
= HV_CLUSTER_IPI_RECOMMENDED
|
894 HV_EX_PROCESSOR_MASKS_RECOMMENDED
}
896 .dependencies
= BIT(HYPERV_FEAT_VPINDEX
)
898 [HYPERV_FEAT_STIMER_DIRECT
] = {
899 .desc
= "direct mode synthetic timers (hv-stimer-direct)",
901 {.fw
= FEAT_HYPERV_EDX
,
902 .bits
= HV_STIMER_DIRECT_MODE_AVAILABLE
}
904 .dependencies
= BIT(HYPERV_FEAT_STIMER
)
908 static struct kvm_cpuid2
*try_get_hv_cpuid(CPUState
*cs
, int max
)
910 struct kvm_cpuid2
*cpuid
;
913 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
914 cpuid
= g_malloc0(size
);
917 r
= kvm_vcpu_ioctl(cs
, KVM_GET_SUPPORTED_HV_CPUID
, cpuid
);
918 if (r
== 0 && cpuid
->nent
>= max
) {
926 fprintf(stderr
, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
935 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
938 static struct kvm_cpuid2
*get_supported_hv_cpuid(CPUState
*cs
)
940 struct kvm_cpuid2
*cpuid
;
941 int max
= 7; /* 0x40000000..0x40000005, 0x4000000A */
944 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
945 * -E2BIG, however, it doesn't report back the right size. Keep increasing
946 * it and re-trying until we succeed.
948 while ((cpuid
= try_get_hv_cpuid(cs
, max
)) == NULL
) {
955 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
956 * leaves from KVM_CAP_HYPERV* and present MSRs data.
958 static struct kvm_cpuid2
*get_supported_hv_cpuid_legacy(CPUState
*cs
)
960 X86CPU
*cpu
= X86_CPU(cs
);
961 struct kvm_cpuid2
*cpuid
;
962 struct kvm_cpuid_entry2
*entry_feat
, *entry_recomm
;
964 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
965 cpuid
= g_malloc0(sizeof(*cpuid
) + 2 * sizeof(*cpuid
->entries
));
968 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
969 entry_feat
= &cpuid
->entries
[0];
970 entry_feat
->function
= HV_CPUID_FEATURES
;
972 entry_recomm
= &cpuid
->entries
[1];
973 entry_recomm
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
974 entry_recomm
->ebx
= cpu
->hyperv_spinlock_attempts
;
976 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0) {
977 entry_feat
->eax
|= HV_HYPERCALL_AVAILABLE
;
978 entry_feat
->eax
|= HV_APIC_ACCESS_AVAILABLE
;
979 entry_feat
->edx
|= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
980 entry_recomm
->eax
|= HV_RELAXED_TIMING_RECOMMENDED
;
981 entry_recomm
->eax
|= HV_APIC_ACCESS_RECOMMENDED
;
984 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) > 0) {
985 entry_feat
->eax
|= HV_TIME_REF_COUNT_AVAILABLE
;
986 entry_feat
->eax
|= HV_REFERENCE_TSC_AVAILABLE
;
989 if (has_msr_hv_frequencies
) {
990 entry_feat
->eax
|= HV_ACCESS_FREQUENCY_MSRS
;
991 entry_feat
->edx
|= HV_FREQUENCY_MSRS_AVAILABLE
;
994 if (has_msr_hv_crash
) {
995 entry_feat
->edx
|= HV_GUEST_CRASH_MSR_AVAILABLE
;
998 if (has_msr_hv_reenlightenment
) {
999 entry_feat
->eax
|= HV_ACCESS_REENLIGHTENMENTS_CONTROL
;
1002 if (has_msr_hv_reset
) {
1003 entry_feat
->eax
|= HV_RESET_AVAILABLE
;
1006 if (has_msr_hv_vpindex
) {
1007 entry_feat
->eax
|= HV_VP_INDEX_AVAILABLE
;
1010 if (has_msr_hv_runtime
) {
1011 entry_feat
->eax
|= HV_VP_RUNTIME_AVAILABLE
;
1014 if (has_msr_hv_synic
) {
1015 unsigned int cap
= cpu
->hyperv_synic_kvm_only
?
1016 KVM_CAP_HYPERV_SYNIC
: KVM_CAP_HYPERV_SYNIC2
;
1018 if (kvm_check_extension(cs
->kvm_state
, cap
) > 0) {
1019 entry_feat
->eax
|= HV_SYNIC_AVAILABLE
;
1023 if (has_msr_hv_stimer
) {
1024 entry_feat
->eax
|= HV_SYNTIMERS_AVAILABLE
;
1027 if (kvm_check_extension(cs
->kvm_state
,
1028 KVM_CAP_HYPERV_TLBFLUSH
) > 0) {
1029 entry_recomm
->eax
|= HV_REMOTE_TLB_FLUSH_RECOMMENDED
;
1030 entry_recomm
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
1033 if (kvm_check_extension(cs
->kvm_state
,
1034 KVM_CAP_HYPERV_ENLIGHTENED_VMCS
) > 0) {
1035 entry_recomm
->eax
|= HV_ENLIGHTENED_VMCS_RECOMMENDED
;
1038 if (kvm_check_extension(cs
->kvm_state
,
1039 KVM_CAP_HYPERV_SEND_IPI
) > 0) {
1040 entry_recomm
->eax
|= HV_CLUSTER_IPI_RECOMMENDED
;
1041 entry_recomm
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
1047 static int hv_cpuid_get_fw(struct kvm_cpuid2
*cpuid
, int fw
, uint32_t *r
)
1049 struct kvm_cpuid_entry2
*entry
;
1054 case FEAT_HYPERV_EAX
:
1056 func
= HV_CPUID_FEATURES
;
1058 case FEAT_HYPERV_EDX
:
1060 func
= HV_CPUID_FEATURES
;
1062 case FEAT_HV_RECOMM_EAX
:
1064 func
= HV_CPUID_ENLIGHTMENT_INFO
;
1070 entry
= cpuid_find_entry(cpuid
, func
, 0);
1089 static int hv_cpuid_check_and_set(CPUState
*cs
, struct kvm_cpuid2
*cpuid
,
1092 X86CPU
*cpu
= X86_CPU(cs
);
1093 CPUX86State
*env
= &cpu
->env
;
1094 uint32_t r
, fw
, bits
;
1098 if (!hyperv_feat_enabled(cpu
, feature
) && !cpu
->hyperv_passthrough
) {
1102 deps
= kvm_hyperv_properties
[feature
].dependencies
;
1104 dep_feat
= ctz64(deps
);
1105 if (!(hyperv_feat_enabled(cpu
, dep_feat
))) {
1107 "Hyper-V %s requires Hyper-V %s\n",
1108 kvm_hyperv_properties
[feature
].desc
,
1109 kvm_hyperv_properties
[dep_feat
].desc
);
1112 deps
&= ~(1ull << dep_feat
);
1115 for (i
= 0; i
< ARRAY_SIZE(kvm_hyperv_properties
[feature
].flags
); i
++) {
1116 fw
= kvm_hyperv_properties
[feature
].flags
[i
].fw
;
1117 bits
= kvm_hyperv_properties
[feature
].flags
[i
].bits
;
1123 if (hv_cpuid_get_fw(cpuid
, fw
, &r
) || (r
& bits
) != bits
) {
1124 if (hyperv_feat_enabled(cpu
, feature
)) {
1126 "Hyper-V %s is not supported by kernel\n",
1127 kvm_hyperv_properties
[feature
].desc
);
1134 env
->features
[fw
] |= bits
;
1137 if (cpu
->hyperv_passthrough
) {
1138 cpu
->hyperv_features
|= BIT(feature
);
1145 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1146 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1147 * extentions are enabled.
1149 static int hyperv_handle_properties(CPUState
*cs
,
1150 struct kvm_cpuid_entry2
*cpuid_ent
)
1152 X86CPU
*cpu
= X86_CPU(cs
);
1153 CPUX86State
*env
= &cpu
->env
;
1154 struct kvm_cpuid2
*cpuid
;
1155 struct kvm_cpuid_entry2
*c
;
1156 uint32_t signature
[3];
1157 uint32_t cpuid_i
= 0;
1160 if (!hyperv_enabled(cpu
))
1163 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) ||
1164 cpu
->hyperv_passthrough
) {
1165 uint16_t evmcs_version
;
1167 r
= kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_ENLIGHTENED_VMCS
, 0,
1168 (uintptr_t)&evmcs_version
);
1170 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) && r
) {
1171 fprintf(stderr
, "Hyper-V %s is not supported by kernel\n",
1172 kvm_hyperv_properties
[HYPERV_FEAT_EVMCS
].desc
);
1177 env
->features
[FEAT_HV_RECOMM_EAX
] |=
1178 HV_ENLIGHTENED_VMCS_RECOMMENDED
;
1179 env
->features
[FEAT_HV_NESTED_EAX
] = evmcs_version
;
1183 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_CPUID
) > 0) {
1184 cpuid
= get_supported_hv_cpuid(cs
);
1186 cpuid
= get_supported_hv_cpuid_legacy(cs
);
1189 if (cpu
->hyperv_passthrough
) {
1190 memcpy(cpuid_ent
, &cpuid
->entries
[0],
1191 cpuid
->nent
* sizeof(cpuid
->entries
[0]));
1193 c
= cpuid_find_entry(cpuid
, HV_CPUID_FEATURES
, 0);
1195 env
->features
[FEAT_HYPERV_EAX
] = c
->eax
;
1196 env
->features
[FEAT_HYPERV_EBX
] = c
->ebx
;
1197 env
->features
[FEAT_HYPERV_EDX
] = c
->eax
;
1199 c
= cpuid_find_entry(cpuid
, HV_CPUID_ENLIGHTMENT_INFO
, 0);
1201 env
->features
[FEAT_HV_RECOMM_EAX
] = c
->eax
;
1203 /* hv-spinlocks may have been overriden */
1204 if (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
) {
1205 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
1208 c
= cpuid_find_entry(cpuid
, HV_CPUID_NESTED_FEATURES
, 0);
1210 env
->features
[FEAT_HV_NESTED_EAX
] = c
->eax
;
1214 if (cpu
->hyperv_no_nonarch_cs
== ON_OFF_AUTO_ON
) {
1215 env
->features
[FEAT_HV_RECOMM_EAX
] |= HV_NO_NONARCH_CORESHARING
;
1216 } else if (cpu
->hyperv_no_nonarch_cs
== ON_OFF_AUTO_AUTO
) {
1217 c
= cpuid_find_entry(cpuid
, HV_CPUID_ENLIGHTMENT_INFO
, 0);
1219 env
->features
[FEAT_HV_RECOMM_EAX
] |=
1220 c
->eax
& HV_NO_NONARCH_CORESHARING
;
1225 r
= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RELAXED
);
1226 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_VAPIC
);
1227 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_TIME
);
1228 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_CRASH
);
1229 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RESET
);
1230 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_VPINDEX
);
1231 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RUNTIME
);
1232 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_SYNIC
);
1233 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_STIMER
);
1234 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_FREQUENCIES
);
1235 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_REENLIGHTENMENT
);
1236 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_TLBFLUSH
);
1237 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_EVMCS
);
1238 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_IPI
);
1239 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_STIMER_DIRECT
);
1241 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1242 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
) &&
1243 !cpu
->hyperv_synic_kvm_only
&&
1244 !hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
)) {
1245 fprintf(stderr
, "Hyper-V %s requires Hyper-V %s\n",
1246 kvm_hyperv_properties
[HYPERV_FEAT_SYNIC
].desc
,
1247 kvm_hyperv_properties
[HYPERV_FEAT_VPINDEX
].desc
);
1251 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1252 env
->features
[FEAT_HYPERV_EDX
] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
1259 if (cpu
->hyperv_passthrough
) {
1260 /* We already copied all feature words from KVM as is */
1265 c
= &cpuid_ent
[cpuid_i
++];
1266 c
->function
= HV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
1267 if (!cpu
->hyperv_vendor_id
) {
1268 memcpy(signature
, "Microsoft Hv", 12);
1270 size_t len
= strlen(cpu
->hyperv_vendor_id
);
1273 error_report("hv-vendor-id truncated to 12 characters");
1276 memset(signature
, 0, 12);
1277 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
1279 c
->eax
= hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) ?
1280 HV_CPUID_NESTED_FEATURES
: HV_CPUID_IMPLEMENT_LIMITS
;
1281 c
->ebx
= signature
[0];
1282 c
->ecx
= signature
[1];
1283 c
->edx
= signature
[2];
1285 c
= &cpuid_ent
[cpuid_i
++];
1286 c
->function
= HV_CPUID_INTERFACE
;
1287 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
1288 c
->eax
= signature
[0];
1293 c
= &cpuid_ent
[cpuid_i
++];
1294 c
->function
= HV_CPUID_VERSION
;
1295 c
->eax
= 0x00001bbc;
1296 c
->ebx
= 0x00060001;
1298 c
= &cpuid_ent
[cpuid_i
++];
1299 c
->function
= HV_CPUID_FEATURES
;
1300 c
->eax
= env
->features
[FEAT_HYPERV_EAX
];
1301 c
->ebx
= env
->features
[FEAT_HYPERV_EBX
];
1302 c
->edx
= env
->features
[FEAT_HYPERV_EDX
];
1304 c
= &cpuid_ent
[cpuid_i
++];
1305 c
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
1306 c
->eax
= env
->features
[FEAT_HV_RECOMM_EAX
];
1307 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
1309 c
= &cpuid_ent
[cpuid_i
++];
1310 c
->function
= HV_CPUID_IMPLEMENT_LIMITS
;
1311 c
->eax
= cpu
->hv_max_vps
;
1314 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
)) {
1317 /* Create zeroed 0x40000006..0x40000009 leaves */
1318 for (function
= HV_CPUID_IMPLEMENT_LIMITS
+ 1;
1319 function
< HV_CPUID_NESTED_FEATURES
; function
++) {
1320 c
= &cpuid_ent
[cpuid_i
++];
1321 c
->function
= function
;
1324 c
= &cpuid_ent
[cpuid_i
++];
1325 c
->function
= HV_CPUID_NESTED_FEATURES
;
1326 c
->eax
= env
->features
[FEAT_HV_NESTED_EAX
];
1336 static Error
*hv_passthrough_mig_blocker
;
1337 static Error
*hv_no_nonarch_cs_mig_blocker
;
1339 static int hyperv_init_vcpu(X86CPU
*cpu
)
1341 CPUState
*cs
= CPU(cpu
);
1342 Error
*local_err
= NULL
;
1345 if (cpu
->hyperv_passthrough
&& hv_passthrough_mig_blocker
== NULL
) {
1346 error_setg(&hv_passthrough_mig_blocker
,
1347 "'hv-passthrough' CPU flag prevents migration, use explicit"
1348 " set of hv-* flags instead");
1349 ret
= migrate_add_blocker(hv_passthrough_mig_blocker
, &local_err
);
1351 error_report_err(local_err
);
1352 error_free(hv_passthrough_mig_blocker
);
1357 if (cpu
->hyperv_no_nonarch_cs
== ON_OFF_AUTO_AUTO
&&
1358 hv_no_nonarch_cs_mig_blocker
== NULL
) {
1359 error_setg(&hv_no_nonarch_cs_mig_blocker
,
1360 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1361 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1362 " make sure SMT is disabled and/or that vCPUs are properly"
1364 ret
= migrate_add_blocker(hv_no_nonarch_cs_mig_blocker
, &local_err
);
1366 error_report_err(local_err
);
1367 error_free(hv_no_nonarch_cs_mig_blocker
);
1372 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
) && !hv_vpindex_settable
) {
1374 * the kernel doesn't support setting vp_index; assert that its value
1378 struct kvm_msrs info
;
1379 struct kvm_msr_entry entries
[1];
1382 .entries
[0].index
= HV_X64_MSR_VP_INDEX
,
1385 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MSRS
, &msr_data
);
1391 if (msr_data
.entries
[0].data
!= hyperv_vp_index(CPU(cpu
))) {
1392 error_report("kernel's vp_index != QEMU's vp_index");
1397 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
1398 uint32_t synic_cap
= cpu
->hyperv_synic_kvm_only
?
1399 KVM_CAP_HYPERV_SYNIC
: KVM_CAP_HYPERV_SYNIC2
;
1400 ret
= kvm_vcpu_enable_cap(cs
, synic_cap
, 0);
1402 error_report("failed to turn on HyperV SynIC in KVM: %s",
1407 if (!cpu
->hyperv_synic_kvm_only
) {
1408 ret
= hyperv_x86_synic_add(cpu
);
1410 error_report("failed to create HyperV SynIC: %s",
1420 static Error
*invtsc_mig_blocker
;
1422 #define KVM_MAX_CPUID_ENTRIES 100
1424 int kvm_arch_init_vcpu(CPUState
*cs
)
1427 struct kvm_cpuid2 cpuid
;
1428 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
1431 * The kernel defines these structs with padding fields so there
1432 * should be no extra padding in our cpuid_data struct.
1434 QEMU_BUILD_BUG_ON(sizeof(cpuid_data
) !=
1435 sizeof(struct kvm_cpuid2
) +
1436 sizeof(struct kvm_cpuid_entry2
) * KVM_MAX_CPUID_ENTRIES
);
1438 X86CPU
*cpu
= X86_CPU(cs
);
1439 CPUX86State
*env
= &cpu
->env
;
1440 uint32_t limit
, i
, j
, cpuid_i
;
1442 struct kvm_cpuid_entry2
*c
;
1443 uint32_t signature
[3];
1444 int kvm_base
= KVM_CPUID_SIGNATURE
;
1445 int max_nested_state_len
;
1447 Error
*local_err
= NULL
;
1449 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
1453 r
= kvm_arch_set_tsc_khz(cs
);
1458 /* vcpu's TSC frequency is either specified by user, or following
1459 * the value used by KVM if the former is not present. In the
1460 * latter case, we query it from KVM and record in env->tsc_khz,
1461 * so that vcpu's TSC frequency can be migrated later via this field.
1463 if (!env
->tsc_khz
) {
1464 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
1465 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
1472 /* Paravirtualization CPUIDs */
1473 r
= hyperv_handle_properties(cs
, cpuid_data
.entries
);
1478 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
1479 has_msr_hv_hypercall
= true;
1482 if (cpu
->expose_kvm
) {
1483 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
1484 c
= &cpuid_data
.entries
[cpuid_i
++];
1485 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
1486 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
1487 c
->ebx
= signature
[0];
1488 c
->ecx
= signature
[1];
1489 c
->edx
= signature
[2];
1491 c
= &cpuid_data
.entries
[cpuid_i
++];
1492 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
1493 c
->eax
= env
->features
[FEAT_KVM
];
1494 c
->edx
= env
->features
[FEAT_KVM_HINTS
];
1497 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
1499 for (i
= 0; i
<= limit
; i
++) {
1500 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1501 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
1504 c
= &cpuid_data
.entries
[cpuid_i
++];
1508 /* Keep reading function 2 till all the input is received */
1512 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
1513 KVM_CPUID_FLAG_STATE_READ_NEXT
;
1514 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1515 times
= c
->eax
& 0xff;
1517 for (j
= 1; j
< times
; ++j
) {
1518 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1519 fprintf(stderr
, "cpuid_data is full, no space for "
1520 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
1523 c
= &cpuid_data
.entries
[cpuid_i
++];
1525 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
1526 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1531 if (env
->nr_dies
< 2) {
1537 for (j
= 0; ; j
++) {
1538 if (i
== 0xd && j
== 64) {
1542 if (i
== 0x1f && j
== 64) {
1547 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1549 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1551 if (i
== 4 && c
->eax
== 0) {
1554 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
1557 if (i
== 0x1f && !(c
->ecx
& 0xff00)) {
1560 if (i
== 0xd && c
->eax
== 0) {
1563 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1564 fprintf(stderr
, "cpuid_data is full, no space for "
1565 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1568 c
= &cpuid_data
.entries
[cpuid_i
++];
1577 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1578 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1581 for (j
= 1; j
<= times
; ++j
) {
1582 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1583 fprintf(stderr
, "cpuid_data is full, no space for "
1584 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1587 c
= &cpuid_data
.entries
[cpuid_i
++];
1590 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1591 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1598 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1599 if (!c
->eax
&& !c
->ebx
&& !c
->ecx
&& !c
->edx
) {
1601 * KVM already returns all zeroes if a CPUID entry is missing,
1602 * so we can omit it and avoid hitting KVM's 80-entry limit.
1610 if (limit
>= 0x0a) {
1613 cpu_x86_cpuid(env
, 0x0a, 0, &eax
, &unused
, &unused
, &edx
);
1615 has_architectural_pmu_version
= eax
& 0xff;
1616 if (has_architectural_pmu_version
> 0) {
1617 num_architectural_pmu_gp_counters
= (eax
& 0xff00) >> 8;
1619 /* Shouldn't be more than 32, since that's the number of bits
1620 * available in EBX to tell us _which_ counters are available.
1623 if (num_architectural_pmu_gp_counters
> MAX_GP_COUNTERS
) {
1624 num_architectural_pmu_gp_counters
= MAX_GP_COUNTERS
;
1627 if (has_architectural_pmu_version
> 1) {
1628 num_architectural_pmu_fixed_counters
= edx
& 0x1f;
1630 if (num_architectural_pmu_fixed_counters
> MAX_FIXED_COUNTERS
) {
1631 num_architectural_pmu_fixed_counters
= MAX_FIXED_COUNTERS
;
1637 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
1639 for (i
= 0x80000000; i
<= limit
; i
++) {
1640 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1641 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
1644 c
= &cpuid_data
.entries
[cpuid_i
++];
1648 /* Query for all AMD cache information leaves */
1649 for (j
= 0; ; j
++) {
1651 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1653 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1658 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1659 fprintf(stderr
, "cpuid_data is full, no space for "
1660 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1663 c
= &cpuid_data
.entries
[cpuid_i
++];
1669 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1670 if (!c
->eax
&& !c
->ebx
&& !c
->ecx
&& !c
->edx
) {
1672 * KVM already returns all zeroes if a CPUID entry is missing,
1673 * so we can omit it and avoid hitting KVM's 80-entry limit.
1681 /* Call Centaur's CPUID instructions they are supported. */
1682 if (env
->cpuid_xlevel2
> 0) {
1683 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
1685 for (i
= 0xC0000000; i
<= limit
; i
++) {
1686 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1687 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
1690 c
= &cpuid_data
.entries
[cpuid_i
++];
1694 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1698 cpuid_data
.cpuid
.nent
= cpuid_i
;
1700 if (((env
->cpuid_version
>> 8)&0xF) >= 6
1701 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
1702 (CPUID_MCE
| CPUID_MCA
)
1703 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
1704 uint64_t mcg_cap
, unsupported_caps
;
1708 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
1710 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
1714 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
1715 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1716 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
1720 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
1721 if (unsupported_caps
) {
1722 if (unsupported_caps
& MCG_LMCE_P
) {
1723 error_report("kvm: LMCE not supported");
1726 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64
,
1730 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
1731 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
1733 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
1738 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
1740 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
1742 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
1743 !!(c
->ecx
& CPUID_EXT_SMX
);
1746 if (env
->mcg_cap
& MCG_LMCE_P
) {
1747 has_msr_mcg_ext_ctl
= has_msr_feature_control
= true;
1750 if (!env
->user_tsc_khz
) {
1751 if ((env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
) &&
1752 invtsc_mig_blocker
== NULL
) {
1753 error_setg(&invtsc_mig_blocker
,
1754 "State blocked by non-migratable CPU device"
1756 r
= migrate_add_blocker(invtsc_mig_blocker
, &local_err
);
1758 error_report_err(local_err
);
1759 error_free(invtsc_mig_blocker
);
1765 if (cpu
->vmware_cpuid_freq
1766 /* Guests depend on 0x40000000 to detect this feature, so only expose
1767 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1769 && kvm_base
== KVM_CPUID_SIGNATURE
1770 /* TSC clock must be stable and known for this feature. */
1771 && tsc_is_stable_and_known(env
)) {
1773 c
= &cpuid_data
.entries
[cpuid_i
++];
1774 c
->function
= KVM_CPUID_SIGNATURE
| 0x10;
1775 c
->eax
= env
->tsc_khz
;
1776 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1777 * APIC_BUS_CYCLE_NS */
1779 c
->ecx
= c
->edx
= 0;
1781 c
= cpuid_find_entry(&cpuid_data
.cpuid
, kvm_base
, 0);
1782 c
->eax
= MAX(c
->eax
, KVM_CPUID_SIGNATURE
| 0x10);
1785 cpuid_data
.cpuid
.nent
= cpuid_i
;
1787 cpuid_data
.cpuid
.padding
= 0;
1788 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
1794 env
->xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
1795 memset(env
->xsave_buf
, 0, sizeof(struct kvm_xsave
));
1798 max_nested_state_len
= kvm_max_nested_state_length();
1799 if (max_nested_state_len
> 0) {
1800 assert(max_nested_state_len
>= offsetof(struct kvm_nested_state
, data
));
1802 if (cpu_has_vmx(env
)) {
1803 struct kvm_vmx_nested_state_hdr
*vmx_hdr
;
1805 env
->nested_state
= g_malloc0(max_nested_state_len
);
1806 env
->nested_state
->size
= max_nested_state_len
;
1807 env
->nested_state
->format
= KVM_STATE_NESTED_FORMAT_VMX
;
1809 vmx_hdr
= &env
->nested_state
->hdr
.vmx
;
1810 vmx_hdr
->vmxon_pa
= -1ull;
1811 vmx_hdr
->vmcs12_pa
= -1ull;
1815 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
1817 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
1818 has_msr_tsc_aux
= false;
1823 r
= hyperv_init_vcpu(cpu
);
1831 migrate_del_blocker(invtsc_mig_blocker
);
1836 int kvm_arch_destroy_vcpu(CPUState
*cs
)
1838 X86CPU
*cpu
= X86_CPU(cs
);
1839 CPUX86State
*env
= &cpu
->env
;
1841 if (cpu
->kvm_msr_buf
) {
1842 g_free(cpu
->kvm_msr_buf
);
1843 cpu
->kvm_msr_buf
= NULL
;
1846 if (env
->nested_state
) {
1847 g_free(env
->nested_state
);
1848 env
->nested_state
= NULL
;
1854 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
1856 CPUX86State
*env
= &cpu
->env
;
1859 if (kvm_irqchip_in_kernel()) {
1860 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
1861 KVM_MP_STATE_UNINITIALIZED
;
1863 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1866 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
1868 for (i
= 0; i
< ARRAY_SIZE(env
->msr_hv_synic_sint
); i
++) {
1869 env
->msr_hv_synic_sint
[i
] = HV_SINT_MASKED
;
1872 hyperv_x86_synic_reset(cpu
);
1874 /* enabled by default */
1875 env
->poll_control_msr
= 1;
1878 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
1880 CPUX86State
*env
= &cpu
->env
;
1882 /* APs get directly into wait-for-SIPI state. */
1883 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
1884 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1888 static int kvm_get_supported_feature_msrs(KVMState
*s
)
1892 if (kvm_feature_msrs
!= NULL
) {
1896 if (!kvm_check_extension(s
, KVM_CAP_GET_MSR_FEATURES
)) {
1900 struct kvm_msr_list msr_list
;
1903 ret
= kvm_ioctl(s
, KVM_GET_MSR_FEATURE_INDEX_LIST
, &msr_list
);
1904 if (ret
< 0 && ret
!= -E2BIG
) {
1905 error_report("Fetch KVM feature MSR list failed: %s",
1910 assert(msr_list
.nmsrs
> 0);
1911 kvm_feature_msrs
= (struct kvm_msr_list
*) \
1912 g_malloc0(sizeof(msr_list
) +
1913 msr_list
.nmsrs
* sizeof(msr_list
.indices
[0]));
1915 kvm_feature_msrs
->nmsrs
= msr_list
.nmsrs
;
1916 ret
= kvm_ioctl(s
, KVM_GET_MSR_FEATURE_INDEX_LIST
, kvm_feature_msrs
);
1919 error_report("Fetch KVM feature MSR list failed: %s",
1921 g_free(kvm_feature_msrs
);
1922 kvm_feature_msrs
= NULL
;
1929 static int kvm_get_supported_msrs(KVMState
*s
)
1932 struct kvm_msr_list msr_list
, *kvm_msr_list
;
1935 * Obtain MSR list from KVM. These are the MSRs that we must
1939 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
1940 if (ret
< 0 && ret
!= -E2BIG
) {
1944 * Old kernel modules had a bug and could write beyond the provided
1945 * memory. Allocate at least a safe amount of 1K.
1947 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
1949 sizeof(msr_list
.indices
[0])));
1951 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
1952 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
1956 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
1957 switch (kvm_msr_list
->indices
[i
]) {
1959 has_msr_star
= true;
1961 case MSR_VM_HSAVE_PA
:
1962 has_msr_hsave_pa
= true;
1965 has_msr_tsc_aux
= true;
1967 case MSR_TSC_ADJUST
:
1968 has_msr_tsc_adjust
= true;
1970 case MSR_IA32_TSCDEADLINE
:
1971 has_msr_tsc_deadline
= true;
1973 case MSR_IA32_SMBASE
:
1974 has_msr_smbase
= true;
1977 has_msr_smi_count
= true;
1979 case MSR_IA32_MISC_ENABLE
:
1980 has_msr_misc_enable
= true;
1982 case MSR_IA32_BNDCFGS
:
1983 has_msr_bndcfgs
= true;
1988 case MSR_IA32_UMWAIT_CONTROL
:
1989 has_msr_umwait
= true;
1991 case HV_X64_MSR_CRASH_CTL
:
1992 has_msr_hv_crash
= true;
1994 case HV_X64_MSR_RESET
:
1995 has_msr_hv_reset
= true;
1997 case HV_X64_MSR_VP_INDEX
:
1998 has_msr_hv_vpindex
= true;
2000 case HV_X64_MSR_VP_RUNTIME
:
2001 has_msr_hv_runtime
= true;
2003 case HV_X64_MSR_SCONTROL
:
2004 has_msr_hv_synic
= true;
2006 case HV_X64_MSR_STIMER0_CONFIG
:
2007 has_msr_hv_stimer
= true;
2009 case HV_X64_MSR_TSC_FREQUENCY
:
2010 has_msr_hv_frequencies
= true;
2012 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
2013 has_msr_hv_reenlightenment
= true;
2015 case MSR_IA32_SPEC_CTRL
:
2016 has_msr_spec_ctrl
= true;
2018 case MSR_IA32_TSX_CTRL
:
2019 has_msr_tsx_ctrl
= true;
2022 has_msr_virt_ssbd
= true;
2024 case MSR_IA32_ARCH_CAPABILITIES
:
2025 has_msr_arch_capabs
= true;
2027 case MSR_IA32_CORE_CAPABILITY
:
2028 has_msr_core_capabs
= true;
2030 case MSR_IA32_VMX_VMFUNC
:
2031 has_msr_vmx_vmfunc
= true;
2033 case MSR_IA32_UCODE_REV
:
2034 has_msr_ucode_rev
= true;
2036 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2037 has_msr_vmx_procbased_ctls2
= true;
2043 g_free(kvm_msr_list
);
2048 static Notifier smram_machine_done
;
2049 static KVMMemoryListener smram_listener
;
2050 static AddressSpace smram_address_space
;
2051 static MemoryRegion smram_as_root
;
2052 static MemoryRegion smram_as_mem
;
2054 static void register_smram_listener(Notifier
*n
, void *unused
)
2056 MemoryRegion
*smram
=
2057 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
2059 /* Outer container... */
2060 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
2061 memory_region_set_enabled(&smram_as_root
, true);
2063 /* ... with two regions inside: normal system memory with low
2066 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
2067 get_system_memory(), 0, ~0ull);
2068 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
2069 memory_region_set_enabled(&smram_as_mem
, true);
2072 /* ... SMRAM with higher priority */
2073 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
2074 memory_region_set_enabled(smram
, true);
2077 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
2078 kvm_memory_listener_register(kvm_state
, &smram_listener
,
2079 &smram_address_space
, 1);
2082 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
2084 uint64_t identity_base
= 0xfffbc000;
2085 uint64_t shadow_mem
;
2087 struct utsname utsname
;
2089 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
2090 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
2091 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
2093 hv_vpindex_settable
= kvm_check_extension(s
, KVM_CAP_HYPERV_VP_INDEX
);
2095 has_exception_payload
= kvm_check_extension(s
, KVM_CAP_EXCEPTION_PAYLOAD
);
2096 if (has_exception_payload
) {
2097 ret
= kvm_vm_enable_cap(s
, KVM_CAP_EXCEPTION_PAYLOAD
, 0, true);
2099 error_report("kvm: Failed to enable exception payload cap: %s",
2105 ret
= kvm_get_supported_msrs(s
);
2110 kvm_get_supported_feature_msrs(s
);
2113 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
2116 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2117 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2118 * Since these must be part of guest physical memory, we need to allocate
2119 * them, both by setting their start addresses in the kernel and by
2120 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2122 * Older KVM versions may not support setting the identity map base. In
2123 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2126 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
2127 /* Allows up to 16M BIOSes. */
2128 identity_base
= 0xfeffc000;
2130 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
2136 /* Set TSS base one page after EPT identity map. */
2137 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
2142 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2143 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
2145 fprintf(stderr
, "e820_add_entry() table is full\n");
2149 shadow_mem
= object_property_get_int(OBJECT(s
), "kvm-shadow-mem", &error_abort
);
2150 if (shadow_mem
!= -1) {
2152 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
2158 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
) &&
2159 object_dynamic_cast(OBJECT(ms
), TYPE_X86_MACHINE
) &&
2160 x86_machine_is_smm_enabled(X86_MACHINE(ms
))) {
2161 smram_machine_done
.notify
= register_smram_listener
;
2162 qemu_add_machine_init_done_notifier(&smram_machine_done
);
2165 if (enable_cpu_pm
) {
2166 int disable_exits
= kvm_check_extension(s
, KVM_CAP_X86_DISABLE_EXITS
);
2169 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2170 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2171 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2173 if (disable_exits
) {
2174 disable_exits
&= (KVM_X86_DISABLE_EXITS_MWAIT
|
2175 KVM_X86_DISABLE_EXITS_HLT
|
2176 KVM_X86_DISABLE_EXITS_PAUSE
|
2177 KVM_X86_DISABLE_EXITS_CSTATE
);
2180 ret
= kvm_vm_enable_cap(s
, KVM_CAP_X86_DISABLE_EXITS
, 0,
2183 error_report("kvm: guest stopping CPU not supported: %s",
2191 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
2193 lhs
->selector
= rhs
->selector
;
2194 lhs
->base
= rhs
->base
;
2195 lhs
->limit
= rhs
->limit
;
2207 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
2209 unsigned flags
= rhs
->flags
;
2210 lhs
->selector
= rhs
->selector
;
2211 lhs
->base
= rhs
->base
;
2212 lhs
->limit
= rhs
->limit
;
2213 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
2214 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
2215 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
2216 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
2217 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
2218 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
2219 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
2220 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
2221 lhs
->unusable
= !lhs
->present
;
2225 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
2227 lhs
->selector
= rhs
->selector
;
2228 lhs
->base
= rhs
->base
;
2229 lhs
->limit
= rhs
->limit
;
2230 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
2231 ((rhs
->present
&& !rhs
->unusable
) * DESC_P_MASK
) |
2232 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
2233 (rhs
->db
<< DESC_B_SHIFT
) |
2234 (rhs
->s
* DESC_S_MASK
) |
2235 (rhs
->l
<< DESC_L_SHIFT
) |
2236 (rhs
->g
* DESC_G_MASK
) |
2237 (rhs
->avl
* DESC_AVL_MASK
);
2240 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
2243 *kvm_reg
= *qemu_reg
;
2245 *qemu_reg
= *kvm_reg
;
2249 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
2251 CPUX86State
*env
= &cpu
->env
;
2252 struct kvm_regs regs
;
2256 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
2262 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
2263 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
2264 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
2265 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
2266 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
2267 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
2268 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
2269 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
2270 #ifdef TARGET_X86_64
2271 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
2272 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
2273 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
2274 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
2275 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
2276 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
2277 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
2278 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
2281 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
2282 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
2285 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
2291 static int kvm_put_fpu(X86CPU
*cpu
)
2293 CPUX86State
*env
= &cpu
->env
;
2297 memset(&fpu
, 0, sizeof fpu
);
2298 fpu
.fsw
= env
->fpus
& ~(7 << 11);
2299 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
2300 fpu
.fcw
= env
->fpuc
;
2301 fpu
.last_opcode
= env
->fpop
;
2302 fpu
.last_ip
= env
->fpip
;
2303 fpu
.last_dp
= env
->fpdp
;
2304 for (i
= 0; i
< 8; ++i
) {
2305 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
2307 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
2308 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2309 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
2310 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
2312 fpu
.mxcsr
= env
->mxcsr
;
2314 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
2317 #define XSAVE_FCW_FSW 0
2318 #define XSAVE_FTW_FOP 1
2319 #define XSAVE_CWD_RIP 2
2320 #define XSAVE_CWD_RDP 4
2321 #define XSAVE_MXCSR 6
2322 #define XSAVE_ST_SPACE 8
2323 #define XSAVE_XMM_SPACE 40
2324 #define XSAVE_XSTATE_BV 128
2325 #define XSAVE_YMMH_SPACE 144
2326 #define XSAVE_BNDREGS 240
2327 #define XSAVE_BNDCSR 256
2328 #define XSAVE_OPMASK 272
2329 #define XSAVE_ZMM_Hi256 288
2330 #define XSAVE_Hi16_ZMM 416
2331 #define XSAVE_PKRU 672
2333 #define XSAVE_BYTE_OFFSET(word_offset) \
2334 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2336 #define ASSERT_OFFSET(word_offset, field) \
2337 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2338 offsetof(X86XSaveArea, field))
2340 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
2341 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
2342 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
2343 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
2344 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
2345 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
2346 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
2347 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
2348 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
2349 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
2350 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
2351 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
2352 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
2353 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
2354 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
2356 static int kvm_put_xsave(X86CPU
*cpu
)
2358 CPUX86State
*env
= &cpu
->env
;
2359 X86XSaveArea
*xsave
= env
->xsave_buf
;
2362 return kvm_put_fpu(cpu
);
2364 x86_cpu_xsave_all_areas(cpu
, xsave
);
2366 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
2369 static int kvm_put_xcrs(X86CPU
*cpu
)
2371 CPUX86State
*env
= &cpu
->env
;
2372 struct kvm_xcrs xcrs
= {};
2380 xcrs
.xcrs
[0].xcr
= 0;
2381 xcrs
.xcrs
[0].value
= env
->xcr0
;
2382 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
2385 static int kvm_put_sregs(X86CPU
*cpu
)
2387 CPUX86State
*env
= &cpu
->env
;
2388 struct kvm_sregs sregs
;
2390 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
2391 if (env
->interrupt_injected
>= 0) {
2392 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
2393 (uint64_t)1 << (env
->interrupt_injected
% 64);
2396 if ((env
->eflags
& VM_MASK
)) {
2397 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
2398 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
2399 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
2400 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
2401 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
2402 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
2404 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
2405 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
2406 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
2407 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
2408 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
2409 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
2412 set_seg(&sregs
.tr
, &env
->tr
);
2413 set_seg(&sregs
.ldt
, &env
->ldt
);
2415 sregs
.idt
.limit
= env
->idt
.limit
;
2416 sregs
.idt
.base
= env
->idt
.base
;
2417 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
2418 sregs
.gdt
.limit
= env
->gdt
.limit
;
2419 sregs
.gdt
.base
= env
->gdt
.base
;
2420 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
2422 sregs
.cr0
= env
->cr
[0];
2423 sregs
.cr2
= env
->cr
[2];
2424 sregs
.cr3
= env
->cr
[3];
2425 sregs
.cr4
= env
->cr
[4];
2427 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
2428 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
2430 sregs
.efer
= env
->efer
;
2432 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
2435 static void kvm_msr_buf_reset(X86CPU
*cpu
)
2437 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
2440 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
2442 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
2443 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
2444 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
2446 assert((void *)(entry
+ 1) <= limit
);
2448 entry
->index
= index
;
2449 entry
->reserved
= 0;
2450 entry
->data
= value
;
2454 static int kvm_put_one_msr(X86CPU
*cpu
, int index
, uint64_t value
)
2456 kvm_msr_buf_reset(cpu
);
2457 kvm_msr_entry_add(cpu
, index
, value
);
2459 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2462 void kvm_put_apicbase(X86CPU
*cpu
, uint64_t value
)
2466 ret
= kvm_put_one_msr(cpu
, MSR_IA32_APICBASE
, value
);
2470 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
2472 CPUX86State
*env
= &cpu
->env
;
2475 if (!has_msr_tsc_deadline
) {
2479 ret
= kvm_put_one_msr(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
2489 * Provide a separate write service for the feature control MSR in order to
2490 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2491 * before writing any other state because forcibly leaving nested mode
2492 * invalidates the VCPU state.
2494 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
2498 if (!has_msr_feature_control
) {
2502 ret
= kvm_put_one_msr(cpu
, MSR_IA32_FEATURE_CONTROL
,
2503 cpu
->env
.msr_ia32_feature_control
);
2512 static uint64_t make_vmx_msr_value(uint32_t index
, uint32_t features
)
2514 uint32_t default1
, can_be_one
, can_be_zero
;
2515 uint32_t must_be_one
;
2518 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2519 default1
= 0x00000016;
2521 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2522 default1
= 0x0401e172;
2524 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2525 default1
= 0x000011ff;
2527 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2528 default1
= 0x00036dff;
2530 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2537 /* If a feature bit is set, the control can be either set or clear.
2538 * Otherwise the value is limited to either 0 or 1 by default1.
2540 can_be_one
= features
| default1
;
2541 can_be_zero
= features
| ~default1
;
2542 must_be_one
= ~can_be_zero
;
2545 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2546 * Bit 32:63 -> 1 if the control bit can be one.
2548 return must_be_one
| (((uint64_t)can_be_one
) << 32);
2551 #define VMCS12_MAX_FIELD_INDEX (0x17)
2553 static void kvm_msr_entry_add_vmx(X86CPU
*cpu
, FeatureWordArray f
)
2555 uint64_t kvm_vmx_basic
=
2556 kvm_arch_get_supported_msr_feature(kvm_state
,
2557 MSR_IA32_VMX_BASIC
);
2559 if (!kvm_vmx_basic
) {
2560 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2561 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2566 uint64_t kvm_vmx_misc
=
2567 kvm_arch_get_supported_msr_feature(kvm_state
,
2569 uint64_t kvm_vmx_ept_vpid
=
2570 kvm_arch_get_supported_msr_feature(kvm_state
,
2571 MSR_IA32_VMX_EPT_VPID_CAP
);
2574 * If the guest is 64-bit, a value of 1 is allowed for the host address
2575 * space size vmexit control.
2577 uint64_t fixed_vmx_exit
= f
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
2578 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE
<< 32 : 0;
2581 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2582 * not change them for backwards compatibility.
2584 uint64_t fixed_vmx_basic
= kvm_vmx_basic
&
2585 (MSR_VMX_BASIC_VMCS_REVISION_MASK
|
2586 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK
|
2587 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK
);
2590 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2591 * change in the future but are always zero for now, clear them to be
2592 * future proof. Bits 32-63 in theory could change, though KVM does
2593 * not support dual-monitor treatment and probably never will; mask
2596 uint64_t fixed_vmx_misc
= kvm_vmx_misc
&
2597 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK
|
2598 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK
);
2601 * EPT memory types should not change either, so we do not bother
2602 * adding features for them.
2604 uint64_t fixed_vmx_ept_mask
=
2605 (f
[FEAT_VMX_SECONDARY_CTLS
] & VMX_SECONDARY_EXEC_ENABLE_EPT
?
2606 MSR_VMX_EPT_UC
| MSR_VMX_EPT_WB
: 0);
2607 uint64_t fixed_vmx_ept_vpid
= kvm_vmx_ept_vpid
& fixed_vmx_ept_mask
;
2609 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
2610 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
2611 f
[FEAT_VMX_PROCBASED_CTLS
]));
2612 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
2613 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
2614 f
[FEAT_VMX_PINBASED_CTLS
]));
2615 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_EXIT_CTLS
,
2616 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS
,
2617 f
[FEAT_VMX_EXIT_CTLS
]) | fixed_vmx_exit
);
2618 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
2619 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
2620 f
[FEAT_VMX_ENTRY_CTLS
]));
2621 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_PROCBASED_CTLS2
,
2622 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2
,
2623 f
[FEAT_VMX_SECONDARY_CTLS
]));
2624 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_EPT_VPID_CAP
,
2625 f
[FEAT_VMX_EPT_VPID_CAPS
] | fixed_vmx_ept_vpid
);
2626 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_BASIC
,
2627 f
[FEAT_VMX_BASIC
] | fixed_vmx_basic
);
2628 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_MISC
,
2629 f
[FEAT_VMX_MISC
] | fixed_vmx_misc
);
2630 if (has_msr_vmx_vmfunc
) {
2631 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_VMFUNC
, f
[FEAT_VMX_VMFUNC
]);
2635 * Just to be safe, write these with constant values. The CRn_FIXED1
2636 * MSRs are generated by KVM based on the vCPU's CPUID.
2638 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_CR0_FIXED0
,
2639 CR0_PE_MASK
| CR0_PG_MASK
| CR0_NE_MASK
);
2640 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_CR4_FIXED0
,
2642 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_VMCS_ENUM
,
2643 VMCS12_MAX_FIELD_INDEX
<< 1);
2646 static int kvm_buf_set_msrs(X86CPU
*cpu
)
2648 int ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2653 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
2654 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
2655 error_report("error: failed to set MSR 0x%" PRIx32
" to 0x%" PRIx64
,
2656 (uint32_t)e
->index
, (uint64_t)e
->data
);
2659 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2663 static void kvm_init_msrs(X86CPU
*cpu
)
2665 CPUX86State
*env
= &cpu
->env
;
2667 kvm_msr_buf_reset(cpu
);
2668 if (has_msr_arch_capabs
) {
2669 kvm_msr_entry_add(cpu
, MSR_IA32_ARCH_CAPABILITIES
,
2670 env
->features
[FEAT_ARCH_CAPABILITIES
]);
2673 if (has_msr_core_capabs
) {
2674 kvm_msr_entry_add(cpu
, MSR_IA32_CORE_CAPABILITY
,
2675 env
->features
[FEAT_CORE_CAPABILITY
]);
2678 if (has_msr_ucode_rev
) {
2679 kvm_msr_entry_add(cpu
, MSR_IA32_UCODE_REV
, cpu
->ucode_rev
);
2683 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2684 * all kernels with MSR features should have them.
2686 if (kvm_feature_msrs
&& cpu_has_vmx(env
)) {
2687 kvm_msr_entry_add_vmx(cpu
, env
->features
);
2690 assert(kvm_buf_set_msrs(cpu
) == 0);
2693 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
2695 CPUX86State
*env
= &cpu
->env
;
2698 kvm_msr_buf_reset(cpu
);
2700 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
2701 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
2702 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
2703 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
2705 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
2707 if (has_msr_hsave_pa
) {
2708 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
2710 if (has_msr_tsc_aux
) {
2711 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
2713 if (has_msr_tsc_adjust
) {
2714 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
2716 if (has_msr_misc_enable
) {
2717 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
2718 env
->msr_ia32_misc_enable
);
2720 if (has_msr_smbase
) {
2721 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
2723 if (has_msr_smi_count
) {
2724 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, env
->msr_smi_count
);
2726 if (has_msr_bndcfgs
) {
2727 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
2730 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
2732 if (has_msr_umwait
) {
2733 kvm_msr_entry_add(cpu
, MSR_IA32_UMWAIT_CONTROL
, env
->umwait
);
2735 if (has_msr_spec_ctrl
) {
2736 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, env
->spec_ctrl
);
2738 if (has_msr_tsx_ctrl
) {
2739 kvm_msr_entry_add(cpu
, MSR_IA32_TSX_CTRL
, env
->tsx_ctrl
);
2741 if (has_msr_virt_ssbd
) {
2742 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, env
->virt_ssbd
);
2745 #ifdef TARGET_X86_64
2746 if (lm_capable_kernel
) {
2747 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
2748 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
2749 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
2750 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
2755 * The following MSRs have side effects on the guest or are too heavy
2756 * for normal writeback. Limit them to reset or full state updates.
2758 if (level
>= KVM_PUT_RESET_STATE
) {
2759 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
2760 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
2761 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
2762 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
2763 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
2765 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
2766 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
2768 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
2769 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
2772 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_POLL_CONTROL
)) {
2773 kvm_msr_entry_add(cpu
, MSR_KVM_POLL_CONTROL
, env
->poll_control_msr
);
2776 if (has_architectural_pmu_version
> 0) {
2777 if (has_architectural_pmu_version
> 1) {
2778 /* Stop the counter. */
2779 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
2780 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2783 /* Set the counter values. */
2784 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
2785 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
2786 env
->msr_fixed_counters
[i
]);
2788 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
2789 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
2790 env
->msr_gp_counters
[i
]);
2791 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
2792 env
->msr_gp_evtsel
[i
]);
2794 if (has_architectural_pmu_version
> 1) {
2795 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
2796 env
->msr_global_status
);
2797 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
2798 env
->msr_global_ovf_ctrl
);
2800 /* Now start the PMU. */
2801 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
2802 env
->msr_fixed_ctr_ctrl
);
2803 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
2804 env
->msr_global_ctrl
);
2808 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2809 * only sync them to KVM on the first cpu
2811 if (current_cpu
== first_cpu
) {
2812 if (has_msr_hv_hypercall
) {
2813 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
2814 env
->msr_hv_guest_os_id
);
2815 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
2816 env
->msr_hv_hypercall
);
2818 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_TIME
)) {
2819 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
,
2822 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_REENLIGHTENMENT
)) {
2823 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
,
2824 env
->msr_hv_reenlightenment_control
);
2825 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
,
2826 env
->msr_hv_tsc_emulation_control
);
2827 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
,
2828 env
->msr_hv_tsc_emulation_status
);
2831 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VAPIC
)) {
2832 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
2835 if (has_msr_hv_crash
) {
2838 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++)
2839 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
2840 env
->msr_hv_crash_params
[j
]);
2842 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
, HV_CRASH_CTL_NOTIFY
);
2844 if (has_msr_hv_runtime
) {
2845 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
2847 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
)
2848 && hv_vpindex_settable
) {
2849 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_INDEX
,
2850 hyperv_vp_index(CPU(cpu
)));
2852 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
2855 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, HV_SYNIC_VERSION
);
2857 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
2858 env
->msr_hv_synic_control
);
2859 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
2860 env
->msr_hv_synic_evt_page
);
2861 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
2862 env
->msr_hv_synic_msg_page
);
2864 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
2865 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
2866 env
->msr_hv_synic_sint
[j
]);
2869 if (has_msr_hv_stimer
) {
2872 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
2873 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
2874 env
->msr_hv_stimer_config
[j
]);
2877 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
2878 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
2879 env
->msr_hv_stimer_count
[j
]);
2882 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
2883 uint64_t phys_mask
= MAKE_64BIT_MASK(0, cpu
->phys_bits
);
2885 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
2886 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
2887 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
2888 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
2889 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
2890 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
2891 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
2892 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
2893 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
2894 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
2895 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
2896 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
2897 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2898 /* The CPU GPs if we write to a bit above the physical limit of
2899 * the host CPU (and KVM emulates that)
2901 uint64_t mask
= env
->mtrr_var
[i
].mask
;
2904 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
2905 env
->mtrr_var
[i
].base
);
2906 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), mask
);
2909 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
2910 int addr_num
= kvm_arch_get_supported_cpuid(kvm_state
,
2911 0x14, 1, R_EAX
) & 0x7;
2913 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
,
2914 env
->msr_rtit_ctrl
);
2915 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
,
2916 env
->msr_rtit_status
);
2917 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
,
2918 env
->msr_rtit_output_base
);
2919 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
,
2920 env
->msr_rtit_output_mask
);
2921 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
,
2922 env
->msr_rtit_cr3_match
);
2923 for (i
= 0; i
< addr_num
; i
++) {
2924 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
,
2925 env
->msr_rtit_addrs
[i
]);
2929 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2930 * kvm_put_msr_feature_control. */
2936 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
2937 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
2938 if (has_msr_mcg_ext_ctl
) {
2939 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, env
->mcg_ext_ctl
);
2941 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2942 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
2946 return kvm_buf_set_msrs(cpu
);
2950 static int kvm_get_fpu(X86CPU
*cpu
)
2952 CPUX86State
*env
= &cpu
->env
;
2956 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
2961 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
2962 env
->fpus
= fpu
.fsw
;
2963 env
->fpuc
= fpu
.fcw
;
2964 env
->fpop
= fpu
.last_opcode
;
2965 env
->fpip
= fpu
.last_ip
;
2966 env
->fpdp
= fpu
.last_dp
;
2967 for (i
= 0; i
< 8; ++i
) {
2968 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
2970 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
2971 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2972 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
2973 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
2975 env
->mxcsr
= fpu
.mxcsr
;
2980 static int kvm_get_xsave(X86CPU
*cpu
)
2982 CPUX86State
*env
= &cpu
->env
;
2983 X86XSaveArea
*xsave
= env
->xsave_buf
;
2987 return kvm_get_fpu(cpu
);
2990 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
2994 x86_cpu_xrstor_all_areas(cpu
, xsave
);
2999 static int kvm_get_xcrs(X86CPU
*cpu
)
3001 CPUX86State
*env
= &cpu
->env
;
3003 struct kvm_xcrs xcrs
;
3009 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
3014 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
3015 /* Only support xcr0 now */
3016 if (xcrs
.xcrs
[i
].xcr
== 0) {
3017 env
->xcr0
= xcrs
.xcrs
[i
].value
;
3024 static int kvm_get_sregs(X86CPU
*cpu
)
3026 CPUX86State
*env
= &cpu
->env
;
3027 struct kvm_sregs sregs
;
3030 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
3035 /* There can only be one pending IRQ set in the bitmap at a time, so try
3036 to find it and save its number instead (-1 for none). */
3037 env
->interrupt_injected
= -1;
3038 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
3039 if (sregs
.interrupt_bitmap
[i
]) {
3040 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
3041 env
->interrupt_injected
= i
* 64 + bit
;
3046 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
3047 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
3048 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
3049 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
3050 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
3051 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
3053 get_seg(&env
->tr
, &sregs
.tr
);
3054 get_seg(&env
->ldt
, &sregs
.ldt
);
3056 env
->idt
.limit
= sregs
.idt
.limit
;
3057 env
->idt
.base
= sregs
.idt
.base
;
3058 env
->gdt
.limit
= sregs
.gdt
.limit
;
3059 env
->gdt
.base
= sregs
.gdt
.base
;
3061 env
->cr
[0] = sregs
.cr0
;
3062 env
->cr
[2] = sregs
.cr2
;
3063 env
->cr
[3] = sregs
.cr3
;
3064 env
->cr
[4] = sregs
.cr4
;
3066 env
->efer
= sregs
.efer
;
3068 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3069 x86_update_hflags(env
);
3074 static int kvm_get_msrs(X86CPU
*cpu
)
3076 CPUX86State
*env
= &cpu
->env
;
3077 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
3079 uint64_t mtrr_top_bits
;
3081 kvm_msr_buf_reset(cpu
);
3083 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
3084 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
3085 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
3086 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
3088 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
3090 if (has_msr_hsave_pa
) {
3091 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
3093 if (has_msr_tsc_aux
) {
3094 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
3096 if (has_msr_tsc_adjust
) {
3097 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
3099 if (has_msr_tsc_deadline
) {
3100 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
3102 if (has_msr_misc_enable
) {
3103 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
3105 if (has_msr_smbase
) {
3106 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
3108 if (has_msr_smi_count
) {
3109 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, 0);
3111 if (has_msr_feature_control
) {
3112 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
3114 if (has_msr_bndcfgs
) {
3115 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
3118 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
3120 if (has_msr_umwait
) {
3121 kvm_msr_entry_add(cpu
, MSR_IA32_UMWAIT_CONTROL
, 0);
3123 if (has_msr_spec_ctrl
) {
3124 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, 0);
3126 if (has_msr_tsx_ctrl
) {
3127 kvm_msr_entry_add(cpu
, MSR_IA32_TSX_CTRL
, 0);
3129 if (has_msr_virt_ssbd
) {
3130 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, 0);
3132 if (!env
->tsc_valid
) {
3133 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
3134 env
->tsc_valid
= !runstate_is_running();
3137 #ifdef TARGET_X86_64
3138 if (lm_capable_kernel
) {
3139 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
3140 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
3141 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
3142 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
3145 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
3146 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
3147 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
3148 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
3150 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
3151 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
3153 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
3154 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
3156 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_POLL_CONTROL
)) {
3157 kvm_msr_entry_add(cpu
, MSR_KVM_POLL_CONTROL
, 1);
3159 if (has_architectural_pmu_version
> 0) {
3160 if (has_architectural_pmu_version
> 1) {
3161 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
3162 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
3163 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
3164 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
3166 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
3167 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
3169 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
3170 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
3171 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
3176 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
3177 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
3178 if (has_msr_mcg_ext_ctl
) {
3179 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, 0);
3181 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
3182 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
3186 if (has_msr_hv_hypercall
) {
3187 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
3188 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
3190 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VAPIC
)) {
3191 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
3193 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_TIME
)) {
3194 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
3196 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_REENLIGHTENMENT
)) {
3197 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
, 0);
3198 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
, 0);
3199 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
, 0);
3201 if (has_msr_hv_crash
) {
3204 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++) {
3205 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
3208 if (has_msr_hv_runtime
) {
3209 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
3211 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
3214 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
3215 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
3216 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
3217 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
3218 kvm_msr_entry_add(cpu
, msr
, 0);
3221 if (has_msr_hv_stimer
) {
3224 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
3226 kvm_msr_entry_add(cpu
, msr
, 0);
3229 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
3230 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
3231 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
3232 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
3233 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
3234 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
3235 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
3236 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
3237 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
3238 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
3239 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
3240 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
3241 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
3242 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
3243 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
3244 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
3248 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
3250 kvm_arch_get_supported_cpuid(kvm_state
, 0x14, 1, R_EAX
) & 0x7;
3252 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
, 0);
3253 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
, 0);
3254 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
, 0);
3255 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
, 0);
3256 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
, 0);
3257 for (i
= 0; i
< addr_num
; i
++) {
3258 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
, 0);
3262 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
3267 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
3268 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
3269 error_report("error: failed to get MSR 0x%" PRIx32
,
3270 (uint32_t)e
->index
);
3273 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
3275 * MTRR masks: Each mask consists of 5 parts
3276 * a 10..0: must be zero
3278 * c n-1.12: actual mask bits
3279 * d 51..n: reserved must be zero
3280 * e 63.52: reserved must be zero
3282 * 'n' is the number of physical bits supported by the CPU and is
3283 * apparently always <= 52. We know our 'n' but don't know what
3284 * the destinations 'n' is; it might be smaller, in which case
3285 * it masks (c) on loading. It might be larger, in which case
3286 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3287 * we're migrating to.
3290 if (cpu
->fill_mtrr_mask
) {
3291 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS
> 52);
3292 assert(cpu
->phys_bits
<= TARGET_PHYS_ADDR_SPACE_BITS
);
3293 mtrr_top_bits
= MAKE_64BIT_MASK(cpu
->phys_bits
, 52 - cpu
->phys_bits
);
3298 for (i
= 0; i
< ret
; i
++) {
3299 uint32_t index
= msrs
[i
].index
;
3301 case MSR_IA32_SYSENTER_CS
:
3302 env
->sysenter_cs
= msrs
[i
].data
;
3304 case MSR_IA32_SYSENTER_ESP
:
3305 env
->sysenter_esp
= msrs
[i
].data
;
3307 case MSR_IA32_SYSENTER_EIP
:
3308 env
->sysenter_eip
= msrs
[i
].data
;
3311 env
->pat
= msrs
[i
].data
;
3314 env
->star
= msrs
[i
].data
;
3316 #ifdef TARGET_X86_64
3318 env
->cstar
= msrs
[i
].data
;
3320 case MSR_KERNELGSBASE
:
3321 env
->kernelgsbase
= msrs
[i
].data
;
3324 env
->fmask
= msrs
[i
].data
;
3327 env
->lstar
= msrs
[i
].data
;
3331 env
->tsc
= msrs
[i
].data
;
3334 env
->tsc_aux
= msrs
[i
].data
;
3336 case MSR_TSC_ADJUST
:
3337 env
->tsc_adjust
= msrs
[i
].data
;
3339 case MSR_IA32_TSCDEADLINE
:
3340 env
->tsc_deadline
= msrs
[i
].data
;
3342 case MSR_VM_HSAVE_PA
:
3343 env
->vm_hsave
= msrs
[i
].data
;
3345 case MSR_KVM_SYSTEM_TIME
:
3346 env
->system_time_msr
= msrs
[i
].data
;
3348 case MSR_KVM_WALL_CLOCK
:
3349 env
->wall_clock_msr
= msrs
[i
].data
;
3351 case MSR_MCG_STATUS
:
3352 env
->mcg_status
= msrs
[i
].data
;
3355 env
->mcg_ctl
= msrs
[i
].data
;
3357 case MSR_MCG_EXT_CTL
:
3358 env
->mcg_ext_ctl
= msrs
[i
].data
;
3360 case MSR_IA32_MISC_ENABLE
:
3361 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
3363 case MSR_IA32_SMBASE
:
3364 env
->smbase
= msrs
[i
].data
;
3367 env
->msr_smi_count
= msrs
[i
].data
;
3369 case MSR_IA32_FEATURE_CONTROL
:
3370 env
->msr_ia32_feature_control
= msrs
[i
].data
;
3372 case MSR_IA32_BNDCFGS
:
3373 env
->msr_bndcfgs
= msrs
[i
].data
;
3376 env
->xss
= msrs
[i
].data
;
3378 case MSR_IA32_UMWAIT_CONTROL
:
3379 env
->umwait
= msrs
[i
].data
;
3382 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
3383 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
3384 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
3387 case MSR_KVM_ASYNC_PF_EN
:
3388 env
->async_pf_en_msr
= msrs
[i
].data
;
3390 case MSR_KVM_PV_EOI_EN
:
3391 env
->pv_eoi_en_msr
= msrs
[i
].data
;
3393 case MSR_KVM_STEAL_TIME
:
3394 env
->steal_time_msr
= msrs
[i
].data
;
3396 case MSR_KVM_POLL_CONTROL
: {
3397 env
->poll_control_msr
= msrs
[i
].data
;
3400 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
3401 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
3403 case MSR_CORE_PERF_GLOBAL_CTRL
:
3404 env
->msr_global_ctrl
= msrs
[i
].data
;
3406 case MSR_CORE_PERF_GLOBAL_STATUS
:
3407 env
->msr_global_status
= msrs
[i
].data
;
3409 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
3410 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
3412 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
3413 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
3415 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
3416 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
3418 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
3419 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
3421 case HV_X64_MSR_HYPERCALL
:
3422 env
->msr_hv_hypercall
= msrs
[i
].data
;
3424 case HV_X64_MSR_GUEST_OS_ID
:
3425 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
3427 case HV_X64_MSR_APIC_ASSIST_PAGE
:
3428 env
->msr_hv_vapic
= msrs
[i
].data
;
3430 case HV_X64_MSR_REFERENCE_TSC
:
3431 env
->msr_hv_tsc
= msrs
[i
].data
;
3433 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
3434 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
3436 case HV_X64_MSR_VP_RUNTIME
:
3437 env
->msr_hv_runtime
= msrs
[i
].data
;
3439 case HV_X64_MSR_SCONTROL
:
3440 env
->msr_hv_synic_control
= msrs
[i
].data
;
3442 case HV_X64_MSR_SIEFP
:
3443 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
3445 case HV_X64_MSR_SIMP
:
3446 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
3448 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
3449 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
3451 case HV_X64_MSR_STIMER0_CONFIG
:
3452 case HV_X64_MSR_STIMER1_CONFIG
:
3453 case HV_X64_MSR_STIMER2_CONFIG
:
3454 case HV_X64_MSR_STIMER3_CONFIG
:
3455 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
3458 case HV_X64_MSR_STIMER0_COUNT
:
3459 case HV_X64_MSR_STIMER1_COUNT
:
3460 case HV_X64_MSR_STIMER2_COUNT
:
3461 case HV_X64_MSR_STIMER3_COUNT
:
3462 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
3465 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
3466 env
->msr_hv_reenlightenment_control
= msrs
[i
].data
;
3468 case HV_X64_MSR_TSC_EMULATION_CONTROL
:
3469 env
->msr_hv_tsc_emulation_control
= msrs
[i
].data
;
3471 case HV_X64_MSR_TSC_EMULATION_STATUS
:
3472 env
->msr_hv_tsc_emulation_status
= msrs
[i
].data
;
3474 case MSR_MTRRdefType
:
3475 env
->mtrr_deftype
= msrs
[i
].data
;
3477 case MSR_MTRRfix64K_00000
:
3478 env
->mtrr_fixed
[0] = msrs
[i
].data
;
3480 case MSR_MTRRfix16K_80000
:
3481 env
->mtrr_fixed
[1] = msrs
[i
].data
;
3483 case MSR_MTRRfix16K_A0000
:
3484 env
->mtrr_fixed
[2] = msrs
[i
].data
;
3486 case MSR_MTRRfix4K_C0000
:
3487 env
->mtrr_fixed
[3] = msrs
[i
].data
;
3489 case MSR_MTRRfix4K_C8000
:
3490 env
->mtrr_fixed
[4] = msrs
[i
].data
;
3492 case MSR_MTRRfix4K_D0000
:
3493 env
->mtrr_fixed
[5] = msrs
[i
].data
;
3495 case MSR_MTRRfix4K_D8000
:
3496 env
->mtrr_fixed
[6] = msrs
[i
].data
;
3498 case MSR_MTRRfix4K_E0000
:
3499 env
->mtrr_fixed
[7] = msrs
[i
].data
;
3501 case MSR_MTRRfix4K_E8000
:
3502 env
->mtrr_fixed
[8] = msrs
[i
].data
;
3504 case MSR_MTRRfix4K_F0000
:
3505 env
->mtrr_fixed
[9] = msrs
[i
].data
;
3507 case MSR_MTRRfix4K_F8000
:
3508 env
->mtrr_fixed
[10] = msrs
[i
].data
;
3510 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
3512 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
|
3515 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
3518 case MSR_IA32_SPEC_CTRL
:
3519 env
->spec_ctrl
= msrs
[i
].data
;
3521 case MSR_IA32_TSX_CTRL
:
3522 env
->tsx_ctrl
= msrs
[i
].data
;
3525 env
->virt_ssbd
= msrs
[i
].data
;
3527 case MSR_IA32_RTIT_CTL
:
3528 env
->msr_rtit_ctrl
= msrs
[i
].data
;
3530 case MSR_IA32_RTIT_STATUS
:
3531 env
->msr_rtit_status
= msrs
[i
].data
;
3533 case MSR_IA32_RTIT_OUTPUT_BASE
:
3534 env
->msr_rtit_output_base
= msrs
[i
].data
;
3536 case MSR_IA32_RTIT_OUTPUT_MASK
:
3537 env
->msr_rtit_output_mask
= msrs
[i
].data
;
3539 case MSR_IA32_RTIT_CR3_MATCH
:
3540 env
->msr_rtit_cr3_match
= msrs
[i
].data
;
3542 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
3543 env
->msr_rtit_addrs
[index
- MSR_IA32_RTIT_ADDR0_A
] = msrs
[i
].data
;
3551 static int kvm_put_mp_state(X86CPU
*cpu
)
3553 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
3555 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
3558 static int kvm_get_mp_state(X86CPU
*cpu
)
3560 CPUState
*cs
= CPU(cpu
);
3561 CPUX86State
*env
= &cpu
->env
;
3562 struct kvm_mp_state mp_state
;
3565 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
3569 env
->mp_state
= mp_state
.mp_state
;
3570 if (kvm_irqchip_in_kernel()) {
3571 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
3576 static int kvm_get_apic(X86CPU
*cpu
)
3578 DeviceState
*apic
= cpu
->apic_state
;
3579 struct kvm_lapic_state kapic
;
3582 if (apic
&& kvm_irqchip_in_kernel()) {
3583 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
3588 kvm_get_apic_state(apic
, &kapic
);
3593 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
3595 CPUState
*cs
= CPU(cpu
);
3596 CPUX86State
*env
= &cpu
->env
;
3597 struct kvm_vcpu_events events
= {};
3599 if (!kvm_has_vcpu_events()) {
3605 if (has_exception_payload
) {
3606 events
.flags
|= KVM_VCPUEVENT_VALID_PAYLOAD
;
3607 events
.exception
.pending
= env
->exception_pending
;
3608 events
.exception_has_payload
= env
->exception_has_payload
;
3609 events
.exception_payload
= env
->exception_payload
;
3611 events
.exception
.nr
= env
->exception_nr
;
3612 events
.exception
.injected
= env
->exception_injected
;
3613 events
.exception
.has_error_code
= env
->has_error_code
;
3614 events
.exception
.error_code
= env
->error_code
;
3616 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
3617 events
.interrupt
.nr
= env
->interrupt_injected
;
3618 events
.interrupt
.soft
= env
->soft_interrupt
;
3620 events
.nmi
.injected
= env
->nmi_injected
;
3621 events
.nmi
.pending
= env
->nmi_pending
;
3622 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
3624 events
.sipi_vector
= env
->sipi_vector
;
3626 if (has_msr_smbase
) {
3627 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
3628 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
3629 if (kvm_irqchip_in_kernel()) {
3630 /* As soon as these are moved to the kernel, remove them
3631 * from cs->interrupt_request.
3633 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
3634 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
3635 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
3637 /* Keep these in cs->interrupt_request. */
3638 events
.smi
.pending
= 0;
3639 events
.smi
.latched_init
= 0;
3641 /* Stop SMI delivery on old machine types to avoid a reboot
3642 * on an inward migration of an old VM.
3644 if (!cpu
->kvm_no_smi_migration
) {
3645 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
3649 if (level
>= KVM_PUT_RESET_STATE
) {
3650 events
.flags
|= KVM_VCPUEVENT_VALID_NMI_PENDING
;
3651 if (env
->mp_state
== KVM_MP_STATE_SIPI_RECEIVED
) {
3652 events
.flags
|= KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
3656 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
3659 static int kvm_get_vcpu_events(X86CPU
*cpu
)
3661 CPUX86State
*env
= &cpu
->env
;
3662 struct kvm_vcpu_events events
;
3665 if (!kvm_has_vcpu_events()) {
3669 memset(&events
, 0, sizeof(events
));
3670 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
3675 if (events
.flags
& KVM_VCPUEVENT_VALID_PAYLOAD
) {
3676 env
->exception_pending
= events
.exception
.pending
;
3677 env
->exception_has_payload
= events
.exception_has_payload
;
3678 env
->exception_payload
= events
.exception_payload
;
3680 env
->exception_pending
= 0;
3681 env
->exception_has_payload
= false;
3683 env
->exception_injected
= events
.exception
.injected
;
3685 (env
->exception_pending
|| env
->exception_injected
) ?
3686 events
.exception
.nr
: -1;
3687 env
->has_error_code
= events
.exception
.has_error_code
;
3688 env
->error_code
= events
.exception
.error_code
;
3690 env
->interrupt_injected
=
3691 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
3692 env
->soft_interrupt
= events
.interrupt
.soft
;
3694 env
->nmi_injected
= events
.nmi
.injected
;
3695 env
->nmi_pending
= events
.nmi
.pending
;
3696 if (events
.nmi
.masked
) {
3697 env
->hflags2
|= HF2_NMI_MASK
;
3699 env
->hflags2
&= ~HF2_NMI_MASK
;
3702 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
3703 if (events
.smi
.smm
) {
3704 env
->hflags
|= HF_SMM_MASK
;
3706 env
->hflags
&= ~HF_SMM_MASK
;
3708 if (events
.smi
.pending
) {
3709 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
3711 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
3713 if (events
.smi
.smm_inside_nmi
) {
3714 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
3716 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
3718 if (events
.smi
.latched_init
) {
3719 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
3721 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
3725 env
->sipi_vector
= events
.sipi_vector
;
3730 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
3732 CPUState
*cs
= CPU(cpu
);
3733 CPUX86State
*env
= &cpu
->env
;
3735 unsigned long reinject_trap
= 0;
3737 if (!kvm_has_vcpu_events()) {
3738 if (env
->exception_nr
== EXCP01_DB
) {
3739 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
3740 } else if (env
->exception_injected
== EXCP03_INT3
) {
3741 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
3743 kvm_reset_exception(env
);
3747 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3748 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3749 * by updating the debug state once again if single-stepping is on.
3750 * Another reason to call kvm_update_guest_debug here is a pending debug
3751 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3752 * reinject them via SET_GUEST_DEBUG.
3754 if (reinject_trap
||
3755 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
3756 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
3761 static int kvm_put_debugregs(X86CPU
*cpu
)
3763 CPUX86State
*env
= &cpu
->env
;
3764 struct kvm_debugregs dbgregs
;
3767 if (!kvm_has_debugregs()) {
3771 memset(&dbgregs
, 0, sizeof(dbgregs
));
3772 for (i
= 0; i
< 4; i
++) {
3773 dbgregs
.db
[i
] = env
->dr
[i
];
3775 dbgregs
.dr6
= env
->dr
[6];
3776 dbgregs
.dr7
= env
->dr
[7];
3779 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
3782 static int kvm_get_debugregs(X86CPU
*cpu
)
3784 CPUX86State
*env
= &cpu
->env
;
3785 struct kvm_debugregs dbgregs
;
3788 if (!kvm_has_debugregs()) {
3792 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
3796 for (i
= 0; i
< 4; i
++) {
3797 env
->dr
[i
] = dbgregs
.db
[i
];
3799 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
3800 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
3805 static int kvm_put_nested_state(X86CPU
*cpu
)
3807 CPUX86State
*env
= &cpu
->env
;
3808 int max_nested_state_len
= kvm_max_nested_state_length();
3810 if (!env
->nested_state
) {
3814 assert(env
->nested_state
->size
<= max_nested_state_len
);
3815 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_NESTED_STATE
, env
->nested_state
);
3818 static int kvm_get_nested_state(X86CPU
*cpu
)
3820 CPUX86State
*env
= &cpu
->env
;
3821 int max_nested_state_len
= kvm_max_nested_state_length();
3824 if (!env
->nested_state
) {
3829 * It is possible that migration restored a smaller size into
3830 * nested_state->hdr.size than what our kernel support.
3831 * We preserve migration origin nested_state->hdr.size for
3832 * call to KVM_SET_NESTED_STATE but wish that our next call
3833 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3835 env
->nested_state
->size
= max_nested_state_len
;
3837 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_NESTED_STATE
, env
->nested_state
);
3842 if (env
->nested_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
) {
3843 env
->hflags
|= HF_GUEST_MASK
;
3845 env
->hflags
&= ~HF_GUEST_MASK
;
3851 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
3853 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3856 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
3858 if (level
>= KVM_PUT_RESET_STATE
) {
3859 ret
= kvm_put_nested_state(x86_cpu
);
3864 ret
= kvm_put_msr_feature_control(x86_cpu
);
3870 if (level
== KVM_PUT_FULL_STATE
) {
3871 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3872 * because TSC frequency mismatch shouldn't abort migration,
3873 * unless the user explicitly asked for a more strict TSC
3874 * setting (e.g. using an explicit "tsc-freq" option).
3876 kvm_arch_set_tsc_khz(cpu
);
3879 ret
= kvm_getput_regs(x86_cpu
, 1);
3883 ret
= kvm_put_xsave(x86_cpu
);
3887 ret
= kvm_put_xcrs(x86_cpu
);
3891 ret
= kvm_put_sregs(x86_cpu
);
3895 /* must be before kvm_put_msrs */
3896 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
3900 ret
= kvm_put_msrs(x86_cpu
, level
);
3904 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
3908 if (level
>= KVM_PUT_RESET_STATE
) {
3909 ret
= kvm_put_mp_state(x86_cpu
);
3915 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
3919 ret
= kvm_put_debugregs(x86_cpu
);
3924 ret
= kvm_guest_debug_workarounds(x86_cpu
);
3931 int kvm_arch_get_registers(CPUState
*cs
)
3933 X86CPU
*cpu
= X86_CPU(cs
);
3936 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
3938 ret
= kvm_get_vcpu_events(cpu
);
3943 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3944 * KVM_GET_REGS and KVM_GET_SREGS.
3946 ret
= kvm_get_mp_state(cpu
);
3950 ret
= kvm_getput_regs(cpu
, 0);
3954 ret
= kvm_get_xsave(cpu
);
3958 ret
= kvm_get_xcrs(cpu
);
3962 ret
= kvm_get_sregs(cpu
);
3966 ret
= kvm_get_msrs(cpu
);
3970 ret
= kvm_get_apic(cpu
);
3974 ret
= kvm_get_debugregs(cpu
);
3978 ret
= kvm_get_nested_state(cpu
);
3984 cpu_sync_bndcs_hflags(&cpu
->env
);
3988 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
3990 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3991 CPUX86State
*env
= &x86_cpu
->env
;
3995 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
3996 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
3997 qemu_mutex_lock_iothread();
3998 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
3999 qemu_mutex_unlock_iothread();
4000 DPRINTF("injected NMI\n");
4001 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
4003 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
4007 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
4008 qemu_mutex_lock_iothread();
4009 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
4010 qemu_mutex_unlock_iothread();
4011 DPRINTF("injected SMI\n");
4012 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
4014 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
4020 if (!kvm_pic_in_kernel()) {
4021 qemu_mutex_lock_iothread();
4024 /* Force the VCPU out of its inner loop to process any INIT requests
4025 * or (for userspace APIC, but it is cheap to combine the checks here)
4026 * pending TPR access reports.
4028 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
4029 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
4030 !(env
->hflags
& HF_SMM_MASK
)) {
4031 cpu
->exit_request
= 1;
4033 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
4034 cpu
->exit_request
= 1;
4038 if (!kvm_pic_in_kernel()) {
4039 /* Try to inject an interrupt if the guest can accept it */
4040 if (run
->ready_for_interrupt_injection
&&
4041 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4042 (env
->eflags
& IF_MASK
)) {
4045 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
4046 irq
= cpu_get_pic_interrupt(env
);
4048 struct kvm_interrupt intr
;
4051 DPRINTF("injected interrupt %d\n", irq
);
4052 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
4055 "KVM: injection failed, interrupt lost (%s)\n",
4061 /* If we have an interrupt but the guest is not ready to receive an
4062 * interrupt, request an interrupt window exit. This will
4063 * cause a return to userspace as soon as the guest is ready to
4064 * receive interrupts. */
4065 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
4066 run
->request_interrupt_window
= 1;
4068 run
->request_interrupt_window
= 0;
4071 DPRINTF("setting tpr\n");
4072 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
4074 qemu_mutex_unlock_iothread();
4078 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
4080 X86CPU
*x86_cpu
= X86_CPU(cpu
);
4081 CPUX86State
*env
= &x86_cpu
->env
;
4083 if (run
->flags
& KVM_RUN_X86_SMM
) {
4084 env
->hflags
|= HF_SMM_MASK
;
4086 env
->hflags
&= ~HF_SMM_MASK
;
4089 env
->eflags
|= IF_MASK
;
4091 env
->eflags
&= ~IF_MASK
;
4094 /* We need to protect the apic state against concurrent accesses from
4095 * different threads in case the userspace irqchip is used. */
4096 if (!kvm_irqchip_in_kernel()) {
4097 qemu_mutex_lock_iothread();
4099 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
4100 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
4101 if (!kvm_irqchip_in_kernel()) {
4102 qemu_mutex_unlock_iothread();
4104 return cpu_get_mem_attrs(env
);
4107 int kvm_arch_process_async_events(CPUState
*cs
)
4109 X86CPU
*cpu
= X86_CPU(cs
);
4110 CPUX86State
*env
= &cpu
->env
;
4112 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
4113 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4114 assert(env
->mcg_cap
);
4116 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
4118 kvm_cpu_synchronize_state(cs
);
4120 if (env
->exception_nr
== EXCP08_DBLE
) {
4121 /* this means triple fault */
4122 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
4123 cs
->exit_request
= 1;
4126 kvm_queue_exception(env
, EXCP12_MCHK
, 0, 0);
4127 env
->has_error_code
= 0;
4130 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
4131 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
4135 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
4136 !(env
->hflags
& HF_SMM_MASK
)) {
4137 kvm_cpu_synchronize_state(cs
);
4141 if (kvm_irqchip_in_kernel()) {
4145 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
4146 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
4147 apic_poll_irq(cpu
->apic_state
);
4149 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4150 (env
->eflags
& IF_MASK
)) ||
4151 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
4154 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
4155 kvm_cpu_synchronize_state(cs
);
4158 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
4159 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
4160 kvm_cpu_synchronize_state(cs
);
4161 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
4162 env
->tpr_access_type
);
4168 static int kvm_handle_halt(X86CPU
*cpu
)
4170 CPUState
*cs
= CPU(cpu
);
4171 CPUX86State
*env
= &cpu
->env
;
4173 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4174 (env
->eflags
& IF_MASK
)) &&
4175 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
4183 static int kvm_handle_tpr_access(X86CPU
*cpu
)
4185 CPUState
*cs
= CPU(cpu
);
4186 struct kvm_run
*run
= cs
->kvm_run
;
4188 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
4189 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
4194 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
4196 static const uint8_t int3
= 0xcc;
4198 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
4199 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
4205 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
4209 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
4210 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
4222 static int nb_hw_breakpoint
;
4224 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
4228 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
4229 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
4230 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
4237 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
4238 target_ulong len
, int type
)
4241 case GDB_BREAKPOINT_HW
:
4244 case GDB_WATCHPOINT_WRITE
:
4245 case GDB_WATCHPOINT_ACCESS
:
4252 if (addr
& (len
- 1)) {
4264 if (nb_hw_breakpoint
== 4) {
4267 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
4270 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
4271 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
4272 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
4278 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
4279 target_ulong len
, int type
)
4283 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
4288 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
4293 void kvm_arch_remove_all_hw_breakpoints(void)
4295 nb_hw_breakpoint
= 0;
4298 static CPUWatchpoint hw_watchpoint
;
4300 static int kvm_handle_debug(X86CPU
*cpu
,
4301 struct kvm_debug_exit_arch
*arch_info
)
4303 CPUState
*cs
= CPU(cpu
);
4304 CPUX86State
*env
= &cpu
->env
;
4308 if (arch_info
->exception
== EXCP01_DB
) {
4309 if (arch_info
->dr6
& DR6_BS
) {
4310 if (cs
->singlestep_enabled
) {
4314 for (n
= 0; n
< 4; n
++) {
4315 if (arch_info
->dr6
& (1 << n
)) {
4316 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
4322 cs
->watchpoint_hit
= &hw_watchpoint
;
4323 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
4324 hw_watchpoint
.flags
= BP_MEM_WRITE
;
4328 cs
->watchpoint_hit
= &hw_watchpoint
;
4329 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
4330 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
4336 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
4340 cpu_synchronize_state(cs
);
4341 assert(env
->exception_nr
== -1);
4344 kvm_queue_exception(env
, arch_info
->exception
,
4345 arch_info
->exception
== EXCP01_DB
,
4347 env
->has_error_code
= 0;
4353 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
4355 const uint8_t type_code
[] = {
4356 [GDB_BREAKPOINT_HW
] = 0x0,
4357 [GDB_WATCHPOINT_WRITE
] = 0x1,
4358 [GDB_WATCHPOINT_ACCESS
] = 0x3
4360 const uint8_t len_code
[] = {
4361 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4365 if (kvm_sw_breakpoints_active(cpu
)) {
4366 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
4368 if (nb_hw_breakpoint
> 0) {
4369 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
4370 dbg
->arch
.debugreg
[7] = 0x0600;
4371 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
4372 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
4373 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
4374 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
4375 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
4380 static bool host_supports_vmx(void)
4382 uint32_t ecx
, unused
;
4384 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
4385 return ecx
& CPUID_EXT_VMX
;
4388 #define VMX_INVALID_GUEST_STATE 0x80000021
4390 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
4392 X86CPU
*cpu
= X86_CPU(cs
);
4396 switch (run
->exit_reason
) {
4398 DPRINTF("handle_hlt\n");
4399 qemu_mutex_lock_iothread();
4400 ret
= kvm_handle_halt(cpu
);
4401 qemu_mutex_unlock_iothread();
4403 case KVM_EXIT_SET_TPR
:
4406 case KVM_EXIT_TPR_ACCESS
:
4407 qemu_mutex_lock_iothread();
4408 ret
= kvm_handle_tpr_access(cpu
);
4409 qemu_mutex_unlock_iothread();
4411 case KVM_EXIT_FAIL_ENTRY
:
4412 code
= run
->fail_entry
.hardware_entry_failure_reason
;
4413 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
4415 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
4417 "\nIf you're running a guest on an Intel machine without "
4418 "unrestricted mode\n"
4419 "support, the failure can be most likely due to the guest "
4420 "entering an invalid\n"
4421 "state for Intel VT. For example, the guest maybe running "
4422 "in big real mode\n"
4423 "which is not supported on less recent Intel processors."
4428 case KVM_EXIT_EXCEPTION
:
4429 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
4430 run
->ex
.exception
, run
->ex
.error_code
);
4433 case KVM_EXIT_DEBUG
:
4434 DPRINTF("kvm_exit_debug\n");
4435 qemu_mutex_lock_iothread();
4436 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
4437 qemu_mutex_unlock_iothread();
4439 case KVM_EXIT_HYPERV
:
4440 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
4442 case KVM_EXIT_IOAPIC_EOI
:
4443 ioapic_eoi_broadcast(run
->eoi
.vector
);
4447 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
4455 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
4457 X86CPU
*cpu
= X86_CPU(cs
);
4458 CPUX86State
*env
= &cpu
->env
;
4460 kvm_cpu_synchronize_state(cs
);
4461 return !(env
->cr
[0] & CR0_PE_MASK
) ||
4462 ((env
->segs
[R_CS
].selector
& 3) != 3);
4465 void kvm_arch_init_irq_routing(KVMState
*s
)
4467 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
4468 /* If kernel can't do irq routing, interrupt source
4469 * override 0->2 cannot be set up as required by HPET.
4470 * So we have to disable it.
4474 /* We know at this point that we're using the in-kernel
4475 * irqchip, so we can use irqfds, and on x86 we know
4476 * we can use msi via irqfd and GSI routing.
4478 kvm_msi_via_irqfd_allowed
= true;
4479 kvm_gsi_routing_allowed
= true;
4481 if (kvm_irqchip_is_split()) {
4484 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4485 MSI routes for signaling interrupts to the local apics. */
4486 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
4487 if (kvm_irqchip_add_msi_route(s
, 0, NULL
) < 0) {
4488 error_report("Could not enable split IRQ mode.");
4495 int kvm_arch_irqchip_create(KVMState
*s
)
4498 if (kvm_kernel_irqchip_split()) {
4499 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
4501 error_report("Could not enable split irqchip mode: %s",
4505 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4506 kvm_split_irqchip
= true;
4514 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
4515 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
4517 X86IOMMUState
*iommu
= x86_iommu_get_default();
4521 MSIMessage src
, dst
;
4522 X86IOMMUClass
*class = X86_IOMMU_GET_CLASS(iommu
);
4524 if (!class->int_remap
) {
4528 src
.address
= route
->u
.msi
.address_hi
;
4529 src
.address
<<= VTD_MSI_ADDR_HI_SHIFT
;
4530 src
.address
|= route
->u
.msi
.address_lo
;
4531 src
.data
= route
->u
.msi
.data
;
4533 ret
= class->int_remap(iommu
, &src
, &dst
, dev
? \
4534 pci_requester_id(dev
) : \
4535 X86_IOMMU_SID_INVALID
);
4537 trace_kvm_x86_fixup_msi_error(route
->gsi
);
4541 route
->u
.msi
.address_hi
= dst
.address
>> VTD_MSI_ADDR_HI_SHIFT
;
4542 route
->u
.msi
.address_lo
= dst
.address
& VTD_MSI_ADDR_LO_MASK
;
4543 route
->u
.msi
.data
= dst
.data
;
4549 typedef struct MSIRouteEntry MSIRouteEntry
;
4551 struct MSIRouteEntry
{
4552 PCIDevice
*dev
; /* Device pointer */
4553 int vector
; /* MSI/MSIX vector index */
4554 int virq
; /* Virtual IRQ index */
4555 QLIST_ENTRY(MSIRouteEntry
) list
;
4558 /* List of used GSI routes */
4559 static QLIST_HEAD(, MSIRouteEntry
) msi_route_list
= \
4560 QLIST_HEAD_INITIALIZER(msi_route_list
);
4562 static void kvm_update_msi_routes_all(void *private, bool global
,
4563 uint32_t index
, uint32_t mask
)
4565 int cnt
= 0, vector
;
4566 MSIRouteEntry
*entry
;
4570 /* TODO: explicit route update */
4571 QLIST_FOREACH(entry
, &msi_route_list
, list
) {
4573 vector
= entry
->vector
;
4575 if (msix_enabled(dev
) && !msix_is_masked(dev
, vector
)) {
4576 msg
= msix_get_message(dev
, vector
);
4577 } else if (msi_enabled(dev
) && !msi_is_masked(dev
, vector
)) {
4578 msg
= msi_get_message(dev
, vector
);
4581 * Either MSI/MSIX is disabled for the device, or the
4582 * specific message was masked out. Skip this one.
4586 kvm_irqchip_update_msi_route(kvm_state
, entry
->virq
, msg
, dev
);
4588 kvm_irqchip_commit_routes(kvm_state
);
4589 trace_kvm_x86_update_msi_routes(cnt
);
4592 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
4593 int vector
, PCIDevice
*dev
)
4595 static bool notify_list_inited
= false;
4596 MSIRouteEntry
*entry
;
4599 /* These are (possibly) IOAPIC routes only used for split
4600 * kernel irqchip mode, while what we are housekeeping are
4601 * PCI devices only. */
4605 entry
= g_new0(MSIRouteEntry
, 1);
4607 entry
->vector
= vector
;
4608 entry
->virq
= route
->gsi
;
4609 QLIST_INSERT_HEAD(&msi_route_list
, entry
, list
);
4611 trace_kvm_x86_add_msi_route(route
->gsi
);
4613 if (!notify_list_inited
) {
4614 /* For the first time we do add route, add ourselves into
4615 * IOMMU's IEC notify list if needed. */
4616 X86IOMMUState
*iommu
= x86_iommu_get_default();
4618 x86_iommu_iec_register_notifier(iommu
,
4619 kvm_update_msi_routes_all
,
4622 notify_list_inited
= true;
4627 int kvm_arch_release_virq_post(int virq
)
4629 MSIRouteEntry
*entry
, *next
;
4630 QLIST_FOREACH_SAFE(entry
, &msi_route_list
, list
, next
) {
4631 if (entry
->virq
== virq
) {
4632 trace_kvm_x86_remove_msi_route(virq
);
4633 QLIST_REMOVE(entry
, list
);
4641 int kvm_arch_msi_data_to_gsi(uint32_t data
)