hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "cpu.h"
  26 #include "hw/hw.h"
  27 #include "hw/timer/m48t59.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/block/fdc.h"
  31 #include "net/net.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/isa/isa.h"
  34 #include "hw/pci/pci.h"
  35 #include "hw/pci/pci_host.h"
  36 #include "hw/ppc/ppc.h"
  37 #include "hw/boards.h"
  38 #include "qemu/error-report.h"
  39 #include "qemu/log.h"
  40 #include "hw/ide.h"
  41 #include "hw/loader.h"
  42 #include "hw/timer/mc146818rtc.h"
  43 #include "hw/isa/pc87312.h"
  44 #include "sysemu/block-backend.h"
  45 #include "sysemu/arch_init.h"
  46 #include "sysemu/qtest.h"
  47 #include "exec/address-spaces.h"
  48 #include "trace.h"
  49 #include "elf.h"
  50 #include "qemu/cutils.h"
  51
  52 /* SMP is not enabled, for now */
  53 #define MAX_CPUS 1
  54
  55 #define MAX_IDE_BUS 2
  56
  57 #define BIOS_SIZE (1024 * 1024)
  58 #define BIOS_FILENAME "ppc_rom.bin"
  59 #define KERNEL_LOAD_ADDR 0x01000000
  60 #define INITRD_LOAD_ADDR 0x01800000
  61
  62 /* Constants for devices init */
  63 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  64 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  65 static const int ide_irq[2] = { 13, 13 };
  66
  67 #define NE2000_NB_MAX 6
  68
  69 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  70 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  71
  72 /* ISA IO ports bridge */
  73 #define PPC_IO_BASE 0x80000000
  74
  75 /* PowerPC control and status registers */
  76 #if 0 // Not used
  77 static struct {
  78     /* IDs */
  79     uint32_t veni_devi;
  80     uint32_t revi;
  81     /* Control and status */
  82     uint32_t gcsr;
  83     uint32_t xcfr;
  84     uint32_t ct32;
  85     uint32_t mcsr;
  86     /* General purpose registers */
  87     uint32_t gprg[6];
  88     /* Exceptions */
  89     uint32_t feen;
  90     uint32_t fest;
  91     uint32_t fema;
  92     uint32_t fecl;
  93     uint32_t eeen;
  94     uint32_t eest;
  95     uint32_t eecl;
  96     uint32_t eeint;
  97     uint32_t eemck0;
  98     uint32_t eemck1;
  99     /* Error diagnostic */
 100 } XCSR;
 101
 102 static void PPC_XCSR_writeb (void *opaque,
 103                              hwaddr addr, uint32_t value)
 104 {
 105     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 106            value);
 107 }
 108
 109 static void PPC_XCSR_writew (void *opaque,
 110                              hwaddr addr, uint32_t value)
 111 {
 112     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 113            value);
 114 }
 115
 116 static void PPC_XCSR_writel (void *opaque,
 117                              hwaddr addr, uint32_t value)
 118 {
 119     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 120            value);
 121 }
 122
 123 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
 124 {
 125     uint32_t retval = 0;
 126
 127     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 128            retval);
 129
 130     return retval;
 131 }
 132
 133 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
 134 {
 135     uint32_t retval = 0;
 136
 137     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 138            retval);
 139
 140     return retval;
 141 }
 142
 143 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
 144 {
 145     uint32_t retval = 0;
 146
 147     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 148            retval);
 149
 150     return retval;
 151 }
 152
 153 static const MemoryRegionOps PPC_XCSR_ops = {
 154     .old_mmio = {
 155         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 156         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 157     },
 158     .endianness = DEVICE_LITTLE_ENDIAN,
 159 };
 160
 161 #endif
 162
 163 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 164 typedef struct sysctrl_t {
 165     qemu_irq reset_irq;
 166     Nvram *nvram;
 167     uint8_t state;
 168     uint8_t syscontrol;
 169     int contiguous_map;
 170     qemu_irq contiguous_map_irq;
 171     int endian;
 172 } sysctrl_t;
 173
 174 enum {
 175     STATE_HARDFILE = 0x01,
 176 };
 177
 178 static sysctrl_t *sysctrl;
 179
 180 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 181 {
 182     sysctrl_t *sysctrl = opaque;
 183
 184     trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
 185     switch (addr) {
 186     case 0x0092:
 187         /* Special port 92 */
 188         /* Check soft reset asked */
 189         if (val & 0x01) {
 190             qemu_irq_raise(sysctrl->reset_irq);
 191         } else {
 192             qemu_irq_lower(sysctrl->reset_irq);
 193         }
 194         /* Check LE mode */
 195         if (val & 0x02) {
 196             sysctrl->endian = 1;
 197         } else {
 198             sysctrl->endian = 0;
 199         }
 200         break;
 201     case 0x0800:
 202         /* Motorola CPU configuration register : read-only */
 203         break;
 204     case 0x0802:
 205         /* Motorola base module feature register : read-only */
 206         break;
 207     case 0x0803:
 208         /* Motorola base module status register : read-only */
 209         break;
 210     case 0x0808:
 211         /* Hardfile light register */
 212         if (val & 1)
 213             sysctrl->state |= STATE_HARDFILE;
 214         else
 215             sysctrl->state &= ~STATE_HARDFILE;
 216         break;
 217     case 0x0810:
 218         /* Password protect 1 register */
 219         if (sysctrl->nvram != NULL) {
 220             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 221             (k->toggle_lock)(sysctrl->nvram, 1);
 222         }
 223         break;
 224     case 0x0812:
 225         /* Password protect 2 register */
 226         if (sysctrl->nvram != NULL) {
 227             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 228             (k->toggle_lock)(sysctrl->nvram, 2);
 229         }
 230         break;
 231     case 0x0814:
 232         /* L2 invalidate register */
 233         //        tlb_flush(first_cpu, 1);
 234         break;
 235     case 0x081C:
 236         /* system control register */
 237         sysctrl->syscontrol = val & 0x0F;
 238         break;
 239     case 0x0850:
 240         /* I/O map type register */
 241         sysctrl->contiguous_map = val & 0x01;
 242         qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
 243         break;
 244     default:
 245         printf("ERROR: unaffected IO port write: %04" PRIx32
 246                " => %02" PRIx32"\n", addr, val);
 247         break;
 248     }
 249 }
 250
 251 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 252 {
 253     sysctrl_t *sysctrl = opaque;
 254     uint32_t retval = 0xFF;
 255
 256     switch (addr) {
 257     case 0x0092:
 258         /* Special port 92 */
 259         retval = sysctrl->endian << 1;
 260         break;
 261     case 0x0800:
 262         /* Motorola CPU configuration register */
 263         retval = 0xEF; /* MPC750 */
 264         break;
 265     case 0x0802:
 266         /* Motorola Base module feature register */
 267         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 268         break;
 269     case 0x0803:
 270         /* Motorola base module status register */
 271         retval = 0xE0; /* Standard MPC750 */
 272         break;
 273     case 0x080C:
 274         /* Equipment present register:
 275          *  no L2 cache
 276          *  no upgrade processor
 277          *  no cards in PCI slots
 278          *  SCSI fuse is bad
 279          */
 280         retval = 0x3C;
 281         break;
 282     case 0x0810:
 283         /* Motorola base module extended feature register */
 284         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 285         break;
 286     case 0x0814:
 287         /* L2 invalidate: don't care */
 288         break;
 289     case 0x0818:
 290         /* Keylock */
 291         retval = 0x00;
 292         break;
 293     case 0x081C:
 294         /* system control register
 295          * 7 - 6 / 1 - 0: L2 cache enable
 296          */
 297         retval = sysctrl->syscontrol;
 298         break;
 299     case 0x0823:
 300         /* */
 301         retval = 0x03; /* no L2 cache */
 302         break;
 303     case 0x0850:
 304         /* I/O map type register */
 305         retval = sysctrl->contiguous_map;
 306         break;
 307     default:
 308         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 309         break;
 310     }
 311     trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
 312
 313     return retval;
 314 }
 315
 316
 317 #define NVRAM_SIZE        0x2000
 318
 319 static void ppc_prep_reset(void *opaque)
 320 {
 321     PowerPCCPU *cpu = opaque;
 322
 323     cpu_reset(CPU(cpu));
 324 }
 325
 326 static const MemoryRegionPortio prep_portio_list[] = {
 327     /* System control ports */
 328     { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 329     { 0x0800, 0x52, 1,
 330       .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 331     /* Special port to get debug messages from Open-Firmware */
 332     { 0x0F00, 4, 1, .write = PPC_debug_write, },
 333     PORTIO_END_OF_LIST(),
 334 };
 335
 336 static PortioList prep_port_list;
 337
 338 /*****************************************************************************/
 339 /* NVRAM helpers */
 340 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
 341 {
 342     NvramClass *k = NVRAM_GET_CLASS(nvram);
 343     return (k->read)(nvram, addr);
 344 }
 345
 346 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
 347 {
 348     NvramClass *k = NVRAM_GET_CLASS(nvram);
 349     (k->write)(nvram, addr, val);
 350 }
 351
 352 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
 353 {
 354     nvram_write(nvram, addr, value);
 355 }
 356
 357 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
 358 {
 359     return nvram_read(nvram, addr);
 360 }
 361
 362 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 363 {
 364     nvram_write(nvram, addr, value >> 8);
 365     nvram_write(nvram, addr + 1, value & 0xFF);
 366 }
 367
 368 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 369 {
 370     uint16_t tmp;
 371
 372     tmp = nvram_read(nvram, addr) << 8;
 373     tmp |= nvram_read(nvram, addr + 1);
 374
 375     return tmp;
 376 }
 377
 378 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 379 {
 380     nvram_write(nvram, addr, value >> 24);
 381     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 382     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 383     nvram_write(nvram, addr + 3, value & 0xFF);
 384 }
 385
 386 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 387                              uint32_t max)
 388 {
 389     int i;
 390
 391     for (i = 0; i < max && str[i] != '\0'; i++) {
 392         nvram_write(nvram, addr + i, str[i]);
 393     }
 394     nvram_write(nvram, addr + i, str[i]);
 395     nvram_write(nvram, addr + max - 1, '\0');
 396 }
 397
 398 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 399 {
 400     uint16_t tmp;
 401     uint16_t pd, pd1, pd2;
 402
 403     tmp = prev >> 8;
 404     pd = prev ^ value;
 405     pd1 = pd & 0x000F;
 406     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 407     tmp ^= (pd1 << 3) | (pd1 << 8);
 408     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 409
 410     return tmp;
 411 }
 412
 413 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 414 {
 415     uint32_t i;
 416     uint16_t crc = 0xFFFF;
 417     int odd;
 418
 419     odd = count & 1;
 420     count &= ~1;
 421     for (i = 0; i != count; i++) {
 422         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 423     }
 424     if (odd) {
 425         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 426     }
 427
 428     return crc;
 429 }
 430
 431 #define CMDLINE_ADDR 0x017ff000
 432
 433 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 434                           const char *arch,
 435                           uint32_t RAM_size, int boot_device,
 436                           uint32_t kernel_image, uint32_t kernel_size,
 437                           const char *cmdline,
 438                           uint32_t initrd_image, uint32_t initrd_size,
 439                           uint32_t NVRAM_image,
 440                           int width, int height, int depth)
 441 {
 442     uint16_t crc;
 443
 444     /* Set parameters for Open Hack'Ware BIOS */
 445     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 446     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 447     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 448     NVRAM_set_string(nvram, 0x20, arch, 16);
 449     NVRAM_set_lword(nvram,  0x30, RAM_size);
 450     NVRAM_set_byte(nvram,   0x34, boot_device);
 451     NVRAM_set_lword(nvram,  0x38, kernel_image);
 452     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 453     if (cmdline) {
 454         /* XXX: put the cmdline in NVRAM too ? */
 455         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 456                          cmdline);
 457         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 458         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 459     } else {
 460         NVRAM_set_lword(nvram,  0x40, 0);
 461         NVRAM_set_lword(nvram,  0x44, 0);
 462     }
 463     NVRAM_set_lword(nvram,  0x48, initrd_image);
 464     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 465     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 466
 467     NVRAM_set_word(nvram,   0x54, width);
 468     NVRAM_set_word(nvram,   0x56, height);
 469     NVRAM_set_word(nvram,   0x58, depth);
 470     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 471     NVRAM_set_word(nvram,   0xFC, crc);
 472
 473     return 0;
 474 }
 475
 476 /* PowerPC PREP hardware initialisation */
 477 static void ppc_prep_init(MachineState *machine)
 478 {
 479     ram_addr_t ram_size = machine->ram_size;
 480     const char *kernel_filename = machine->kernel_filename;
 481     const char *kernel_cmdline = machine->kernel_cmdline;
 482     const char *initrd_filename = machine->initrd_filename;
 483     const char *boot_device = machine->boot_order;
 484     MemoryRegion *sysmem = get_system_memory();
 485     PowerPCCPU *cpu = NULL;
 486     CPUPPCState *env = NULL;
 487     Nvram *m48t59;
 488 #if 0
 489     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 490 #endif
 491     int linux_boot, i, nb_nics1;
 492     MemoryRegion *ram = g_new(MemoryRegion, 1);
 493     uint32_t kernel_base, initrd_base;
 494     long kernel_size, initrd_size;
 495     DeviceState *dev;
 496     PCIHostState *pcihost;
 497     PCIBus *pci_bus;
 498     PCIDevice *pci;
 499     ISABus *isa_bus;
 500     ISADevice *isa;
 501     int ppc_boot_device;
 502     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 503
 504     sysctrl = g_malloc0(sizeof(sysctrl_t));
 505
 506     linux_boot = (kernel_filename != NULL);
 507
 508     /* init CPUs */
 509     if (machine->cpu_model == NULL)
 510         machine->cpu_model = "602";
 511     for (i = 0; i < smp_cpus; i++) {
 512         cpu = cpu_ppc_init(machine->cpu_model);
 513         if (cpu == NULL) {
 514             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 515             exit(1);
 516         }
 517         env = &cpu->env;
 518
 519         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 520             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 521             cpu_ppc_tb_init(env, 7812500UL);
 522         } else {
 523             /* Set time-base frequency to 100 Mhz */
 524             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 525         }
 526         qemu_register_reset(ppc_prep_reset, cpu);
 527     }
 528
 529     /* allocate RAM */
 530     memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
 531     memory_region_add_subregion(sysmem, 0, ram);
 532
 533     if (linux_boot) {
 534         kernel_base = KERNEL_LOAD_ADDR;
 535         /* now we can load the kernel */
 536         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 537                                           ram_size - kernel_base);
 538         if (kernel_size < 0) {
 539             error_report("could not load kernel '%s'", kernel_filename);
 540             exit(1);
 541         }
 542         /* load initrd */
 543         if (initrd_filename) {
 544             initrd_base = INITRD_LOAD_ADDR;
 545             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 546                                               ram_size - initrd_base);
 547             if (initrd_size < 0) {
 548                 error_report("could not load initial ram disk '%s'",
 549                              initrd_filename);
 550                 exit(1);
 551             }
 552         } else {
 553             initrd_base = 0;
 554             initrd_size = 0;
 555         }
 556         ppc_boot_device = 'm';
 557     } else {
 558         kernel_base = 0;
 559         kernel_size = 0;
 560         initrd_base = 0;
 561         initrd_size = 0;
 562         ppc_boot_device = '\0';
 563         /* For now, OHW cannot boot from the network. */
 564         for (i = 0; boot_device[i] != '\0'; i++) {
 565             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 566                 ppc_boot_device = boot_device[i];
 567                 break;
 568             }
 569         }
 570         if (ppc_boot_device == '\0') {
 571             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 572             exit(1);
 573         }
 574     }
 575
 576     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 577         error_report("Only 6xx bus is supported on PREP machine");
 578         exit(1);
 579     }
 580
 581     dev = qdev_create(NULL, "raven-pcihost");
 582     if (bios_name == NULL) {
 583         bios_name = BIOS_FILENAME;
 584     }
 585     qdev_prop_set_string(dev, "bios-name", bios_name);
 586     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 587     pcihost = PCI_HOST_BRIDGE(dev);
 588     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 589     qdev_init_nofail(dev);
 590     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 591     if (pci_bus == NULL) {
 592         fprintf(stderr, "Couldn't create PCI host controller.\n");
 593         exit(1);
 594     }
 595     sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
 596
 597     /* PCI -> ISA bridge */
 598     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 599     cpu = POWERPC_CPU(first_cpu);
 600     qdev_connect_gpio_out(&pci->qdev, 0,
 601                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 602     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 603     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 604     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 605     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 606     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
 607
 608     /* Super I/O (parallel + serial ports) */
 609     isa = isa_create(isa_bus, TYPE_PC87312);
 610     dev = DEVICE(isa);
 611     qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
 612     qdev_init_nofail(dev);
 613
 614     /* init basic PC hardware */
 615     pci_vga_init(pci_bus);
 616
 617     nb_nics1 = nb_nics;
 618     if (nb_nics1 > NE2000_NB_MAX)
 619         nb_nics1 = NE2000_NB_MAX;
 620     for(i = 0; i < nb_nics1; i++) {
 621         if (nd_table[i].model == NULL) {
 622             nd_table[i].model = g_strdup("ne2k_isa");
 623         }
 624         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 625             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 626                             &nd_table[i]);
 627         } else {
 628             pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 629         }
 630     }
 631
 632     ide_drive_get(hd, ARRAY_SIZE(hd));
 633     for(i = 0; i < MAX_IDE_BUS; i++) {
 634         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 635                      hd[2 * i],
 636                      hd[2 * i + 1]);
 637     }
 638     isa_create_simple(isa_bus, "i8042");
 639
 640     cpu = POWERPC_CPU(first_cpu);
 641     sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 642
 643     portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
 644     portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
 645
 646     /* PowerPC control and status register group */
 647 #if 0
 648     memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 649     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 650 #endif
 651
 652     if (machine_usb(machine)) {
 653         pci_create_simple(pci_bus, -1, "pci-ohci");
 654     }
 655
 656     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
 657     if (m48t59 == NULL)
 658         return;
 659     sysctrl->nvram = m48t59;
 660
 661     /* Initialise NVRAM */
 662     PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 663                          ppc_boot_device,
 664                          kernel_base, kernel_size,
 665                          kernel_cmdline,
 666                          initrd_base, initrd_size,
 667                          /* XXX: need an option to load a NVRAM image */
 668                          0,
 669                          graphic_width, graphic_height, graphic_depth);
 670 }
 671
 672 static void prep_machine_init(MachineClass *mc)
 673 {
 674     mc->desc = "PowerPC PREP platform";
 675     mc->init = ppc_prep_init;
 676     mc->max_cpus = MAX_CPUS;
 677     mc->default_boot_order = "cad";
 678 }
 679
 680 DEFINE_MACHINE("prep", prep_machine_init)