target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 /* QEMU addressing/paging config */
  24 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
  25 #if defined(TARGET_RISCV64)
  26 #define TARGET_LONG_BITS 64
  27 #define TARGET_PHYS_ADDR_SPACE_BITS 50
  28 #define TARGET_VIRT_ADDR_SPACE_BITS 39
  29 #elif defined(TARGET_RISCV32)
  30 #define TARGET_LONG_BITS 32
  31 #define TARGET_PHYS_ADDR_SPACE_BITS 34
  32 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  33 #endif
  34
  35 #define TCG_GUEST_DEFAULT_MO 0
  36
  37 #define ELF_MACHINE EM_RISCV
  38 #define CPUArchState struct CPURISCVState
  39
  40 #include "qemu-common.h"
  41 #include "qom/cpu.h"
  42 #include "exec/cpu-defs.h"
  43 #include "fpu/softfloat.h"
  44
  45 #define TYPE_RISCV_CPU "riscv-cpu"
  46
  47 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  48 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  49
  50 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  51 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
  52 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
  53 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
  54 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
  55 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
  56 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
  57 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  58 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  59 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  60 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  61
  62 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  63 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  64
  65 #if defined(TARGET_RISCV32)
  66 #define RVXLEN RV32
  67 #elif defined(TARGET_RISCV64)
  68 #define RVXLEN RV64
  69 #endif
  70
  71 #define RV(x) ((target_ulong)1 << (x - 'A'))
  72
  73 #define RVI RV('I')
  74 #define RVM RV('M')
  75 #define RVA RV('A')
  76 #define RVF RV('F')
  77 #define RVD RV('D')
  78 #define RVC RV('C')
  79 #define RVS RV('S')
  80 #define RVU RV('U')
  81
  82 /* S extension denotes that Supervisor mode exists, however it is possible
  83    to have a core that support S mode but does not have an MMU and there
  84    is currently no bit in misa to indicate whether an MMU exists or not
  85    so a cpu features bitfield is required */
  86 enum {
  87     RISCV_FEATURE_MMU
  88 };
  89
  90 #define USER_VERSION_2_02_0 0x00020200
  91 #define PRIV_VERSION_1_09_1 0x00010901
  92 #define PRIV_VERSION_1_10_0 0x00011000
  93
  94 #define TRANSLATE_FAIL 1
  95 #define TRANSLATE_SUCCESS 0
  96 #define NB_MMU_MODES 4
  97 #define MMU_USER_IDX 3
  98
  99 #define MAX_RISCV_PMPS (16)
 100
 101 typedef struct CPURISCVState CPURISCVState;
 102
 103 #include "pmp.h"
 104
 105 struct CPURISCVState {
 106     target_ulong gpr[32];
 107     uint64_t fpr[32]; /* assume both F and D extensions */
 108     target_ulong pc;
 109     target_ulong load_res;
 110     target_ulong load_val;
 111
 112     target_ulong frm;
 113
 114     target_ulong badaddr;
 115
 116     target_ulong user_ver;
 117     target_ulong priv_ver;
 118     target_ulong misa;
 119
 120     uint32_t features;
 121
 122 #ifndef CONFIG_USER_ONLY
 123     target_ulong priv;
 124     target_ulong resetvec;
 125
 126     target_ulong mhartid;
 127     target_ulong mstatus;
 128     /*
 129      * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
 130      * by I/O threads and other vCPUs, so hold the iothread mutex before
 131      * operating on it.  CPU_INTERRUPT_HARD should be in effect iff this is
 132      * non-zero.  Use riscv_cpu_set_local_interrupt.
 133      */
 134     uint32_t mip;        /* allow atomic_read for >= 32-bit hosts */
 135     target_ulong mie;
 136     target_ulong mideleg;
 137
 138     target_ulong sptbr;  /* until: priv-1.9.1 */
 139     target_ulong satp;   /* since: priv-1.10.0 */
 140     target_ulong sbadaddr;
 141     target_ulong mbadaddr;
 142     target_ulong medeleg;
 143
 144     target_ulong stvec;
 145     target_ulong sepc;
 146     target_ulong scause;
 147
 148     target_ulong mtvec;
 149     target_ulong mepc;
 150     target_ulong mcause;
 151     target_ulong mtval;  /* since: priv-1.10.0 */
 152
 153     uint32_t mucounteren;
 154     uint32_t mscounteren;
 155     target_ulong scounteren; /* since: priv-1.10.0 */
 156     target_ulong mcounteren; /* since: priv-1.10.0 */
 157
 158     target_ulong sscratch;
 159     target_ulong mscratch;
 160
 161     /* temporary htif regs */
 162     uint64_t mfromhost;
 163     uint64_t mtohost;
 164     uint64_t timecmp;
 165
 166     /* physical memory protection */
 167     pmp_table_t pmp_state;
 168 #endif
 169
 170     float_status fp_status;
 171
 172     /* QEMU */
 173     CPU_COMMON
 174
 175     /* Fields from here on are preserved across CPU reset. */
 176     QEMUTimer *timer; /* Internal timer */
 177 };
 178
 179 #define RISCV_CPU_CLASS(klass) \
 180     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 181 #define RISCV_CPU(obj) \
 182     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 183 #define RISCV_CPU_GET_CLASS(obj) \
 184     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 185
 186 /**
 187  * RISCVCPUClass:
 188  * @parent_realize: The parent class' realize handler.
 189  * @parent_reset: The parent class' reset handler.
 190  *
 191  * A RISCV CPU model.
 192  */
 193 typedef struct RISCVCPUClass {
 194     /*< private >*/
 195     CPUClass parent_class;
 196     /*< public >*/
 197     DeviceRealize parent_realize;
 198     void (*parent_reset)(CPUState *cpu);
 199 } RISCVCPUClass;
 200
 201 /**
 202  * RISCVCPU:
 203  * @env: #CPURISCVState
 204  *
 205  * A RISCV CPU.
 206  */
 207 typedef struct RISCVCPU {
 208     /*< private >*/
 209     CPUState parent_obj;
 210     /*< public >*/
 211     CPURISCVState env;
 212 } RISCVCPU;
 213
 214 static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
 215 {
 216     return container_of(env, RISCVCPU, env);
 217 }
 218
 219 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 220 {
 221     return (env->misa & ext) != 0;
 222 }
 223
 224 static inline bool riscv_feature(CPURISCVState *env, int feature)
 225 {
 226     return env->features & (1ULL << feature);
 227 }
 228
 229 #include "cpu_user.h"
 230 #include "cpu_bits.h"
 231
 232 extern const char * const riscv_int_regnames[];
 233 extern const char * const riscv_fpr_regnames[];
 234 extern const char * const riscv_excp_names[];
 235 extern const char * const riscv_intr_names[];
 236
 237 #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e))
 238 #define ENV_OFFSET offsetof(RISCVCPU, env)
 239
 240 void riscv_cpu_do_interrupt(CPUState *cpu);
 241 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 242 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 243 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 244 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 245 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 246 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 247                                     MMUAccessType access_type, int mmu_idx,
 248                                     uintptr_t retaddr);
 249 int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
 250                               int rw, int mmu_idx);
 251
 252 char *riscv_isa_string(RISCVCPU *cpu);
 253 void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 254
 255 #define cpu_init(cpu_model) cpu_generic_init(TYPE_RISCV_CPU, cpu_model)
 256 #define cpu_signal_handler cpu_riscv_signal_handler
 257 #define cpu_list riscv_cpu_list
 258 #define cpu_mmu_index riscv_cpu_mmu_index
 259
 260 void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
 261
 262 void riscv_translate_init(void);
 263 RISCVCPU *cpu_riscv_init(const char *cpu_model);
 264 int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
 265 void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
 266                                           uint32_t exception, uintptr_t pc);
 267
 268 target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
 269 void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
 270
 271 #define TB_FLAGS_MMU_MASK  3
 272 #define TB_FLAGS_FP_ENABLE MSTATUS_FS
 273
 274 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 275                                         target_ulong *cs_base, uint32_t *flags)
 276 {
 277     *pc = env->pc;
 278     *cs_base = 0;
 279 #ifdef CONFIG_USER_ONLY
 280     *flags = TB_FLAGS_FP_ENABLE;
 281 #else
 282     *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 283 #endif
 284 }
 285
 286 void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
 287         target_ulong csrno);
 288 target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
 289
 290 #ifndef CONFIG_USER_ONLY
 291 void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value);
 292 #endif
 293
 294 #include "exec/cpu-all.h"
 295
 296 #endif /* RISCV_CPU_H */