2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, int nr_irqs
,
99 Error
*local_err
= NULL
;
101 obj
= object_new(TYPE_ICS_SIMPLE
);
102 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
103 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
105 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &error_fatal
);
106 object_property_set_bool(obj
, true, "realized", &local_err
);
108 error_propagate(errp
, local_err
);
112 spapr
->ics
= ICS_BASE(obj
);
114 xics_spapr_init(spapr
);
117 #define ICS_IRQ_FREE(ics, srcno) \
118 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
120 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
123 ICSState
*ics
= spapr
->ics
;
127 if (!ics_valid_irq(ics
, irq
)) {
128 error_setg(errp
, "IRQ %d is invalid", irq
);
132 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
133 error_setg(errp
, "IRQ %d is not free", irq
);
137 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
141 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
143 ICSState
*ics
= spapr
->ics
;
144 uint32_t srcno
= irq
- ics
->offset
;
147 if (ics_valid_irq(ics
, irq
)) {
148 trace_spapr_irq_free(0, irq
, num
);
149 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
150 if (ICS_IRQ_FREE(ics
, i
)) {
151 trace_spapr_irq_free_warn(0, i
);
153 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
158 static qemu_irq
spapr_qirq_xics(SpaprMachineState
*spapr
, int irq
)
160 ICSState
*ics
= spapr
->ics
;
161 uint32_t srcno
= irq
- ics
->offset
;
163 if (ics_valid_irq(ics
, irq
)) {
164 return spapr
->qirqs
[srcno
];
170 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
175 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
177 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
180 ics_pic_print_info(spapr
->ics
, mon
);
183 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
184 PowerPCCPU
*cpu
, Error
**errp
)
186 Error
*local_err
= NULL
;
188 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
190 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
193 error_propagate(errp
, local_err
);
197 spapr_cpu
->icp
= ICP(obj
);
200 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
202 if (!kvm_irqchip_in_kernel()) {
205 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
206 icp_resend(spapr_cpu_state(cpu
)->icp
);
212 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
214 SpaprMachineState
*spapr
= opaque
;
216 ics_simple_set_irq(spapr
->ics
, srcno
, val
);
219 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
221 Error
*local_err
= NULL
;
223 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
225 error_propagate(errp
, local_err
);
230 static const char *spapr_irq_get_nodename_xics(SpaprMachineState
*spapr
)
232 return XICS_NODENAME
;
235 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
238 xics_kvm_connect(spapr
, errp
);
242 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
243 #define SPAPR_IRQ_XICS_NR_MSIS \
244 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
246 SpaprIrq spapr_irq_xics
= {
247 .nr_irqs
= SPAPR_IRQ_XICS_NR_IRQS
,
248 .nr_msis
= SPAPR_IRQ_XICS_NR_MSIS
,
249 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
251 .init
= spapr_irq_init_xics
,
252 .claim
= spapr_irq_claim_xics
,
253 .free
= spapr_irq_free_xics
,
254 .qirq
= spapr_qirq_xics
,
255 .print_info
= spapr_irq_print_info_xics
,
256 .dt_populate
= spapr_dt_xics
,
257 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
258 .post_load
= spapr_irq_post_load_xics
,
259 .reset
= spapr_irq_reset_xics
,
260 .set_irq
= spapr_irq_set_irq_xics
,
261 .get_nodename
= spapr_irq_get_nodename_xics
,
262 .init_kvm
= spapr_irq_init_kvm_xics
,
268 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, int nr_irqs
,
271 uint32_t nr_servers
= spapr_max_server_number(spapr
);
275 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
276 qdev_prop_set_uint32(dev
, "nr-irqs", nr_irqs
);
278 * 8 XIVE END structures per CPU. One for each available priority
280 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
281 qdev_init_nofail(dev
);
283 spapr
->xive
= SPAPR_XIVE(dev
);
285 /* Enable the CPU IPIs */
286 for (i
= 0; i
< nr_servers
; ++i
) {
287 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
290 spapr_xive_hcall_init(spapr
);
293 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
296 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
297 error_setg(errp
, "IRQ %d is invalid", irq
);
303 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
307 for (i
= irq
; i
< irq
+ num
; ++i
) {
308 spapr_xive_irq_free(spapr
->xive
, i
);
312 static qemu_irq
spapr_qirq_xive(SpaprMachineState
*spapr
, int irq
)
314 SpaprXive
*xive
= spapr
->xive
;
316 if (irq
>= xive
->nr_irqs
) {
320 /* The sPAPR machine/device should have claimed the IRQ before */
321 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
323 return spapr
->qirqs
[irq
];
326 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
332 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
334 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
337 spapr_xive_pic_print_info(spapr
->xive
, mon
);
340 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
341 PowerPCCPU
*cpu
, Error
**errp
)
343 Error
*local_err
= NULL
;
345 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
347 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
349 error_propagate(errp
, local_err
);
353 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
356 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
357 * don't beneficiate from the reset of the XIVE IRQ backend
359 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
362 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
364 return spapr_xive_post_load(spapr
->xive
, version_id
);
367 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
370 Error
*local_err
= NULL
;
373 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
375 /* (TCG) Set the OS CAM line of the thread interrupt context. */
376 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
379 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
381 error_propagate(errp
, local_err
);
385 /* Activate the XIVE MMIOs */
386 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
389 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
391 SpaprMachineState
*spapr
= opaque
;
393 if (kvm_irqchip_in_kernel()) {
394 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
396 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
400 static const char *spapr_irq_get_nodename_xive(SpaprMachineState
*spapr
)
402 return spapr
->xive
->nodename
;
405 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
408 kvmppc_xive_connect(spapr
->xive
, errp
);
413 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
417 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
418 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
420 SpaprIrq spapr_irq_xive
= {
421 .nr_irqs
= SPAPR_IRQ_XIVE_NR_IRQS
,
422 .nr_msis
= SPAPR_IRQ_XIVE_NR_MSIS
,
423 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
425 .init
= spapr_irq_init_xive
,
426 .claim
= spapr_irq_claim_xive
,
427 .free
= spapr_irq_free_xive
,
428 .qirq
= spapr_qirq_xive
,
429 .print_info
= spapr_irq_print_info_xive
,
430 .dt_populate
= spapr_dt_xive
,
431 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
432 .post_load
= spapr_irq_post_load_xive
,
433 .reset
= spapr_irq_reset_xive
,
434 .set_irq
= spapr_irq_set_irq_xive
,
435 .get_nodename
= spapr_irq_get_nodename_xive
,
436 .init_kvm
= spapr_irq_init_kvm_xive
,
440 * Dual XIVE and XICS IRQ backend.
442 * Both interrupt mode, XIVE and XICS, objects are created but the
443 * machine starts in legacy interrupt mode (XICS). It can be changed
444 * by the CAS negotiation process and, in that case, the new mode is
445 * activated after an extra machine reset.
449 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
452 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
454 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
455 &spapr_irq_xive
: &spapr_irq_xics
;
458 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, int nr_irqs
,
461 Error
*local_err
= NULL
;
463 spapr_irq_xics
.init(spapr
, spapr_irq_xics
.nr_irqs
, &local_err
);
465 error_propagate(errp
, local_err
);
469 spapr_irq_xive
.init(spapr
, spapr_irq_xive
.nr_irqs
, &local_err
);
471 error_propagate(errp
, local_err
);
476 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
479 Error
*local_err
= NULL
;
482 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
484 error_propagate(errp
, local_err
);
488 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
490 error_propagate(errp
, local_err
);
497 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
499 spapr_irq_xics
.free(spapr
, irq
, num
);
500 spapr_irq_xive
.free(spapr
, irq
, num
);
503 static qemu_irq
spapr_qirq_dual(SpaprMachineState
*spapr
, int irq
)
505 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
508 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
510 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
513 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
514 uint32_t nr_servers
, void *fdt
,
517 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
520 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
521 PowerPCCPU
*cpu
, Error
**errp
)
523 Error
*local_err
= NULL
;
525 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
527 error_propagate(errp
, local_err
);
531 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
534 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
537 * Force a reset of the XIVE backend after migration. The machine
538 * defaults to XICS at startup.
540 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
541 if (kvm_irqchip_in_kernel()) {
542 xics_kvm_disconnect(spapr
, &error_fatal
);
544 spapr_irq_xive
.reset(spapr
, &error_fatal
);
547 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
550 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
552 Error
*local_err
= NULL
;
555 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
558 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
560 /* Destroy all KVM devices */
561 if (kvm_irqchip_in_kernel()) {
562 xics_kvm_disconnect(spapr
, &local_err
);
564 error_propagate(errp
, local_err
);
565 error_prepend(errp
, "KVM XICS disconnect failed: ");
568 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
570 error_propagate(errp
, local_err
);
571 error_prepend(errp
, "KVM XIVE disconnect failed: ");
576 spapr_irq_current(spapr
)->reset(spapr
, errp
);
579 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
581 SpaprMachineState
*spapr
= opaque
;
583 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
586 static const char *spapr_irq_get_nodename_dual(SpaprMachineState
*spapr
)
588 return spapr_irq_current(spapr
)->get_nodename(spapr
);
592 * Define values in sync with the XIVE and XICS backend
594 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
595 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
597 SpaprIrq spapr_irq_dual
= {
598 .nr_irqs
= SPAPR_IRQ_DUAL_NR_IRQS
,
599 .nr_msis
= SPAPR_IRQ_DUAL_NR_MSIS
,
600 .ov5
= SPAPR_OV5_XIVE_BOTH
,
602 .init
= spapr_irq_init_dual
,
603 .claim
= spapr_irq_claim_dual
,
604 .free
= spapr_irq_free_dual
,
605 .qirq
= spapr_qirq_dual
,
606 .print_info
= spapr_irq_print_info_dual
,
607 .dt_populate
= spapr_irq_dt_populate_dual
,
608 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
609 .post_load
= spapr_irq_post_load_dual
,
610 .reset
= spapr_irq_reset_dual
,
611 .set_irq
= spapr_irq_set_irq_dual
,
612 .get_nodename
= spapr_irq_get_nodename_dual
,
613 .init_kvm
= NULL
, /* should not be used */
617 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
619 MachineState
*machine
= MACHINE(spapr
);
622 * Sanity checks on non-P9 machines. On these, XIVE is not
623 * advertised, see spapr_dt_ov5_platform_support()
625 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
626 0, spapr
->max_compat_pvr
)) {
628 * If the 'dual' interrupt mode is selected, force XICS as CAS
629 * negotiation is useless.
631 if (spapr
->irq
== &spapr_irq_dual
) {
632 spapr
->irq
= &spapr_irq_xics
;
637 * Non-P9 machines using only XIVE is a bogus setup. We have two
638 * scenarios to take into account because of the compat mode:
640 * 1. POWER7/8 machines should fail to init later on when creating
641 * the XIVE interrupt presenters because a POWER9 exception
644 * 2. POWER9 machines using the POWER8 compat mode won't fail and
645 * will let the OS boot with a partial XIVE setup : DT
646 * properties but no hcalls.
648 * To cover both and not confuse the OS, add an early failure in
651 if (spapr
->irq
== &spapr_irq_xive
) {
652 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
658 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
659 * re-created. Detect that early to avoid QEMU to exit later when the
663 spapr
->irq
== &spapr_irq_dual
&&
664 machine_kernel_irqchip_required(machine
) &&
665 xics_kvm_has_broken_disconnect(spapr
)) {
666 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
672 * sPAPR IRQ frontend routines for devices
674 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
676 MachineState
*machine
= MACHINE(spapr
);
677 Error
*local_err
= NULL
;
679 if (machine_kernel_irqchip_split(machine
)) {
680 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
684 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
686 "kernel_irqchip requested but only available with KVM");
690 spapr_irq_check(spapr
, &local_err
);
692 error_propagate(errp
, local_err
);
696 /* Initialize the MSI IRQ allocator. */
697 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
698 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
701 spapr
->irq
->init(spapr
, spapr
->irq
->nr_irqs
, errp
);
703 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
704 spapr
->irq
->nr_irqs
);
707 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
709 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
712 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
714 spapr
->irq
->free(spapr
, irq
, num
);
717 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
719 return spapr
->irq
->qirq(spapr
, irq
);
722 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
724 return spapr
->irq
->post_load(spapr
, version_id
);
727 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
729 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
731 if (spapr
->irq
->reset
) {
732 spapr
->irq
->reset(spapr
, errp
);
736 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
738 const char *nodename
= spapr
->irq
->get_nodename(spapr
);
741 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
743 error_setg(errp
, "Can't find node \"%s\": %s", nodename
,
744 fdt_strerror(offset
));
748 phandle
= fdt_get_phandle(fdt
, offset
);
750 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
758 * XICS legacy routines - to deprecate one day
761 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
765 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
766 if (num
> (ics
->nr_irqs
- first
)) {
769 for (i
= first
; i
< first
+ num
; ++i
) {
770 if (!ICS_IRQ_FREE(ics
, i
)) {
774 if (i
== (first
+ num
)) {
782 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
784 ICSState
*ics
= spapr
->ics
;
790 * MSIMesage::data is used for storing VIRQ so
791 * it has to be aligned to num to support multiple
792 * MSI vectors. MSI-X is not affected by this.
793 * The hint is used for the first IRQ, the rest should
794 * be allocated continuously.
797 assert((num
== 1) || (num
== 2) || (num
== 4) ||
798 (num
== 8) || (num
== 16) || (num
== 32));
799 first
= ics_find_free_block(ics
, num
, num
);
801 first
= ics_find_free_block(ics
, num
, 1);
805 error_setg(errp
, "can't find a free %d-IRQ block", num
);
809 return first
+ ics
->offset
;
812 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
814 SpaprIrq spapr_irq_xics_legacy
= {
815 .nr_irqs
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
816 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
817 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
819 .init
= spapr_irq_init_xics
,
820 .claim
= spapr_irq_claim_xics
,
821 .free
= spapr_irq_free_xics
,
822 .qirq
= spapr_qirq_xics
,
823 .print_info
= spapr_irq_print_info_xics
,
824 .dt_populate
= spapr_dt_xics
,
825 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
826 .post_load
= spapr_irq_post_load_xics
,
827 .reset
= spapr_irq_reset_xics
,
828 .set_irq
= spapr_irq_set_irq_xics
,
829 .get_nodename
= spapr_irq_get_nodename_xics
,
830 .init_kvm
= spapr_irq_init_kvm_xics
,