2 * QEMU PowerPC PowerNV XSCOM bus
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/module.h"
23 #include "sysemu/hw_accel.h"
24 #include "target/ppc/cpu.h"
25 #include "hw/sysbus.h"
27 #include "hw/ppc/fdt.h"
28 #include "hw/ppc/pnv.h"
29 #include "hw/ppc/pnv_xscom.h"
34 #define PRD_P8_IPOLL_REG_MASK 0x01020013
35 #define PRD_P8_IPOLL_REG_STATUS 0x01020014
36 #define PRD_P9_IPOLL_REG_MASK 0x000F0033
37 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034
39 static void xscom_complete(CPUState
*cs
, uint64_t hmer_bits
)
42 * TODO: When the read/write comes from the monitor, NULL is
43 * passed for the cpu, and no CPU completion is generated.
46 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
47 CPUPPCState
*env
= &cpu
->env
;
50 * TODO: Need a CPU helper to set HMER, also handle generation
53 cpu_synchronize_state(cs
);
54 env
->spr
[SPR_HMER
] |= hmer_bits
;
58 static uint32_t pnv_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
60 addr
&= (PNV_XSCOM_SIZE
- 1);
62 if (pnv_chip_is_power9(chip
)) {
65 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
69 static uint64_t xscom_read_default(PnvChip
*chip
, uint32_t pcba
)
73 return PNV_CHIP_GET_CLASS(chip
)->chip_cfam_id
;
74 case 0x18002: /* ECID2 */
77 case 0x1010c00: /* PIBAM FIR */
78 case 0x1010c03: /* PIBAM FIR MASK */
81 case PRD_P8_IPOLL_REG_MASK
:
82 case PRD_P8_IPOLL_REG_STATUS
:
83 case PRD_P9_IPOLL_REG_MASK
:
84 case PRD_P9_IPOLL_REG_STATUS
:
87 case 0x0090018: /* Receive status reg */
88 case 0x0090012: /* log register */
89 case 0x0090013: /* error register */
92 case 0x2020007: /* ADU stuff, log register */
93 case 0x2020009: /* ADU stuff, error register */
94 case 0x202000f: /* ADU stuff, receive status register*/
96 case 0x2013f00: /* PBA stuff */
97 case 0x2013f01: /* PBA stuff */
98 case 0x2013f02: /* PBA stuff */
99 case 0x2013f03: /* PBA stuff */
100 case 0x2013f04: /* PBA stuff */
101 case 0x2013f05: /* PBA stuff */
102 case 0x2013f06: /* PBA stuff */
103 case 0x2013f07: /* PBA stuff */
105 case 0x2013028: /* CAPP stuff */
106 case 0x201302a: /* CAPP stuff */
107 case 0x2013801: /* CAPP stuff */
108 case 0x2013802: /* CAPP stuff */
125 static bool xscom_write_default(PnvChip
*chip
, uint32_t pcba
, uint64_t val
)
127 /* We ignore writes to these */
129 case 0xf000f: /* chip id is RO */
130 case 0x1010c00: /* PIBAM FIR */
131 case 0x1010c01: /* PIBAM FIR */
132 case 0x1010c02: /* PIBAM FIR */
133 case 0x1010c03: /* PIBAM FIR MASK */
134 case 0x1010c04: /* PIBAM FIR MASK */
135 case 0x1010c05: /* PIBAM FIR MASK */
137 case 0x0090018: /* Receive status reg */
138 case 0x0090012: /* log register */
139 case 0x0090013: /* error register */
142 case 0x2020007: /* ADU stuff, log register */
143 case 0x2020009: /* ADU stuff, error register */
144 case 0x202000f: /* ADU stuff, receive status register*/
146 case 0x2013028: /* CAPP stuff */
147 case 0x201302a: /* CAPP stuff */
148 case 0x2013801: /* CAPP stuff */
149 case 0x2013802: /* CAPP stuff */
161 /* P8 PRD registers */
162 case PRD_P8_IPOLL_REG_MASK
:
163 case PRD_P8_IPOLL_REG_STATUS
:
164 case PRD_P9_IPOLL_REG_MASK
:
165 case PRD_P9_IPOLL_REG_STATUS
:
172 static uint64_t xscom_read(void *opaque
, hwaddr addr
, unsigned width
)
174 PnvChip
*chip
= opaque
;
175 uint32_t pcba
= pnv_xscom_pcba(chip
, addr
);
179 /* Handle some SCOMs here before dispatch */
180 val
= xscom_read_default(chip
, pcba
);
185 val
= address_space_ldq(&chip
->xscom_as
, (uint64_t) pcba
<< 3,
186 MEMTXATTRS_UNSPECIFIED
, &result
);
187 if (result
!= MEMTX_OK
) {
188 qemu_log_mask(LOG_GUEST_ERROR
, "XSCOM read failed at @0x%"
189 HWADDR_PRIx
" pcba=0x%08x\n", addr
, pcba
);
190 xscom_complete(current_cpu
, HMER_XSCOM_FAIL
| HMER_XSCOM_DONE
);
195 xscom_complete(current_cpu
, HMER_XSCOM_DONE
);
199 static void xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
202 PnvChip
*chip
= opaque
;
203 uint32_t pcba
= pnv_xscom_pcba(chip
, addr
);
206 /* Handle some SCOMs here before dispatch */
207 if (xscom_write_default(chip
, pcba
, val
)) {
211 address_space_stq(&chip
->xscom_as
, (uint64_t) pcba
<< 3, val
,
212 MEMTXATTRS_UNSPECIFIED
, &result
);
213 if (result
!= MEMTX_OK
) {
214 qemu_log_mask(LOG_GUEST_ERROR
, "XSCOM write failed at @0x%"
215 HWADDR_PRIx
" pcba=0x%08x data=0x%" PRIx64
"\n",
217 xscom_complete(current_cpu
, HMER_XSCOM_FAIL
| HMER_XSCOM_DONE
);
222 xscom_complete(current_cpu
, HMER_XSCOM_DONE
);
225 const MemoryRegionOps pnv_xscom_ops
= {
227 .write
= xscom_write
,
228 .valid
.min_access_size
= 8,
229 .valid
.max_access_size
= 8,
230 .impl
.min_access_size
= 8,
231 .impl
.max_access_size
= 8,
232 .endianness
= DEVICE_BIG_ENDIAN
,
235 void pnv_xscom_realize(PnvChip
*chip
, uint64_t size
, Error
**errp
)
237 SysBusDevice
*sbd
= SYS_BUS_DEVICE(chip
);
240 name
= g_strdup_printf("xscom-%x", chip
->chip_id
);
241 memory_region_init_io(&chip
->xscom_mmio
, OBJECT(chip
), &pnv_xscom_ops
,
243 sysbus_init_mmio(sbd
, &chip
->xscom_mmio
);
245 memory_region_init(&chip
->xscom
, OBJECT(chip
), name
, size
);
246 address_space_init(&chip
->xscom_as
, &chip
->xscom
, name
);
250 static const TypeInfo pnv_xscom_interface_info
= {
251 .name
= TYPE_PNV_XSCOM_INTERFACE
,
252 .parent
= TYPE_INTERFACE
,
253 .class_size
= sizeof(PnvXScomInterfaceClass
),
256 static void pnv_xscom_register_types(void)
258 type_register_static(&pnv_xscom_interface_info
);
261 type_init(pnv_xscom_register_types
)
263 typedef struct ForeachPopulateArgs
{
266 } ForeachPopulateArgs
;
268 static int xscom_dt_child(Object
*child
, void *opaque
)
270 if (object_dynamic_cast(child
, TYPE_PNV_XSCOM_INTERFACE
)) {
271 ForeachPopulateArgs
*args
= opaque
;
272 PnvXScomInterface
*xd
= PNV_XSCOM_INTERFACE(child
);
273 PnvXScomInterfaceClass
*xc
= PNV_XSCOM_INTERFACE_GET_CLASS(xd
);
276 _FDT((xc
->dt_xscom(xd
, args
->fdt
, args
->xscom_offset
)));
282 static const char compat_p8
[] = "ibm,power8-xscom\0ibm,xscom";
283 static const char compat_p9
[] = "ibm,power9-xscom\0ibm,xscom";
285 int pnv_dt_xscom(PnvChip
*chip
, void *fdt
, int root_offset
)
289 ForeachPopulateArgs args
;
292 if (pnv_chip_is_power9(chip
)) {
293 reg
[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip
));
294 reg
[1] = cpu_to_be64(PNV9_XSCOM_SIZE
);
296 reg
[0] = cpu_to_be64(PNV_XSCOM_BASE(chip
));
297 reg
[1] = cpu_to_be64(PNV_XSCOM_SIZE
);
300 name
= g_strdup_printf("xscom@%" PRIx64
, be64_to_cpu(reg
[0]));
301 xscom_offset
= fdt_add_subnode(fdt
, root_offset
, name
);
304 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "ibm,chip-id", chip
->chip_id
)));
305 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "#address-cells", 1)));
306 _FDT((fdt_setprop_cell(fdt
, xscom_offset
, "#size-cells", 1)));
307 _FDT((fdt_setprop(fdt
, xscom_offset
, "reg", reg
, sizeof(reg
))));
309 if (pnv_chip_is_power9(chip
)) {
310 _FDT((fdt_setprop(fdt
, xscom_offset
, "compatible", compat_p9
,
311 sizeof(compat_p9
))));
313 _FDT((fdt_setprop(fdt
, xscom_offset
, "compatible", compat_p8
,
314 sizeof(compat_p8
))));
317 _FDT((fdt_setprop(fdt
, xscom_offset
, "scom-controller", NULL
, 0)));
320 args
.xscom_offset
= xscom_offset
;
322 object_child_foreach(OBJECT(chip
), xscom_dt_child
, &args
);
326 void pnv_xscom_add_subregion(PnvChip
*chip
, hwaddr offset
, MemoryRegion
*mr
)
328 memory_region_add_subregion(&chip
->xscom
, offset
<< 3, mr
);
331 void pnv_xscom_region_init(MemoryRegion
*mr
,
332 struct Object
*owner
,
333 const MemoryRegionOps
*ops
,
338 memory_region_init_io(mr
, owner
, ops
, opaque
, name
, size
<< 3);