hw/arm/smmuv3-internal.h

   1 /*
   2  * ARM SMMUv3 support - Internal API
   3  *
   4  * Copyright (C) 2014-2016 Broadcom Corporation
   5  * Copyright (c) 2017 Red Hat, Inc.
   6  * Written by Prem Mallappa, Eric Auger
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef HW_ARM_SMMUV3_INTERNAL_H
  22 #define HW_ARM_SMMUV3_INTERNAL_H
  23
  24 #include "hw/arm/smmu-common.h"
  25
  26 typedef enum SMMUTranslationStatus {
  27     SMMU_TRANS_DISABLE,
  28     SMMU_TRANS_ABORT,
  29     SMMU_TRANS_BYPASS,
  30     SMMU_TRANS_ERROR,
  31     SMMU_TRANS_SUCCESS,
  32 } SMMUTranslationStatus;
  33
  34 /* MMIO Registers */
  35
  36 REG32(IDR0,                0x0)
  37     FIELD(IDR0, S1P,         1 , 1)
  38     FIELD(IDR0, TTF,         2 , 2)
  39     FIELD(IDR0, COHACC,      4 , 1)
  40     FIELD(IDR0, ASID16,      12, 1)
  41     FIELD(IDR0, TTENDIAN,    21, 2)
  42     FIELD(IDR0, STALL_MODEL, 24, 2)
  43     FIELD(IDR0, TERM_MODEL,  26, 1)
  44     FIELD(IDR0, STLEVEL,     27, 2)
  45
  46 REG32(IDR1,                0x4)
  47     FIELD(IDR1, SIDSIZE,      0 , 6)
  48     FIELD(IDR1, EVENTQS,      16, 5)
  49     FIELD(IDR1, CMDQS,        21, 5)
  50
  51 #define SMMU_IDR1_SIDSIZE 16
  52 #define SMMU_CMDQS   19
  53 #define SMMU_EVENTQS 19
  54
  55 REG32(IDR2,                0x8)
  56 REG32(IDR3,                0xc)
  57 REG32(IDR4,                0x10)
  58 REG32(IDR5,                0x14)
  59      FIELD(IDR5, OAS,         0, 3);
  60      FIELD(IDR5, GRAN4K,      4, 1);
  61      FIELD(IDR5, GRAN16K,     5, 1);
  62      FIELD(IDR5, GRAN64K,     6, 1);
  63
  64 #define SMMU_IDR5_OAS 4
  65
  66 REG32(IIDR,                0x18)
  67 REG32(AIDR,                0x1c)
  68 REG32(CR0,                 0x20)
  69     FIELD(CR0, SMMU_ENABLE,   0, 1)
  70     FIELD(CR0, EVENTQEN,      2, 1)
  71     FIELD(CR0, CMDQEN,        3, 1)
  72
  73 #define SMMU_CR0_RESERVED 0xFFFFFC20
  74
  75 REG32(CR0ACK,              0x24)
  76 REG32(CR1,                 0x28)
  77 REG32(CR2,                 0x2c)
  78 REG32(STATUSR,             0x40)
  79 REG32(IRQ_CTRL,            0x50)
  80     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
  81     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
  82     FIELD(IRQ_CTRL, EVENTQ_IRQEN,        2, 1)
  83
  84 REG32(IRQ_CTRL_ACK,        0x54)
  85 REG32(GERROR,              0x60)
  86     FIELD(GERROR, CMDQ_ERR,           0, 1)
  87     FIELD(GERROR, EVENTQ_ABT_ERR,     2, 1)
  88     FIELD(GERROR, PRIQ_ABT_ERR,       3, 1)
  89     FIELD(GERROR, MSI_CMDQ_ABT_ERR,   4, 1)
  90     FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
  91     FIELD(GERROR, MSI_PRIQ_ABT_ERR,   6, 1)
  92     FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
  93     FIELD(GERROR, MSI_SFM_ERR,        8, 1)
  94
  95 REG32(GERRORN,             0x64)
  96
  97 #define A_GERROR_IRQ_CFG0  0x68 /* 64b */
  98 REG32(GERROR_IRQ_CFG1, 0x70)
  99 REG32(GERROR_IRQ_CFG2, 0x74)
 100
 101 #define A_STRTAB_BASE      0x80 /* 64b */
 102
 103 #define SMMU_BASE_ADDR_MASK 0xfffffffffffc0
 104
 105 REG32(STRTAB_BASE_CFG,     0x88)
 106     FIELD(STRTAB_BASE_CFG, FMT,      16, 2)
 107     FIELD(STRTAB_BASE_CFG, SPLIT,    6 , 5)
 108     FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
 109
 110 #define A_CMDQ_BASE        0x90 /* 64b */
 111 REG32(CMDQ_PROD,           0x98)
 112 REG32(CMDQ_CONS,           0x9c)
 113     FIELD(CMDQ_CONS, ERR, 24, 7)
 114
 115 #define A_EVENTQ_BASE      0xa0 /* 64b */
 116 REG32(EVENTQ_PROD,         0xa8)
 117 REG32(EVENTQ_CONS,         0xac)
 118
 119 #define A_EVENTQ_IRQ_CFG0  0xb0 /* 64b */
 120 REG32(EVENTQ_IRQ_CFG1,     0xb8)
 121 REG32(EVENTQ_IRQ_CFG2,     0xbc)
 122
 123 #define A_IDREGS           0xfd0
 124
 125 static inline int smmu_enabled(SMMUv3State *s)
 126 {
 127     return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
 128 }
 129
 130 /* Command Queue Entry */
 131 typedef struct Cmd {
 132     uint32_t word[4];
 133 } Cmd;
 134
 135 /* Event Queue Entry */
 136 typedef struct Evt  {
 137     uint32_t word[8];
 138 } Evt;
 139
 140 static inline uint32_t smmuv3_idreg(int regoffset)
 141 {
 142     /*
 143      * Return the value of the Primecell/Corelink ID registers at the
 144      * specified offset from the first ID register.
 145      * These value indicate an ARM implementation of MMU600 p1
 146      */
 147     static const uint8_t smmuv3_ids[] = {
 148         0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
 149     };
 150     return smmuv3_ids[regoffset / 4];
 151 }
 152
 153 static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
 154 {
 155     return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
 156 }
 157
 158 static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
 159 {
 160     return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
 161 }
 162
 163 /* Queue Handling */
 164
 165 #define Q_BASE(q)          ((q)->base & SMMU_BASE_ADDR_MASK)
 166 #define WRAP_MASK(q)       (1 << (q)->log2size)
 167 #define INDEX_MASK(q)      (((1 << (q)->log2size)) - 1)
 168 #define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)
 169
 170 #define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
 171 #define Q_PROD(q) ((q)->prod & INDEX_MASK(q))
 172
 173 #define Q_CONS_ENTRY(q)  (Q_BASE(q) + (q)->entry_size * Q_CONS(q))
 174 #define Q_PROD_ENTRY(q)  (Q_BASE(q) + (q)->entry_size * Q_PROD(q))
 175
 176 #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size)
 177 #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size)
 178
 179 static inline bool smmuv3_q_full(SMMUQueue *q)
 180 {
 181     return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q);
 182 }
 183
 184 static inline bool smmuv3_q_empty(SMMUQueue *q)
 185 {
 186     return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q));
 187 }
 188
 189 static inline void queue_prod_incr(SMMUQueue *q)
 190 {
 191     q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q);
 192 }
 193
 194 static inline void queue_cons_incr(SMMUQueue *q)
 195 {
 196     /*
 197      * We have to use deposit for the CONS registers to preserve
 198      * the ERR field in the high bits.
 199      */
 200     q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
 201 }
 202
 203 static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
 204 {
 205     return FIELD_EX32(s->cr[0], CR0, CMDQEN);
 206 }
 207
 208 static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
 209 {
 210     return FIELD_EX32(s->cr[0], CR0, EVENTQEN);
 211 }
 212
 213 static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
 214 {
 215     s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
 216 }
 217
 218 /* Commands */
 219
 220 typedef enum SMMUCommandType {
 221     SMMU_CMD_NONE            = 0x00,
 222     SMMU_CMD_PREFETCH_CONFIG       ,
 223     SMMU_CMD_PREFETCH_ADDR,
 224     SMMU_CMD_CFGI_STE,
 225     SMMU_CMD_CFGI_STE_RANGE,
 226     SMMU_CMD_CFGI_CD,
 227     SMMU_CMD_CFGI_CD_ALL,
 228     SMMU_CMD_CFGI_ALL,
 229     SMMU_CMD_TLBI_NH_ALL     = 0x10,
 230     SMMU_CMD_TLBI_NH_ASID,
 231     SMMU_CMD_TLBI_NH_VA,
 232     SMMU_CMD_TLBI_NH_VAA,
 233     SMMU_CMD_TLBI_EL3_ALL    = 0x18,
 234     SMMU_CMD_TLBI_EL3_VA     = 0x1a,
 235     SMMU_CMD_TLBI_EL2_ALL    = 0x20,
 236     SMMU_CMD_TLBI_EL2_ASID,
 237     SMMU_CMD_TLBI_EL2_VA,
 238     SMMU_CMD_TLBI_EL2_VAA,
 239     SMMU_CMD_TLBI_S12_VMALL  = 0x28,
 240     SMMU_CMD_TLBI_S2_IPA     = 0x2a,
 241     SMMU_CMD_TLBI_NSNH_ALL   = 0x30,
 242     SMMU_CMD_ATC_INV         = 0x40,
 243     SMMU_CMD_PRI_RESP,
 244     SMMU_CMD_RESUME          = 0x44,
 245     SMMU_CMD_STALL_TERM,
 246     SMMU_CMD_SYNC,
 247 } SMMUCommandType;
 248
 249 static const char *cmd_stringify[] = {
 250     [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
 251     [SMMU_CMD_PREFETCH_ADDR]   = "SMMU_CMD_PREFETCH_ADDR",
 252     [SMMU_CMD_CFGI_STE]        = "SMMU_CMD_CFGI_STE",
 253     [SMMU_CMD_CFGI_STE_RANGE]  = "SMMU_CMD_CFGI_STE_RANGE",
 254     [SMMU_CMD_CFGI_CD]         = "SMMU_CMD_CFGI_CD",
 255     [SMMU_CMD_CFGI_CD_ALL]     = "SMMU_CMD_CFGI_CD_ALL",
 256     [SMMU_CMD_CFGI_ALL]        = "SMMU_CMD_CFGI_ALL",
 257     [SMMU_CMD_TLBI_NH_ALL]     = "SMMU_CMD_TLBI_NH_ALL",
 258     [SMMU_CMD_TLBI_NH_ASID]    = "SMMU_CMD_TLBI_NH_ASID",
 259     [SMMU_CMD_TLBI_NH_VA]      = "SMMU_CMD_TLBI_NH_VA",
 260     [SMMU_CMD_TLBI_NH_VAA]     = "SMMU_CMD_TLBI_NH_VAA",
 261     [SMMU_CMD_TLBI_EL3_ALL]    = "SMMU_CMD_TLBI_EL3_ALL",
 262     [SMMU_CMD_TLBI_EL3_VA]     = "SMMU_CMD_TLBI_EL3_VA",
 263     [SMMU_CMD_TLBI_EL2_ALL]    = "SMMU_CMD_TLBI_EL2_ALL",
 264     [SMMU_CMD_TLBI_EL2_ASID]   = "SMMU_CMD_TLBI_EL2_ASID",
 265     [SMMU_CMD_TLBI_EL2_VA]     = "SMMU_CMD_TLBI_EL2_VA",
 266     [SMMU_CMD_TLBI_EL2_VAA]    = "SMMU_CMD_TLBI_EL2_VAA",
 267     [SMMU_CMD_TLBI_S12_VMALL]  = "SMMU_CMD_TLBI_S12_VMALL",
 268     [SMMU_CMD_TLBI_S2_IPA]     = "SMMU_CMD_TLBI_S2_IPA",
 269     [SMMU_CMD_TLBI_NSNH_ALL]   = "SMMU_CMD_TLBI_NSNH_ALL",
 270     [SMMU_CMD_ATC_INV]         = "SMMU_CMD_ATC_INV",
 271     [SMMU_CMD_PRI_RESP]        = "SMMU_CMD_PRI_RESP",
 272     [SMMU_CMD_RESUME]          = "SMMU_CMD_RESUME",
 273     [SMMU_CMD_STALL_TERM]      = "SMMU_CMD_STALL_TERM",
 274     [SMMU_CMD_SYNC]            = "SMMU_CMD_SYNC",
 275 };
 276
 277 static inline const char *smmu_cmd_string(SMMUCommandType type)
 278 {
 279     if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) {
 280         return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN";
 281     } else {
 282         return "INVALID";
 283     }
 284 }
 285
 286 /* CMDQ fields */
 287
 288 typedef enum {
 289     SMMU_CERROR_NONE = 0,
 290     SMMU_CERROR_ILL,
 291     SMMU_CERROR_ABT,
 292     SMMU_CERROR_ATC_INV_SYNC,
 293 } SMMUCmdError;
 294
 295 enum { /* Command completion notification */
 296     CMD_SYNC_SIG_NONE,
 297     CMD_SYNC_SIG_IRQ,
 298     CMD_SYNC_SIG_SEV,
 299 };
 300
 301 #define CMD_TYPE(x)         extract32((x)->word[0], 0 , 8)
 302 #define CMD_NUM(x)          extract32((x)->word[0], 12 , 5)
 303 #define CMD_SCALE(x)        extract32((x)->word[0], 20 , 5)
 304 #define CMD_SSEC(x)         extract32((x)->word[0], 10, 1)
 305 #define CMD_SSV(x)          extract32((x)->word[0], 11, 1)
 306 #define CMD_RESUME_AC(x)    extract32((x)->word[0], 12, 1)
 307 #define CMD_RESUME_AB(x)    extract32((x)->word[0], 13, 1)
 308 #define CMD_SYNC_CS(x)      extract32((x)->word[0], 12, 2)
 309 #define CMD_SSID(x)         extract32((x)->word[0], 12, 20)
 310 #define CMD_SID(x)          ((x)->word[1])
 311 #define CMD_VMID(x)         extract32((x)->word[1], 0 , 16)
 312 #define CMD_ASID(x)         extract32((x)->word[1], 16, 16)
 313 #define CMD_RESUME_STAG(x)  extract32((x)->word[2], 0 , 16)
 314 #define CMD_RESP(x)         extract32((x)->word[2], 11, 2)
 315 #define CMD_LEAF(x)         extract32((x)->word[2], 0 , 1)
 316 #define CMD_TTL(x)          extract32((x)->word[2], 8 , 2)
 317 #define CMD_TG(x)           extract32((x)->word[2], 10, 2)
 318 #define CMD_STE_RANGE(x)    extract32((x)->word[2], 0 , 5)
 319 #define CMD_ADDR(x) ({                                        \
 320             uint64_t high = (uint64_t)(x)->word[3];           \
 321             uint64_t low = extract32((x)->word[2], 12, 20);    \
 322             uint64_t addr = high << 32 | (low << 12);         \
 323             addr;                                             \
 324         })
 325
 326 #define SMMU_FEATURE_2LVL_STE (1 << 0)
 327
 328 /* Events */
 329
 330 typedef enum SMMUEventType {
 331     SMMU_EVT_NONE               = 0x00,
 332     SMMU_EVT_F_UUT                    ,
 333     SMMU_EVT_C_BAD_STREAMID           ,
 334     SMMU_EVT_F_STE_FETCH              ,
 335     SMMU_EVT_C_BAD_STE                ,
 336     SMMU_EVT_F_BAD_ATS_TREQ           ,
 337     SMMU_EVT_F_STREAM_DISABLED        ,
 338     SMMU_EVT_F_TRANS_FORBIDDEN        ,
 339     SMMU_EVT_C_BAD_SUBSTREAMID        ,
 340     SMMU_EVT_F_CD_FETCH               ,
 341     SMMU_EVT_C_BAD_CD                 ,
 342     SMMU_EVT_F_WALK_EABT              ,
 343     SMMU_EVT_F_TRANSLATION      = 0x10,
 344     SMMU_EVT_F_ADDR_SIZE              ,
 345     SMMU_EVT_F_ACCESS                 ,
 346     SMMU_EVT_F_PERMISSION             ,
 347     SMMU_EVT_F_TLB_CONFLICT     = 0x20,
 348     SMMU_EVT_F_CFG_CONFLICT           ,
 349     SMMU_EVT_E_PAGE_REQ         = 0x24,
 350 } SMMUEventType;
 351
 352 static const char *event_stringify[] = {
 353     [SMMU_EVT_NONE]                     = "no recorded event",
 354     [SMMU_EVT_F_UUT]                    = "SMMU_EVT_F_UUT",
 355     [SMMU_EVT_C_BAD_STREAMID]           = "SMMU_EVT_C_BAD_STREAMID",
 356     [SMMU_EVT_F_STE_FETCH]              = "SMMU_EVT_F_STE_FETCH",
 357     [SMMU_EVT_C_BAD_STE]                = "SMMU_EVT_C_BAD_STE",
 358     [SMMU_EVT_F_BAD_ATS_TREQ]           = "SMMU_EVT_F_BAD_ATS_TREQ",
 359     [SMMU_EVT_F_STREAM_DISABLED]        = "SMMU_EVT_F_STREAM_DISABLED",
 360     [SMMU_EVT_F_TRANS_FORBIDDEN]        = "SMMU_EVT_F_TRANS_FORBIDDEN",
 361     [SMMU_EVT_C_BAD_SUBSTREAMID]        = "SMMU_EVT_C_BAD_SUBSTREAMID",
 362     [SMMU_EVT_F_CD_FETCH]               = "SMMU_EVT_F_CD_FETCH",
 363     [SMMU_EVT_C_BAD_CD]                 = "SMMU_EVT_C_BAD_CD",
 364     [SMMU_EVT_F_WALK_EABT]              = "SMMU_EVT_F_WALK_EABT",
 365     [SMMU_EVT_F_TRANSLATION]            = "SMMU_EVT_F_TRANSLATION",
 366     [SMMU_EVT_F_ADDR_SIZE]              = "SMMU_EVT_F_ADDR_SIZE",
 367     [SMMU_EVT_F_ACCESS]                 = "SMMU_EVT_F_ACCESS",
 368     [SMMU_EVT_F_PERMISSION]             = "SMMU_EVT_F_PERMISSION",
 369     [SMMU_EVT_F_TLB_CONFLICT]           = "SMMU_EVT_F_TLB_CONFLICT",
 370     [SMMU_EVT_F_CFG_CONFLICT]           = "SMMU_EVT_F_CFG_CONFLICT",
 371     [SMMU_EVT_E_PAGE_REQ]               = "SMMU_EVT_E_PAGE_REQ",
 372 };
 373
 374 static inline const char *smmu_event_string(SMMUEventType type)
 375 {
 376     if (type < ARRAY_SIZE(event_stringify)) {
 377         return event_stringify[type] ? event_stringify[type] : "UNKNOWN";
 378     } else {
 379         return "INVALID";
 380     }
 381 }
 382
 383 /*  Encode an event record */
 384 typedef struct SMMUEventInfo {
 385     SMMUEventType type;
 386     uint32_t sid;
 387     bool recorded;
 388     bool record_trans_faults;
 389     bool inval_ste_allowed;
 390     union {
 391         struct {
 392             uint32_t ssid;
 393             bool ssv;
 394             dma_addr_t addr;
 395             bool rnw;
 396             bool pnu;
 397             bool ind;
 398        } f_uut;
 399        struct SSIDInfo {
 400             uint32_t ssid;
 401             bool ssv;
 402        } c_bad_streamid;
 403        struct SSIDAddrInfo {
 404             uint32_t ssid;
 405             bool ssv;
 406             dma_addr_t addr;
 407        } f_ste_fetch;
 408        struct SSIDInfo c_bad_ste;
 409        struct {
 410             dma_addr_t addr;
 411             bool rnw;
 412        } f_transl_forbidden;
 413        struct {
 414             uint32_t ssid;
 415        } c_bad_substream;
 416        struct SSIDAddrInfo f_cd_fetch;
 417        struct SSIDInfo c_bad_cd;
 418        struct FullInfo {
 419             bool stall;
 420             uint16_t stag;
 421             uint32_t ssid;
 422             bool ssv;
 423             bool s2;
 424             dma_addr_t addr;
 425             bool rnw;
 426             bool pnu;
 427             bool ind;
 428             uint8_t class;
 429             dma_addr_t addr2;
 430        } f_walk_eabt;
 431        struct FullInfo f_translation;
 432        struct FullInfo f_addr_size;
 433        struct FullInfo f_access;
 434        struct FullInfo f_permission;
 435        struct SSIDInfo f_cfg_conflict;
 436        /**
 437         * not supported yet:
 438         * F_BAD_ATS_TREQ
 439         * F_BAD_ATS_TREQ
 440         * F_TLB_CONFLICT
 441         * E_PAGE_REQUEST
 442         * IMPDEF_EVENTn
 443         */
 444     } u;
 445 } SMMUEventInfo;
 446
 447 /* EVTQ fields */
 448
 449 #define EVT_Q_OVERFLOW        (1 << 31)
 450
 451 #define EVT_SET_TYPE(x, v)  ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
 452 #define EVT_SET_SSV(x, v)   ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
 453 #define EVT_SET_SSID(x, v)  ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
 454 #define EVT_SET_SID(x, v)   ((x)->word[1] = v)
 455 #define EVT_SET_STAG(x, v)  ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
 456 #define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
 457 #define EVT_SET_PNU(x, v)   ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
 458 #define EVT_SET_IND(x, v)   ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
 459 #define EVT_SET_RNW(x, v)   ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
 460 #define EVT_SET_S2(x, v)    ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
 461 #define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
 462 #define EVT_SET_ADDR(x, addr)                             \
 463     do {                                                  \
 464             (x)->word[5] = (uint32_t)(addr >> 32);        \
 465             (x)->word[4] = (uint32_t)(addr & 0xffffffff); \
 466     } while (0)
 467 #define EVT_SET_ADDR2(x, addr)                            \
 468     do {                                                  \
 469             (x)->word[7] = (uint32_t)(addr >> 32);        \
 470             (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
 471     } while (0)
 472
 473 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
 474
 475 /* Configuration Data */
 476
 477 /* STE Level 1 Descriptor */
 478 typedef struct STEDesc {
 479     uint32_t word[2];
 480 } STEDesc;
 481
 482 /* CD Level 1 Descriptor */
 483 typedef struct CDDesc {
 484     uint32_t word[2];
 485 } CDDesc;
 486
 487 /* Stream Table Entry(STE) */
 488 typedef struct STE {
 489     uint32_t word[16];
 490 } STE;
 491
 492 /* Context Descriptor(CD) */
 493 typedef struct CD {
 494     uint32_t word[16];
 495 } CD;
 496
 497 /* STE fields */
 498
 499 #define STE_VALID(x)   extract32((x)->word[0], 0, 1)
 500
 501 #define STE_CONFIG(x)  extract32((x)->word[0], 1, 3)
 502 #define STE_CFG_S1_ENABLED(config) (config & 0x1)
 503 #define STE_CFG_S2_ENABLED(config) (config & 0x2)
 504 #define STE_CFG_ABORT(config)      (!(config & 0x4))
 505 #define STE_CFG_BYPASS(config)     (config == 0x4)
 506
 507 #define STE_S1FMT(x)       extract32((x)->word[0], 4 , 2)
 508 #define STE_S1CDMAX(x)     extract32((x)->word[1], 27, 5)
 509 #define STE_S1STALLD(x)    extract32((x)->word[2], 27, 1)
 510 #define STE_EATS(x)        extract32((x)->word[2], 28, 2)
 511 #define STE_STRW(x)        extract32((x)->word[2], 30, 2)
 512 #define STE_S2VMID(x)      extract32((x)->word[4], 0 , 16)
 513 #define STE_S2T0SZ(x)      extract32((x)->word[5], 0 , 6)
 514 #define STE_S2SL0(x)       extract32((x)->word[5], 6 , 2)
 515 #define STE_S2TG(x)        extract32((x)->word[5], 14, 2)
 516 #define STE_S2PS(x)        extract32((x)->word[5], 16, 3)
 517 #define STE_S2AA64(x)      extract32((x)->word[5], 19, 1)
 518 #define STE_S2HD(x)        extract32((x)->word[5], 24, 1)
 519 #define STE_S2HA(x)        extract32((x)->word[5], 25, 1)
 520 #define STE_S2S(x)         extract32((x)->word[5], 26, 1)
 521 #define STE_CTXPTR(x)                                           \
 522     ({                                                          \
 523         unsigned long addr;                                     \
 524         addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32;  \
 525         addr |= (uint64_t)((x)->word[0] & 0xffffffc0);          \
 526         addr;                                                   \
 527     })
 528
 529 #define STE_S2TTB(x)                                            \
 530     ({                                                          \
 531         unsigned long addr;                                     \
 532         addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32;  \
 533         addr |= (uint64_t)((x)->word[6] & 0xfffffff0);          \
 534         addr;                                                   \
 535     })
 536
 537 static inline int oas2bits(int oas_field)
 538 {
 539     switch (oas_field) {
 540     case 0:
 541         return 32;
 542     case 1:
 543         return 36;
 544     case 2:
 545         return 40;
 546     case 3:
 547         return 42;
 548     case 4:
 549         return 44;
 550     case 5:
 551         return 48;
 552     }
 553     return -1;
 554 }
 555
 556 static inline int pa_range(STE *ste)
 557 {
 558     int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
 559
 560     if (!STE_S2AA64(ste)) {
 561         return 40;
 562     }
 563
 564     return oas2bits(oas_field);
 565 }
 566
 567 #define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
 568
 569 /* CD fields */
 570
 571 #define CD_VALID(x)   extract32((x)->word[0], 30, 1)
 572 #define CD_ASID(x)    extract32((x)->word[1], 16, 16)
 573 #define CD_TTB(x, sel)                                      \
 574     ({                                                      \
 575         uint64_t hi, lo;                                    \
 576         hi = extract32((x)->word[(sel) * 2 + 3], 0, 19);    \
 577         hi <<= 32;                                          \
 578         lo = (x)->word[(sel) * 2 + 2] & ~0xfULL;            \
 579         hi | lo;                                            \
 580     })
 581
 582 #define CD_TSZ(x, sel)   extract32((x)->word[0], (16 * (sel)) + 0, 6)
 583 #define CD_TG(x, sel)    extract32((x)->word[0], (16 * (sel)) + 6, 2)
 584 #define CD_EPD(x, sel)   extract32((x)->word[0], (16 * (sel)) + 14, 1)
 585 #define CD_ENDI(x)       extract32((x)->word[0], 15, 1)
 586 #define CD_IPS(x)        extract32((x)->word[1], 0 , 3)
 587 #define CD_TBI(x)        extract32((x)->word[1], 6 , 2)
 588 #define CD_HD(x)         extract32((x)->word[1], 10 , 1)
 589 #define CD_HA(x)         extract32((x)->word[1], 11 , 1)
 590 #define CD_S(x)          extract32((x)->word[1], 12, 1)
 591 #define CD_R(x)          extract32((x)->word[1], 13, 1)
 592 #define CD_A(x)          extract32((x)->word[1], 14, 1)
 593 #define CD_AARCH64(x)    extract32((x)->word[1], 9 , 1)
 594
 595 #define CDM_VALID(x)    ((x)->word[0] & 0x1)
 596
 597 static inline int is_cd_valid(SMMUv3State *s, STE *ste, CD *cd)
 598 {
 599     return CD_VALID(cd);
 600 }
 601
 602 /**
 603  * tg2granule - Decodes the CD translation granule size field according
 604  * to the ttbr in use
 605  * @bits: TG0/1 fields
 606  * @ttbr: ttbr index in use
 607  */
 608 static inline int tg2granule(int bits, int ttbr)
 609 {
 610     switch (bits) {
 611     case 0:
 612         return ttbr ? 0  : 12;
 613     case 1:
 614         return ttbr ? 14 : 16;
 615     case 2:
 616         return ttbr ? 12 : 14;
 617     case 3:
 618         return ttbr ? 16 :  0;
 619     default:
 620         return 0;
 621     }
 622 }
 623
 624 static inline uint64_t l1std_l2ptr(STEDesc *desc)
 625 {
 626     uint64_t hi, lo;
 627
 628     hi = desc->word[1];
 629     lo = desc->word[0] & ~0x1fULL;
 630     return hi << 32 | lo;
 631 }
 632
 633 #define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
 634
 635 #endif