4 * Copyright IBM, Corp. 2012-2013
7 * Anthony Liguori <aliguori@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
13 #include "libqos/pci.h"
15 #include "hw/pci/pci_regs.h"
18 void qpci_device_foreach(QPCIBus
*bus
, int vendor_id
, int device_id
,
19 void (*func
)(QPCIDevice
*dev
, int devfn
, void *data
),
24 for (slot
= 0; slot
< 32; slot
++) {
27 for (fn
= 0; fn
< 8; fn
++) {
30 dev
= qpci_device_find(bus
, QPCI_DEVFN(slot
, fn
));
35 if (vendor_id
!= -1 &&
36 qpci_config_readw(dev
, PCI_VENDOR_ID
) != vendor_id
) {
40 if (device_id
!= -1 &&
41 qpci_config_readw(dev
, PCI_DEVICE_ID
) != device_id
) {
45 func(dev
, QPCI_DEVFN(slot
, fn
), data
);
50 QPCIDevice
*qpci_device_find(QPCIBus
*bus
, int devfn
)
54 dev
= g_malloc0(sizeof(*dev
));
58 if (qpci_config_readw(dev
, PCI_VENDOR_ID
) == 0xFFFF) {
66 void qpci_device_enable(QPCIDevice
*dev
)
70 /* FIXME -- does this need to be a bus callout? */
71 cmd
= qpci_config_readw(dev
, PCI_COMMAND
);
72 cmd
|= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
;
73 qpci_config_writew(dev
, PCI_COMMAND
, cmd
);
76 uint8_t qpci_find_capability(QPCIDevice
*dev
, uint8_t id
)
79 uint8_t addr
= qpci_config_readb(dev
, PCI_CAPABILITY_LIST
);
82 cap
= qpci_config_readb(dev
, addr
);
84 addr
= qpci_config_readb(dev
, addr
+ PCI_CAP_LIST_NEXT
);
86 } while (cap
!= id
&& addr
!= 0);
91 void qpci_msix_enable(QPCIDevice
*dev
)
100 addr
= qpci_find_capability(dev
, PCI_CAP_ID_MSIX
);
101 g_assert_cmphex(addr
, !=, 0);
103 val
= qpci_config_readw(dev
, addr
+ PCI_MSIX_FLAGS
);
104 qpci_config_writew(dev
, addr
+ PCI_MSIX_FLAGS
, val
| PCI_MSIX_FLAGS_ENABLE
);
106 table
= qpci_config_readl(dev
, addr
+ PCI_MSIX_TABLE
);
107 bir_table
= table
& PCI_MSIX_FLAGS_BIRMASK
;
108 offset
= qpci_iomap(dev
, bir_table
, NULL
);
109 dev
->msix_table
= offset
+ (table
& ~PCI_MSIX_FLAGS_BIRMASK
);
111 table
= qpci_config_readl(dev
, addr
+ PCI_MSIX_PBA
);
112 bir_pba
= table
& PCI_MSIX_FLAGS_BIRMASK
;
113 if (bir_pba
!= bir_table
) {
114 offset
= qpci_iomap(dev
, bir_pba
, NULL
);
116 dev
->msix_pba
= offset
+ (table
& ~PCI_MSIX_FLAGS_BIRMASK
);
118 g_assert(dev
->msix_table
!= NULL
);
119 g_assert(dev
->msix_pba
!= NULL
);
120 dev
->msix_enabled
= true;
123 void qpci_msix_disable(QPCIDevice
*dev
)
128 g_assert(dev
->msix_enabled
);
129 addr
= qpci_find_capability(dev
, PCI_CAP_ID_MSIX
);
130 g_assert_cmphex(addr
, !=, 0);
131 val
= qpci_config_readw(dev
, addr
+ PCI_MSIX_FLAGS
);
132 qpci_config_writew(dev
, addr
+ PCI_MSIX_FLAGS
,
133 val
& ~PCI_MSIX_FLAGS_ENABLE
);
135 qpci_iounmap(dev
, dev
->msix_table
);
136 qpci_iounmap(dev
, dev
->msix_pba
);
137 dev
->msix_enabled
= 0;
138 dev
->msix_table
= NULL
;
139 dev
->msix_pba
= NULL
;
142 bool qpci_msix_pending(QPCIDevice
*dev
, uint16_t entry
)
145 uint8_t bit_n
= entry
% 32;
146 void *addr
= dev
->msix_pba
+ (entry
/ 32) * PCI_MSIX_ENTRY_SIZE
/ 4;
148 g_assert(dev
->msix_enabled
);
149 pba_entry
= qpci_io_readl(dev
, addr
);
150 qpci_io_writel(dev
, addr
, pba_entry
& ~(1 << bit_n
));
151 return (pba_entry
& (1 << bit_n
)) != 0;
154 bool qpci_msix_masked(QPCIDevice
*dev
, uint16_t entry
)
158 void *vector_addr
= dev
->msix_table
+ (entry
* PCI_MSIX_ENTRY_SIZE
);
160 g_assert(dev
->msix_enabled
);
161 addr
= qpci_find_capability(dev
, PCI_CAP_ID_MSIX
);
162 g_assert_cmphex(addr
, !=, 0);
163 val
= qpci_config_readw(dev
, addr
+ PCI_MSIX_FLAGS
);
165 if (val
& PCI_MSIX_FLAGS_MASKALL
) {
168 return (qpci_io_readl(dev
, vector_addr
+ PCI_MSIX_ENTRY_VECTOR_CTRL
)
169 & PCI_MSIX_ENTRY_CTRL_MASKBIT
) != 0;
173 uint16_t qpci_msix_table_size(QPCIDevice
*dev
)
178 addr
= qpci_find_capability(dev
, PCI_CAP_ID_MSIX
);
179 g_assert_cmphex(addr
, !=, 0);
181 control
= qpci_config_readw(dev
, addr
+ PCI_MSIX_FLAGS
);
182 return (control
& PCI_MSIX_FLAGS_QSIZE
) + 1;
185 uint8_t qpci_config_readb(QPCIDevice
*dev
, uint8_t offset
)
187 return dev
->bus
->config_readb(dev
->bus
, dev
->devfn
, offset
);
190 uint16_t qpci_config_readw(QPCIDevice
*dev
, uint8_t offset
)
192 return dev
->bus
->config_readw(dev
->bus
, dev
->devfn
, offset
);
195 uint32_t qpci_config_readl(QPCIDevice
*dev
, uint8_t offset
)
197 return dev
->bus
->config_readl(dev
->bus
, dev
->devfn
, offset
);
201 void qpci_config_writeb(QPCIDevice
*dev
, uint8_t offset
, uint8_t value
)
203 dev
->bus
->config_writeb(dev
->bus
, dev
->devfn
, offset
, value
);
206 void qpci_config_writew(QPCIDevice
*dev
, uint8_t offset
, uint16_t value
)
208 dev
->bus
->config_writew(dev
->bus
, dev
->devfn
, offset
, value
);
211 void qpci_config_writel(QPCIDevice
*dev
, uint8_t offset
, uint32_t value
)
213 dev
->bus
->config_writel(dev
->bus
, dev
->devfn
, offset
, value
);
217 uint8_t qpci_io_readb(QPCIDevice
*dev
, void *data
)
219 return dev
->bus
->io_readb(dev
->bus
, data
);
222 uint16_t qpci_io_readw(QPCIDevice
*dev
, void *data
)
224 return dev
->bus
->io_readw(dev
->bus
, data
);
227 uint32_t qpci_io_readl(QPCIDevice
*dev
, void *data
)
229 return dev
->bus
->io_readl(dev
->bus
, data
);
233 void qpci_io_writeb(QPCIDevice
*dev
, void *data
, uint8_t value
)
235 dev
->bus
->io_writeb(dev
->bus
, data
, value
);
238 void qpci_io_writew(QPCIDevice
*dev
, void *data
, uint16_t value
)
240 dev
->bus
->io_writew(dev
->bus
, data
, value
);
243 void qpci_io_writel(QPCIDevice
*dev
, void *data
, uint32_t value
)
245 dev
->bus
->io_writel(dev
->bus
, data
, value
);
248 void *qpci_iomap(QPCIDevice
*dev
, int barno
, uint64_t *sizeptr
)
250 return dev
->bus
->iomap(dev
->bus
, dev
, barno
, sizeptr
);
253 void qpci_iounmap(QPCIDevice
*dev
, void *data
)
255 dev
->bus
->iounmap(dev
->bus
, data
);