tests/libqos/pci.c

   1 /*
   2  * libqos PCI bindings
   3  *
   4  * Copyright IBM, Corp. 2012-2013
   5  *
   6  * Authors:
   7  *  Anthony Liguori   <aliguori@us.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "libqos/pci.h"
  14
  15 #include "hw/pci/pci_regs.h"
  16 #include <glib.h>
  17
  18 void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
  19                          void (*func)(QPCIDevice *dev, int devfn, void *data),
  20                          void *data)
  21 {
  22     int slot;
  23
  24     for (slot = 0; slot < 32; slot++) {
  25         int fn;
  26
  27         for (fn = 0; fn < 8; fn++) {
  28             QPCIDevice *dev;
  29
  30             dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
  31             if (!dev) {
  32                 continue;
  33             }
  34
  35             if (vendor_id != -1 &&
  36                 qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
  37                 continue;
  38             }
  39
  40             if (device_id != -1 &&
  41                 qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
  42                 continue;
  43             }
  44
  45             func(dev, QPCI_DEVFN(slot, fn), data);
  46         }
  47     }
  48 }
  49
  50 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
  51 {
  52     QPCIDevice *dev;
  53
  54     dev = g_malloc0(sizeof(*dev));
  55     dev->bus = bus;
  56     dev->devfn = devfn;
  57
  58     if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
  59         g_free(dev);
  60         return NULL;
  61     }
  62
  63     return dev;
  64 }
  65
  66 void qpci_device_enable(QPCIDevice *dev)
  67 {
  68     uint16_t cmd;
  69
  70     /* FIXME -- does this need to be a bus callout? */
  71     cmd = qpci_config_readw(dev, PCI_COMMAND);
  72     cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  73     qpci_config_writew(dev, PCI_COMMAND, cmd);
  74 }
  75
  76 uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id)
  77 {
  78     uint8_t cap;
  79     uint8_t addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
  80
  81     do {
  82         cap = qpci_config_readb(dev, addr);
  83         if (cap != id) {
  84             addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT);
  85         }
  86     } while (cap != id && addr != 0);
  87
  88     return addr;
  89 }
  90
  91 void qpci_msix_enable(QPCIDevice *dev)
  92 {
  93     uint8_t addr;
  94     uint16_t val;
  95     uint32_t table;
  96     uint8_t bir_table;
  97     uint8_t bir_pba;
  98     void *offset;
  99
 100     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 101     g_assert_cmphex(addr, !=, 0);
 102
 103     val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 104     qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
 105
 106     table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
 107     bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
 108     offset = qpci_iomap(dev, bir_table, NULL);
 109     dev->msix_table = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK);
 110
 111     table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
 112     bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
 113     if (bir_pba != bir_table) {
 114         offset = qpci_iomap(dev, bir_pba, NULL);
 115     }
 116     dev->msix_pba = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK);
 117
 118     g_assert(dev->msix_table != NULL);
 119     g_assert(dev->msix_pba != NULL);
 120     dev->msix_enabled = true;
 121 }
 122
 123 void qpci_msix_disable(QPCIDevice *dev)
 124 {
 125     uint8_t addr;
 126     uint16_t val;
 127
 128     g_assert(dev->msix_enabled);
 129     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 130     g_assert_cmphex(addr, !=, 0);
 131     val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 132     qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
 133                                                 val & ~PCI_MSIX_FLAGS_ENABLE);
 134
 135     qpci_iounmap(dev, dev->msix_table);
 136     qpci_iounmap(dev, dev->msix_pba);
 137     dev->msix_enabled = 0;
 138     dev->msix_table = NULL;
 139     dev->msix_pba = NULL;
 140 }
 141
 142 bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
 143 {
 144     uint32_t pba_entry;
 145     uint8_t bit_n = entry % 32;
 146     void *addr = dev->msix_pba + (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
 147
 148     g_assert(dev->msix_enabled);
 149     pba_entry = qpci_io_readl(dev, addr);
 150     qpci_io_writel(dev, addr, pba_entry & ~(1 << bit_n));
 151     return (pba_entry & (1 << bit_n)) != 0;
 152 }
 153
 154 bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
 155 {
 156     uint8_t addr;
 157     uint16_t val;
 158     void *vector_addr = dev->msix_table + (entry * PCI_MSIX_ENTRY_SIZE);
 159
 160     g_assert(dev->msix_enabled);
 161     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 162     g_assert_cmphex(addr, !=, 0);
 163     val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 164
 165     if (val & PCI_MSIX_FLAGS_MASKALL) {
 166         return true;
 167     } else {
 168         return (qpci_io_readl(dev, vector_addr + PCI_MSIX_ENTRY_VECTOR_CTRL)
 169                                             & PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0;
 170     }
 171 }
 172
 173 uint16_t qpci_msix_table_size(QPCIDevice *dev)
 174 {
 175     uint8_t addr;
 176     uint16_t control;
 177
 178     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 179     g_assert_cmphex(addr, !=, 0);
 180
 181     control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 182     return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
 183 }
 184
 185 uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
 186 {
 187     return dev->bus->config_readb(dev->bus, dev->devfn, offset);
 188 }
 189
 190 uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
 191 {
 192     return dev->bus->config_readw(dev->bus, dev->devfn, offset);
 193 }
 194
 195 uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
 196 {
 197     return dev->bus->config_readl(dev->bus, dev->devfn, offset);
 198 }
 199
 200
 201 void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
 202 {
 203     dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
 204 }
 205
 206 void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
 207 {
 208     dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
 209 }
 210
 211 void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
 212 {
 213     dev->bus->config_writel(dev->bus, dev->devfn, offset, value);
 214 }
 215
 216
 217 uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
 218 {
 219     return dev->bus->io_readb(dev->bus, data);
 220 }
 221
 222 uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
 223 {
 224     return dev->bus->io_readw(dev->bus, data);
 225 }
 226
 227 uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
 228 {
 229     return dev->bus->io_readl(dev->bus, data);
 230 }
 231
 232
 233 void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
 234 {
 235     dev->bus->io_writeb(dev->bus, data, value);
 236 }
 237
 238 void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
 239 {
 240     dev->bus->io_writew(dev->bus, data, value);
 241 }
 242
 243 void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
 244 {
 245     dev->bus->io_writel(dev->bus, data, value);
 246 }
 247
 248 void *qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
 249 {
 250     return dev->bus->iomap(dev->bus, dev, barno, sizeptr);
 251 }
 252
 253 void qpci_iounmap(QPCIDevice *dev, void *data)
 254 {
 255     dev->bus->iounmap(dev->bus, data);
 256 }
 257
 258