2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/smbios/smbios.h"
41 #include "hw/loader.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
56 #include "hw/xen/xen.h"
57 #include "ui/qemu-spice.h"
58 #include "exec/memory.h"
59 #include "exec/address-spaces.h"
60 #include "sysemu/arch_init.h"
61 #include "qemu/bitmap.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "qemu/option.h"
65 #include "hw/acpi/acpi.h"
66 #include "hw/acpi/cpu_hotplug.h"
67 #include "hw/boards.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/net/ne2000-isa.h"
78 /* debug PC/ISA interrupts */
82 #define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
85 #define DPRINTF(fmt, ...)
88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
94 #define E820_NR_ENTRIES 16
100 } QEMU_PACKED
__attribute((__aligned__(4)));
104 struct e820_entry entry
[E820_NR_ENTRIES
];
105 } QEMU_PACKED
__attribute((__aligned__(4)));
107 static struct e820_table e820_reserve
;
108 static struct e820_entry
*e820_table
;
109 static unsigned e820_entries
;
110 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
112 void gsi_handler(void *opaque
, int n
, int level
)
114 GSIState
*s
= opaque
;
116 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
117 if (n
< ISA_NUM_IRQS
) {
118 qemu_set_irq(s
->i8259_irq
[n
], level
);
120 qemu_set_irq(s
->ioapic_irq
[n
], level
);
123 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
128 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
130 return 0xffffffffffffffffULL
;
133 /* MSDOS compatibility mode FPU exception support */
134 static qemu_irq ferr_irq
;
136 void pc_register_ferr_irq(qemu_irq irq
)
141 /* XXX: add IGNNE support */
142 void cpu_set_ferr(CPUX86State
*s
)
144 qemu_irq_raise(ferr_irq
);
147 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
150 qemu_irq_lower(ferr_irq
);
153 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
155 return 0xffffffffffffffffULL
;
159 uint64_t cpu_get_tsc(CPUX86State
*env
)
161 return cpu_get_ticks();
165 int cpu_get_pic_interrupt(CPUX86State
*env
)
167 X86CPU
*cpu
= x86_env_get_cpu(env
);
170 if (!kvm_irqchip_in_kernel()) {
171 intno
= apic_get_interrupt(cpu
->apic_state
);
175 /* read the irq from the PIC */
176 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
181 intno
= pic_read_irq(isa_pic
);
185 static void pic_irq_request(void *opaque
, int irq
, int level
)
187 CPUState
*cs
= first_cpu
;
188 X86CPU
*cpu
= X86_CPU(cs
);
190 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
191 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
194 if (apic_accept_pic_intr(cpu
->apic_state
)) {
195 apic_deliver_pic_intr(cpu
->apic_state
, level
);
200 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
202 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
207 /* PC cmos mappings */
209 #define REG_EQUIPMENT_BYTE 0x14
211 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
216 case FLOPPY_DRIVE_TYPE_144
:
217 /* 1.44 Mb 3"5 drive */
220 case FLOPPY_DRIVE_TYPE_288
:
221 /* 2.88 Mb 3"5 drive */
224 case FLOPPY_DRIVE_TYPE_120
:
225 /* 1.2 Mb 5"5 drive */
228 case FLOPPY_DRIVE_TYPE_NONE
:
236 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
237 int16_t cylinders
, int8_t heads
, int8_t sectors
)
239 rtc_set_memory(s
, type_ofs
, 47);
240 rtc_set_memory(s
, info_ofs
, cylinders
);
241 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
242 rtc_set_memory(s
, info_ofs
+ 2, heads
);
243 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
244 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
245 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
246 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
247 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
248 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
251 /* convert boot_device letter to something recognizable by the bios */
252 static int boot_device2nibble(char boot_device
)
254 switch(boot_device
) {
257 return 0x01; /* floppy boot */
259 return 0x02; /* hard drive boot */
261 return 0x03; /* CD-ROM boot */
263 return 0x04; /* Network boot */
268 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
270 #define PC_MAX_BOOT_DEVICES 3
271 int nbds
, bds
[3] = { 0, };
274 nbds
= strlen(boot_device
);
275 if (nbds
> PC_MAX_BOOT_DEVICES
) {
276 error_setg(errp
, "Too many boot devices for PC");
279 for (i
= 0; i
< nbds
; i
++) {
280 bds
[i
] = boot_device2nibble(boot_device
[i
]);
282 error_setg(errp
, "Invalid boot device for PC: '%c'",
287 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
288 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
291 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
293 set_boot_dev(opaque
, boot_device
, errp
);
296 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
299 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
300 FLOPPY_DRIVE_TYPE_NONE
};
304 for (i
= 0; i
< 2; i
++) {
305 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
308 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
309 cmos_get_fd_drive_type(fd_type
[1]);
310 rtc_set_memory(rtc_state
, 0x10, val
);
312 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
314 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
317 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
324 val
|= 0x01; /* 1 drive, ready for boot */
327 val
|= 0x41; /* 2 drives, ready for boot */
330 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
333 typedef struct pc_cmos_init_late_arg
{
334 ISADevice
*rtc_state
;
336 } pc_cmos_init_late_arg
;
338 typedef struct check_fdc_state
{
343 static int check_fdc(Object
*obj
, void *opaque
)
345 CheckFdcState
*state
= opaque
;
348 Error
*local_err
= NULL
;
350 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
355 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
356 if (local_err
|| iobase
!= 0x3f0) {
357 error_free(local_err
);
362 state
->multiple
= true;
364 state
->floppy
= ISA_DEVICE(obj
);
369 static const char * const fdc_container_path
[] = {
370 "/unattached", "/peripheral", "/peripheral-anon"
374 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
377 ISADevice
*pc_find_fdc0(void)
381 CheckFdcState state
= { 0 };
383 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
384 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
385 object_child_foreach(container
, check_fdc
, &state
);
388 if (state
.multiple
) {
389 warn_report("multiple floppy disk controllers with "
390 "iobase=0x3f0 have been found");
391 error_printf("the one being picked for CMOS setup might not reflect "
398 static void pc_cmos_init_late(void *opaque
)
400 pc_cmos_init_late_arg
*arg
= opaque
;
401 ISADevice
*s
= arg
->rtc_state
;
403 int8_t heads
, sectors
;
408 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
409 &cylinders
, &heads
, §ors
) >= 0) {
410 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
413 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
414 &cylinders
, &heads
, §ors
) >= 0) {
415 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
418 rtc_set_memory(s
, 0x12, val
);
421 for (i
= 0; i
< 4; i
++) {
422 /* NOTE: ide_get_geometry() returns the physical
423 geometry. It is always such that: 1 <= sects <= 63, 1
424 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
425 geometry can be different if a translation is done. */
426 if (arg
->idebus
[i
/ 2] &&
427 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
428 &cylinders
, &heads
, §ors
) >= 0) {
429 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
430 assert((trans
& ~3) == 0);
431 val
|= trans
<< (i
* 2);
434 rtc_set_memory(s
, 0x39, val
);
436 pc_cmos_init_floppy(s
, pc_find_fdc0());
438 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
441 void pc_cmos_init(PCMachineState
*pcms
,
442 BusState
*idebus0
, BusState
*idebus1
,
446 static pc_cmos_init_late_arg arg
;
448 /* various important CMOS locations needed by PC/Bochs bios */
451 /* base memory (first MiB) */
452 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
453 rtc_set_memory(s
, 0x15, val
);
454 rtc_set_memory(s
, 0x16, val
>> 8);
455 /* extended memory (next 64MiB) */
456 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
457 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
463 rtc_set_memory(s
, 0x17, val
);
464 rtc_set_memory(s
, 0x18, val
>> 8);
465 rtc_set_memory(s
, 0x30, val
);
466 rtc_set_memory(s
, 0x31, val
>> 8);
467 /* memory between 16MiB and 4GiB */
468 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
469 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
475 rtc_set_memory(s
, 0x34, val
);
476 rtc_set_memory(s
, 0x35, val
>> 8);
477 /* memory above 4GiB */
478 val
= pcms
->above_4g_mem_size
/ 65536;
479 rtc_set_memory(s
, 0x5b, val
);
480 rtc_set_memory(s
, 0x5c, val
>> 8);
481 rtc_set_memory(s
, 0x5d, val
>> 16);
483 object_property_add_link(OBJECT(pcms
), "rtc_state",
485 (Object
**)&pcms
->rtc
,
486 object_property_allow_set_link
,
487 OBJ_PROP_LINK_STRONG
, &error_abort
);
488 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
489 "rtc_state", &error_abort
);
491 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
494 val
|= 0x02; /* FPU is there */
495 val
|= 0x04; /* PS/2 mouse installed */
496 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
498 /* hard drives and FDC */
500 arg
.idebus
[0] = idebus0
;
501 arg
.idebus
[1] = idebus1
;
502 qemu_register_reset(pc_cmos_init_late
, &arg
);
505 #define TYPE_PORT92 "port92"
506 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
508 /* port 92 stuff: could be split off */
509 typedef struct Port92State
{
510 ISADevice parent_obj
;
517 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
520 Port92State
*s
= opaque
;
521 int oldval
= s
->outport
;
523 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
525 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
526 if ((val
& 1) && !(oldval
& 1)) {
527 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
531 static uint64_t port92_read(void *opaque
, hwaddr addr
,
534 Port92State
*s
= opaque
;
538 DPRINTF("port92: read 0x%02x\n", ret
);
542 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
544 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
547 static const VMStateDescription vmstate_port92_isa
= {
550 .minimum_version_id
= 1,
551 .fields
= (VMStateField
[]) {
552 VMSTATE_UINT8(outport
, Port92State
),
553 VMSTATE_END_OF_LIST()
557 static void port92_reset(DeviceState
*d
)
559 Port92State
*s
= PORT92(d
);
564 static const MemoryRegionOps port92_ops
= {
566 .write
= port92_write
,
568 .min_access_size
= 1,
569 .max_access_size
= 1,
571 .endianness
= DEVICE_LITTLE_ENDIAN
,
574 static void port92_initfn(Object
*obj
)
576 Port92State
*s
= PORT92(obj
);
578 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
582 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
585 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
587 ISADevice
*isadev
= ISA_DEVICE(dev
);
588 Port92State
*s
= PORT92(dev
);
590 isa_register_ioport(isadev
, &s
->io
, 0x92);
593 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
595 DeviceClass
*dc
= DEVICE_CLASS(klass
);
597 dc
->realize
= port92_realizefn
;
598 dc
->reset
= port92_reset
;
599 dc
->vmsd
= &vmstate_port92_isa
;
601 * Reason: unlike ordinary ISA devices, this one needs additional
602 * wiring: its A20 output line needs to be wired up by
605 dc
->user_creatable
= false;
608 static const TypeInfo port92_info
= {
610 .parent
= TYPE_ISA_DEVICE
,
611 .instance_size
= sizeof(Port92State
),
612 .instance_init
= port92_initfn
,
613 .class_init
= port92_class_initfn
,
616 static void port92_register_types(void)
618 type_register_static(&port92_info
);
621 type_init(port92_register_types
)
623 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
625 X86CPU
*cpu
= opaque
;
627 /* XXX: send to all CPUs ? */
628 /* XXX: add logic to handle multiple A20 line sources */
629 x86_cpu_set_a20(cpu
, level
);
632 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
634 int index
= le32_to_cpu(e820_reserve
.count
);
635 struct e820_entry
*entry
;
637 if (type
!= E820_RAM
) {
638 /* old FW_CFG_E820_TABLE entry -- reservations only */
639 if (index
>= E820_NR_ENTRIES
) {
642 entry
= &e820_reserve
.entry
[index
++];
644 entry
->address
= cpu_to_le64(address
);
645 entry
->length
= cpu_to_le64(length
);
646 entry
->type
= cpu_to_le32(type
);
648 e820_reserve
.count
= cpu_to_le32(index
);
651 /* new "etc/e820" file -- include ram too */
652 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
653 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
654 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
655 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
661 int e820_get_num_entries(void)
666 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
668 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
669 *address
= le64_to_cpu(e820_table
[idx
].address
);
670 *length
= le64_to_cpu(e820_table
[idx
].length
);
676 /* Enables contiguous-apic-ID mode, for compatibility */
677 static bool compat_apic_id_mode
;
679 void enable_compat_apic_id_mode(void)
681 compat_apic_id_mode
= true;
684 /* Calculates initial APIC ID for a specific CPU index
686 * Currently we need to be able to calculate the APIC ID from the CPU index
687 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
688 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
689 * all CPUs up to max_cpus.
691 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
696 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
697 if (compat_apic_id_mode
) {
698 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
699 error_report("APIC IDs set in compatibility mode, "
700 "CPU topology won't match the configuration");
709 static void pc_build_smbios(PCMachineState
*pcms
)
711 uint8_t *smbios_tables
, *smbios_anchor
;
712 size_t smbios_tables_len
, smbios_anchor_len
;
713 struct smbios_phys_mem_area
*mem_array
;
714 unsigned i
, array_count
;
715 MachineState
*ms
= MACHINE(pcms
);
716 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
718 /* tell smbios about cpuid version and features */
719 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
721 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
723 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
724 smbios_tables
, smbios_tables_len
);
727 /* build the array of physical mem area from e820 table */
728 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
729 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
732 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
733 mem_array
[array_count
].address
= addr
;
734 mem_array
[array_count
].length
= len
;
738 smbios_get_tables(mem_array
, array_count
,
739 &smbios_tables
, &smbios_tables_len
,
740 &smbios_anchor
, &smbios_anchor_len
);
744 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
745 smbios_tables
, smbios_tables_len
);
746 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
747 smbios_anchor
, smbios_anchor_len
);
751 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
754 uint64_t *numa_fw_cfg
;
756 const CPUArchIdList
*cpus
;
757 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
759 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
760 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
762 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
764 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
765 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
766 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
767 * for CPU hotplug also uses APIC ID and not "CPU index".
768 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
769 * but the "limit to the APIC ID values SeaBIOS may see".
771 * So for compatibility reasons with old BIOSes we are stuck with
772 * "etc/max-cpus" actually being apic_id_limit
774 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
775 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
776 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
777 acpi_tables
, acpi_tables_len
);
778 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
780 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
781 &e820_reserve
, sizeof(e820_reserve
));
782 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
783 sizeof(struct e820_entry
) * e820_entries
);
785 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
786 /* allocate memory for the NUMA channel: one (64bit) word for the number
787 * of nodes, one word for each VCPU->node and one word for each node to
788 * hold the amount of memory.
790 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
791 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
792 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
793 for (i
= 0; i
< cpus
->len
; i
++) {
794 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
795 assert(apic_id
< pcms
->apic_id_limit
);
796 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
798 for (i
= 0; i
< nb_numa_nodes
; i
++) {
799 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
800 cpu_to_le64(numa_info
[i
].node_mem
);
802 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
803 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
804 sizeof(*numa_fw_cfg
));
809 static long get_file_size(FILE *f
)
813 /* XXX: on Unix systems, using fstat() probably makes more sense */
816 fseek(f
, 0, SEEK_END
);
818 fseek(f
, where
, SEEK_SET
);
823 /* setup_data types */
825 #define SETUP_E820_EXT 1
835 } __attribute__((packed
));
837 static void load_linux(PCMachineState
*pcms
,
841 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
842 int dtb_size
, setup_data_offset
;
844 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
845 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
848 MachineState
*machine
= MACHINE(pcms
);
849 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
850 struct setup_data
*setup_data
;
851 const char *kernel_filename
= machine
->kernel_filename
;
852 const char *initrd_filename
= machine
->initrd_filename
;
853 const char *dtb_filename
= machine
->dtb
;
854 const char *kernel_cmdline
= machine
->kernel_cmdline
;
856 /* Align to 16 bytes as a paranoia measure */
857 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
859 /* load the kernel header */
860 f
= fopen(kernel_filename
, "rb");
861 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
862 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
863 MIN(ARRAY_SIZE(header
), kernel_size
)) {
864 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
865 kernel_filename
, strerror(errno
));
869 /* kernel protocol version */
871 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
873 if (ldl_p(header
+0x202) == 0x53726448) {
874 protocol
= lduw_p(header
+0x206);
876 /* This looks like a multiboot kernel. If it is, let's stop
877 treating it like a Linux kernel. */
878 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
879 kernel_cmdline
, kernel_size
, header
)) {
885 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
888 cmdline_addr
= 0x9a000 - cmdline_size
;
890 } else if (protocol
< 0x202) {
891 /* High but ancient kernel */
893 cmdline_addr
= 0x9a000 - cmdline_size
;
894 prot_addr
= 0x100000;
896 /* High and recent kernel */
898 cmdline_addr
= 0x20000;
899 prot_addr
= 0x100000;
904 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
905 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
906 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
912 /* highest address for loading the initrd */
913 if (protocol
>= 0x203) {
914 initrd_max
= ldl_p(header
+0x22c);
916 initrd_max
= 0x37ffffff;
919 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
920 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
923 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
924 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
925 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
927 if (protocol
>= 0x202) {
928 stl_p(header
+0x228, cmdline_addr
);
930 stw_p(header
+0x20, 0xA33F);
931 stw_p(header
+0x22, cmdline_addr
-real_addr
);
934 /* handle vga= parameter */
935 vmode
= strstr(kernel_cmdline
, "vga=");
937 unsigned int video_mode
;
940 if (!strncmp(vmode
, "normal", 6)) {
942 } else if (!strncmp(vmode
, "ext", 3)) {
944 } else if (!strncmp(vmode
, "ask", 3)) {
947 video_mode
= strtol(vmode
, NULL
, 0);
949 stw_p(header
+0x1fa, video_mode
);
953 /* High nybble = B reserved for QEMU; low nybble is revision number.
954 If this code is substantially changed, you may want to consider
955 incrementing the revision. */
956 if (protocol
>= 0x200) {
957 header
[0x210] = 0xB0;
960 if (protocol
>= 0x201) {
961 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
962 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
966 if (initrd_filename
) {
967 if (protocol
< 0x200) {
968 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
972 initrd_size
= get_image_size(initrd_filename
);
973 if (initrd_size
< 0) {
974 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
975 initrd_filename
, strerror(errno
));
979 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
981 initrd_data
= g_malloc(initrd_size
);
982 load_image(initrd_filename
, initrd_data
);
984 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
985 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
986 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
988 stl_p(header
+0x218, initrd_addr
);
989 stl_p(header
+0x21c, initrd_size
);
992 /* load kernel and setup */
993 setup_size
= header
[0x1f1];
994 if (setup_size
== 0) {
997 setup_size
= (setup_size
+1)*512;
998 if (setup_size
> kernel_size
) {
999 fprintf(stderr
, "qemu: invalid kernel header\n");
1002 kernel_size
-= setup_size
;
1004 setup
= g_malloc(setup_size
);
1005 kernel
= g_malloc(kernel_size
);
1006 fseek(f
, 0, SEEK_SET
);
1007 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1008 fprintf(stderr
, "fread() failed\n");
1011 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1012 fprintf(stderr
, "fread() failed\n");
1017 /* append dtb to kernel */
1019 if (protocol
< 0x209) {
1020 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1024 dtb_size
= get_image_size(dtb_filename
);
1025 if (dtb_size
<= 0) {
1026 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1027 dtb_filename
, strerror(errno
));
1031 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1032 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1033 kernel
= g_realloc(kernel
, kernel_size
);
1035 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1037 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1038 setup_data
->next
= 0;
1039 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1040 setup_data
->len
= cpu_to_le32(dtb_size
);
1042 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1045 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1047 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1048 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1049 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1051 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1052 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1053 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1055 option_rom
[nb_option_roms
].bootindex
= 0;
1056 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1057 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1058 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1063 #define NE2000_NB_MAX 6
1065 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1067 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1069 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1071 static int nb_ne2k
= 0;
1073 if (nb_ne2k
== NE2000_NB_MAX
)
1075 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1076 ne2000_irq
[nb_ne2k
], nd
);
1080 DeviceState
*cpu_get_current_apic(void)
1083 X86CPU
*cpu
= X86_CPU(current_cpu
);
1084 return cpu
->apic_state
;
1090 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1092 X86CPU
*cpu
= opaque
;
1095 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1099 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1102 Error
*local_err
= NULL
;
1104 cpu
= object_new(typename
);
1106 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1107 object_property_set_bool(cpu
, true, "realized", &local_err
);
1110 error_propagate(errp
, local_err
);
1113 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1115 MachineState
*ms
= MACHINE(qdev_get_machine());
1116 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1117 Error
*local_err
= NULL
;
1120 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1124 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1125 error_setg(errp
, "Unable to add CPU: %" PRIi64
1126 ", resulting APIC ID (%" PRIi64
") is too large",
1131 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1133 error_propagate(errp
, local_err
);
1138 void pc_cpus_init(PCMachineState
*pcms
)
1141 const CPUArchIdList
*possible_cpus
;
1142 MachineState
*ms
= MACHINE(pcms
);
1143 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1145 /* Calculates the limit to CPU APIC ID values
1147 * Limit for the APIC ID value, so that all
1148 * CPU APIC IDs are < pcms->apic_id_limit.
1150 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1152 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1153 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1154 for (i
= 0; i
< smp_cpus
; i
++) {
1155 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1160 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1162 MachineState
*ms
= MACHINE(pcms
);
1163 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1164 CPUX86State
*env
= &cpu
->env
;
1165 uint32_t unused
, ecx
, edx
;
1166 uint64_t feature_control_bits
= 0;
1169 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1170 if (ecx
& CPUID_EXT_VMX
) {
1171 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1174 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1175 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1176 (env
->mcg_cap
& MCG_LMCE_P
)) {
1177 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1180 if (!feature_control_bits
) {
1184 val
= g_malloc(sizeof(*val
));
1185 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1186 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1189 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1191 if (cpus_count
> 0xff) {
1192 /* If the number of CPUs can't be represented in 8 bits, the
1193 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1194 * to make old BIOSes fail more predictably.
1196 rtc_set_memory(rtc
, 0x5f, 0);
1198 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1203 void pc_machine_done(Notifier
*notifier
, void *data
)
1205 PCMachineState
*pcms
= container_of(notifier
,
1206 PCMachineState
, machine_done
);
1207 PCIBus
*bus
= pcms
->bus
;
1209 /* set the number of CPUs */
1210 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1213 int extra_hosts
= 0;
1215 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1216 /* look for expander root buses */
1217 if (pci_bus_is_root(bus
)) {
1221 if (extra_hosts
&& pcms
->fw_cfg
) {
1222 uint64_t *val
= g_malloc(sizeof(*val
));
1223 *val
= cpu_to_le64(extra_hosts
);
1224 fw_cfg_add_file(pcms
->fw_cfg
,
1225 "etc/extra-pci-roots", val
, sizeof(*val
));
1231 pc_build_smbios(pcms
);
1232 pc_build_feature_control_file(pcms
);
1233 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1234 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1237 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1238 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1240 if (!iommu
|| !iommu
->x86_iommu
.intr_supported
||
1241 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1242 error_report("current -smp configuration requires "
1243 "Extended Interrupt Mode enabled. "
1244 "You can add an IOMMU using: "
1245 "-device intel-iommu,intremap=on,eim=on");
1251 void pc_guest_info_init(PCMachineState
*pcms
)
1255 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1256 pcms
->numa_nodes
= nb_numa_nodes
;
1257 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1258 sizeof *pcms
->node_mem
);
1259 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1260 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1263 pcms
->machine_done
.notify
= pc_machine_done
;
1264 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1267 /* setup pci memory address space mapping into system address space */
1268 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1269 MemoryRegion
*pci_address_space
)
1271 /* Set to lower priority than RAM */
1272 memory_region_add_subregion_overlap(system_memory
, 0x0,
1273 pci_address_space
, -1);
1276 void pc_acpi_init(const char *default_dsdt
)
1280 if (acpi_tables
!= NULL
) {
1281 /* manually set via -acpitable, leave it alone */
1285 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1286 if (filename
== NULL
) {
1287 warn_report("failed to find %s", default_dsdt
);
1289 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("acpi"), NULL
, 0,
1293 qemu_opt_set(opts
, "file", filename
, &error_abort
);
1295 acpi_table_add_builtin(opts
, &err
);
1297 warn_reportf_err(err
, "failed to load %s: ", filename
);
1303 void xen_load_linux(PCMachineState
*pcms
)
1308 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1310 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1311 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1314 load_linux(pcms
, fw_cfg
);
1315 for (i
= 0; i
< nb_option_roms
; i
++) {
1316 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1317 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1318 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1319 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1321 pcms
->fw_cfg
= fw_cfg
;
1324 void pc_memory_init(PCMachineState
*pcms
,
1325 MemoryRegion
*system_memory
,
1326 MemoryRegion
*rom_memory
,
1327 MemoryRegion
**ram_memory
)
1330 MemoryRegion
*ram
, *option_rom_mr
;
1331 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1333 MachineState
*machine
= MACHINE(pcms
);
1334 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1336 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1337 pcms
->above_4g_mem_size
);
1339 linux_boot
= (machine
->kernel_filename
!= NULL
);
1341 /* Allocate RAM. We allocate it as a single memory region and use
1342 * aliases to address portions of it, mostly for backwards compatibility
1343 * with older qemus that used qemu_ram_alloc().
1345 ram
= g_malloc(sizeof(*ram
));
1346 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1349 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1350 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1351 0, pcms
->below_4g_mem_size
);
1352 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1353 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1354 if (pcms
->above_4g_mem_size
> 0) {
1355 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1356 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1357 pcms
->below_4g_mem_size
,
1358 pcms
->above_4g_mem_size
);
1359 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1361 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1364 if (!pcmc
->has_reserved_memory
&&
1365 (machine
->ram_slots
||
1366 (machine
->maxram_size
> machine
->ram_size
))) {
1367 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1369 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1374 /* always allocate the device memory information */
1375 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1377 /* initialize device memory address space */
1378 if (pcmc
->has_reserved_memory
&&
1379 (machine
->ram_size
< machine
->maxram_size
)) {
1380 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1382 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1383 error_report("unsupported amount of memory slots: %"PRIu64
,
1384 machine
->ram_slots
);
1388 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1389 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1390 error_report("maximum memory size must by aligned to multiple of "
1391 "%d bytes", TARGET_PAGE_SIZE
);
1395 machine
->device_memory
->base
=
1396 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
1398 if (pcmc
->enforce_aligned_dimm
) {
1399 /* size device region assuming 1G page max alignment per slot */
1400 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
1403 if ((machine
->device_memory
->base
+ device_mem_size
) <
1405 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1406 machine
->maxram_size
);
1410 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1411 "device-memory", device_mem_size
);
1412 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1413 &machine
->device_memory
->mr
);
1416 /* Initialize PC system firmware */
1417 pc_system_firmware_init(rom_memory
, !pcmc
->pci_enabled
);
1419 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1420 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1422 if (pcmc
->pci_enabled
) {
1423 memory_region_set_readonly(option_rom_mr
, true);
1425 memory_region_add_subregion_overlap(rom_memory
,
1430 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1434 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1435 uint64_t *val
= g_malloc(sizeof(*val
));
1436 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1437 uint64_t res_mem_end
= machine
->device_memory
->base
;
1439 if (!pcmc
->broken_reserved_end
) {
1440 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1442 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1443 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1447 load_linux(pcms
, fw_cfg
);
1450 for (i
= 0; i
< nb_option_roms
; i
++) {
1451 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1453 pcms
->fw_cfg
= fw_cfg
;
1455 /* Init default IOAPIC address space */
1456 pcms
->ioapic_as
= &address_space_memory
;
1460 * The 64bit pci hole starts after "above 4G RAM" and
1461 * potentially the space reserved for memory hotplug.
1463 uint64_t pc_pci_hole64_start(void)
1465 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1466 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1467 MachineState
*ms
= MACHINE(pcms
);
1468 uint64_t hole64_start
= 0;
1470 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
1471 hole64_start
= ms
->device_memory
->base
;
1472 if (!pcmc
->broken_reserved_end
) {
1473 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
1476 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1479 return ROUND_UP(hole64_start
, 1 * GiB
);
1482 qemu_irq
pc_allocate_cpu_irq(void)
1484 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1487 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1489 DeviceState
*dev
= NULL
;
1491 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1493 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1494 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1495 } else if (isa_bus
) {
1496 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1497 dev
= isadev
? DEVICE(isadev
) : NULL
;
1499 rom_reset_order_override();
1503 static const MemoryRegionOps ioport80_io_ops
= {
1504 .write
= ioport80_write
,
1505 .read
= ioport80_read
,
1506 .endianness
= DEVICE_NATIVE_ENDIAN
,
1508 .min_access_size
= 1,
1509 .max_access_size
= 1,
1513 static const MemoryRegionOps ioportF0_io_ops
= {
1514 .write
= ioportF0_write
,
1515 .read
= ioportF0_read
,
1516 .endianness
= DEVICE_NATIVE_ENDIAN
,
1518 .min_access_size
= 1,
1519 .max_access_size
= 1,
1523 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
1526 DriveInfo
*fd
[MAX_FD
];
1528 ISADevice
*i8042
, *port92
, *vmmouse
;
1530 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1531 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1533 for (i
= 0; i
< MAX_FD
; i
++) {
1534 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1535 create_fdctrl
|= !!fd
[i
];
1537 if (create_fdctrl
) {
1538 fdctrl_init_isa(isa_bus
, fd
);
1541 i8042
= isa_create_simple(isa_bus
, "i8042");
1543 vmport_init(isa_bus
);
1544 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1549 DeviceState
*dev
= DEVICE(vmmouse
);
1550 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1551 qdev_init_nofail(dev
);
1553 port92
= isa_create_simple(isa_bus
, "port92");
1555 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1556 i8042_setup_a20_line(i8042
, a20_line
[0]);
1557 port92_init(port92
, a20_line
[1]);
1561 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1562 ISADevice
**rtc_state
,
1569 DeviceState
*hpet
= NULL
;
1570 int pit_isa_irq
= 0;
1571 qemu_irq pit_alt_irq
= NULL
;
1572 qemu_irq rtc_irq
= NULL
;
1573 ISADevice
*pit
= NULL
;
1574 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1575 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1577 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1578 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1580 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1581 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1584 * Check if an HPET shall be created.
1586 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1587 * when the HPET wants to take over. Thus we have to disable the latter.
1589 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1590 /* In order to set property, here not using sysbus_try_create_simple */
1591 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1593 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1594 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1597 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1600 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1602 qdev_init_nofail(hpet
);
1603 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1605 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1606 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1609 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1610 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1613 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
1615 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1617 if (!xen_enabled() && has_pit
) {
1618 if (kvm_pit_in_kernel()) {
1619 pit
= kvm_pit_init(isa_bus
, 0x40);
1621 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1624 /* connect PIT to output control line of the HPET */
1625 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1627 pcspk_init(isa_bus
, pit
);
1630 i8257_dma_init(isa_bus
, 0);
1633 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
1636 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1640 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1641 for (i
= 0; i
< nb_nics
; i
++) {
1642 NICInfo
*nd
= &nd_table
[i
];
1643 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
1645 if (g_str_equal(model
, "ne2k_isa")) {
1646 pc_init_ne2k_isa(isa_bus
, nd
);
1648 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1651 rom_reset_order_override();
1654 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1660 if (kvm_ioapic_in_kernel()) {
1661 dev
= qdev_create(NULL
, "kvm-ioapic");
1663 dev
= qdev_create(NULL
, "ioapic");
1666 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1667 "ioapic", OBJECT(dev
), NULL
);
1669 qdev_init_nofail(dev
);
1670 d
= SYS_BUS_DEVICE(dev
);
1671 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1673 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1674 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1678 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
1681 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1682 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1685 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1686 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1687 * addition to cover this case.
1689 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1691 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1695 if (is_nvdimm
&& !pcms
->acpi_nvdimm_state
.is_enabled
) {
1696 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1700 pc_dimm_pre_plug(dev
, MACHINE(hotplug_dev
), errp
);
1703 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
1704 DeviceState
*dev
, Error
**errp
)
1706 HotplugHandlerClass
*hhc
;
1707 Error
*local_err
= NULL
;
1708 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1709 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1710 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
1711 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
1712 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
, &error_abort
);
1713 uint64_t align
= TARGET_PAGE_SIZE
;
1714 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1716 if (pcmc
->enforce_aligned_dimm
) {
1717 align
= memory_region_get_alignment(mr
);
1720 pc_dimm_plug(dev
, MACHINE(pcms
), align
, &local_err
);
1726 nvdimm_plug(&pcms
->acpi_nvdimm_state
);
1729 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1730 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
1732 error_propagate(errp
, local_err
);
1735 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
1736 DeviceState
*dev
, Error
**errp
)
1738 HotplugHandlerClass
*hhc
;
1739 Error
*local_err
= NULL
;
1740 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1743 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1744 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1745 * addition to cover this case.
1747 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1748 error_setg(&local_err
,
1749 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1753 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
1754 error_setg(&local_err
,
1755 "nvdimm device hot unplug is not supported yet.");
1759 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1760 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1763 error_propagate(errp
, local_err
);
1766 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
1767 DeviceState
*dev
, Error
**errp
)
1769 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1770 HotplugHandlerClass
*hhc
;
1771 Error
*local_err
= NULL
;
1773 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1774 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1780 pc_dimm_unplug(dev
, MACHINE(pcms
));
1781 object_unparent(OBJECT(dev
));
1784 error_propagate(errp
, local_err
);
1787 static int pc_apic_cmp(const void *a
, const void *b
)
1789 CPUArchId
*apic_a
= (CPUArchId
*)a
;
1790 CPUArchId
*apic_b
= (CPUArchId
*)b
;
1792 return apic_a
->arch_id
- apic_b
->arch_id
;
1795 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1796 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1797 * entry corresponding to CPU's apic_id returns NULL.
1799 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
1801 CPUArchId apic_id
, *found_cpu
;
1803 apic_id
.arch_id
= id
;
1804 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
1805 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
1807 if (found_cpu
&& idx
) {
1808 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
1813 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
1814 DeviceState
*dev
, Error
**errp
)
1816 CPUArchId
*found_cpu
;
1817 HotplugHandlerClass
*hhc
;
1818 Error
*local_err
= NULL
;
1819 X86CPU
*cpu
= X86_CPU(dev
);
1820 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1822 if (pcms
->acpi_dev
) {
1823 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1824 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1830 /* increment the number of CPUs */
1833 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1836 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1839 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1840 found_cpu
->cpu
= OBJECT(dev
);
1842 error_propagate(errp
, local_err
);
1844 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
1845 DeviceState
*dev
, Error
**errp
)
1848 HotplugHandlerClass
*hhc
;
1849 Error
*local_err
= NULL
;
1850 X86CPU
*cpu
= X86_CPU(dev
);
1851 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1853 if (!pcms
->acpi_dev
) {
1854 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
1858 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1861 error_setg(&local_err
, "Boot CPU is unpluggable");
1865 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1866 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1873 error_propagate(errp
, local_err
);
1877 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
1878 DeviceState
*dev
, Error
**errp
)
1880 CPUArchId
*found_cpu
;
1881 HotplugHandlerClass
*hhc
;
1882 Error
*local_err
= NULL
;
1883 X86CPU
*cpu
= X86_CPU(dev
);
1884 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1886 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1887 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1893 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1894 found_cpu
->cpu
= NULL
;
1895 object_unparent(OBJECT(dev
));
1897 /* decrement the number of CPUs */
1899 /* Update the number of CPUs in CMOS */
1900 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1901 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1903 error_propagate(errp
, local_err
);
1906 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
1907 DeviceState
*dev
, Error
**errp
)
1911 CPUArchId
*cpu_slot
;
1912 X86CPUTopoInfo topo
;
1913 X86CPU
*cpu
= X86_CPU(dev
);
1914 MachineState
*ms
= MACHINE(hotplug_dev
);
1915 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1917 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
1918 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
1923 /* if APIC ID is not set, set it based on socket/core/thread properties */
1924 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
1925 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
1927 if (cpu
->socket_id
< 0) {
1928 error_setg(errp
, "CPU socket-id is not set");
1930 } else if (cpu
->socket_id
> max_socket
) {
1931 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
1932 cpu
->socket_id
, max_socket
);
1935 if (cpu
->core_id
< 0) {
1936 error_setg(errp
, "CPU core-id is not set");
1938 } else if (cpu
->core_id
> (smp_cores
- 1)) {
1939 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
1940 cpu
->core_id
, smp_cores
- 1);
1943 if (cpu
->thread_id
< 0) {
1944 error_setg(errp
, "CPU thread-id is not set");
1946 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
1947 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
1948 cpu
->thread_id
, smp_threads
- 1);
1952 topo
.pkg_id
= cpu
->socket_id
;
1953 topo
.core_id
= cpu
->core_id
;
1954 topo
.smt_id
= cpu
->thread_id
;
1955 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
1958 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1960 MachineState
*ms
= MACHINE(pcms
);
1962 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
1963 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1964 " APIC ID %" PRIu32
", valid index range 0:%d",
1965 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
1966 ms
->possible_cpus
->len
- 1);
1970 if (cpu_slot
->cpu
) {
1971 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
1976 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1977 * so that machine_query_hotpluggable_cpus would show correct values
1979 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1980 * once -smp refactoring is complete and there will be CPU private
1981 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1982 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
1983 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
1984 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
1985 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
1988 cpu
->socket_id
= topo
.pkg_id
;
1990 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
1991 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
1992 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
1995 cpu
->core_id
= topo
.core_id
;
1997 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
1998 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
1999 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2002 cpu
->thread_id
= topo
.smt_id
;
2004 if (cpu
->hyperv_vpindex
&& !kvm_hv_vpindex_settable()) {
2005 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2010 cs
->cpu_index
= idx
;
2012 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2015 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2016 DeviceState
*dev
, Error
**errp
)
2018 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2019 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2020 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2021 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2025 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2026 DeviceState
*dev
, Error
**errp
)
2028 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2029 pc_memory_plug(hotplug_dev
, dev
, errp
);
2030 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2031 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2035 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2036 DeviceState
*dev
, Error
**errp
)
2038 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2039 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2040 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2041 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2043 error_setg(errp
, "acpi: device unplug request for not supported device"
2044 " type: %s", object_get_typename(OBJECT(dev
)));
2048 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2049 DeviceState
*dev
, Error
**errp
)
2051 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2052 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2053 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2054 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2056 error_setg(errp
, "acpi: device unplug for not supported device"
2057 " type: %s", object_get_typename(OBJECT(dev
)));
2061 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
2064 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2065 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2066 return HOTPLUG_HANDLER(machine
);
2073 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2074 const char *name
, void *opaque
,
2077 MachineState
*ms
= MACHINE(obj
);
2078 int64_t value
= memory_region_size(&ms
->device_memory
->mr
);
2080 visit_type_int(v
, name
, &value
, errp
);
2083 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2084 const char *name
, void *opaque
,
2087 PCMachineState
*pcms
= PC_MACHINE(obj
);
2088 uint64_t value
= pcms
->max_ram_below_4g
;
2090 visit_type_size(v
, name
, &value
, errp
);
2093 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2094 const char *name
, void *opaque
,
2097 PCMachineState
*pcms
= PC_MACHINE(obj
);
2098 Error
*error
= NULL
;
2101 visit_type_size(v
, name
, &value
, &error
);
2103 error_propagate(errp
, error
);
2106 if (value
> 4 * GiB
) {
2108 "Machine option 'max-ram-below-4g=%"PRIu64
2109 "' expects size less than or equal to 4G", value
);
2110 error_propagate(errp
, error
);
2114 if (value
< 1 * MiB
) {
2115 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2116 "BIOS may not work with less than 1MiB", value
);
2119 pcms
->max_ram_below_4g
= value
;
2122 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2123 void *opaque
, Error
**errp
)
2125 PCMachineState
*pcms
= PC_MACHINE(obj
);
2126 OnOffAuto vmport
= pcms
->vmport
;
2128 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2131 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2132 void *opaque
, Error
**errp
)
2134 PCMachineState
*pcms
= PC_MACHINE(obj
);
2136 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2139 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2141 bool smm_available
= false;
2143 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2147 if (tcg_enabled() || qtest_enabled()) {
2148 smm_available
= true;
2149 } else if (kvm_enabled()) {
2150 smm_available
= kvm_has_smm();
2153 if (smm_available
) {
2157 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2158 error_report("System Management Mode not supported by this hypervisor.");
2164 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2165 void *opaque
, Error
**errp
)
2167 PCMachineState
*pcms
= PC_MACHINE(obj
);
2168 OnOffAuto smm
= pcms
->smm
;
2170 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2173 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2174 void *opaque
, Error
**errp
)
2176 PCMachineState
*pcms
= PC_MACHINE(obj
);
2178 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2181 static bool pc_machine_get_nvdimm(Object
*obj
, Error
**errp
)
2183 PCMachineState
*pcms
= PC_MACHINE(obj
);
2185 return pcms
->acpi_nvdimm_state
.is_enabled
;
2188 static void pc_machine_set_nvdimm(Object
*obj
, bool value
, Error
**errp
)
2190 PCMachineState
*pcms
= PC_MACHINE(obj
);
2192 pcms
->acpi_nvdimm_state
.is_enabled
= value
;
2195 static char *pc_machine_get_nvdimm_persistence(Object
*obj
, Error
**errp
)
2197 PCMachineState
*pcms
= PC_MACHINE(obj
);
2199 return g_strdup(pcms
->acpi_nvdimm_state
.persistence_string
);
2202 static void pc_machine_set_nvdimm_persistence(Object
*obj
, const char *value
,
2205 PCMachineState
*pcms
= PC_MACHINE(obj
);
2206 AcpiNVDIMMState
*nvdimm_state
= &pcms
->acpi_nvdimm_state
;
2208 if (strcmp(value
, "cpu") == 0)
2209 nvdimm_state
->persistence
= 3;
2210 else if (strcmp(value
, "mem-ctrl") == 0)
2211 nvdimm_state
->persistence
= 2;
2213 error_report("-machine nvdimm-persistence=%s: unsupported option", value
);
2217 g_free(nvdimm_state
->persistence_string
);
2218 nvdimm_state
->persistence_string
= g_strdup(value
);
2221 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2223 PCMachineState
*pcms
= PC_MACHINE(obj
);
2228 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2230 PCMachineState
*pcms
= PC_MACHINE(obj
);
2232 pcms
->smbus
= value
;
2235 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2237 PCMachineState
*pcms
= PC_MACHINE(obj
);
2242 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2244 PCMachineState
*pcms
= PC_MACHINE(obj
);
2249 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2251 PCMachineState
*pcms
= PC_MACHINE(obj
);
2256 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2258 PCMachineState
*pcms
= PC_MACHINE(obj
);
2263 static void pc_machine_initfn(Object
*obj
)
2265 PCMachineState
*pcms
= PC_MACHINE(obj
);
2267 pcms
->max_ram_below_4g
= 0; /* use default */
2268 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2269 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2270 /* nvdimm is disabled on default. */
2271 pcms
->acpi_nvdimm_state
.is_enabled
= false;
2272 /* acpi build is enabled by default if machine supports it */
2273 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2279 static void pc_machine_reset(void)
2284 qemu_devices_reset();
2286 /* Reset APIC after devices have been reset to cancel
2287 * any changes that qemu_devices_reset() might have done.
2292 if (cpu
->apic_state
) {
2293 device_reset(cpu
->apic_state
);
2298 static CpuInstanceProperties
2299 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2301 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2302 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2304 assert(cpu_index
< possible_cpus
->len
);
2305 return possible_cpus
->cpus
[cpu_index
].props
;
2308 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2310 X86CPUTopoInfo topo
;
2312 assert(idx
< ms
->possible_cpus
->len
);
2313 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2314 smp_cores
, smp_threads
, &topo
);
2315 return topo
.pkg_id
% nb_numa_nodes
;
2318 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2322 if (ms
->possible_cpus
) {
2324 * make sure that max_cpus hasn't changed since the first use, i.e.
2325 * -smp hasn't been parsed after it
2327 assert(ms
->possible_cpus
->len
== max_cpus
);
2328 return ms
->possible_cpus
;
2331 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2332 sizeof(CPUArchId
) * max_cpus
);
2333 ms
->possible_cpus
->len
= max_cpus
;
2334 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2335 X86CPUTopoInfo topo
;
2337 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2338 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2339 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
2340 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2341 smp_cores
, smp_threads
, &topo
);
2342 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2343 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2344 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2345 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2346 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2347 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2349 return ms
->possible_cpus
;
2352 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2354 /* cpu index isn't used */
2358 X86CPU
*cpu
= X86_CPU(cs
);
2360 if (!cpu
->apic_state
) {
2361 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2363 apic_deliver_nmi(cpu
->apic_state
);
2368 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2370 MachineClass
*mc
= MACHINE_CLASS(oc
);
2371 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2372 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2373 NMIClass
*nc
= NMI_CLASS(oc
);
2375 pcmc
->pci_enabled
= true;
2376 pcmc
->has_acpi_build
= true;
2377 pcmc
->rsdp_in_ram
= true;
2378 pcmc
->smbios_defaults
= true;
2379 pcmc
->smbios_uuid_encoded
= true;
2380 pcmc
->gigabyte_align
= true;
2381 pcmc
->has_reserved_memory
= true;
2382 pcmc
->kvmclock_enabled
= true;
2383 pcmc
->enforce_aligned_dimm
= true;
2384 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2385 * to be used at the moment, 32K should be enough for a while. */
2386 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2387 pcmc
->save_tsc_khz
= true;
2388 pcmc
->linuxboot_dma_enabled
= true;
2389 assert(!mc
->get_hotplug_handler
);
2390 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
2391 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2392 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2393 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2394 mc
->auto_enable_numa_with_memhp
= true;
2395 mc
->has_hotpluggable_cpus
= true;
2396 mc
->default_boot_order
= "cad";
2397 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2398 mc
->block_default_type
= IF_IDE
;
2400 mc
->reset
= pc_machine_reset
;
2401 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2402 hc
->plug
= pc_machine_device_plug_cb
;
2403 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2404 hc
->unplug
= pc_machine_device_unplug_cb
;
2405 nc
->nmi_monitor_handler
= x86_nmi
;
2406 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2408 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
2409 pc_machine_get_device_memory_region_size
, NULL
,
2410 NULL
, NULL
, &error_abort
);
2412 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2413 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2414 NULL
, NULL
, &error_abort
);
2416 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2417 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2419 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2420 pc_machine_get_smm
, pc_machine_set_smm
,
2421 NULL
, NULL
, &error_abort
);
2422 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2423 "Enable SMM (pc & q35)", &error_abort
);
2425 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2426 pc_machine_get_vmport
, pc_machine_set_vmport
,
2427 NULL
, NULL
, &error_abort
);
2428 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2429 "Enable vmport (pc & q35)", &error_abort
);
2431 object_class_property_add_bool(oc
, PC_MACHINE_NVDIMM
,
2432 pc_machine_get_nvdimm
, pc_machine_set_nvdimm
, &error_abort
);
2434 object_class_property_add_str(oc
, PC_MACHINE_NVDIMM_PERSIST
,
2435 pc_machine_get_nvdimm_persistence
,
2436 pc_machine_set_nvdimm_persistence
, &error_abort
);
2438 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2439 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2441 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2442 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2444 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2445 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2448 static const TypeInfo pc_machine_info
= {
2449 .name
= TYPE_PC_MACHINE
,
2450 .parent
= TYPE_MACHINE
,
2452 .instance_size
= sizeof(PCMachineState
),
2453 .instance_init
= pc_machine_initfn
,
2454 .class_size
= sizeof(PCMachineClass
),
2455 .class_init
= pc_machine_class_init
,
2456 .interfaces
= (InterfaceInfo
[]) {
2457 { TYPE_HOTPLUG_HANDLER
},
2463 static void pc_machine_register_types(void)
2465 type_register_static(&pc_machine_info
);
2468 type_init(pc_machine_register_types
)