target/mips/translate.h

   1 /*
   2  *  MIPS translation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * SPDX-License-Identifier: LGPL-2.1-or-later
   7  */
   8 #ifndef TARGET_MIPS_TRANSLATE_H
   9 #define TARGET_MIPS_TRANSLATE_H
  10
  11 #include "exec/translator.h"
  12
  13 #define MIPS_DEBUG_DISAS 0
  14
  15 typedef struct DisasContext {
  16     DisasContextBase base;
  17     target_ulong saved_pc;
  18     target_ulong page_start;
  19     uint32_t opcode;
  20     uint64_t insn_flags;
  21     int32_t CP0_Config1;
  22     int32_t CP0_Config2;
  23     int32_t CP0_Config3;
  24     int32_t CP0_Config5;
  25     /* Routine used to access memory */
  26     int mem_idx;
  27     MemOp default_tcg_memop_mask;
  28     uint32_t hflags, saved_hflags;
  29     target_ulong btarget;
  30     bool ulri;
  31     int kscrexist;
  32     bool rxi;
  33     int ie;
  34     bool bi;
  35     bool bp;
  36     uint64_t PAMask;
  37     bool mvh;
  38     bool eva;
  39     bool sc;
  40     int CP0_LLAddr_shift;
  41     bool ps;
  42     bool vp;
  43     bool cmgcr;
  44     bool mrp;
  45     bool nan2008;
  46     bool abs2008;
  47     bool saar;
  48     bool mi;
  49     int gi;
  50 } DisasContext;
  51
  52 /* MIPS major opcodes */
  53 #define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
  54
  55 #define OPC_CP1 (0x11 << 26)
  56
  57 /* Coprocessor 1 (rs field) */
  58 #define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
  59
  60 /* Values for the fmt field in FP instructions */
  61 enum {
  62     /* 0 - 15 are reserved */
  63     FMT_S = 16,          /* single fp */
  64     FMT_D = 17,          /* double fp */
  65     FMT_E = 18,          /* extended fp */
  66     FMT_Q = 19,          /* quad fp */
  67     FMT_W = 20,          /* 32-bit fixed */
  68     FMT_L = 21,          /* 64-bit fixed */
  69     FMT_PS = 22,         /* paired single fp */
  70     /* 23 - 31 are reserved */
  71 };
  72
  73 enum {
  74     OPC_MFC1     = (0x00 << 21) | OPC_CP1,
  75     OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
  76     OPC_CFC1     = (0x02 << 21) | OPC_CP1,
  77     OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
  78     OPC_MTC1     = (0x04 << 21) | OPC_CP1,
  79     OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
  80     OPC_CTC1     = (0x06 << 21) | OPC_CP1,
  81     OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
  82     OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
  83     OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
  84     OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
  85     OPC_BZ_V     = (0x0B << 21) | OPC_CP1,
  86     OPC_BNZ_V    = (0x0F << 21) | OPC_CP1,
  87     OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
  88     OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
  89     OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
  90     OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
  91     OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
  92     OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
  93     OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
  94     OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
  95     OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
  96     OPC_BZ_B     = (0x18 << 21) | OPC_CP1,
  97     OPC_BZ_H     = (0x19 << 21) | OPC_CP1,
  98     OPC_BZ_W     = (0x1A << 21) | OPC_CP1,
  99     OPC_BZ_D     = (0x1B << 21) | OPC_CP1,
 100     OPC_BNZ_B    = (0x1C << 21) | OPC_CP1,
 101     OPC_BNZ_H    = (0x1D << 21) | OPC_CP1,
 102     OPC_BNZ_W    = (0x1E << 21) | OPC_CP1,
 103     OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,
 104 };
 105
 106 #define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
 107 #define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
 108
 109 enum {
 110     OPC_BC1F     = (0x00 << 16) | OPC_BC1,
 111     OPC_BC1T     = (0x01 << 16) | OPC_BC1,
 112     OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
 113     OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
 114 };
 115
 116 enum {
 117     OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
 118     OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
 119 };
 120
 121 enum {
 122     OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
 123     OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
 124 };
 125
 126 void generate_exception(DisasContext *ctx, int excp);
 127 void generate_exception_err(DisasContext *ctx, int excp, int err);
 128 void generate_exception_end(DisasContext *ctx, int excp);
 129 void gen_reserved_instruction(DisasContext *ctx);
 130
 131 void check_insn(DisasContext *ctx, uint64_t flags);
 132 #ifdef TARGET_MIPS64
 133 void check_mips_64(DisasContext *ctx);
 134 #endif
 135 void check_cp0_enabled(DisasContext *ctx);
 136 void check_cp1_enabled(DisasContext *ctx);
 137 void check_cp1_64bitmode(DisasContext *ctx);
 138 void check_cp1_registers(DisasContext *ctx, int regs);
 139 void check_cop1x(DisasContext *ctx);
 140
 141 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
 142 void gen_move_low32(TCGv ret, TCGv_i64 arg);
 143 void gen_move_high32(TCGv ret, TCGv_i64 arg);
 144 void gen_load_gpr(TCGv t, int reg);
 145 void gen_store_gpr(TCGv t, int reg);
 146 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 147 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 148 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 149 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 150 int get_fp_bit(int cc);
 151
 152 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
 153
 154 extern TCGv cpu_gpr[32], cpu_PC;
 155 extern TCGv_i32 fpu_fcr0, fpu_fcr31;
 156 extern TCGv_i64 fpu_f64[32];
 157 extern TCGv bcond;
 158
 159 #define LOG_DISAS(...)                                                        \
 160     do {                                                                      \
 161         if (MIPS_DEBUG_DISAS) {                                               \
 162             qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
 163         }                                                                     \
 164     } while (0)
 165
 166 #define MIPS_INVAL(op)                                                        \
 167     do {                                                                      \
 168         if (MIPS_DEBUG_DISAS) {                                               \
 169             qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
 170                           TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
 171                           ctx->base.pc_next, ctx->opcode, op,                 \
 172                           ctx->opcode >> 26, ctx->opcode & 0x3F,              \
 173                           ((ctx->opcode >> 16) & 0x1F));                      \
 174         }                                                                     \
 175     } while (0)
 176
 177 #endif