target/sh4: use cpu_loop_exit_restore
[qemu/ar7.git] / qom / cpu.c
blobf02e9c0fae1af0a4384241cf2488b2bdc0717b86
1 /*
2 * QEMU CPU model
4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "qom/cpu.h"
25 #include "sysemu/hw_accel.h"
26 #include "qemu/notify.h"
27 #include "qemu/log.h"
28 #include "exec/log.h"
29 #include "qemu/error-report.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/qdev-properties.h"
32 #include "trace-root.h"
34 bool cpu_exists(int64_t id)
36 CPUState *cpu;
38 CPU_FOREACH(cpu) {
39 CPUClass *cc = CPU_GET_CLASS(cpu);
41 if (cc->get_arch_id(cpu) == id) {
42 return true;
45 return false;
48 CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
50 char *str, *name, *featurestr;
51 CPUState *cpu = NULL;
52 ObjectClass *oc;
53 CPUClass *cc;
54 Error *err = NULL;
56 str = g_strdup(cpu_model);
57 name = strtok(str, ",");
59 oc = cpu_class_by_name(typename, name);
60 if (oc == NULL) {
61 g_free(str);
62 return NULL;
65 cc = CPU_CLASS(oc);
66 featurestr = strtok(NULL, ",");
67 /* TODO: all callers of cpu_generic_init() need to be converted to
68 * call parse_features() only once, before calling cpu_generic_init().
70 cc->parse_features(object_class_get_name(oc), featurestr, &err);
71 g_free(str);
72 if (err != NULL) {
73 goto out;
76 cpu = CPU(object_new(object_class_get_name(oc)));
77 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
79 out:
80 if (err != NULL) {
81 error_report_err(err);
82 object_unref(OBJECT(cpu));
83 return NULL;
86 return cpu;
89 bool cpu_paging_enabled(const CPUState *cpu)
91 CPUClass *cc = CPU_GET_CLASS(cpu);
93 return cc->get_paging_enabled(cpu);
96 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
98 return false;
101 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
102 Error **errp)
104 CPUClass *cc = CPU_GET_CLASS(cpu);
106 cc->get_memory_mapping(cpu, list, errp);
109 static void cpu_common_get_memory_mapping(CPUState *cpu,
110 MemoryMappingList *list,
111 Error **errp)
113 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
116 /* Resetting the IRQ comes from across the code base so we take the
117 * BQL here if we need to. cpu_interrupt assumes it is held.*/
118 void cpu_reset_interrupt(CPUState *cpu, int mask)
120 bool need_lock = !qemu_mutex_iothread_locked();
122 if (need_lock) {
123 qemu_mutex_lock_iothread();
125 cpu->interrupt_request &= ~mask;
126 if (need_lock) {
127 qemu_mutex_unlock_iothread();
131 void cpu_exit(CPUState *cpu)
133 atomic_set(&cpu->exit_request, 1);
134 /* Ensure cpu_exec will see the exit request after TCG has exited. */
135 smp_wmb();
136 atomic_set(&cpu->icount_decr.u16.high, -1);
139 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
140 void *opaque)
142 CPUClass *cc = CPU_GET_CLASS(cpu);
144 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
147 static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
148 CPUState *cpu, void *opaque)
150 return 0;
153 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
154 int cpuid, void *opaque)
156 CPUClass *cc = CPU_GET_CLASS(cpu);
158 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
161 static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
162 CPUState *cpu, int cpuid,
163 void *opaque)
165 return -1;
168 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
169 void *opaque)
171 CPUClass *cc = CPU_GET_CLASS(cpu);
173 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
176 static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
177 CPUState *cpu, void *opaque)
179 return 0;
182 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
183 int cpuid, void *opaque)
185 CPUClass *cc = CPU_GET_CLASS(cpu);
187 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
190 static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
191 CPUState *cpu, int cpuid,
192 void *opaque)
194 return -1;
198 static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
200 return 0;
203 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
205 return 0;
208 static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
210 /* If no extra check is required, QEMU watchpoint match can be considered
211 * as an architectural match.
213 return true;
216 bool target_words_bigendian(void);
217 static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
219 return target_words_bigendian();
222 static void cpu_common_noop(CPUState *cpu)
226 static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
228 return false;
231 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
233 CPUClass *cc = CPU_GET_CLASS(cpu);
234 GuestPanicInformation *res = NULL;
236 if (cc->get_crash_info) {
237 res = cc->get_crash_info(cpu);
239 return res;
242 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
243 int flags)
245 CPUClass *cc = CPU_GET_CLASS(cpu);
247 if (cc->dump_state) {
248 cpu_synchronize_state(cpu);
249 cc->dump_state(cpu, f, cpu_fprintf, flags);
253 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
254 int flags)
256 CPUClass *cc = CPU_GET_CLASS(cpu);
258 if (cc->dump_statistics) {
259 cc->dump_statistics(cpu, f, cpu_fprintf, flags);
263 void cpu_reset(CPUState *cpu)
265 CPUClass *klass = CPU_GET_CLASS(cpu);
267 if (klass->reset != NULL) {
268 (*klass->reset)(cpu);
271 trace_guest_cpu_reset(cpu);
274 static void cpu_common_reset(CPUState *cpu)
276 CPUClass *cc = CPU_GET_CLASS(cpu);
277 int i;
279 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
280 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
281 log_cpu_state(cpu, cc->reset_dump_flags);
284 cpu->interrupt_request = 0;
285 cpu->halted = 0;
286 cpu->mem_io_pc = 0;
287 cpu->mem_io_vaddr = 0;
288 cpu->icount_extra = 0;
289 cpu->icount_decr.u32 = 0;
290 cpu->can_do_io = 1;
291 cpu->exception_index = -1;
292 cpu->crash_occurred = false;
294 if (tcg_enabled()) {
295 for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {
296 atomic_set(&cpu->tb_jmp_cache[i], NULL);
299 #ifdef CONFIG_SOFTMMU
300 tlb_flush(cpu, 0);
301 #endif
305 static bool cpu_common_has_work(CPUState *cs)
307 return false;
310 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
312 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
314 return cc->class_by_name(cpu_model);
317 static ObjectClass *cpu_common_class_by_name(const char *cpu_model)
319 return NULL;
322 static void cpu_common_parse_features(const char *typename, char *features,
323 Error **errp)
325 char *featurestr; /* Single "key=value" string being parsed */
326 char *val;
327 static bool cpu_globals_initialized;
329 /* TODO: all callers of ->parse_features() need to be changed to
330 * call it only once, so we can remove this check (or change it
331 * to assert(!cpu_globals_initialized).
332 * Current callers of ->parse_features() are:
333 * - cpu_generic_init()
335 if (cpu_globals_initialized) {
336 return;
338 cpu_globals_initialized = true;
340 featurestr = features ? strtok(features, ",") : NULL;
342 while (featurestr) {
343 val = strchr(featurestr, '=');
344 if (val) {
345 GlobalProperty *prop = g_new0(typeof(*prop), 1);
346 *val = 0;
347 val++;
348 prop->driver = typename;
349 prop->property = g_strdup(featurestr);
350 prop->value = g_strdup(val);
351 prop->errp = &error_fatal;
352 qdev_prop_register_global(prop);
353 } else {
354 error_setg(errp, "Expected key=value format, found %s.",
355 featurestr);
356 return;
358 featurestr = strtok(NULL, ",");
362 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
364 CPUState *cpu = CPU(dev);
366 if (dev->hotplugged) {
367 cpu_synchronize_post_init(cpu);
368 cpu_resume(cpu);
371 /* NOTE: latest generic point where the cpu is fully realized */
372 trace_init_vcpu(cpu);
375 static void cpu_common_unrealizefn(DeviceState *dev, Error **errp)
377 CPUState *cpu = CPU(dev);
378 /* NOTE: latest generic point before the cpu is fully unrealized */
379 trace_fini_vcpu(cpu);
380 cpu_exec_unrealizefn(cpu);
383 static void cpu_common_initfn(Object *obj)
385 CPUState *cpu = CPU(obj);
386 CPUClass *cc = CPU_GET_CLASS(obj);
388 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
389 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
390 /* *-user doesn't have configurable SMP topology */
391 /* the default value is changed by qemu_init_vcpu() for softmmu */
392 cpu->nr_cores = 1;
393 cpu->nr_threads = 1;
395 qemu_mutex_init(&cpu->work_mutex);
396 QTAILQ_INIT(&cpu->breakpoints);
397 QTAILQ_INIT(&cpu->watchpoints);
399 cpu->trace_dstate = bitmap_new(trace_get_vcpu_event_count());
401 cpu_exec_initfn(cpu);
404 static void cpu_common_finalize(Object *obj)
406 CPUState *cpu = CPU(obj);
407 g_free(cpu->trace_dstate);
410 static int64_t cpu_common_get_arch_id(CPUState *cpu)
412 return cpu->cpu_index;
415 static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
417 return addr;
420 static void cpu_class_init(ObjectClass *klass, void *data)
422 DeviceClass *dc = DEVICE_CLASS(klass);
423 CPUClass *k = CPU_CLASS(klass);
425 k->class_by_name = cpu_common_class_by_name;
426 k->parse_features = cpu_common_parse_features;
427 k->reset = cpu_common_reset;
428 k->get_arch_id = cpu_common_get_arch_id;
429 k->has_work = cpu_common_has_work;
430 k->get_paging_enabled = cpu_common_get_paging_enabled;
431 k->get_memory_mapping = cpu_common_get_memory_mapping;
432 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
433 k->write_elf32_note = cpu_common_write_elf32_note;
434 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
435 k->write_elf64_note = cpu_common_write_elf64_note;
436 k->gdb_read_register = cpu_common_gdb_read_register;
437 k->gdb_write_register = cpu_common_gdb_write_register;
438 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
439 k->debug_excp_handler = cpu_common_noop;
440 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
441 k->cpu_exec_enter = cpu_common_noop;
442 k->cpu_exec_exit = cpu_common_noop;
443 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
444 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
445 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
446 dc->realize = cpu_common_realizefn;
447 dc->unrealize = cpu_common_unrealizefn;
449 * Reason: CPUs still need special care by board code: wiring up
450 * IRQs, adding reset handlers, halting non-first CPUs, ...
452 dc->cannot_instantiate_with_device_add_yet = true;
455 static const TypeInfo cpu_type_info = {
456 .name = TYPE_CPU,
457 .parent = TYPE_DEVICE,
458 .instance_size = sizeof(CPUState),
459 .instance_init = cpu_common_initfn,
460 .instance_finalize = cpu_common_finalize,
461 .abstract = true,
462 .class_size = sizeof(CPUClass),
463 .class_init = cpu_class_init,
466 static void cpu_register_types(void)
468 type_register_static(&cpu_type_info);
471 type_init(cpu_register_types)