hw/net/pcnet-pci.c

   1 /*
   2  * QEMU AMD PC-Net II (Am79C970A) PCI emulation
   3  *
   4  * Copyright (c) 2004 Antony T Curtis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* This software was written to be compatible with the specification:
  26  * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  27  * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "hw/pci/pci.h"
  32 #include "net/net.h"
  33 #include "qemu/module.h"
  34 #include "qemu/timer.h"
  35 #include "sysemu/dma.h"
  36 #include "sysemu/sysemu.h"
  37 #include "trace.h"
  38
  39 #include "pcnet.h"
  40
  41 //#define PCNET_DEBUG
  42 //#define PCNET_DEBUG_IO
  43 //#define PCNET_DEBUG_BCR
  44 //#define PCNET_DEBUG_CSR
  45 //#define PCNET_DEBUG_RMD
  46 //#define PCNET_DEBUG_TMD
  47 //#define PCNET_DEBUG_MATCH
  48
  49 #define TYPE_PCI_PCNET "pcnet"
  50
  51 #define PCI_PCNET(obj) \
  52      OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
  53
  54 typedef struct {
  55     /*< private >*/
  56     PCIDevice parent_obj;
  57     /*< public >*/
  58
  59     PCNetState state;
  60     MemoryRegion io_bar;
  61 } PCIPCNetState;
  62
  63 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
  64 {
  65     PCNetState *s = opaque;
  66
  67     trace_pcnet_aprom_writeb(opaque, addr, val);
  68     if (BCR_APROMWE(s)) {
  69         s->prom[addr & 15] = val;
  70     }
  71 }
  72
  73 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
  74 {
  75     PCNetState *s = opaque;
  76     uint32_t val = s->prom[addr & 15];
  77
  78     trace_pcnet_aprom_readb(opaque, addr, val);
  79     return val;
  80 }
  81
  82 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
  83                                   unsigned size)
  84 {
  85     PCNetState *d = opaque;
  86
  87     trace_pcnet_ioport_read(opaque, addr, size);
  88     if (addr < 0x10) {
  89         if (!BCR_DWIO(d) && size == 1) {
  90             return pcnet_aprom_readb(d, addr);
  91         } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
  92             return pcnet_aprom_readb(d, addr) |
  93                    (pcnet_aprom_readb(d, addr + 1) << 8);
  94         } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
  95             return pcnet_aprom_readb(d, addr) |
  96                    (pcnet_aprom_readb(d, addr + 1) << 8) |
  97                    (pcnet_aprom_readb(d, addr + 2) << 16) |
  98                    (pcnet_aprom_readb(d, addr + 3) << 24);
  99         }
 100     } else {
 101         if (size == 2) {
 102             return pcnet_ioport_readw(d, addr);
 103         } else if (size == 4) {
 104             return pcnet_ioport_readl(d, addr);
 105         }
 106     }
 107     return ((uint64_t)1 << (size * 8)) - 1;
 108 }
 109
 110 static void pcnet_ioport_write(void *opaque, hwaddr addr,
 111                                uint64_t data, unsigned size)
 112 {
 113     PCNetState *d = opaque;
 114
 115     trace_pcnet_ioport_write(opaque, addr, data, size);
 116     if (addr < 0x10) {
 117         if (!BCR_DWIO(d) && size == 1) {
 118             pcnet_aprom_writeb(d, addr, data);
 119         } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
 120             pcnet_aprom_writeb(d, addr, data & 0xff);
 121             pcnet_aprom_writeb(d, addr + 1, data >> 8);
 122         } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
 123             pcnet_aprom_writeb(d, addr, data & 0xff);
 124             pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
 125             pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
 126             pcnet_aprom_writeb(d, addr + 3, data >> 24);
 127         }
 128     } else {
 129         if (size == 2) {
 130             pcnet_ioport_writew(d, addr, data);
 131         } else if (size == 4) {
 132             pcnet_ioport_writel(d, addr, data);
 133         }
 134     }
 135 }
 136
 137 static const MemoryRegionOps pcnet_io_ops = {
 138     .read = pcnet_ioport_read,
 139     .write = pcnet_ioport_write,
 140     .endianness = DEVICE_LITTLE_ENDIAN,
 141 };
 142
 143 static const VMStateDescription vmstate_pci_pcnet = {
 144     .name = "pcnet",
 145     .version_id = 3,
 146     .minimum_version_id = 2,
 147     .fields = (VMStateField[]) {
 148         VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
 149         VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
 150         VMSTATE_END_OF_LIST()
 151     }
 152 };
 153
 154 /* PCI interface */
 155
 156 static const MemoryRegionOps pcnet_mmio_ops = {
 157     .read = pcnet_ioport_read,
 158     .write = pcnet_ioport_write,
 159     .valid.min_access_size = 1,
 160     .valid.max_access_size = 4,
 161     .impl.min_access_size = 1,
 162     .impl.max_access_size = 4,
 163     .endianness = DEVICE_LITTLE_ENDIAN,
 164 };
 165
 166 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
 167                                       uint8_t *buf, int len, int do_bswap)
 168 {
 169     pci_dma_write(dma_opaque, addr, buf, len);
 170 }
 171
 172 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
 173                                      uint8_t *buf, int len, int do_bswap)
 174 {
 175     pci_dma_read(dma_opaque, addr, buf, len);
 176 }
 177
 178 static void pci_pcnet_uninit(PCIDevice *dev)
 179 {
 180     PCIPCNetState *d = PCI_PCNET(dev);
 181
 182     qemu_free_irq(d->state.irq);
 183     timer_del(d->state.poll_timer);
 184     timer_free(d->state.poll_timer);
 185     qemu_del_nic(d->state.nic);
 186 }
 187
 188 static NetClientInfo net_pci_pcnet_info = {
 189     .type = NET_CLIENT_DRIVER_NIC,
 190     .size = sizeof(NICState),
 191     .receive = pcnet_receive,
 192     .link_status_changed = pcnet_set_link_status,
 193 };
 194
 195 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
 196 {
 197     PCIPCNetState *d = PCI_PCNET(pci_dev);
 198     PCNetState *s = &d->state;
 199     uint8_t *pci_conf;
 200
 201 #if 0
 202     printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
 203         sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
 204 #endif
 205
 206     pci_conf = pci_dev->config;
 207
 208     pci_set_word(pci_conf + PCI_STATUS,
 209                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
 210
 211     pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
 212     pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
 213
 214     pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
 215     pci_conf[PCI_MIN_GNT] = 0x06;
 216     pci_conf[PCI_MAX_LAT] = 0xff;
 217
 218     /* Handler for memory-mapped I/O */
 219     memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
 220                           "pcnet-mmio", PCNET_PNPMMIO_SIZE);
 221
 222     memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
 223                           PCNET_IOPORT_SIZE);
 224     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
 225
 226     pci_register_bar(pci_dev, 1, 0, &s->mmio);
 227
 228     s->irq = pci_allocate_irq(pci_dev);
 229     s->phys_mem_read = pci_physical_memory_read;
 230     s->phys_mem_write = pci_physical_memory_write;
 231     s->dma_opaque = pci_dev;
 232
 233     pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
 234 }
 235
 236 static void pci_reset(DeviceState *dev)
 237 {
 238     PCIPCNetState *d = PCI_PCNET(dev);
 239
 240     pcnet_h_reset(&d->state);
 241 }
 242
 243 static void pcnet_instance_init(Object *obj)
 244 {
 245     PCIPCNetState *d = PCI_PCNET(obj);
 246     PCNetState *s = &d->state;
 247
 248     device_add_bootindex_property(obj, &s->conf.bootindex,
 249                                   "bootindex", "/ethernet-phy@0",
 250                                   DEVICE(obj), NULL);
 251 }
 252
 253 static Property pcnet_properties[] = {
 254     DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
 255     DEFINE_PROP_END_OF_LIST(),
 256 };
 257
 258 static void pcnet_class_init(ObjectClass *klass, void *data)
 259 {
 260     DeviceClass *dc = DEVICE_CLASS(klass);
 261     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 262
 263     k->realize = pci_pcnet_realize;
 264     k->exit = pci_pcnet_uninit;
 265     k->romfile = "efi-pcnet.rom",
 266     k->vendor_id = PCI_VENDOR_ID_AMD;
 267     k->device_id = PCI_DEVICE_ID_AMD_LANCE;
 268     k->revision = 0x10;
 269     k->class_id = PCI_CLASS_NETWORK_ETHERNET;
 270     dc->reset = pci_reset;
 271     dc->vmsd = &vmstate_pci_pcnet;
 272     dc->props = pcnet_properties;
 273     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 274 }
 275
 276 static const TypeInfo pcnet_info = {
 277     .name          = TYPE_PCI_PCNET,
 278     .parent        = TYPE_PCI_DEVICE,
 279     .instance_size = sizeof(PCIPCNetState),
 280     .class_init    = pcnet_class_init,
 281     .instance_init = pcnet_instance_init,
 282     .interfaces = (InterfaceInfo[]) {
 283         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 284         { },
 285     },
 286 };
 287
 288 static void pci_pcnet_register_types(void)
 289 {
 290     type_register_static(&pcnet_info);
 291 }
 292
 293 type_init(pci_pcnet_register_types)