include/exec/cpu_ldst.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2.1 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 /*
  20  * Generate inline load/store functions for all MMU modes (typically
  21  * at least _user and _kernel) as well as _data versions, for all data
  22  * sizes.
  23  *
  24  * Used by target op helpers.
  25  *
  26  * The syntax for the accessors is:
  27  *
  28  * load:  cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
  29  *        cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
  30  *        cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
  31  *
  32  * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
  33  *        cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
  34  *        cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
  35  *
  36  * sign is:
  37  * (empty): for 32 and 64 bit sizes
  38  *   u    : unsigned
  39  *   s    : signed
  40  *
  41  * size is:
  42  *   b: 8 bits
  43  *   w: 16 bits
  44  *   l: 32 bits
  45  *   q: 64 bits
  46  *
  47  * end is:
  48  * (empty): for target native endian, or for 8 bit access
  49  *     _be: for forced big endian
  50  *     _le: for forced little endian
  51  *
  52  * mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
  53  * The "mmuidx" suffix carries an extra mmu_idx argument that specifies
  54  * the index to use; the "data" and "code" suffixes take the index from
  55  * cpu_mmu_index().
  56  */
  57 #ifndef CPU_LDST_H
  58 #define CPU_LDST_H
  59
  60 #if defined(CONFIG_USER_ONLY)
  61 /* sparc32plus has 64bit long but 32bit space address
  62  * this can make bad result with g2h() and h2g()
  63  */
  64 #if TARGET_VIRT_ADDR_SPACE_BITS <= 32
  65 typedef uint32_t abi_ptr;
  66 #define TARGET_ABI_FMT_ptr "%x"
  67 #else
  68 typedef uint64_t abi_ptr;
  69 #define TARGET_ABI_FMT_ptr "%"PRIx64
  70 #endif
  71
  72 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
  73 #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base))
  74
  75 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
  76 #define guest_addr_valid(x) (1)
  77 #else
  78 #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX)
  79 #endif
  80
  81 static inline bool guest_range_valid(abi_ulong start, abi_ulong len)
  82 {
  83     return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1;
  84 }
  85
  86 #define h2g_valid(x) \
  87     (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \
  88      (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX)
  89
  90 #define h2g_nocheck(x) ({ \
  91     uintptr_t __ret = (uintptr_t)(x) - guest_base; \
  92     (abi_ptr)__ret; \
  93 })
  94
  95 #define h2g(x) ({ \
  96     /* Check if given address fits target address space */ \
  97     assert(h2g_valid(x)); \
  98     h2g_nocheck(x); \
  99 })
 100 #else
 101 typedef target_ulong abi_ptr;
 102 #define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
 103 #endif
 104
 105 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
 106 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
 107
 108 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
 109 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
 110 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
 111 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
 112
 113 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
 114 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
 115 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
 116 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
 117
 118 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 119 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 120
 121 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 122 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 123 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 124 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 125
 126 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 127 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 128 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 129 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
 130
 131 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 132
 133 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 134 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 135 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 136
 137 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 138 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
 139 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 140
 141 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
 142                      uint32_t val, uintptr_t ra);
 143
 144 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
 145                         uint32_t val, uintptr_t ra);
 146 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
 147                         uint32_t val, uintptr_t ra);
 148 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
 149                         uint64_t val, uintptr_t ra);
 150
 151 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
 152                         uint32_t val, uintptr_t ra);
 153 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
 154                         uint32_t val, uintptr_t ra);
 155 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
 156                         uint64_t val, uintptr_t ra);
 157
 158 #if defined(CONFIG_USER_ONLY)
 159
 160 extern __thread uintptr_t helper_retaddr;
 161
 162 static inline void set_helper_retaddr(uintptr_t ra)
 163 {
 164     helper_retaddr = ra;
 165     /*
 166      * Ensure that this write is visible to the SIGSEGV handler that
 167      * may be invoked due to a subsequent invalid memory operation.
 168      */
 169     signal_barrier();
 170 }
 171
 172 static inline void clear_helper_retaddr(void)
 173 {
 174     /*
 175      * Ensure that previous memory operations have succeeded before
 176      * removing the data visible to the signal handler.
 177      */
 178     signal_barrier();
 179     helper_retaddr = 0;
 180 }
 181
 182 /*
 183  * Provide the same *_mmuidx_ra interface as for softmmu.
 184  * The mmu_idx argument is ignored.
 185  */
 186
 187 static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 188                                           int mmu_idx, uintptr_t ra)
 189 {
 190     return cpu_ldub_data_ra(env, addr, ra);
 191 }
 192
 193 static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 194                                      int mmu_idx, uintptr_t ra)
 195 {
 196     return cpu_ldsb_data_ra(env, addr, ra);
 197 }
 198
 199 static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 200                                              int mmu_idx, uintptr_t ra)
 201 {
 202     return cpu_lduw_be_data_ra(env, addr, ra);
 203 }
 204
 205 static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 206                                         int mmu_idx, uintptr_t ra)
 207 {
 208     return cpu_ldsw_be_data_ra(env, addr, ra);
 209 }
 210
 211 static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 212                                             int mmu_idx, uintptr_t ra)
 213 {
 214     return cpu_ldl_be_data_ra(env, addr, ra);
 215 }
 216
 217 static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 218                                             int mmu_idx, uintptr_t ra)
 219 {
 220     return cpu_ldq_be_data_ra(env, addr, ra);
 221 }
 222
 223 static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 224                                              int mmu_idx, uintptr_t ra)
 225 {
 226     return cpu_lduw_le_data_ra(env, addr, ra);
 227 }
 228
 229 static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 230                                         int mmu_idx, uintptr_t ra)
 231 {
 232     return cpu_ldsw_le_data_ra(env, addr, ra);
 233 }
 234
 235 static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 236                                             int mmu_idx, uintptr_t ra)
 237 {
 238     return cpu_ldl_le_data_ra(env, addr, ra);
 239 }
 240
 241 static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 242                                             int mmu_idx, uintptr_t ra)
 243 {
 244     return cpu_ldq_le_data_ra(env, addr, ra);
 245 }
 246
 247 static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 248                                      uint32_t val, int mmu_idx, uintptr_t ra)
 249 {
 250     cpu_stb_data_ra(env, addr, val, ra);
 251 }
 252
 253 static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 254                                         uint32_t val, int mmu_idx,
 255                                         uintptr_t ra)
 256 {
 257     cpu_stw_be_data_ra(env, addr, val, ra);
 258 }
 259
 260 static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 261                                         uint32_t val, int mmu_idx,
 262                                         uintptr_t ra)
 263 {
 264     cpu_stl_be_data_ra(env, addr, val, ra);
 265 }
 266
 267 static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 268                                         uint64_t val, int mmu_idx,
 269                                         uintptr_t ra)
 270 {
 271     cpu_stq_be_data_ra(env, addr, val, ra);
 272 }
 273
 274 static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 275                                         uint32_t val, int mmu_idx,
 276                                         uintptr_t ra)
 277 {
 278     cpu_stw_le_data_ra(env, addr, val, ra);
 279 }
 280
 281 static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 282                                         uint32_t val, int mmu_idx,
 283                                         uintptr_t ra)
 284 {
 285     cpu_stl_le_data_ra(env, addr, val, ra);
 286 }
 287
 288 static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 289                                         uint64_t val, int mmu_idx,
 290                                         uintptr_t ra)
 291 {
 292     cpu_stq_le_data_ra(env, addr, val, ra);
 293 }
 294
 295 #else
 296
 297 /* Needed for TCG_OVERSIZED_GUEST */
 298 #include "tcg/tcg.h"
 299
 300 static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
 301 {
 302 #if TCG_OVERSIZED_GUEST
 303     return entry->addr_write;
 304 #else
 305     return qatomic_read(&entry->addr_write);
 306 #endif
 307 }
 308
 309 /* Find the TLB index corresponding to the mmu_idx + address pair.  */
 310 static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
 311                                   target_ulong addr)
 312 {
 313     uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
 314
 315     return (addr >> TARGET_PAGE_BITS) & size_mask;
 316 }
 317
 318 /* Find the TLB entry corresponding to the mmu_idx + address pair.  */
 319 static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
 320                                      target_ulong addr)
 321 {
 322     return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
 323 }
 324
 325 uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 326                             int mmu_idx, uintptr_t ra);
 327 int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 328                        int mmu_idx, uintptr_t ra);
 329
 330 uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 331                                int mmu_idx, uintptr_t ra);
 332 int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 333                           int mmu_idx, uintptr_t ra);
 334 uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 335                               int mmu_idx, uintptr_t ra);
 336 uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 337                               int mmu_idx, uintptr_t ra);
 338
 339 uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 340                                int mmu_idx, uintptr_t ra);
 341 int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 342                           int mmu_idx, uintptr_t ra);
 343 uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 344                               int mmu_idx, uintptr_t ra);
 345 uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 346                               int mmu_idx, uintptr_t ra);
 347
 348 void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 349                        int mmu_idx, uintptr_t retaddr);
 350
 351 void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 352                           int mmu_idx, uintptr_t retaddr);
 353 void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 354                           int mmu_idx, uintptr_t retaddr);
 355 void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 356                           int mmu_idx, uintptr_t retaddr);
 357
 358 void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 359                           int mmu_idx, uintptr_t retaddr);
 360 void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 361                           int mmu_idx, uintptr_t retaddr);
 362 void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 363                           int mmu_idx, uintptr_t retaddr);
 364
 365 #endif /* defined(CONFIG_USER_ONLY) */
 366
 367 #ifdef TARGET_WORDS_BIGENDIAN
 368 # define cpu_lduw_data        cpu_lduw_be_data
 369 # define cpu_ldsw_data        cpu_ldsw_be_data
 370 # define cpu_ldl_data         cpu_ldl_be_data
 371 # define cpu_ldq_data         cpu_ldq_be_data
 372 # define cpu_lduw_data_ra     cpu_lduw_be_data_ra
 373 # define cpu_ldsw_data_ra     cpu_ldsw_be_data_ra
 374 # define cpu_ldl_data_ra      cpu_ldl_be_data_ra
 375 # define cpu_ldq_data_ra      cpu_ldq_be_data_ra
 376 # define cpu_lduw_mmuidx_ra   cpu_lduw_be_mmuidx_ra
 377 # define cpu_ldsw_mmuidx_ra   cpu_ldsw_be_mmuidx_ra
 378 # define cpu_ldl_mmuidx_ra    cpu_ldl_be_mmuidx_ra
 379 # define cpu_ldq_mmuidx_ra    cpu_ldq_be_mmuidx_ra
 380 # define cpu_stw_data         cpu_stw_be_data
 381 # define cpu_stl_data         cpu_stl_be_data
 382 # define cpu_stq_data         cpu_stq_be_data
 383 # define cpu_stw_data_ra      cpu_stw_be_data_ra
 384 # define cpu_stl_data_ra      cpu_stl_be_data_ra
 385 # define cpu_stq_data_ra      cpu_stq_be_data_ra
 386 # define cpu_stw_mmuidx_ra    cpu_stw_be_mmuidx_ra
 387 # define cpu_stl_mmuidx_ra    cpu_stl_be_mmuidx_ra
 388 # define cpu_stq_mmuidx_ra    cpu_stq_be_mmuidx_ra
 389 #else
 390 # define cpu_lduw_data        cpu_lduw_le_data
 391 # define cpu_ldsw_data        cpu_ldsw_le_data
 392 # define cpu_ldl_data         cpu_ldl_le_data
 393 # define cpu_ldq_data         cpu_ldq_le_data
 394 # define cpu_lduw_data_ra     cpu_lduw_le_data_ra
 395 # define cpu_ldsw_data_ra     cpu_ldsw_le_data_ra
 396 # define cpu_ldl_data_ra      cpu_ldl_le_data_ra
 397 # define cpu_ldq_data_ra      cpu_ldq_le_data_ra
 398 # define cpu_lduw_mmuidx_ra   cpu_lduw_le_mmuidx_ra
 399 # define cpu_ldsw_mmuidx_ra   cpu_ldsw_le_mmuidx_ra
 400 # define cpu_ldl_mmuidx_ra    cpu_ldl_le_mmuidx_ra
 401 # define cpu_ldq_mmuidx_ra    cpu_ldq_le_mmuidx_ra
 402 # define cpu_stw_data         cpu_stw_le_data
 403 # define cpu_stl_data         cpu_stl_le_data
 404 # define cpu_stq_data         cpu_stq_le_data
 405 # define cpu_stw_data_ra      cpu_stw_le_data_ra
 406 # define cpu_stl_data_ra      cpu_stl_le_data_ra
 407 # define cpu_stq_data_ra      cpu_stq_le_data_ra
 408 # define cpu_stw_mmuidx_ra    cpu_stw_le_mmuidx_ra
 409 # define cpu_stl_mmuidx_ra    cpu_stl_le_mmuidx_ra
 410 # define cpu_stq_mmuidx_ra    cpu_stq_le_mmuidx_ra
 411 #endif
 412
 413 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
 414 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
 415 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
 416 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
 417
 418 static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
 419 {
 420     return (int8_t)cpu_ldub_code(env, addr);
 421 }
 422
 423 static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
 424 {
 425     return (int16_t)cpu_lduw_code(env, addr);
 426 }
 427
 428 /**
 429  * tlb_vaddr_to_host:
 430  * @env: CPUArchState
 431  * @addr: guest virtual address to look up
 432  * @access_type: 0 for read, 1 for write, 2 for execute
 433  * @mmu_idx: MMU index to use for lookup
 434  *
 435  * Look up the specified guest virtual index in the TCG softmmu TLB.
 436  * If we can translate a host virtual address suitable for direct RAM
 437  * access, without causing a guest exception, then return it.
 438  * Otherwise (TLB entry is for an I/O access, guest software
 439  * TLB fill required, etc) return NULL.
 440  */
 441 #ifdef CONFIG_USER_ONLY
 442 static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 443                                       MMUAccessType access_type, int mmu_idx)
 444 {
 445     return g2h(addr);
 446 }
 447 #else
 448 void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
 449                         MMUAccessType access_type, int mmu_idx);
 450 #endif
 451
 452 #endif /* CPU_LDST_H */