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virtio: cleanup VMSTATE_VIRTIO_DEVICE
[qemu/ar7.git] / target-i386 / kvm.c
blobee1f53e5695358b0608e244587476100ac953aa4
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
40
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
47 #include "trace.h"
48
49 //#define DEBUG_KVM
50
51 #ifdef DEBUG_KVM
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF(fmt, ...) \
56 do { } while (0)
57 #endif
58
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
61
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
65
66 #ifndef BUS_MCEERR_AR
67 #define BUS_MCEERR_AR 4
68 #endif
69 #ifndef BUS_MCEERR_AO
70 #define BUS_MCEERR_AO 5
71 #endif
72
73 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78 };
79
80 static bool has_msr_star;
81 static bool has_msr_hsave_pa;
82 static bool has_msr_tsc_aux;
83 static bool has_msr_tsc_adjust;
84 static bool has_msr_tsc_deadline;
85 static bool has_msr_feature_control;
86 static bool has_msr_misc_enable;
87 static bool has_msr_smbase;
88 static bool has_msr_bndcfgs;
89 static int lm_capable_kernel;
90 static bool has_msr_hv_hypercall;
91 static bool has_msr_hv_crash;
92 static bool has_msr_hv_reset;
93 static bool has_msr_hv_vpindex;
94 static bool has_msr_hv_runtime;
95 static bool has_msr_hv_synic;
96 static bool has_msr_hv_stimer;
97 static bool has_msr_xss;
98
99 static bool has_msr_architectural_pmu;
100 static uint32_t num_architectural_pmu_counters;
101
102 static int has_xsave;
103 static int has_xcrs;
104 static int has_pit_state2;
105
106 static bool has_msr_mcg_ext_ctl;
107
108 static struct kvm_cpuid2 *cpuid_cache;
109
110 int kvm_has_pit_state2(void)
111 {
112 return has_pit_state2;
113 }
114
115 bool kvm_has_smm(void)
116 {
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118 }
119
120 bool kvm_allows_irq0_override(void)
121 {
122 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
123 }
124
125 static int kvm_get_tsc(CPUState *cs)
126 {
127 X86CPU *cpu = X86_CPU(cs);
128 CPUX86State *env = &cpu->env;
129 struct {
130 struct kvm_msrs info;
131 struct kvm_msr_entry entries[1];
132 } msr_data;
133 int ret;
134
135 if (env->tsc_valid) {
136 return 0;
137 }
138
139 msr_data.info.nmsrs = 1;
140 msr_data.entries[0].index = MSR_IA32_TSC;
141 env->tsc_valid = !runstate_is_running();
142
143 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
144 if (ret < 0) {
145 return ret;
146 }
147
148 assert(ret == 1);
149 env->tsc = msr_data.entries[0].data;
150 return 0;
151 }
152
153 static inline void do_kvm_synchronize_tsc(CPUState *cpu, void *arg)
154 {
155 kvm_get_tsc(cpu);
156 }
157
158 void kvm_synchronize_all_tsc(void)
159 {
160 CPUState *cpu;
161
162 if (kvm_enabled()) {
163 CPU_FOREACH(cpu) {
164 run_on_cpu(cpu, do_kvm_synchronize_tsc, NULL);
165 }
166 }
167 }
168
169 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
170 {
171 struct kvm_cpuid2 *cpuid;
172 int r, size;
173
174 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
175 cpuid = g_malloc0(size);
176 cpuid->nent = max;
177 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
178 if (r == 0 && cpuid->nent >= max) {
179 r = -E2BIG;
180 }
181 if (r < 0) {
182 if (r == -E2BIG) {
183 g_free(cpuid);
184 return NULL;
185 } else {
186 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
187 strerror(-r));
188 exit(1);
189 }
190 }
191 return cpuid;
192 }
193
194 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
195 * for all entries.
196 */
197 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
198 {
199 struct kvm_cpuid2 *cpuid;
200 int max = 1;
201
202 if (cpuid_cache != NULL) {
203 return cpuid_cache;
204 }
205 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
206 max *= 2;
207 }
208 cpuid_cache = cpuid;
209 return cpuid;
210 }
211
212 static const struct kvm_para_features {
213 int cap;
214 int feature;
215 } para_features[] = {
216 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
217 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
218 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
219 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
220 };
221
222 static int get_para_features(KVMState *s)
223 {
224 int i, features = 0;
225
226 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
227 if (kvm_check_extension(s, para_features[i].cap)) {
228 features |= (1 << para_features[i].feature);
229 }
230 }
231
232 return features;
233 }
234
235
236 /* Returns the value for a specific register on the cpuid entry
237 */
238 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
239 {
240 uint32_t ret = 0;
241 switch (reg) {
242 case R_EAX:
243 ret = entry->eax;
244 break;
245 case R_EBX:
246 ret = entry->ebx;
247 break;
248 case R_ECX:
249 ret = entry->ecx;
250 break;
251 case R_EDX:
252 ret = entry->edx;
253 break;
254 }
255 return ret;
256 }
257
258 /* Find matching entry for function/index on kvm_cpuid2 struct
259 */
260 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
261 uint32_t function,
262 uint32_t index)
263 {
264 int i;
265 for (i = 0; i < cpuid->nent; ++i) {
266 if (cpuid->entries[i].function == function &&
267 cpuid->entries[i].index == index) {
268 return &cpuid->entries[i];
269 }
270 }
271 /* not found: */
272 return NULL;
273 }
274
275 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
276 uint32_t index, int reg)
277 {
278 struct kvm_cpuid2 *cpuid;
279 uint32_t ret = 0;
280 uint32_t cpuid_1_edx;
281 bool found = false;
282
283 cpuid = get_supported_cpuid(s);
284
285 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
286 if (entry) {
287 found = true;
288 ret = cpuid_entry_get_reg(entry, reg);
289 }
290
291 /* Fixups for the data returned by KVM, below */
292
293 if (function == 1 && reg == R_EDX) {
294 /* KVM before 2.6.30 misreports the following features */
295 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
296 } else if (function == 1 && reg == R_ECX) {
297 /* We can set the hypervisor flag, even if KVM does not return it on
298 * GET_SUPPORTED_CPUID
299 */
300 ret |= CPUID_EXT_HYPERVISOR;
301 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
302 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
303 * and the irqchip is in the kernel.
304 */
305 if (kvm_irqchip_in_kernel() &&
306 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
307 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
308 }
309
310 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
311 * without the in-kernel irqchip
312 */
313 if (!kvm_irqchip_in_kernel()) {
314 ret &= ~CPUID_EXT_X2APIC;
315 }
316 } else if (function == 6 && reg == R_EAX) {
317 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
318 } else if (function == 0x80000001 && reg == R_EDX) {
319 /* On Intel, kvm returns cpuid according to the Intel spec,
320 * so add missing bits according to the AMD spec:
321 */
322 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
323 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
324 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
325 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
326 * be enabled without the in-kernel irqchip
327 */
328 if (!kvm_irqchip_in_kernel()) {
329 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
330 }
331 }
332
333 /* fallback for older kernels */
334 if ((function == KVM_CPUID_FEATURES) && !found) {
335 ret = get_para_features(s);
336 }
337
338 return ret;
339 }
340
341 typedef struct HWPoisonPage {
342 ram_addr_t ram_addr;
343 QLIST_ENTRY(HWPoisonPage) list;
344 } HWPoisonPage;
345
346 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
347 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
348
349 static void kvm_unpoison_all(void *param)
350 {
351 HWPoisonPage *page, *next_page;
352
353 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
354 QLIST_REMOVE(page, list);
355 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
356 g_free(page);
357 }
358 }
359
360 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
361 {
362 HWPoisonPage *page;
363
364 QLIST_FOREACH(page, &hwpoison_page_list, list) {
365 if (page->ram_addr == ram_addr) {
366 return;
367 }
368 }
369 page = g_new(HWPoisonPage, 1);
370 page->ram_addr = ram_addr;
371 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
372 }
373
374 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
375 int *max_banks)
376 {
377 int r;
378
379 r = kvm_check_extension(s, KVM_CAP_MCE);
380 if (r > 0) {
381 *max_banks = r;
382 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
383 }
384 return -ENOSYS;
385 }
386
387 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
388 {
389 CPUState *cs = CPU(cpu);
390 CPUX86State *env = &cpu->env;
391 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
392 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
393 uint64_t mcg_status = MCG_STATUS_MCIP;
394 int flags = 0;
395
396 if (code == BUS_MCEERR_AR) {
397 status |= MCI_STATUS_AR | 0x134;
398 mcg_status |= MCG_STATUS_EIPV;
399 } else {
400 status |= 0xc0;
401 mcg_status |= MCG_STATUS_RIPV;
402 }
403
404 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
405 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
406 * guest kernel back into env->mcg_ext_ctl.
407 */
408 cpu_synchronize_state(cs);
409 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
410 mcg_status |= MCG_STATUS_LMCE;
411 flags = 0;
412 }
413
414 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
415 (MCM_ADDR_PHYS << 6) | 0xc, flags);
416 }
417
418 static void hardware_memory_error(void)
419 {
420 fprintf(stderr, "Hardware memory error!\n");
421 exit(1);
422 }
423
424 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
425 {
426 X86CPU *cpu = X86_CPU(c);
427 CPUX86State *env = &cpu->env;
428 ram_addr_t ram_addr;
429 hwaddr paddr;
430
431 if ((env->mcg_cap & MCG_SER_P) && addr
432 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
433 ram_addr = qemu_ram_addr_from_host(addr);
434 if (ram_addr == RAM_ADDR_INVALID ||
435 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
436 fprintf(stderr, "Hardware memory error for memory used by "
437 "QEMU itself instead of guest system!\n");
438 /* Hope we are lucky for AO MCE */
439 if (code == BUS_MCEERR_AO) {
440 return 0;
441 } else {
442 hardware_memory_error();
443 }
444 }
445 kvm_hwpoison_page_add(ram_addr);
446 kvm_mce_inject(cpu, paddr, code);
447 } else {
448 if (code == BUS_MCEERR_AO) {
449 return 0;
450 } else if (code == BUS_MCEERR_AR) {
451 hardware_memory_error();
452 } else {
453 return 1;
454 }
455 }
456 return 0;
457 }
458
459 int kvm_arch_on_sigbus(int code, void *addr)
460 {
461 X86CPU *cpu = X86_CPU(first_cpu);
462
463 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
464 ram_addr_t ram_addr;
465 hwaddr paddr;
466
467 /* Hope we are lucky for AO MCE */
468 ram_addr = qemu_ram_addr_from_host(addr);
469 if (ram_addr == RAM_ADDR_INVALID ||
470 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
471 addr, &paddr)) {
472 fprintf(stderr, "Hardware memory error for memory used by "
473 "QEMU itself instead of guest system!: %p\n", addr);
474 return 0;
475 }
476 kvm_hwpoison_page_add(ram_addr);
477 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
478 } else {
479 if (code == BUS_MCEERR_AO) {
480 return 0;
481 } else if (code == BUS_MCEERR_AR) {
482 hardware_memory_error();
483 } else {
484 return 1;
485 }
486 }
487 return 0;
488 }
489
490 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
491 {
492 CPUX86State *env = &cpu->env;
493
494 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
495 unsigned int bank, bank_num = env->mcg_cap & 0xff;
496 struct kvm_x86_mce mce;
497
498 env->exception_injected = -1;
499
500 /*
501 * There must be at least one bank in use if an MCE is pending.
502 * Find it and use its values for the event injection.
503 */
504 for (bank = 0; bank < bank_num; bank++) {
505 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
506 break;
507 }
508 }
509 assert(bank < bank_num);
510
511 mce.bank = bank;
512 mce.status = env->mce_banks[bank * 4 + 1];
513 mce.mcg_status = env->mcg_status;
514 mce.addr = env->mce_banks[bank * 4 + 2];
515 mce.misc = env->mce_banks[bank * 4 + 3];
516
517 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
518 }
519 return 0;
520 }
521
522 static void cpu_update_state(void *opaque, int running, RunState state)
523 {
524 CPUX86State *env = opaque;
525
526 if (running) {
527 env->tsc_valid = false;
528 }
529 }
530
531 unsigned long kvm_arch_vcpu_id(CPUState *cs)
532 {
533 X86CPU *cpu = X86_CPU(cs);
534 return cpu->apic_id;
535 }
536
537 #ifndef KVM_CPUID_SIGNATURE_NEXT
538 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
539 #endif
540
541 static bool hyperv_hypercall_available(X86CPU *cpu)
542 {
543 return cpu->hyperv_vapic ||
544 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
545 }
546
547 static bool hyperv_enabled(X86CPU *cpu)
548 {
549 CPUState *cs = CPU(cpu);
550 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
551 (hyperv_hypercall_available(cpu) ||
552 cpu->hyperv_time ||
553 cpu->hyperv_relaxed_timing ||
554 cpu->hyperv_crash ||
555 cpu->hyperv_reset ||
556 cpu->hyperv_vpindex ||
557 cpu->hyperv_runtime ||
558 cpu->hyperv_synic ||
559 cpu->hyperv_stimer);
560 }
561
562 static int kvm_arch_set_tsc_khz(CPUState *cs)
563 {
564 X86CPU *cpu = X86_CPU(cs);
565 CPUX86State *env = &cpu->env;
566 int r;
567
568 if (!env->tsc_khz) {
569 return 0;
570 }
571
572 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
573 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
574 -ENOTSUP;
575 if (r < 0) {
576 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
577 * TSC frequency doesn't match the one we want.
578 */
579 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
580 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
581 -ENOTSUP;
582 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
583 error_report("warning: TSC frequency mismatch between "
584 "VM (%" PRId64 " kHz) and host (%d kHz), "
585 "and TSC scaling unavailable",
586 env->tsc_khz, cur_freq);
587 return r;
588 }
589 }
590
591 return 0;
592 }
593
594 static int hyperv_handle_properties(CPUState *cs)
595 {
596 X86CPU *cpu = X86_CPU(cs);
597 CPUX86State *env = &cpu->env;
598
599 if (cpu->hyperv_time &&
600 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
601 cpu->hyperv_time = false;
602 }
603
604 if (cpu->hyperv_relaxed_timing) {
605 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
606 }
607 if (cpu->hyperv_vapic) {
608 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
609 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
610 }
611 if (cpu->hyperv_time) {
612 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
613 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
614 env->features[FEAT_HYPERV_EAX] |= 0x200;
615 }
616 if (cpu->hyperv_crash && has_msr_hv_crash) {
617 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
618 }
619 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
620 if (cpu->hyperv_reset && has_msr_hv_reset) {
621 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
622 }
623 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
624 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
625 }
626 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
627 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
628 }
629 if (cpu->hyperv_synic) {
630 int sint;
631
632 if (!has_msr_hv_synic ||
633 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
634 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
635 return -ENOSYS;
636 }
637
638 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
639 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
640 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
641 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
642 }
643 }
644 if (cpu->hyperv_stimer) {
645 if (!has_msr_hv_stimer) {
646 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
647 return -ENOSYS;
648 }
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
650 }
651 return 0;
652 }
653
654 static Error *invtsc_mig_blocker;
655
656 #define KVM_MAX_CPUID_ENTRIES 100
657
658 int kvm_arch_init_vcpu(CPUState *cs)
659 {
660 struct {
661 struct kvm_cpuid2 cpuid;
662 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
663 } QEMU_PACKED cpuid_data;
664 X86CPU *cpu = X86_CPU(cs);
665 CPUX86State *env = &cpu->env;
666 uint32_t limit, i, j, cpuid_i;
667 uint32_t unused;
668 struct kvm_cpuid_entry2 *c;
669 uint32_t signature[3];
670 int kvm_base = KVM_CPUID_SIGNATURE;
671 int r;
672
673 memset(&cpuid_data, 0, sizeof(cpuid_data));
674
675 cpuid_i = 0;
676
677 /* Paravirtualization CPUIDs */
678 if (hyperv_enabled(cpu)) {
679 c = &cpuid_data.entries[cpuid_i++];
680 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
681 if (!cpu->hyperv_vendor_id) {
682 memcpy(signature, "Microsoft Hv", 12);
683 } else {
684 size_t len = strlen(cpu->hyperv_vendor_id);
685
686 if (len > 12) {
687 error_report("hv-vendor-id truncated to 12 characters");
688 len = 12;
689 }
690 memset(signature, 0, 12);
691 memcpy(signature, cpu->hyperv_vendor_id, len);
692 }
693 c->eax = HYPERV_CPUID_MIN;
694 c->ebx = signature[0];
695 c->ecx = signature[1];
696 c->edx = signature[2];
697
698 c = &cpuid_data.entries[cpuid_i++];
699 c->function = HYPERV_CPUID_INTERFACE;
700 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
701 c->eax = signature[0];
702 c->ebx = 0;
703 c->ecx = 0;
704 c->edx = 0;
705
706 c = &cpuid_data.entries[cpuid_i++];
707 c->function = HYPERV_CPUID_VERSION;
708 c->eax = 0x00001bbc;
709 c->ebx = 0x00060001;
710
711 c = &cpuid_data.entries[cpuid_i++];
712 c->function = HYPERV_CPUID_FEATURES;
713 r = hyperv_handle_properties(cs);
714 if (r) {
715 return r;
716 }
717 c->eax = env->features[FEAT_HYPERV_EAX];
718 c->ebx = env->features[FEAT_HYPERV_EBX];
719 c->edx = env->features[FEAT_HYPERV_EDX];
720
721 c = &cpuid_data.entries[cpuid_i++];
722 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
723 if (cpu->hyperv_relaxed_timing) {
724 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
725 }
726 if (cpu->hyperv_vapic) {
727 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
728 }
729 c->ebx = cpu->hyperv_spinlock_attempts;
730
731 c = &cpuid_data.entries[cpuid_i++];
732 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
733 c->eax = 0x40;
734 c->ebx = 0x40;
735
736 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
737 has_msr_hv_hypercall = true;
738 }
739
740 if (cpu->expose_kvm) {
741 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
742 c = &cpuid_data.entries[cpuid_i++];
743 c->function = KVM_CPUID_SIGNATURE | kvm_base;
744 c->eax = KVM_CPUID_FEATURES | kvm_base;
745 c->ebx = signature[0];
746 c->ecx = signature[1];
747 c->edx = signature[2];
748
749 c = &cpuid_data.entries[cpuid_i++];
750 c->function = KVM_CPUID_FEATURES | kvm_base;
751 c->eax = env->features[FEAT_KVM];
752 }
753
754 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
755
756 for (i = 0; i <= limit; i++) {
757 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
758 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
759 abort();
760 }
761 c = &cpuid_data.entries[cpuid_i++];
762
763 switch (i) {
764 case 2: {
765 /* Keep reading function 2 till all the input is received */
766 int times;
767
768 c->function = i;
769 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
770 KVM_CPUID_FLAG_STATE_READ_NEXT;
771 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
772 times = c->eax & 0xff;
773
774 for (j = 1; j < times; ++j) {
775 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
776 fprintf(stderr, "cpuid_data is full, no space for "
777 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
778 abort();
779 }
780 c = &cpuid_data.entries[cpuid_i++];
781 c->function = i;
782 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
783 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
784 }
785 break;
786 }
787 case 4:
788 case 0xb:
789 case 0xd:
790 for (j = 0; ; j++) {
791 if (i == 0xd && j == 64) {
792 break;
793 }
794 c->function = i;
795 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
796 c->index = j;
797 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
798
799 if (i == 4 && c->eax == 0) {
800 break;
801 }
802 if (i == 0xb && !(c->ecx & 0xff00)) {
803 break;
804 }
805 if (i == 0xd && c->eax == 0) {
806 continue;
807 }
808 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
809 fprintf(stderr, "cpuid_data is full, no space for "
810 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
811 abort();
812 }
813 c = &cpuid_data.entries[cpuid_i++];
814 }
815 break;
816 default:
817 c->function = i;
818 c->flags = 0;
819 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
820 break;
821 }
822 }
823
824 if (limit >= 0x0a) {
825 uint32_t ver;
826
827 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
828 if ((ver & 0xff) > 0) {
829 has_msr_architectural_pmu = true;
830 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
831
832 /* Shouldn't be more than 32, since that's the number of bits
833 * available in EBX to tell us _which_ counters are available.
834 * Play it safe.
835 */
836 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
837 num_architectural_pmu_counters = MAX_GP_COUNTERS;
838 }
839 }
840 }
841
842 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
843
844 for (i = 0x80000000; i <= limit; i++) {
845 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
846 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
847 abort();
848 }
849 c = &cpuid_data.entries[cpuid_i++];
850
851 c->function = i;
852 c->flags = 0;
853 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
854 }
855
856 /* Call Centaur's CPUID instructions they are supported. */
857 if (env->cpuid_xlevel2 > 0) {
858 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
859
860 for (i = 0xC0000000; i <= limit; i++) {
861 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
862 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
863 abort();
864 }
865 c = &cpuid_data.entries[cpuid_i++];
866
867 c->function = i;
868 c->flags = 0;
869 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
870 }
871 }
872
873 cpuid_data.cpuid.nent = cpuid_i;
874
875 if (((env->cpuid_version >> 8)&0xF) >= 6
876 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
877 (CPUID_MCE | CPUID_MCA)
878 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
879 uint64_t mcg_cap, unsupported_caps;
880 int banks;
881 int ret;
882
883 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
884 if (ret < 0) {
885 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
886 return ret;
887 }
888
889 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
890 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
891 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
892 return -ENOTSUP;
893 }
894
895 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
896 if (unsupported_caps) {
897 if (unsupported_caps & MCG_LMCE_P) {
898 error_report("kvm: LMCE not supported");
899 return -ENOTSUP;
900 }
901 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
902 unsupported_caps);
903 }
904
905 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
906 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
907 if (ret < 0) {
908 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
909 return ret;
910 }
911 }
912
913 qemu_add_vm_change_state_handler(cpu_update_state, env);
914
915 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
916 if (c) {
917 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
918 !!(c->ecx & CPUID_EXT_SMX);
919 }
920
921 if (env->mcg_cap & MCG_LMCE_P) {
922 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
923 }
924
925 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
926 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
927 /* for migration */
928 error_setg(&invtsc_mig_blocker,
929 "State blocked by non-migratable CPU device"
930 " (invtsc flag)");
931 migrate_add_blocker(invtsc_mig_blocker);
932 /* for savevm */
933 vmstate_x86_cpu.unmigratable = 1;
934 }
935
936 cpuid_data.cpuid.padding = 0;
937 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
938 if (r) {
939 return r;
940 }
941
942 r = kvm_arch_set_tsc_khz(cs);
943 if (r < 0) {
944 return r;
945 }
946
947 /* vcpu's TSC frequency is either specified by user, or following
948 * the value used by KVM if the former is not present. In the
949 * latter case, we query it from KVM and record in env->tsc_khz,
950 * so that vcpu's TSC frequency can be migrated later via this field.
951 */
952 if (!env->tsc_khz) {
953 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
954 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
955 -ENOTSUP;
956 if (r > 0) {
957 env->tsc_khz = r;
958 }
959 }
960
961 if (has_xsave) {
962 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
963 }
964 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
965
966 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
967 has_msr_tsc_aux = false;
968 }
969
970 return 0;
971 }
972
973 void kvm_arch_reset_vcpu(X86CPU *cpu)
974 {
975 CPUX86State *env = &cpu->env;
976
977 env->exception_injected = -1;
978 env->interrupt_injected = -1;
979 env->xcr0 = 1;
980 if (kvm_irqchip_in_kernel()) {
981 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
982 KVM_MP_STATE_UNINITIALIZED;
983 } else {
984 env->mp_state = KVM_MP_STATE_RUNNABLE;
985 }
986 }
987
988 void kvm_arch_do_init_vcpu(X86CPU *cpu)
989 {
990 CPUX86State *env = &cpu->env;
991
992 /* APs get directly into wait-for-SIPI state. */
993 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
994 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
995 }
996 }
997
998 static int kvm_get_supported_msrs(KVMState *s)
999 {
1000 static int kvm_supported_msrs;
1001 int ret = 0;
1002
1003 /* first time */
1004 if (kvm_supported_msrs == 0) {
1005 struct kvm_msr_list msr_list, *kvm_msr_list;
1006
1007 kvm_supported_msrs = -1;
1008
1009 /* Obtain MSR list from KVM. These are the MSRs that we must
1010 * save/restore */
1011 msr_list.nmsrs = 0;
1012 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1013 if (ret < 0 && ret != -E2BIG) {
1014 return ret;
1015 }
1016 /* Old kernel modules had a bug and could write beyond the provided
1017 memory. Allocate at least a safe amount of 1K. */
1018 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1019 msr_list.nmsrs *
1020 sizeof(msr_list.indices[0])));
1021
1022 kvm_msr_list->nmsrs = msr_list.nmsrs;
1023 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1024 if (ret >= 0) {
1025 int i;
1026
1027 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1028 if (kvm_msr_list->indices[i] == MSR_STAR) {
1029 has_msr_star = true;
1030 continue;
1031 }
1032 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1033 has_msr_hsave_pa = true;
1034 continue;
1035 }
1036 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1037 has_msr_tsc_aux = true;
1038 continue;
1039 }
1040 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1041 has_msr_tsc_adjust = true;
1042 continue;
1043 }
1044 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1045 has_msr_tsc_deadline = true;
1046 continue;
1047 }
1048 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1049 has_msr_smbase = true;
1050 continue;
1051 }
1052 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1053 has_msr_misc_enable = true;
1054 continue;
1055 }
1056 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1057 has_msr_bndcfgs = true;
1058 continue;
1059 }
1060 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1061 has_msr_xss = true;
1062 continue;
1063 }
1064 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1065 has_msr_hv_crash = true;
1066 continue;
1067 }
1068 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1069 has_msr_hv_reset = true;
1070 continue;
1071 }
1072 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1073 has_msr_hv_vpindex = true;
1074 continue;
1075 }
1076 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1077 has_msr_hv_runtime = true;
1078 continue;
1079 }
1080 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1081 has_msr_hv_synic = true;
1082 continue;
1083 }
1084 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1085 has_msr_hv_stimer = true;
1086 continue;
1087 }
1088 }
1089 }
1090
1091 g_free(kvm_msr_list);
1092 }
1093
1094 return ret;
1095 }
1096
1097 static Notifier smram_machine_done;
1098 static KVMMemoryListener smram_listener;
1099 static AddressSpace smram_address_space;
1100 static MemoryRegion smram_as_root;
1101 static MemoryRegion smram_as_mem;
1102
1103 static void register_smram_listener(Notifier *n, void *unused)
1104 {
1105 MemoryRegion *smram =
1106 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1107
1108 /* Outer container... */
1109 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1110 memory_region_set_enabled(&smram_as_root, true);
1111
1112 /* ... with two regions inside: normal system memory with low
1113 * priority, and...
1114 */
1115 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1116 get_system_memory(), 0, ~0ull);
1117 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1118 memory_region_set_enabled(&smram_as_mem, true);
1119
1120 if (smram) {
1121 /* ... SMRAM with higher priority */
1122 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1123 memory_region_set_enabled(smram, true);
1124 }
1125
1126 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1127 kvm_memory_listener_register(kvm_state, &smram_listener,
1128 &smram_address_space, 1);
1129 }
1130
1131 int kvm_arch_init(MachineState *ms, KVMState *s)
1132 {
1133 uint64_t identity_base = 0xfffbc000;
1134 uint64_t shadow_mem;
1135 int ret;
1136 struct utsname utsname;
1137
1138 #ifdef KVM_CAP_XSAVE
1139 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1140 #endif
1141
1142 #ifdef KVM_CAP_XCRS
1143 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1144 #endif
1145
1146 #ifdef KVM_CAP_PIT_STATE2
1147 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1148 #endif
1149
1150 ret = kvm_get_supported_msrs(s);
1151 if (ret < 0) {
1152 return ret;
1153 }
1154
1155 uname(&utsname);
1156 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1157
1158 /*
1159 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1160 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1161 * Since these must be part of guest physical memory, we need to allocate
1162 * them, both by setting their start addresses in the kernel and by
1163 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1164 *
1165 * Older KVM versions may not support setting the identity map base. In
1166 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1167 * size.
1168 */
1169 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1170 /* Allows up to 16M BIOSes. */
1171 identity_base = 0xfeffc000;
1172
1173 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1174 if (ret < 0) {
1175 return ret;
1176 }
1177 }
1178
1179 /* Set TSS base one page after EPT identity map. */
1180 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1181 if (ret < 0) {
1182 return ret;
1183 }
1184
1185 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1186 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1187 if (ret < 0) {
1188 fprintf(stderr, "e820_add_entry() table is full\n");
1189 return ret;
1190 }
1191 qemu_register_reset(kvm_unpoison_all, NULL);
1192
1193 shadow_mem = machine_kvm_shadow_mem(ms);
1194 if (shadow_mem != -1) {
1195 shadow_mem /= 4096;
1196 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1197 if (ret < 0) {
1198 return ret;
1199 }
1200 }
1201
1202 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1203 smram_machine_done.notify = register_smram_listener;
1204 qemu_add_machine_init_done_notifier(&smram_machine_done);
1205 }
1206 return 0;
1207 }
1208
1209 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1210 {
1211 lhs->selector = rhs->selector;
1212 lhs->base = rhs->base;
1213 lhs->limit = rhs->limit;
1214 lhs->type = 3;
1215 lhs->present = 1;
1216 lhs->dpl = 3;
1217 lhs->db = 0;
1218 lhs->s = 1;
1219 lhs->l = 0;
1220 lhs->g = 0;
1221 lhs->avl = 0;
1222 lhs->unusable = 0;
1223 }
1224
1225 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1226 {
1227 unsigned flags = rhs->flags;
1228 lhs->selector = rhs->selector;
1229 lhs->base = rhs->base;
1230 lhs->limit = rhs->limit;
1231 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1232 lhs->present = (flags & DESC_P_MASK) != 0;
1233 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1234 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1235 lhs->s = (flags & DESC_S_MASK) != 0;
1236 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1237 lhs->g = (flags & DESC_G_MASK) != 0;
1238 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1239 lhs->unusable = !lhs->present;
1240 lhs->padding = 0;
1241 }
1242
1243 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1244 {
1245 lhs->selector = rhs->selector;
1246 lhs->base = rhs->base;
1247 lhs->limit = rhs->limit;
1248 if (rhs->unusable) {
1249 lhs->flags = 0;
1250 } else {
1251 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1252 (rhs->present * DESC_P_MASK) |
1253 (rhs->dpl << DESC_DPL_SHIFT) |
1254 (rhs->db << DESC_B_SHIFT) |
1255 (rhs->s * DESC_S_MASK) |
1256 (rhs->l << DESC_L_SHIFT) |
1257 (rhs->g * DESC_G_MASK) |
1258 (rhs->avl * DESC_AVL_MASK);
1259 }
1260 }
1261
1262 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1263 {
1264 if (set) {
1265 *kvm_reg = *qemu_reg;
1266 } else {
1267 *qemu_reg = *kvm_reg;
1268 }
1269 }
1270
1271 static int kvm_getput_regs(X86CPU *cpu, int set)
1272 {
1273 CPUX86State *env = &cpu->env;
1274 struct kvm_regs regs;
1275 int ret = 0;
1276
1277 if (!set) {
1278 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1279 if (ret < 0) {
1280 return ret;
1281 }
1282 }
1283
1284 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1285 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1286 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1287 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1288 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1289 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1290 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1291 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1292 #ifdef TARGET_X86_64
1293 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1294 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1295 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1296 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1297 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1298 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1299 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1300 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1301 #endif
1302
1303 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1304 kvm_getput_reg(&regs.rip, &env->eip, set);
1305
1306 if (set) {
1307 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1308 }
1309
1310 return ret;
1311 }
1312
1313 static int kvm_put_fpu(X86CPU *cpu)
1314 {
1315 CPUX86State *env = &cpu->env;
1316 struct kvm_fpu fpu;
1317 int i;
1318
1319 memset(&fpu, 0, sizeof fpu);
1320 fpu.fsw = env->fpus & ~(7 << 11);
1321 fpu.fsw |= (env->fpstt & 7) << 11;
1322 fpu.fcw = env->fpuc;
1323 fpu.last_opcode = env->fpop;
1324 fpu.last_ip = env->fpip;
1325 fpu.last_dp = env->fpdp;
1326 for (i = 0; i < 8; ++i) {
1327 fpu.ftwx |= (!env->fptags[i]) << i;
1328 }
1329 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1330 for (i = 0; i < CPU_NB_REGS; i++) {
1331 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1332 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1333 }
1334 fpu.mxcsr = env->mxcsr;
1335
1336 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1337 }
1338
1339 #define XSAVE_FCW_FSW 0
1340 #define XSAVE_FTW_FOP 1
1341 #define XSAVE_CWD_RIP 2
1342 #define XSAVE_CWD_RDP 4
1343 #define XSAVE_MXCSR 6
1344 #define XSAVE_ST_SPACE 8
1345 #define XSAVE_XMM_SPACE 40
1346 #define XSAVE_XSTATE_BV 128
1347 #define XSAVE_YMMH_SPACE 144
1348 #define XSAVE_BNDREGS 240
1349 #define XSAVE_BNDCSR 256
1350 #define XSAVE_OPMASK 272
1351 #define XSAVE_ZMM_Hi256 288
1352 #define XSAVE_Hi16_ZMM 416
1353 #define XSAVE_PKRU 672
1354
1355 #define XSAVE_BYTE_OFFSET(word_offset) \
1356 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1357
1358 #define ASSERT_OFFSET(word_offset, field) \
1359 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1360 offsetof(X86XSaveArea, field))
1361
1362 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1363 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1364 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1365 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1366 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1367 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1368 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1369 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1370 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1371 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1372 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1373 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1374 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1375 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1376 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1377
1378 static int kvm_put_xsave(X86CPU *cpu)
1379 {
1380 CPUX86State *env = &cpu->env;
1381 X86XSaveArea *xsave = env->kvm_xsave_buf;
1382 uint16_t cwd, swd, twd;
1383 int i;
1384
1385 if (!has_xsave) {
1386 return kvm_put_fpu(cpu);
1387 }
1388
1389 memset(xsave, 0, sizeof(struct kvm_xsave));
1390 twd = 0;
1391 swd = env->fpus & ~(7 << 11);
1392 swd |= (env->fpstt & 7) << 11;
1393 cwd = env->fpuc;
1394 for (i = 0; i < 8; ++i) {
1395 twd |= (!env->fptags[i]) << i;
1396 }
1397 xsave->legacy.fcw = cwd;
1398 xsave->legacy.fsw = swd;
1399 xsave->legacy.ftw = twd;
1400 xsave->legacy.fpop = env->fpop;
1401 xsave->legacy.fpip = env->fpip;
1402 xsave->legacy.fpdp = env->fpdp;
1403 memcpy(&xsave->legacy.fpregs, env->fpregs,
1404 sizeof env->fpregs);
1405 xsave->legacy.mxcsr = env->mxcsr;
1406 xsave->header.xstate_bv = env->xstate_bv;
1407 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1408 sizeof env->bnd_regs);
1409 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1410 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1411 sizeof env->opmask_regs);
1412
1413 for (i = 0; i < CPU_NB_REGS; i++) {
1414 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1415 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1416 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1417 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1418 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1419 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1420 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1421 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1422 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1423 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1424 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1425 }
1426
1427 #ifdef TARGET_X86_64
1428 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1429 16 * sizeof env->xmm_regs[16]);
1430 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1431 #endif
1432 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1433 }
1434
1435 static int kvm_put_xcrs(X86CPU *cpu)
1436 {
1437 CPUX86State *env = &cpu->env;
1438 struct kvm_xcrs xcrs = {};
1439
1440 if (!has_xcrs) {
1441 return 0;
1442 }
1443
1444 xcrs.nr_xcrs = 1;
1445 xcrs.flags = 0;
1446 xcrs.xcrs[0].xcr = 0;
1447 xcrs.xcrs[0].value = env->xcr0;
1448 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1449 }
1450
1451 static int kvm_put_sregs(X86CPU *cpu)
1452 {
1453 CPUX86State *env = &cpu->env;
1454 struct kvm_sregs sregs;
1455
1456 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1457 if (env->interrupt_injected >= 0) {
1458 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1459 (uint64_t)1 << (env->interrupt_injected % 64);
1460 }
1461
1462 if ((env->eflags & VM_MASK)) {
1463 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1464 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1465 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1466 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1467 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1468 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1469 } else {
1470 set_seg(&sregs.cs, &env->segs[R_CS]);
1471 set_seg(&sregs.ds, &env->segs[R_DS]);
1472 set_seg(&sregs.es, &env->segs[R_ES]);
1473 set_seg(&sregs.fs, &env->segs[R_FS]);
1474 set_seg(&sregs.gs, &env->segs[R_GS]);
1475 set_seg(&sregs.ss, &env->segs[R_SS]);
1476 }
1477
1478 set_seg(&sregs.tr, &env->tr);
1479 set_seg(&sregs.ldt, &env->ldt);
1480
1481 sregs.idt.limit = env->idt.limit;
1482 sregs.idt.base = env->idt.base;
1483 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1484 sregs.gdt.limit = env->gdt.limit;
1485 sregs.gdt.base = env->gdt.base;
1486 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1487
1488 sregs.cr0 = env->cr[0];
1489 sregs.cr2 = env->cr[2];
1490 sregs.cr3 = env->cr[3];
1491 sregs.cr4 = env->cr[4];
1492
1493 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1494 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1495
1496 sregs.efer = env->efer;
1497
1498 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1499 }
1500
1501 static void kvm_msr_buf_reset(X86CPU *cpu)
1502 {
1503 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1504 }
1505
1506 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1507 {
1508 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1509 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1510 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1511
1512 assert((void *)(entry + 1) <= limit);
1513
1514 entry->index = index;
1515 entry->reserved = 0;
1516 entry->data = value;
1517 msrs->nmsrs++;
1518 }
1519
1520 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1521 {
1522 kvm_msr_buf_reset(cpu);
1523 kvm_msr_entry_add(cpu, index, value);
1524
1525 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1526 }
1527
1528 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1529 {
1530 int ret;
1531
1532 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1533 assert(ret == 1);
1534 }
1535
1536 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1537 {
1538 CPUX86State *env = &cpu->env;
1539 int ret;
1540
1541 if (!has_msr_tsc_deadline) {
1542 return 0;
1543 }
1544
1545 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1546 if (ret < 0) {
1547 return ret;
1548 }
1549
1550 assert(ret == 1);
1551 return 0;
1552 }
1553
1554 /*
1555 * Provide a separate write service for the feature control MSR in order to
1556 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1557 * before writing any other state because forcibly leaving nested mode
1558 * invalidates the VCPU state.
1559 */
1560 static int kvm_put_msr_feature_control(X86CPU *cpu)
1561 {
1562 int ret;
1563
1564 if (!has_msr_feature_control) {
1565 return 0;
1566 }
1567
1568 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1569 cpu->env.msr_ia32_feature_control);
1570 if (ret < 0) {
1571 return ret;
1572 }
1573
1574 assert(ret == 1);
1575 return 0;
1576 }
1577
1578 static int kvm_put_msrs(X86CPU *cpu, int level)
1579 {
1580 CPUX86State *env = &cpu->env;
1581 int i;
1582 int ret;
1583
1584 kvm_msr_buf_reset(cpu);
1585
1586 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1587 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1588 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1589 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1590 if (has_msr_star) {
1591 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1592 }
1593 if (has_msr_hsave_pa) {
1594 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1595 }
1596 if (has_msr_tsc_aux) {
1597 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1598 }
1599 if (has_msr_tsc_adjust) {
1600 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1601 }
1602 if (has_msr_misc_enable) {
1603 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1604 env->msr_ia32_misc_enable);
1605 }
1606 if (has_msr_smbase) {
1607 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1608 }
1609 if (has_msr_bndcfgs) {
1610 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1611 }
1612 if (has_msr_xss) {
1613 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1614 }
1615 #ifdef TARGET_X86_64
1616 if (lm_capable_kernel) {
1617 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1618 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1619 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1620 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1621 }
1622 #endif
1623 /*
1624 * The following MSRs have side effects on the guest or are too heavy
1625 * for normal writeback. Limit them to reset or full state updates.
1626 */
1627 if (level >= KVM_PUT_RESET_STATE) {
1628 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1629 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1630 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1631 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1632 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1633 }
1634 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1635 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1636 }
1637 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1638 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1639 }
1640 if (has_msr_architectural_pmu) {
1641 /* Stop the counter. */
1642 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1643 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1644
1645 /* Set the counter values. */
1646 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1647 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1648 env->msr_fixed_counters[i]);
1649 }
1650 for (i = 0; i < num_architectural_pmu_counters; i++) {
1651 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1652 env->msr_gp_counters[i]);
1653 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1654 env->msr_gp_evtsel[i]);
1655 }
1656 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1657 env->msr_global_status);
1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1659 env->msr_global_ovf_ctrl);
1660
1661 /* Now start the PMU. */
1662 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1663 env->msr_fixed_ctr_ctrl);
1664 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1665 env->msr_global_ctrl);
1666 }
1667 if (has_msr_hv_hypercall) {
1668 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1669 env->msr_hv_guest_os_id);
1670 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1671 env->msr_hv_hypercall);
1672 }
1673 if (cpu->hyperv_vapic) {
1674 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1675 env->msr_hv_vapic);
1676 }
1677 if (cpu->hyperv_time) {
1678 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1679 }
1680 if (has_msr_hv_crash) {
1681 int j;
1682
1683 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1684 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1685 env->msr_hv_crash_params[j]);
1686
1687 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1688 HV_X64_MSR_CRASH_CTL_NOTIFY);
1689 }
1690 if (has_msr_hv_runtime) {
1691 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1692 }
1693 if (cpu->hyperv_synic) {
1694 int j;
1695
1696 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1697 env->msr_hv_synic_control);
1698 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1699 env->msr_hv_synic_version);
1700 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1701 env->msr_hv_synic_evt_page);
1702 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1703 env->msr_hv_synic_msg_page);
1704
1705 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1706 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1707 env->msr_hv_synic_sint[j]);
1708 }
1709 }
1710 if (has_msr_hv_stimer) {
1711 int j;
1712
1713 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1714 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1715 env->msr_hv_stimer_config[j]);
1716 }
1717
1718 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1719 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1720 env->msr_hv_stimer_count[j]);
1721 }
1722 }
1723 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1724 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1725
1726 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1727 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1728 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1731 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1732 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1733 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1734 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1735 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1736 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1737 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1738 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1739 /* The CPU GPs if we write to a bit above the physical limit of
1740 * the host CPU (and KVM emulates that)
1741 */
1742 uint64_t mask = env->mtrr_var[i].mask;
1743 mask &= phys_mask;
1744
1745 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1746 env->mtrr_var[i].base);
1747 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1748 }
1749 }
1750
1751 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1752 * kvm_put_msr_feature_control. */
1753 }
1754 if (env->mcg_cap) {
1755 int i;
1756
1757 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1758 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1759 if (has_msr_mcg_ext_ctl) {
1760 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1761 }
1762 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1763 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1764 }
1765 }
1766
1767 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1768 if (ret < 0) {
1769 return ret;
1770 }
1771
1772 assert(ret == cpu->kvm_msr_buf->nmsrs);
1773 return 0;
1774 }
1775
1776
1777 static int kvm_get_fpu(X86CPU *cpu)
1778 {
1779 CPUX86State *env = &cpu->env;
1780 struct kvm_fpu fpu;
1781 int i, ret;
1782
1783 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1784 if (ret < 0) {
1785 return ret;
1786 }
1787
1788 env->fpstt = (fpu.fsw >> 11) & 7;
1789 env->fpus = fpu.fsw;
1790 env->fpuc = fpu.fcw;
1791 env->fpop = fpu.last_opcode;
1792 env->fpip = fpu.last_ip;
1793 env->fpdp = fpu.last_dp;
1794 for (i = 0; i < 8; ++i) {
1795 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1796 }
1797 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1798 for (i = 0; i < CPU_NB_REGS; i++) {
1799 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1800 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1801 }
1802 env->mxcsr = fpu.mxcsr;
1803
1804 return 0;
1805 }
1806
1807 static int kvm_get_xsave(X86CPU *cpu)
1808 {
1809 CPUX86State *env = &cpu->env;
1810 X86XSaveArea *xsave = env->kvm_xsave_buf;
1811 int ret, i;
1812 uint16_t cwd, swd, twd;
1813
1814 if (!has_xsave) {
1815 return kvm_get_fpu(cpu);
1816 }
1817
1818 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1819 if (ret < 0) {
1820 return ret;
1821 }
1822
1823 cwd = xsave->legacy.fcw;
1824 swd = xsave->legacy.fsw;
1825 twd = xsave->legacy.ftw;
1826 env->fpop = xsave->legacy.fpop;
1827 env->fpstt = (swd >> 11) & 7;
1828 env->fpus = swd;
1829 env->fpuc = cwd;
1830 for (i = 0; i < 8; ++i) {
1831 env->fptags[i] = !((twd >> i) & 1);
1832 }
1833 env->fpip = xsave->legacy.fpip;
1834 env->fpdp = xsave->legacy.fpdp;
1835 env->mxcsr = xsave->legacy.mxcsr;
1836 memcpy(env->fpregs, &xsave->legacy.fpregs,
1837 sizeof env->fpregs);
1838 env->xstate_bv = xsave->header.xstate_bv;
1839 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1840 sizeof env->bnd_regs);
1841 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1842 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1843 sizeof env->opmask_regs);
1844
1845 for (i = 0; i < CPU_NB_REGS; i++) {
1846 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1847 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1848 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1849 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1850 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1851 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1852 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1853 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1854 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1855 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1856 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1857 }
1858
1859 #ifdef TARGET_X86_64
1860 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1861 16 * sizeof env->xmm_regs[16]);
1862 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1863 #endif
1864 return 0;
1865 }
1866
1867 static int kvm_get_xcrs(X86CPU *cpu)
1868 {
1869 CPUX86State *env = &cpu->env;
1870 int i, ret;
1871 struct kvm_xcrs xcrs;
1872
1873 if (!has_xcrs) {
1874 return 0;
1875 }
1876
1877 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1878 if (ret < 0) {
1879 return ret;
1880 }
1881
1882 for (i = 0; i < xcrs.nr_xcrs; i++) {
1883 /* Only support xcr0 now */
1884 if (xcrs.xcrs[i].xcr == 0) {
1885 env->xcr0 = xcrs.xcrs[i].value;
1886 break;
1887 }
1888 }
1889 return 0;
1890 }
1891
1892 static int kvm_get_sregs(X86CPU *cpu)
1893 {
1894 CPUX86State *env = &cpu->env;
1895 struct kvm_sregs sregs;
1896 uint32_t hflags;
1897 int bit, i, ret;
1898
1899 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1900 if (ret < 0) {
1901 return ret;
1902 }
1903
1904 /* There can only be one pending IRQ set in the bitmap at a time, so try
1905 to find it and save its number instead (-1 for none). */
1906 env->interrupt_injected = -1;
1907 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1908 if (sregs.interrupt_bitmap[i]) {
1909 bit = ctz64(sregs.interrupt_bitmap[i]);
1910 env->interrupt_injected = i * 64 + bit;
1911 break;
1912 }
1913 }
1914
1915 get_seg(&env->segs[R_CS], &sregs.cs);
1916 get_seg(&env->segs[R_DS], &sregs.ds);
1917 get_seg(&env->segs[R_ES], &sregs.es);
1918 get_seg(&env->segs[R_FS], &sregs.fs);
1919 get_seg(&env->segs[R_GS], &sregs.gs);
1920 get_seg(&env->segs[R_SS], &sregs.ss);
1921
1922 get_seg(&env->tr, &sregs.tr);
1923 get_seg(&env->ldt, &sregs.ldt);
1924
1925 env->idt.limit = sregs.idt.limit;
1926 env->idt.base = sregs.idt.base;
1927 env->gdt.limit = sregs.gdt.limit;
1928 env->gdt.base = sregs.gdt.base;
1929
1930 env->cr[0] = sregs.cr0;
1931 env->cr[2] = sregs.cr2;
1932 env->cr[3] = sregs.cr3;
1933 env->cr[4] = sregs.cr4;
1934
1935 env->efer = sregs.efer;
1936
1937 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1938
1939 #define HFLAG_COPY_MASK \
1940 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1941 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1942 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1943 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1944
1945 hflags = env->hflags & HFLAG_COPY_MASK;
1946 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1947 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1948 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1949 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1950 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1951
1952 if (env->cr[4] & CR4_OSFXSR_MASK) {
1953 hflags |= HF_OSFXSR_MASK;
1954 }
1955
1956 if (env->efer & MSR_EFER_LMA) {
1957 hflags |= HF_LMA_MASK;
1958 }
1959
1960 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1961 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1962 } else {
1963 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1964 (DESC_B_SHIFT - HF_CS32_SHIFT);
1965 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1966 (DESC_B_SHIFT - HF_SS32_SHIFT);
1967 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1968 !(hflags & HF_CS32_MASK)) {
1969 hflags |= HF_ADDSEG_MASK;
1970 } else {
1971 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1972 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1973 }
1974 }
1975 env->hflags = hflags;
1976
1977 return 0;
1978 }
1979
1980 static int kvm_get_msrs(X86CPU *cpu)
1981 {
1982 CPUX86State *env = &cpu->env;
1983 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1984 int ret, i;
1985 uint64_t mtrr_top_bits;
1986
1987 kvm_msr_buf_reset(cpu);
1988
1989 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1990 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1991 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1992 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1993 if (has_msr_star) {
1994 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1995 }
1996 if (has_msr_hsave_pa) {
1997 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1998 }
1999 if (has_msr_tsc_aux) {
2000 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2001 }
2002 if (has_msr_tsc_adjust) {
2003 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2004 }
2005 if (has_msr_tsc_deadline) {
2006 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2007 }
2008 if (has_msr_misc_enable) {
2009 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2010 }
2011 if (has_msr_smbase) {
2012 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2013 }
2014 if (has_msr_feature_control) {
2015 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2016 }
2017 if (has_msr_bndcfgs) {
2018 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2019 }
2020 if (has_msr_xss) {
2021 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2022 }
2023
2024
2025 if (!env->tsc_valid) {
2026 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2027 env->tsc_valid = !runstate_is_running();
2028 }
2029
2030 #ifdef TARGET_X86_64
2031 if (lm_capable_kernel) {
2032 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2033 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2034 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2035 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2036 }
2037 #endif
2038 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2039 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2040 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2041 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2042 }
2043 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2044 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2045 }
2046 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2047 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2048 }
2049 if (has_msr_architectural_pmu) {
2050 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2052 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2053 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2054 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2055 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2056 }
2057 for (i = 0; i < num_architectural_pmu_counters; i++) {
2058 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2059 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2060 }
2061 }
2062
2063 if (env->mcg_cap) {
2064 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2065 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2066 if (has_msr_mcg_ext_ctl) {
2067 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2068 }
2069 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2070 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2071 }
2072 }
2073
2074 if (has_msr_hv_hypercall) {
2075 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2076 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2077 }
2078 if (cpu->hyperv_vapic) {
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2080 }
2081 if (cpu->hyperv_time) {
2082 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2083 }
2084 if (has_msr_hv_crash) {
2085 int j;
2086
2087 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2088 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2089 }
2090 }
2091 if (has_msr_hv_runtime) {
2092 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2093 }
2094 if (cpu->hyperv_synic) {
2095 uint32_t msr;
2096
2097 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2098 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2099 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2100 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2101 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2102 kvm_msr_entry_add(cpu, msr, 0);
2103 }
2104 }
2105 if (has_msr_hv_stimer) {
2106 uint32_t msr;
2107
2108 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2109 msr++) {
2110 kvm_msr_entry_add(cpu, msr, 0);
2111 }
2112 }
2113 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2114 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2115 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2116 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2117 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2124 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2125 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2126 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2127 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2128 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2129 }
2130 }
2131
2132 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2133 if (ret < 0) {
2134 return ret;
2135 }
2136
2137 assert(ret == cpu->kvm_msr_buf->nmsrs);
2138 /*
2139 * MTRR masks: Each mask consists of 5 parts
2140 * a 10..0: must be zero
2141 * b 11 : valid bit
2142 * c n-1.12: actual mask bits
2143 * d 51..n: reserved must be zero
2144 * e 63.52: reserved must be zero
2145 *
2146 * 'n' is the number of physical bits supported by the CPU and is
2147 * apparently always <= 52. We know our 'n' but don't know what
2148 * the destinations 'n' is; it might be smaller, in which case
2149 * it masks (c) on loading. It might be larger, in which case
2150 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2151 * we're migrating to.
2152 */
2153
2154 if (cpu->fill_mtrr_mask) {
2155 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2156 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2157 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2158 } else {
2159 mtrr_top_bits = 0;
2160 }
2161
2162 for (i = 0; i < ret; i++) {
2163 uint32_t index = msrs[i].index;
2164 switch (index) {
2165 case MSR_IA32_SYSENTER_CS:
2166 env->sysenter_cs = msrs[i].data;
2167 break;
2168 case MSR_IA32_SYSENTER_ESP:
2169 env->sysenter_esp = msrs[i].data;
2170 break;
2171 case MSR_IA32_SYSENTER_EIP:
2172 env->sysenter_eip = msrs[i].data;
2173 break;
2174 case MSR_PAT:
2175 env->pat = msrs[i].data;
2176 break;
2177 case MSR_STAR:
2178 env->star = msrs[i].data;
2179 break;
2180 #ifdef TARGET_X86_64
2181 case MSR_CSTAR:
2182 env->cstar = msrs[i].data;
2183 break;
2184 case MSR_KERNELGSBASE:
2185 env->kernelgsbase = msrs[i].data;
2186 break;
2187 case MSR_FMASK:
2188 env->fmask = msrs[i].data;
2189 break;
2190 case MSR_LSTAR:
2191 env->lstar = msrs[i].data;
2192 break;
2193 #endif
2194 case MSR_IA32_TSC:
2195 env->tsc = msrs[i].data;
2196 break;
2197 case MSR_TSC_AUX:
2198 env->tsc_aux = msrs[i].data;
2199 break;
2200 case MSR_TSC_ADJUST:
2201 env->tsc_adjust = msrs[i].data;
2202 break;
2203 case MSR_IA32_TSCDEADLINE:
2204 env->tsc_deadline = msrs[i].data;
2205 break;
2206 case MSR_VM_HSAVE_PA:
2207 env->vm_hsave = msrs[i].data;
2208 break;
2209 case MSR_KVM_SYSTEM_TIME:
2210 env->system_time_msr = msrs[i].data;
2211 break;
2212 case MSR_KVM_WALL_CLOCK:
2213 env->wall_clock_msr = msrs[i].data;
2214 break;
2215 case MSR_MCG_STATUS:
2216 env->mcg_status = msrs[i].data;
2217 break;
2218 case MSR_MCG_CTL:
2219 env->mcg_ctl = msrs[i].data;
2220 break;
2221 case MSR_MCG_EXT_CTL:
2222 env->mcg_ext_ctl = msrs[i].data;
2223 break;
2224 case MSR_IA32_MISC_ENABLE:
2225 env->msr_ia32_misc_enable = msrs[i].data;
2226 break;
2227 case MSR_IA32_SMBASE:
2228 env->smbase = msrs[i].data;
2229 break;
2230 case MSR_IA32_FEATURE_CONTROL:
2231 env->msr_ia32_feature_control = msrs[i].data;
2232 break;
2233 case MSR_IA32_BNDCFGS:
2234 env->msr_bndcfgs = msrs[i].data;
2235 break;
2236 case MSR_IA32_XSS:
2237 env->xss = msrs[i].data;
2238 break;
2239 default:
2240 if (msrs[i].index >= MSR_MC0_CTL &&
2241 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2242 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2243 }
2244 break;
2245 case MSR_KVM_ASYNC_PF_EN:
2246 env->async_pf_en_msr = msrs[i].data;
2247 break;
2248 case MSR_KVM_PV_EOI_EN:
2249 env->pv_eoi_en_msr = msrs[i].data;
2250 break;
2251 case MSR_KVM_STEAL_TIME:
2252 env->steal_time_msr = msrs[i].data;
2253 break;
2254 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2255 env->msr_fixed_ctr_ctrl = msrs[i].data;
2256 break;
2257 case MSR_CORE_PERF_GLOBAL_CTRL:
2258 env->msr_global_ctrl = msrs[i].data;
2259 break;
2260 case MSR_CORE_PERF_GLOBAL_STATUS:
2261 env->msr_global_status = msrs[i].data;
2262 break;
2263 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2264 env->msr_global_ovf_ctrl = msrs[i].data;
2265 break;
2266 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2267 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2268 break;
2269 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2270 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2271 break;
2272 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2273 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2274 break;
2275 case HV_X64_MSR_HYPERCALL:
2276 env->msr_hv_hypercall = msrs[i].data;
2277 break;
2278 case HV_X64_MSR_GUEST_OS_ID:
2279 env->msr_hv_guest_os_id = msrs[i].data;
2280 break;
2281 case HV_X64_MSR_APIC_ASSIST_PAGE:
2282 env->msr_hv_vapic = msrs[i].data;
2283 break;
2284 case HV_X64_MSR_REFERENCE_TSC:
2285 env->msr_hv_tsc = msrs[i].data;
2286 break;
2287 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2288 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2289 break;
2290 case HV_X64_MSR_VP_RUNTIME:
2291 env->msr_hv_runtime = msrs[i].data;
2292 break;
2293 case HV_X64_MSR_SCONTROL:
2294 env->msr_hv_synic_control = msrs[i].data;
2295 break;
2296 case HV_X64_MSR_SVERSION:
2297 env->msr_hv_synic_version = msrs[i].data;
2298 break;
2299 case HV_X64_MSR_SIEFP:
2300 env->msr_hv_synic_evt_page = msrs[i].data;
2301 break;
2302 case HV_X64_MSR_SIMP:
2303 env->msr_hv_synic_msg_page = msrs[i].data;
2304 break;
2305 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2306 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2307 break;
2308 case HV_X64_MSR_STIMER0_CONFIG:
2309 case HV_X64_MSR_STIMER1_CONFIG:
2310 case HV_X64_MSR_STIMER2_CONFIG:
2311 case HV_X64_MSR_STIMER3_CONFIG:
2312 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2313 msrs[i].data;
2314 break;
2315 case HV_X64_MSR_STIMER0_COUNT:
2316 case HV_X64_MSR_STIMER1_COUNT:
2317 case HV_X64_MSR_STIMER2_COUNT:
2318 case HV_X64_MSR_STIMER3_COUNT:
2319 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2320 msrs[i].data;
2321 break;
2322 case MSR_MTRRdefType:
2323 env->mtrr_deftype = msrs[i].data;
2324 break;
2325 case MSR_MTRRfix64K_00000:
2326 env->mtrr_fixed[0] = msrs[i].data;
2327 break;
2328 case MSR_MTRRfix16K_80000:
2329 env->mtrr_fixed[1] = msrs[i].data;
2330 break;
2331 case MSR_MTRRfix16K_A0000:
2332 env->mtrr_fixed[2] = msrs[i].data;
2333 break;
2334 case MSR_MTRRfix4K_C0000:
2335 env->mtrr_fixed[3] = msrs[i].data;
2336 break;
2337 case MSR_MTRRfix4K_C8000:
2338 env->mtrr_fixed[4] = msrs[i].data;
2339 break;
2340 case MSR_MTRRfix4K_D0000:
2341 env->mtrr_fixed[5] = msrs[i].data;
2342 break;
2343 case MSR_MTRRfix4K_D8000:
2344 env->mtrr_fixed[6] = msrs[i].data;
2345 break;
2346 case MSR_MTRRfix4K_E0000:
2347 env->mtrr_fixed[7] = msrs[i].data;
2348 break;
2349 case MSR_MTRRfix4K_E8000:
2350 env->mtrr_fixed[8] = msrs[i].data;
2351 break;
2352 case MSR_MTRRfix4K_F0000:
2353 env->mtrr_fixed[9] = msrs[i].data;
2354 break;
2355 case MSR_MTRRfix4K_F8000:
2356 env->mtrr_fixed[10] = msrs[i].data;
2357 break;
2358 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2359 if (index & 1) {
2360 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2361 mtrr_top_bits;
2362 } else {
2363 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2364 }
2365 break;
2366 }
2367 }
2368
2369 return 0;
2370 }
2371
2372 static int kvm_put_mp_state(X86CPU *cpu)
2373 {
2374 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2375
2376 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2377 }
2378
2379 static int kvm_get_mp_state(X86CPU *cpu)
2380 {
2381 CPUState *cs = CPU(cpu);
2382 CPUX86State *env = &cpu->env;
2383 struct kvm_mp_state mp_state;
2384 int ret;
2385
2386 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2387 if (ret < 0) {
2388 return ret;
2389 }
2390 env->mp_state = mp_state.mp_state;
2391 if (kvm_irqchip_in_kernel()) {
2392 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2393 }
2394 return 0;
2395 }
2396
2397 static int kvm_get_apic(X86CPU *cpu)
2398 {
2399 DeviceState *apic = cpu->apic_state;
2400 struct kvm_lapic_state kapic;
2401 int ret;
2402
2403 if (apic && kvm_irqchip_in_kernel()) {
2404 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2405 if (ret < 0) {
2406 return ret;
2407 }
2408
2409 kvm_get_apic_state(apic, &kapic);
2410 }
2411 return 0;
2412 }
2413
2414 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2415 {
2416 CPUState *cs = CPU(cpu);
2417 CPUX86State *env = &cpu->env;
2418 struct kvm_vcpu_events events = {};
2419
2420 if (!kvm_has_vcpu_events()) {
2421 return 0;
2422 }
2423
2424 events.exception.injected = (env->exception_injected >= 0);
2425 events.exception.nr = env->exception_injected;
2426 events.exception.has_error_code = env->has_error_code;
2427 events.exception.error_code = env->error_code;
2428 events.exception.pad = 0;
2429
2430 events.interrupt.injected = (env->interrupt_injected >= 0);
2431 events.interrupt.nr = env->interrupt_injected;
2432 events.interrupt.soft = env->soft_interrupt;
2433
2434 events.nmi.injected = env->nmi_injected;
2435 events.nmi.pending = env->nmi_pending;
2436 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2437 events.nmi.pad = 0;
2438
2439 events.sipi_vector = env->sipi_vector;
2440 events.flags = 0;
2441
2442 if (has_msr_smbase) {
2443 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2444 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2445 if (kvm_irqchip_in_kernel()) {
2446 /* As soon as these are moved to the kernel, remove them
2447 * from cs->interrupt_request.
2448 */
2449 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2450 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2451 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2452 } else {
2453 /* Keep these in cs->interrupt_request. */
2454 events.smi.pending = 0;
2455 events.smi.latched_init = 0;
2456 }
2457 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2458 }
2459
2460 if (level >= KVM_PUT_RESET_STATE) {
2461 events.flags |=
2462 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2463 }
2464
2465 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2466 }
2467
2468 static int kvm_get_vcpu_events(X86CPU *cpu)
2469 {
2470 CPUX86State *env = &cpu->env;
2471 struct kvm_vcpu_events events;
2472 int ret;
2473
2474 if (!kvm_has_vcpu_events()) {
2475 return 0;
2476 }
2477
2478 memset(&events, 0, sizeof(events));
2479 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2480 if (ret < 0) {
2481 return ret;
2482 }
2483 env->exception_injected =
2484 events.exception.injected ? events.exception.nr : -1;
2485 env->has_error_code = events.exception.has_error_code;
2486 env->error_code = events.exception.error_code;
2487
2488 env->interrupt_injected =
2489 events.interrupt.injected ? events.interrupt.nr : -1;
2490 env->soft_interrupt = events.interrupt.soft;
2491
2492 env->nmi_injected = events.nmi.injected;
2493 env->nmi_pending = events.nmi.pending;
2494 if (events.nmi.masked) {
2495 env->hflags2 |= HF2_NMI_MASK;
2496 } else {
2497 env->hflags2 &= ~HF2_NMI_MASK;
2498 }
2499
2500 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2501 if (events.smi.smm) {
2502 env->hflags |= HF_SMM_MASK;
2503 } else {
2504 env->hflags &= ~HF_SMM_MASK;
2505 }
2506 if (events.smi.pending) {
2507 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2508 } else {
2509 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2510 }
2511 if (events.smi.smm_inside_nmi) {
2512 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2513 } else {
2514 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2515 }
2516 if (events.smi.latched_init) {
2517 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2518 } else {
2519 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2520 }
2521 }
2522
2523 env->sipi_vector = events.sipi_vector;
2524
2525 return 0;
2526 }
2527
2528 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2529 {
2530 CPUState *cs = CPU(cpu);
2531 CPUX86State *env = &cpu->env;
2532 int ret = 0;
2533 unsigned long reinject_trap = 0;
2534
2535 if (!kvm_has_vcpu_events()) {
2536 if (env->exception_injected == 1) {
2537 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2538 } else if (env->exception_injected == 3) {
2539 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2540 }
2541 env->exception_injected = -1;
2542 }
2543
2544 /*
2545 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2546 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2547 * by updating the debug state once again if single-stepping is on.
2548 * Another reason to call kvm_update_guest_debug here is a pending debug
2549 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2550 * reinject them via SET_GUEST_DEBUG.
2551 */
2552 if (reinject_trap ||
2553 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2554 ret = kvm_update_guest_debug(cs, reinject_trap);
2555 }
2556 return ret;
2557 }
2558
2559 static int kvm_put_debugregs(X86CPU *cpu)
2560 {
2561 CPUX86State *env = &cpu->env;
2562 struct kvm_debugregs dbgregs;
2563 int i;
2564
2565 if (!kvm_has_debugregs()) {
2566 return 0;
2567 }
2568
2569 for (i = 0; i < 4; i++) {
2570 dbgregs.db[i] = env->dr[i];
2571 }
2572 dbgregs.dr6 = env->dr[6];
2573 dbgregs.dr7 = env->dr[7];
2574 dbgregs.flags = 0;
2575
2576 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2577 }
2578
2579 static int kvm_get_debugregs(X86CPU *cpu)
2580 {
2581 CPUX86State *env = &cpu->env;
2582 struct kvm_debugregs dbgregs;
2583 int i, ret;
2584
2585 if (!kvm_has_debugregs()) {
2586 return 0;
2587 }
2588
2589 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2590 if (ret < 0) {
2591 return ret;
2592 }
2593 for (i = 0; i < 4; i++) {
2594 env->dr[i] = dbgregs.db[i];
2595 }
2596 env->dr[4] = env->dr[6] = dbgregs.dr6;
2597 env->dr[5] = env->dr[7] = dbgregs.dr7;
2598
2599 return 0;
2600 }
2601
2602 int kvm_arch_put_registers(CPUState *cpu, int level)
2603 {
2604 X86CPU *x86_cpu = X86_CPU(cpu);
2605 int ret;
2606
2607 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2608
2609 if (level >= KVM_PUT_RESET_STATE) {
2610 ret = kvm_put_msr_feature_control(x86_cpu);
2611 if (ret < 0) {
2612 return ret;
2613 }
2614 }
2615
2616 if (level == KVM_PUT_FULL_STATE) {
2617 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2618 * because TSC frequency mismatch shouldn't abort migration,
2619 * unless the user explicitly asked for a more strict TSC
2620 * setting (e.g. using an explicit "tsc-freq" option).
2621 */
2622 kvm_arch_set_tsc_khz(cpu);
2623 }
2624
2625 ret = kvm_getput_regs(x86_cpu, 1);
2626 if (ret < 0) {
2627 return ret;
2628 }
2629 ret = kvm_put_xsave(x86_cpu);
2630 if (ret < 0) {
2631 return ret;
2632 }
2633 ret = kvm_put_xcrs(x86_cpu);
2634 if (ret < 0) {
2635 return ret;
2636 }
2637 ret = kvm_put_sregs(x86_cpu);
2638 if (ret < 0) {
2639 return ret;
2640 }
2641 /* must be before kvm_put_msrs */
2642 ret = kvm_inject_mce_oldstyle(x86_cpu);
2643 if (ret < 0) {
2644 return ret;
2645 }
2646 ret = kvm_put_msrs(x86_cpu, level);
2647 if (ret < 0) {
2648 return ret;
2649 }
2650 if (level >= KVM_PUT_RESET_STATE) {
2651 ret = kvm_put_mp_state(x86_cpu);
2652 if (ret < 0) {
2653 return ret;
2654 }
2655 }
2656
2657 ret = kvm_put_tscdeadline_msr(x86_cpu);
2658 if (ret < 0) {
2659 return ret;
2660 }
2661
2662 ret = kvm_put_vcpu_events(x86_cpu, level);
2663 if (ret < 0) {
2664 return ret;
2665 }
2666 ret = kvm_put_debugregs(x86_cpu);
2667 if (ret < 0) {
2668 return ret;
2669 }
2670 /* must be last */
2671 ret = kvm_guest_debug_workarounds(x86_cpu);
2672 if (ret < 0) {
2673 return ret;
2674 }
2675 return 0;
2676 }
2677
2678 int kvm_arch_get_registers(CPUState *cs)
2679 {
2680 X86CPU *cpu = X86_CPU(cs);
2681 int ret;
2682
2683 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2684
2685 ret = kvm_getput_regs(cpu, 0);
2686 if (ret < 0) {
2687 goto out;
2688 }
2689 ret = kvm_get_xsave(cpu);
2690 if (ret < 0) {
2691 goto out;
2692 }
2693 ret = kvm_get_xcrs(cpu);
2694 if (ret < 0) {
2695 goto out;
2696 }
2697 ret = kvm_get_sregs(cpu);
2698 if (ret < 0) {
2699 goto out;
2700 }
2701 ret = kvm_get_msrs(cpu);
2702 if (ret < 0) {
2703 goto out;
2704 }
2705 ret = kvm_get_mp_state(cpu);
2706 if (ret < 0) {
2707 goto out;
2708 }
2709 ret = kvm_get_apic(cpu);
2710 if (ret < 0) {
2711 goto out;
2712 }
2713 ret = kvm_get_vcpu_events(cpu);
2714 if (ret < 0) {
2715 goto out;
2716 }
2717 ret = kvm_get_debugregs(cpu);
2718 if (ret < 0) {
2719 goto out;
2720 }
2721 ret = 0;
2722 out:
2723 cpu_sync_bndcs_hflags(&cpu->env);
2724 return ret;
2725 }
2726
2727 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2728 {
2729 X86CPU *x86_cpu = X86_CPU(cpu);
2730 CPUX86State *env = &x86_cpu->env;
2731 int ret;
2732
2733 /* Inject NMI */
2734 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2735 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2736 qemu_mutex_lock_iothread();
2737 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2738 qemu_mutex_unlock_iothread();
2739 DPRINTF("injected NMI\n");
2740 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2741 if (ret < 0) {
2742 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2743 strerror(-ret));
2744 }
2745 }
2746 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2747 qemu_mutex_lock_iothread();
2748 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2749 qemu_mutex_unlock_iothread();
2750 DPRINTF("injected SMI\n");
2751 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2752 if (ret < 0) {
2753 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2754 strerror(-ret));
2755 }
2756 }
2757 }
2758
2759 if (!kvm_pic_in_kernel()) {
2760 qemu_mutex_lock_iothread();
2761 }
2762
2763 /* Force the VCPU out of its inner loop to process any INIT requests
2764 * or (for userspace APIC, but it is cheap to combine the checks here)
2765 * pending TPR access reports.
2766 */
2767 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2768 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2769 !(env->hflags & HF_SMM_MASK)) {
2770 cpu->exit_request = 1;
2771 }
2772 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2773 cpu->exit_request = 1;
2774 }
2775 }
2776
2777 if (!kvm_pic_in_kernel()) {
2778 /* Try to inject an interrupt if the guest can accept it */
2779 if (run->ready_for_interrupt_injection &&
2780 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2781 (env->eflags & IF_MASK)) {
2782 int irq;
2783
2784 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2785 irq = cpu_get_pic_interrupt(env);
2786 if (irq >= 0) {
2787 struct kvm_interrupt intr;
2788
2789 intr.irq = irq;
2790 DPRINTF("injected interrupt %d\n", irq);
2791 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2792 if (ret < 0) {
2793 fprintf(stderr,
2794 "KVM: injection failed, interrupt lost (%s)\n",
2795 strerror(-ret));
2796 }
2797 }
2798 }
2799
2800 /* If we have an interrupt but the guest is not ready to receive an
2801 * interrupt, request an interrupt window exit. This will
2802 * cause a return to userspace as soon as the guest is ready to
2803 * receive interrupts. */
2804 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2805 run->request_interrupt_window = 1;
2806 } else {
2807 run->request_interrupt_window = 0;
2808 }
2809
2810 DPRINTF("setting tpr\n");
2811 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2812
2813 qemu_mutex_unlock_iothread();
2814 }
2815 }
2816
2817 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2818 {
2819 X86CPU *x86_cpu = X86_CPU(cpu);
2820 CPUX86State *env = &x86_cpu->env;
2821
2822 if (run->flags & KVM_RUN_X86_SMM) {
2823 env->hflags |= HF_SMM_MASK;
2824 } else {
2825 env->hflags &= HF_SMM_MASK;
2826 }
2827 if (run->if_flag) {
2828 env->eflags |= IF_MASK;
2829 } else {
2830 env->eflags &= ~IF_MASK;
2831 }
2832
2833 /* We need to protect the apic state against concurrent accesses from
2834 * different threads in case the userspace irqchip is used. */
2835 if (!kvm_irqchip_in_kernel()) {
2836 qemu_mutex_lock_iothread();
2837 }
2838 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2839 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2840 if (!kvm_irqchip_in_kernel()) {
2841 qemu_mutex_unlock_iothread();
2842 }
2843 return cpu_get_mem_attrs(env);
2844 }
2845
2846 int kvm_arch_process_async_events(CPUState *cs)
2847 {
2848 X86CPU *cpu = X86_CPU(cs);
2849 CPUX86State *env = &cpu->env;
2850
2851 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2852 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2853 assert(env->mcg_cap);
2854
2855 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2856
2857 kvm_cpu_synchronize_state(cs);
2858
2859 if (env->exception_injected == EXCP08_DBLE) {
2860 /* this means triple fault */
2861 qemu_system_reset_request();
2862 cs->exit_request = 1;
2863 return 0;
2864 }
2865 env->exception_injected = EXCP12_MCHK;
2866 env->has_error_code = 0;
2867
2868 cs->halted = 0;
2869 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2870 env->mp_state = KVM_MP_STATE_RUNNABLE;
2871 }
2872 }
2873
2874 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2875 !(env->hflags & HF_SMM_MASK)) {
2876 kvm_cpu_synchronize_state(cs);
2877 do_cpu_init(cpu);
2878 }
2879
2880 if (kvm_irqchip_in_kernel()) {
2881 return 0;
2882 }
2883
2884 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2885 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2886 apic_poll_irq(cpu->apic_state);
2887 }
2888 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2889 (env->eflags & IF_MASK)) ||
2890 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2891 cs->halted = 0;
2892 }
2893 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2894 kvm_cpu_synchronize_state(cs);
2895 do_cpu_sipi(cpu);
2896 }
2897 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2898 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2899 kvm_cpu_synchronize_state(cs);
2900 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2901 env->tpr_access_type);
2902 }
2903
2904 return cs->halted;
2905 }
2906
2907 static int kvm_handle_halt(X86CPU *cpu)
2908 {
2909 CPUState *cs = CPU(cpu);
2910 CPUX86State *env = &cpu->env;
2911
2912 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2913 (env->eflags & IF_MASK)) &&
2914 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2915 cs->halted = 1;
2916 return EXCP_HLT;
2917 }
2918
2919 return 0;
2920 }
2921
2922 static int kvm_handle_tpr_access(X86CPU *cpu)
2923 {
2924 CPUState *cs = CPU(cpu);
2925 struct kvm_run *run = cs->kvm_run;
2926
2927 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2928 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2929 : TPR_ACCESS_READ);
2930 return 1;
2931 }
2932
2933 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2934 {
2935 static const uint8_t int3 = 0xcc;
2936
2937 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2938 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2939 return -EINVAL;
2940 }
2941 return 0;
2942 }
2943
2944 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2945 {
2946 uint8_t int3;
2947
2948 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2949 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2950 return -EINVAL;
2951 }
2952 return 0;
2953 }
2954
2955 static struct {
2956 target_ulong addr;
2957 int len;
2958 int type;
2959 } hw_breakpoint[4];
2960
2961 static int nb_hw_breakpoint;
2962
2963 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2964 {
2965 int n;
2966
2967 for (n = 0; n < nb_hw_breakpoint; n++) {
2968 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2969 (hw_breakpoint[n].len == len || len == -1)) {
2970 return n;
2971 }
2972 }
2973 return -1;
2974 }
2975
2976 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2977 target_ulong len, int type)
2978 {
2979 switch (type) {
2980 case GDB_BREAKPOINT_HW:
2981 len = 1;
2982 break;
2983 case GDB_WATCHPOINT_WRITE:
2984 case GDB_WATCHPOINT_ACCESS:
2985 switch (len) {
2986 case 1:
2987 break;
2988 case 2:
2989 case 4:
2990 case 8:
2991 if (addr & (len - 1)) {
2992 return -EINVAL;
2993 }
2994 break;
2995 default:
2996 return -EINVAL;
2997 }
2998 break;
2999 default:
3000 return -ENOSYS;
3001 }
3002
3003 if (nb_hw_breakpoint == 4) {
3004 return -ENOBUFS;
3005 }
3006 if (find_hw_breakpoint(addr, len, type) >= 0) {
3007 return -EEXIST;
3008 }
3009 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3010 hw_breakpoint[nb_hw_breakpoint].len = len;
3011 hw_breakpoint[nb_hw_breakpoint].type = type;
3012 nb_hw_breakpoint++;
3013
3014 return 0;
3015 }
3016
3017 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3018 target_ulong len, int type)
3019 {
3020 int n;
3021
3022 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3023 if (n < 0) {
3024 return -ENOENT;
3025 }
3026 nb_hw_breakpoint--;
3027 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3028
3029 return 0;
3030 }
3031
3032 void kvm_arch_remove_all_hw_breakpoints(void)
3033 {
3034 nb_hw_breakpoint = 0;
3035 }
3036
3037 static CPUWatchpoint hw_watchpoint;
3038
3039 static int kvm_handle_debug(X86CPU *cpu,
3040 struct kvm_debug_exit_arch *arch_info)
3041 {
3042 CPUState *cs = CPU(cpu);
3043 CPUX86State *env = &cpu->env;
3044 int ret = 0;
3045 int n;
3046
3047 if (arch_info->exception == 1) {
3048 if (arch_info->dr6 & (1 << 14)) {
3049 if (cs->singlestep_enabled) {
3050 ret = EXCP_DEBUG;
3051 }
3052 } else {
3053 for (n = 0; n < 4; n++) {
3054 if (arch_info->dr6 & (1 << n)) {
3055 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3056 case 0x0:
3057 ret = EXCP_DEBUG;
3058 break;
3059 case 0x1:
3060 ret = EXCP_DEBUG;
3061 cs->watchpoint_hit = &hw_watchpoint;
3062 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3063 hw_watchpoint.flags = BP_MEM_WRITE;
3064 break;
3065 case 0x3:
3066 ret = EXCP_DEBUG;
3067 cs->watchpoint_hit = &hw_watchpoint;
3068 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3069 hw_watchpoint.flags = BP_MEM_ACCESS;
3070 break;
3071 }
3072 }
3073 }
3074 }
3075 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3076 ret = EXCP_DEBUG;
3077 }
3078 if (ret == 0) {
3079 cpu_synchronize_state(cs);
3080 assert(env->exception_injected == -1);
3081
3082 /* pass to guest */
3083 env->exception_injected = arch_info->exception;
3084 env->has_error_code = 0;
3085 }
3086
3087 return ret;
3088 }
3089
3090 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3091 {
3092 const uint8_t type_code[] = {
3093 [GDB_BREAKPOINT_HW] = 0x0,
3094 [GDB_WATCHPOINT_WRITE] = 0x1,
3095 [GDB_WATCHPOINT_ACCESS] = 0x3
3096 };
3097 const uint8_t len_code[] = {
3098 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3099 };
3100 int n;
3101
3102 if (kvm_sw_breakpoints_active(cpu)) {
3103 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3104 }
3105 if (nb_hw_breakpoint > 0) {
3106 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3107 dbg->arch.debugreg[7] = 0x0600;
3108 for (n = 0; n < nb_hw_breakpoint; n++) {
3109 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3110 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3111 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3112 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3113 }
3114 }
3115 }
3116
3117 static bool host_supports_vmx(void)
3118 {
3119 uint32_t ecx, unused;
3120
3121 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3122 return ecx & CPUID_EXT_VMX;
3123 }
3124
3125 #define VMX_INVALID_GUEST_STATE 0x80000021
3126
3127 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3128 {
3129 X86CPU *cpu = X86_CPU(cs);
3130 uint64_t code;
3131 int ret;
3132
3133 switch (run->exit_reason) {
3134 case KVM_EXIT_HLT:
3135 DPRINTF("handle_hlt\n");
3136 qemu_mutex_lock_iothread();
3137 ret = kvm_handle_halt(cpu);
3138 qemu_mutex_unlock_iothread();
3139 break;
3140 case KVM_EXIT_SET_TPR:
3141 ret = 0;
3142 break;
3143 case KVM_EXIT_TPR_ACCESS:
3144 qemu_mutex_lock_iothread();
3145 ret = kvm_handle_tpr_access(cpu);
3146 qemu_mutex_unlock_iothread();
3147 break;
3148 case KVM_EXIT_FAIL_ENTRY:
3149 code = run->fail_entry.hardware_entry_failure_reason;
3150 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3151 code);
3152 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3153 fprintf(stderr,
3154 "\nIf you're running a guest on an Intel machine without "
3155 "unrestricted mode\n"
3156 "support, the failure can be most likely due to the guest "
3157 "entering an invalid\n"
3158 "state for Intel VT. For example, the guest maybe running "
3159 "in big real mode\n"
3160 "which is not supported on less recent Intel processors."
3161 "\n\n");
3162 }
3163 ret = -1;
3164 break;
3165 case KVM_EXIT_EXCEPTION:
3166 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3167 run->ex.exception, run->ex.error_code);
3168 ret = -1;
3169 break;
3170 case KVM_EXIT_DEBUG:
3171 DPRINTF("kvm_exit_debug\n");
3172 qemu_mutex_lock_iothread();
3173 ret = kvm_handle_debug(cpu, &run->debug.arch);
3174 qemu_mutex_unlock_iothread();
3175 break;
3176 case KVM_EXIT_HYPERV:
3177 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3178 break;
3179 case KVM_EXIT_IOAPIC_EOI:
3180 ioapic_eoi_broadcast(run->eoi.vector);
3181 ret = 0;
3182 break;
3183 default:
3184 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3185 ret = -1;
3186 break;
3187 }
3188
3189 return ret;
3190 }
3191
3192 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3193 {
3194 X86CPU *cpu = X86_CPU(cs);
3195 CPUX86State *env = &cpu->env;
3196
3197 kvm_cpu_synchronize_state(cs);
3198 return !(env->cr[0] & CR0_PE_MASK) ||
3199 ((env->segs[R_CS].selector & 3) != 3);
3200 }
3201
3202 void kvm_arch_init_irq_routing(KVMState *s)
3203 {
3204 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3205 /* If kernel can't do irq routing, interrupt source
3206 * override 0->2 cannot be set up as required by HPET.
3207 * So we have to disable it.
3208 */
3209 no_hpet = 1;
3210 }
3211 /* We know at this point that we're using the in-kernel
3212 * irqchip, so we can use irqfds, and on x86 we know
3213 * we can use msi via irqfd and GSI routing.
3214 */
3215 kvm_msi_via_irqfd_allowed = true;
3216 kvm_gsi_routing_allowed = true;
3217
3218 if (kvm_irqchip_is_split()) {
3219 int i;
3220
3221 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3222 MSI routes for signaling interrupts to the local apics. */
3223 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3224 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3225 error_report("Could not enable split IRQ mode.");
3226 exit(1);
3227 }
3228 }
3229 }
3230 }
3231
3232 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3233 {
3234 int ret;
3235 if (machine_kernel_irqchip_split(ms)) {
3236 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3237 if (ret) {
3238 error_report("Could not enable split irqchip mode: %s",
3239 strerror(-ret));
3240 exit(1);
3241 } else {
3242 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3243 kvm_split_irqchip = true;
3244 return 1;
3245 }
3246 } else {
3247 return 0;
3248 }
3249 }
3250
3251 /* Classic KVM device assignment interface. Will remain x86 only. */
3252 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3253 uint32_t flags, uint32_t *dev_id)
3254 {
3255 struct kvm_assigned_pci_dev dev_data = {
3256 .segnr = dev_addr->domain,
3257 .busnr = dev_addr->bus,
3258 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3259 .flags = flags,
3260 };
3261 int ret;
3262
3263 dev_data.assigned_dev_id =
3264 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3265
3266 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3267 if (ret < 0) {
3268 return ret;
3269 }
3270
3271 *dev_id = dev_data.assigned_dev_id;
3272
3273 return 0;
3274 }
3275
3276 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3277 {
3278 struct kvm_assigned_pci_dev dev_data = {
3279 .assigned_dev_id = dev_id,
3280 };
3281
3282 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3283 }
3284
3285 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3286 uint32_t irq_type, uint32_t guest_irq)
3287 {
3288 struct kvm_assigned_irq assigned_irq = {
3289 .assigned_dev_id = dev_id,
3290 .guest_irq = guest_irq,
3291 .flags = irq_type,
3292 };
3293
3294 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3295 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3296 } else {
3297 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3298 }
3299 }
3300
3301 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3302 uint32_t guest_irq)
3303 {
3304 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3305 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3306
3307 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3308 }
3309
3310 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3311 {
3312 struct kvm_assigned_pci_dev dev_data = {
3313 .assigned_dev_id = dev_id,
3314 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3315 };
3316
3317 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3318 }
3319
3320 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3321 uint32_t type)
3322 {
3323 struct kvm_assigned_irq assigned_irq = {
3324 .assigned_dev_id = dev_id,
3325 .flags = type,
3326 };
3327
3328 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3329 }
3330
3331 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3332 {
3333 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3334 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3335 }
3336
3337 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3338 {
3339 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3340 KVM_DEV_IRQ_GUEST_MSI, virq);
3341 }
3342
3343 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3344 {
3345 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3346 KVM_DEV_IRQ_HOST_MSI);
3347 }
3348
3349 bool kvm_device_msix_supported(KVMState *s)
3350 {
3351 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3352 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3353 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3354 }
3355
3356 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3357 uint32_t nr_vectors)
3358 {
3359 struct kvm_assigned_msix_nr msix_nr = {
3360 .assigned_dev_id = dev_id,
3361 .entry_nr = nr_vectors,
3362 };
3363
3364 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3365 }
3366
3367 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3368 int virq)
3369 {
3370 struct kvm_assigned_msix_entry msix_entry = {
3371 .assigned_dev_id = dev_id,
3372 .gsi = virq,
3373 .entry = vector,
3374 };
3375
3376 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3377 }
3378
3379 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3380 {
3381 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3382 KVM_DEV_IRQ_GUEST_MSIX, 0);
3383 }
3384
3385 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3386 {
3387 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3388 KVM_DEV_IRQ_HOST_MSIX);
3389 }
3390
3391 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3392 uint64_t address, uint32_t data, PCIDevice *dev)
3393 {
3394 X86IOMMUState *iommu = x86_iommu_get_default();
3395
3396 if (iommu) {
3397 int ret;
3398 MSIMessage src, dst;
3399 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3400
3401 src.address = route->u.msi.address_hi;
3402 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3403 src.address |= route->u.msi.address_lo;
3404 src.data = route->u.msi.data;
3405
3406 ret = class->int_remap(iommu, &src, &dst, dev ? \
3407 pci_requester_id(dev) : \
3408 X86_IOMMU_SID_INVALID);
3409 if (ret) {
3410 trace_kvm_x86_fixup_msi_error(route->gsi);
3411 return 1;
3412 }
3413
3414 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3415 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3416 route->u.msi.data = dst.data;
3417 }
3418
3419 return 0;
3420 }
3421
3422 typedef struct MSIRouteEntry MSIRouteEntry;
3423
3424 struct MSIRouteEntry {
3425 PCIDevice *dev; /* Device pointer */
3426 int vector; /* MSI/MSIX vector index */
3427 int virq; /* Virtual IRQ index */
3428 QLIST_ENTRY(MSIRouteEntry) list;
3429 };
3430
3431 /* List of used GSI routes */
3432 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3433 QLIST_HEAD_INITIALIZER(msi_route_list);
3434
3435 static void kvm_update_msi_routes_all(void *private, bool global,
3436 uint32_t index, uint32_t mask)
3437 {
3438 int cnt = 0;
3439 MSIRouteEntry *entry;
3440 MSIMessage msg;
3441 /* TODO: explicit route update */
3442 QLIST_FOREACH(entry, &msi_route_list, list) {
3443 cnt++;
3444 msg = pci_get_msi_message(entry->dev, entry->vector);
3445 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3446 msg, entry->dev);
3447 }
3448 kvm_irqchip_commit_routes(kvm_state);
3449 trace_kvm_x86_update_msi_routes(cnt);
3450 }
3451
3452 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3453 int vector, PCIDevice *dev)
3454 {
3455 static bool notify_list_inited = false;
3456 MSIRouteEntry *entry;
3457
3458 if (!dev) {
3459 /* These are (possibly) IOAPIC routes only used for split
3460 * kernel irqchip mode, while what we are housekeeping are
3461 * PCI devices only. */
3462 return 0;
3463 }
3464
3465 entry = g_new0(MSIRouteEntry, 1);
3466 entry->dev = dev;
3467 entry->vector = vector;
3468 entry->virq = route->gsi;
3469 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3470
3471 trace_kvm_x86_add_msi_route(route->gsi);
3472
3473 if (!notify_list_inited) {
3474 /* For the first time we do add route, add ourselves into
3475 * IOMMU's IEC notify list if needed. */
3476 X86IOMMUState *iommu = x86_iommu_get_default();
3477 if (iommu) {
3478 x86_iommu_iec_register_notifier(iommu,
3479 kvm_update_msi_routes_all,
3480 NULL);
3481 }
3482 notify_list_inited = true;
3483 }
3484 return 0;
3485 }
3486
3487 int kvm_arch_release_virq_post(int virq)
3488 {
3489 MSIRouteEntry *entry, *next;
3490 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3491 if (entry->virq == virq) {
3492 trace_kvm_x86_remove_msi_route(virq);
3493 QLIST_REMOVE(entry, list);
3494 break;
3495 }
3496 }
3497 return 0;
3498 }
3499
3500 int kvm_arch_msi_data_to_gsi(uint32_t data)
3501 {
3502 abort();
3503 }
AR7 emulation for QEMU