1 /* Xtensa configuration-specific ISA information.
3 Copyright (c) 2003-2019 Tensilica Inc.
5 Permission is hereby granted, free of charge, to any person obtaining
6 a copy of this software and associated documentation files (the
7 "Software"), to deal in the Software without restriction, including
8 without limitation the rights to use, copy, modify, merge, publish,
9 distribute, sublicense, and/or sell copies of the Software, and to
10 permit persons to whom the Software is furnished to do so, subject to
11 the following conditions:
13 The above copyright notice and this permission notice shall be included
14 in all copies or substantial portions of the Software.
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "xtensa-isa.h"
25 #include "xtensa-isa-internal.h"
30 static xtensa_sysreg_internal sysregs[] = {
35 { "PTEVADDR", 83, 0 },
37 { "CONFIGID0", 176, 0 },
38 { "CONFIGID1", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
44 { "CCOMPARE0", 240, 0 },
45 { "CCOMPARE1", 241, 0 },
46 { "VECBASE", 231, 0 },
49 { "EXCSAVE1", 209, 0 },
50 { "EXCSAVE2", 210, 0 },
52 { "EXCCAUSE", 232, 0 },
54 { "EXCVADDR", 238, 0 },
55 { "WINDOWBASE", 72, 0 },
56 { "WINDOWSTART", 73, 0 },
62 { "INTENABLE", 228, 0 },
63 { "ICOUNTLEVEL", 237, 0 },
64 { "DEBUGCAUSE", 233, 0 },
68 { "CPENABLE", 224, 0 },
69 { "SCOMPARE1", 12, 0 },
71 { "THREADPTR", 231, 1 },
72 { "AE_OVF_SAR", 240, 1 },
73 { "AE_BITHEAD", 241, 1 },
74 { "AE_TS_FTS_BU_BP", 242, 1 },
75 { "AE_SD_NO", 243, 1 }
78 #define NUM_SYSREGS 45
79 #define MAX_SPECIAL_REG 245
80 #define MAX_USER_REG 243
83 /* Processor states. */
85 static xtensa_state_internal states[] = {
90 { "INTERRUPT", 12, 0 },
96 { "EXCSAVE1", 32, 0 },
97 { "EXCSAVE2", 32, 0 },
100 { "PSINTLEVEL", 4, 0 },
106 { "EXCVADDR", 32, 0 },
107 { "WindowBase", 3, 0 },
108 { "WindowStart", 8, 0 },
109 { "PSCALLINC", 2, 0 },
114 { "THREADPTR", 32, 0 },
115 { "LITBADDR", 20, 0 },
119 { "InOCDMode", 1, 0 },
120 { "INTENABLE", 12, 0 },
121 { "ICOUNTLEVEL", 4, 0 },
122 { "DEBUGCAUSE", 6, 0 },
124 { "CCOMPARE0", 32, 0 },
125 { "CCOMPARE1", 32, 0 },
129 { "INSTPGSZID4", 2, 0 },
130 { "DATAPGSZID4", 2, 0 },
132 { "CPENABLE", 2, 0 },
133 { "SCOMPARE1", 32, 0 },
135 { "CCON", 1, XTENSA_STATE_IS_EXPORTED },
136 { "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED },
137 { "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED },
138 { "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED },
139 { "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED },
140 { "AE_OVERFLOW", 1, 0 },
142 { "AE_BITHEAD", 32, 0 },
143 { "AE_BITPTR", 4, 0 },
144 { "AE_BITSUSED", 4, 0 },
145 { "AE_TABLESIZE", 4, 0 },
146 { "AE_FIRST_TS", 4, 0 },
147 { "AE_NEXTOFFSET", 27, 0 },
148 { "AE_SEARCHDONE", 1, 0 }
151 #define NUM_STATES 63
153 enum xtensa_state_id {
207 STATE_WMPINT_TOGGLEEN,
220 /* Field definitions. */
223 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
226 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
231 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
234 tie_t = (val << 28) >> 28;
235 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
239 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
242 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
247 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
250 tie_t = (val << 28) >> 28;
251 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
255 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
258 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
263 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
266 tie_t = (val << 28) >> 28;
267 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
271 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
274 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
279 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
282 tie_t = (val << 28) >> 28;
283 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
287 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
290 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
295 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
298 tie_t = (val << 28) >> 28;
299 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
303 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
306 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
311 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
314 tie_t = (val << 28) >> 28;
315 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
319 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
322 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
327 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
330 tie_t = (val << 30) >> 30;
331 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
335 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
338 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
343 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
346 tie_t = (val << 30) >> 30;
347 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
351 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
354 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
355 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
360 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
363 tie_t = (val << 28) >> 28;
364 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
365 tie_t = (val << 24) >> 28;
366 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
370 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
373 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
374 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
379 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
382 tie_t = (val << 28) >> 28;
383 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
384 tie_t = (val << 24) >> 28;
385 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
389 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
392 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
397 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
400 tie_t = (val << 29) >> 29;
401 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
405 Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
408 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
413 Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
416 tie_t = (val << 31) >> 31;
417 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
421 Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
424 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
429 Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
432 tie_t = (val << 30) >> 30;
433 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
437 Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
440 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
445 Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
448 tie_t = (val << 30) >> 30;
449 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
453 Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
456 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
461 Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
464 tie_t = (val << 31) >> 31;
465 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
469 Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
472 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
477 Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
480 tie_t = (val << 30) >> 30;
481 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
485 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
488 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
493 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
496 tie_t = (val << 28) >> 28;
497 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
501 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
504 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
509 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
512 tie_t = (val << 28) >> 28;
513 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
517 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
520 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
525 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
528 tie_t = (val << 28) >> 28;
529 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
533 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
536 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
541 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
544 tie_t = (val << 28) >> 28;
545 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
549 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
552 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
557 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
560 tie_t = (val << 31) >> 31;
561 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
565 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
568 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
573 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
576 tie_t = (val << 31) >> 31;
577 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
581 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
584 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
589 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
592 tie_t = (val << 28) >> 28;
593 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
597 Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
600 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
601 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
602 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
607 Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
610 tie_t = (val << 28) >> 28;
611 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
612 tie_t = (val << 27) >> 31;
613 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
614 tie_t = (val << 22) >> 27;
615 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
619 Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
622 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
627 Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
630 tie_t = (val << 25) >> 25;
631 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
635 Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
638 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
639 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
644 Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
647 tie_t = (val << 28) >> 28;
648 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
649 tie_t = (val << 26) >> 30;
650 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
654 Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
657 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
658 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
663 Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
666 tie_t = (val << 31) >> 31;
667 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
668 tie_t = (val << 22) >> 23;
669 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
673 Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
676 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
681 Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
684 tie_t = (val << 29) >> 29;
685 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
689 Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
692 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
693 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
698 Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
701 tie_t = (val << 31) >> 31;
702 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
703 tie_t = (val << 22) >> 23;
704 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
708 Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
711 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
712 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
713 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
718 Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
721 tie_t = (val << 31) >> 31;
722 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
723 tie_t = (val << 27) >> 28;
724 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
725 tie_t = (val << 25) >> 30;
726 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
730 Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
733 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
734 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
735 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
740 Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
743 tie_t = (val << 31) >> 31;
744 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
745 tie_t = (val << 27) >> 28;
746 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
747 tie_t = (val << 25) >> 30;
748 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
752 Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
755 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
756 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
757 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
762 Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
765 tie_t = (val << 31) >> 31;
766 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
767 tie_t = (val << 27) >> 28;
768 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
769 tie_t = (val << 25) >> 30;
770 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
774 Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
777 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
778 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
779 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
784 Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
787 tie_t = (val << 31) >> 31;
788 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
789 tie_t = (val << 27) >> 28;
790 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
791 tie_t = (val << 25) >> 30;
792 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
796 Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
799 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
800 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
805 Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
808 tie_t = (val << 30) >> 30;
809 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
810 tie_t = (val << 28) >> 30;
811 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
815 Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
818 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
823 Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
826 tie_t = (val << 29) >> 29;
827 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
831 Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
834 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
835 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
836 tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
841 Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
844 tie_t = (val << 31) >> 31;
845 insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
846 tie_t = (val << 29) >> 30;
847 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
848 tie_t = (val << 27) >> 30;
849 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
853 Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn)
856 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
861 Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
864 tie_t = (val << 30) >> 30;
865 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
869 Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
872 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
873 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
878 Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
881 tie_t = (val << 28) >> 28;
882 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
883 tie_t = (val << 26) >> 30;
884 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
888 Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
891 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
892 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
897 Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
900 tie_t = (val << 28) >> 28;
901 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
902 tie_t = (val << 26) >> 30;
903 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
907 Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
910 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
915 Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
918 tie_t = (val << 30) >> 30;
919 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
923 Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
926 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
927 tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
932 Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
935 tie_t = (val << 28) >> 28;
936 insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
937 tie_t = (val << 25) >> 29;
938 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
942 Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
945 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
946 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
951 Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
954 tie_t = (val << 31) >> 31;
955 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
956 tie_t = (val << 22) >> 23;
957 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
961 Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
964 tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
965 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
966 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
971 Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
974 tie_t = (val << 31) >> 31;
975 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
976 tie_t = (val << 30) >> 31;
977 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
978 tie_t = (val << 23) >> 25;
979 insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
983 Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn)
986 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
991 Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
994 tie_t = (val << 30) >> 30;
995 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
999 Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1002 tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
1003 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
1004 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1009 Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1012 tie_t = (val << 31) >> 31;
1013 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1014 tie_t = (val << 29) >> 30;
1015 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
1016 tie_t = (val << 22) >> 25;
1017 insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
1021 Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1024 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1029 Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1032 tie_t = (val << 31) >> 31;
1033 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1037 Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1040 tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
1041 tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
1046 Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1049 tie_t = (val << 28) >> 28;
1050 insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
1051 tie_t = (val << 21) >> 25;
1052 insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
1056 Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1059 tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
1060 tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
1065 Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1068 tie_t = (val << 28) >> 28;
1069 insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
1070 tie_t = (val << 21) >> 25;
1071 insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
1075 Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1078 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
1079 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1084 Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1087 tie_t = (val << 31) >> 31;
1088 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1089 tie_t = (val << 22) >> 23;
1090 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
1094 Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1097 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
1098 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1103 Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1106 tie_t = (val << 31) >> 31;
1107 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1108 tie_t = (val << 22) >> 23;
1109 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
1113 Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1116 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1117 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1118 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1123 Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1126 tie_t = (val << 28) >> 28;
1127 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1128 tie_t = (val << 26) >> 30;
1129 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1130 tie_t = (val << 21) >> 27;
1131 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1135 Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1138 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1139 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1144 Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1147 tie_t = (val << 25) >> 25;
1148 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1149 tie_t = (val << 20) >> 27;
1150 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1154 Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1157 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1158 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1163 Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1166 tie_t = (val << 28) >> 28;
1167 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1168 tie_t = (val << 23) >> 27;
1169 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1173 Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1176 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1181 Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1184 tie_t = (val << 30) >> 30;
1185 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1189 Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1192 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1193 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1194 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1199 Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1202 tie_t = (val << 28) >> 28;
1203 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1204 tie_t = (val << 26) >> 30;
1205 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1206 tie_t = (val << 21) >> 27;
1207 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1211 Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1214 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1215 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1216 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1221 Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1224 tie_t = (val << 25) >> 25;
1225 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1226 tie_t = (val << 24) >> 31;
1227 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1228 tie_t = (val << 21) >> 29;
1229 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1233 Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1236 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1241 Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1244 tie_t = (val << 31) >> 31;
1245 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1249 Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1252 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1253 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1254 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1259 Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1262 tie_t = (val << 28) >> 28;
1263 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1264 tie_t = (val << 27) >> 31;
1265 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1266 tie_t = (val << 22) >> 27;
1267 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1271 Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1274 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1275 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
1276 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1281 Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1284 tie_t = (val << 28) >> 28;
1285 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1286 tie_t = (val << 26) >> 30;
1287 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
1288 tie_t = (val << 21) >> 27;
1289 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1293 Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1296 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
1297 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1302 Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1305 tie_t = (val << 25) >> 25;
1306 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1307 tie_t = (val << 20) >> 27;
1308 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
1312 Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1315 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1316 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1317 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1322 Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1325 tie_t = (val << 31) >> 31;
1326 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1327 tie_t = (val << 27) >> 28;
1328 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1329 tie_t = (val << 25) >> 30;
1330 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1334 Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1337 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1338 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1339 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1344 Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1347 tie_t = (val << 31) >> 31;
1348 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1349 tie_t = (val << 27) >> 28;
1350 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1351 tie_t = (val << 25) >> 30;
1352 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1356 Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1359 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1360 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1365 Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1368 tie_t = (val << 30) >> 30;
1369 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1370 tie_t = (val << 28) >> 30;
1371 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1375 Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1378 tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26);
1383 Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1386 tie_t = (val << 26) >> 26;
1387 insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3);
1391 Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1394 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1395 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1396 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1401 Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1404 tie_t = (val << 31) >> 31;
1405 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1406 tie_t = (val << 27) >> 28;
1407 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1408 tie_t = (val << 25) >> 30;
1409 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1413 Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1416 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1417 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1418 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1423 Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1426 tie_t = (val << 31) >> 31;
1427 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1428 tie_t = (val << 27) >> 28;
1429 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1430 tie_t = (val << 25) >> 30;
1431 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1435 Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1438 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1439 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1440 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1445 Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1448 tie_t = (val << 31) >> 31;
1449 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1450 tie_t = (val << 27) >> 28;
1451 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1452 tie_t = (val << 25) >> 30;
1453 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1457 Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1460 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1461 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1466 Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1469 tie_t = (val << 30) >> 30;
1470 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1471 tie_t = (val << 28) >> 30;
1472 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1476 Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1479 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1480 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1485 Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1488 tie_t = (val << 30) >> 30;
1489 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1490 tie_t = (val << 28) >> 30;
1491 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1495 Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1498 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1499 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1500 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1505 Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1508 tie_t = (val << 31) >> 31;
1509 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1510 tie_t = (val << 27) >> 28;
1511 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1512 tie_t = (val << 25) >> 30;
1513 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1517 Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1520 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1521 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1522 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1527 Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1530 tie_t = (val << 31) >> 31;
1531 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1532 tie_t = (val << 27) >> 28;
1533 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1534 tie_t = (val << 25) >> 30;
1535 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1539 Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1542 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1543 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1544 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1549 Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1552 tie_t = (val << 31) >> 31;
1553 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1554 tie_t = (val << 27) >> 28;
1555 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1556 tie_t = (val << 25) >> 30;
1557 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1561 Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1564 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1565 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1570 Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1573 tie_t = (val << 29) >> 29;
1574 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1575 tie_t = (val << 27) >> 30;
1576 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1580 Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1583 tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27);
1588 Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1591 tie_t = (val << 27) >> 27;
1592 insn[0] = (insn[0] & ~0xf8) | (tie_t << 3);
1596 Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1599 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1600 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1601 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1606 Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1609 tie_t = (val << 31) >> 31;
1610 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1611 tie_t = (val << 27) >> 28;
1612 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1613 tie_t = (val << 25) >> 30;
1614 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1618 Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1621 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1622 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1623 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1628 Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1631 tie_t = (val << 31) >> 31;
1632 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1633 tie_t = (val << 27) >> 28;
1634 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1635 tie_t = (val << 25) >> 30;
1636 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1640 Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1643 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1644 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1645 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1650 Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1653 tie_t = (val << 31) >> 31;
1654 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1655 tie_t = (val << 27) >> 28;
1656 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1657 tie_t = (val << 25) >> 30;
1658 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1662 Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1665 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1666 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
1667 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
1672 Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1675 tie_t = (val << 31) >> 31;
1676 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
1677 tie_t = (val << 27) >> 28;
1678 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
1679 tie_t = (val << 25) >> 30;
1680 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1684 Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1687 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1688 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1689 tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
1694 Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1697 tie_t = (val << 30) >> 30;
1698 insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
1699 tie_t = (val << 28) >> 30;
1700 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1701 tie_t = (val << 26) >> 30;
1702 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1706 Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1709 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1714 Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1717 tie_t = (val << 31) >> 31;
1718 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1722 Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1725 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1726 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1727 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
1732 Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1735 tie_t = (val << 29) >> 29;
1736 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
1737 tie_t = (val << 27) >> 30;
1738 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1739 tie_t = (val << 25) >> 30;
1740 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1744 Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1747 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1748 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
1749 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
1754 Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1757 tie_t = (val << 29) >> 29;
1758 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
1759 tie_t = (val << 27) >> 30;
1760 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
1761 tie_t = (val << 25) >> 30;
1762 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1766 Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1769 tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
1774 Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1777 tie_t = (val << 31) >> 31;
1778 insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
1782 Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1785 tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
1786 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1791 Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1794 tie_t = (val << 25) >> 25;
1795 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1796 tie_t = (val << 23) >> 30;
1797 insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
1801 Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1804 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1805 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1810 Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1813 tie_t = (val << 25) >> 25;
1814 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1815 tie_t = (val << 22) >> 29;
1816 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1820 Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1823 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1824 tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27);
1829 Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1832 tie_t = (val << 27) >> 27;
1833 insn[0] = (insn[0] & ~0x7c) | (tie_t << 2);
1834 tie_t = (val << 24) >> 29;
1835 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1839 Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1842 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
1843 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
1848 Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1851 tie_t = (val << 30) >> 30;
1852 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
1853 tie_t = (val << 28) >> 30;
1854 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
1858 Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1861 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1862 tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
1867 Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1870 tie_t = (val << 23) >> 23;
1871 insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
1872 tie_t = (val << 20) >> 29;
1873 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1877 Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1880 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1881 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1886 Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1889 tie_t = (val << 25) >> 25;
1890 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1891 tie_t = (val << 22) >> 29;
1892 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1896 Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1899 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1900 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1905 Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1908 tie_t = (val << 25) >> 25;
1909 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1910 tie_t = (val << 22) >> 29;
1911 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1915 Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1918 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1919 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1924 Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1927 tie_t = (val << 29) >> 29;
1928 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1929 tie_t = (val << 26) >> 29;
1930 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1934 Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1937 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1938 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1943 Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1946 tie_t = (val << 29) >> 29;
1947 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1948 tie_t = (val << 26) >> 29;
1949 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1953 Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1956 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1957 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1962 Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1965 tie_t = (val << 25) >> 25;
1966 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1967 tie_t = (val << 22) >> 29;
1968 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1972 Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1975 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1976 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1981 Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
1984 tie_t = (val << 25) >> 25;
1985 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1986 tie_t = (val << 22) >> 29;
1987 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
1991 Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
1994 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
1995 tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
2000 Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2003 tie_t = (val << 23) >> 23;
2004 insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
2005 tie_t = (val << 20) >> 29;
2006 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2010 Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2013 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2014 tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26);
2019 Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2022 tie_t = (val << 26) >> 26;
2023 insn[0] = (insn[0] & ~0x7e) | (tie_t << 1);
2024 tie_t = (val << 23) >> 29;
2025 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2029 Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2032 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2033 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
2038 Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2041 tie_t = (val << 31) >> 31;
2042 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
2043 tie_t = (val << 29) >> 30;
2044 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2048 Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2051 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2052 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2057 Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2060 tie_t = (val << 25) >> 25;
2061 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2062 tie_t = (val << 22) >> 29;
2063 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2067 Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2070 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2071 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2076 Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2079 tie_t = (val << 25) >> 25;
2080 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2081 tie_t = (val << 22) >> 29;
2082 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2086 Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2089 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2090 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2095 Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2098 tie_t = (val << 25) >> 25;
2099 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2100 tie_t = (val << 22) >> 29;
2101 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2105 Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2108 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2109 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2114 Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2117 tie_t = (val << 25) >> 25;
2118 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2119 tie_t = (val << 22) >> 29;
2120 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2124 Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2127 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
2132 Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2135 tie_t = (val << 27) >> 27;
2136 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
2140 Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2143 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
2144 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2149 Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2152 tie_t = (val << 31) >> 31;
2153 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2154 tie_t = (val << 22) >> 23;
2155 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
2159 Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2162 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
2163 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2168 Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2171 tie_t = (val << 31) >> 31;
2172 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2173 tie_t = (val << 22) >> 23;
2174 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
2178 Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2181 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
2182 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2187 Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2190 tie_t = (val << 31) >> 31;
2191 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2192 tie_t = (val << 22) >> 23;
2193 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
2197 Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2200 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2205 Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2208 tie_t = (val << 30) >> 30;
2209 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2213 Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2216 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2221 Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2224 tie_t = (val << 29) >> 29;
2225 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2229 Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2232 tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
2233 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
2238 Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2241 tie_t = (val << 31) >> 31;
2242 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
2243 tie_t = (val << 24) >> 25;
2244 insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
2248 Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2251 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
2252 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2257 Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2260 tie_t = (val << 29) >> 29;
2261 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2262 tie_t = (val << 27) >> 30;
2263 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2267 Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2270 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2271 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2276 Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2279 tie_t = (val << 31) >> 31;
2280 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2281 tie_t = (val << 28) >> 29;
2282 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2286 Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2289 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
2290 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2295 Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2298 tie_t = (val << 30) >> 30;
2299 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2300 tie_t = (val << 28) >> 30;
2301 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2305 Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2308 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
2309 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2314 Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2317 tie_t = (val << 29) >> 29;
2318 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2319 tie_t = (val << 26) >> 29;
2320 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
2324 Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2327 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
2332 Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2335 tie_t = (val << 30) >> 30;
2336 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2340 Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2343 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2344 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2345 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2350 Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2353 tie_t = (val << 28) >> 28;
2354 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2355 tie_t = (val << 26) >> 30;
2356 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2357 tie_t = (val << 24) >> 30;
2358 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2362 Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2365 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2366 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2367 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2372 Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2375 tie_t = (val << 28) >> 28;
2376 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2377 tie_t = (val << 26) >> 30;
2378 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2379 tie_t = (val << 24) >> 30;
2380 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2384 Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2387 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2388 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2389 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2394 Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2397 tie_t = (val << 28) >> 28;
2398 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2399 tie_t = (val << 26) >> 30;
2400 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2401 tie_t = (val << 24) >> 30;
2402 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2406 Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2409 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2410 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2411 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2416 Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2419 tie_t = (val << 28) >> 28;
2420 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2421 tie_t = (val << 26) >> 30;
2422 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2423 tie_t = (val << 24) >> 30;
2424 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2428 Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2431 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2432 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2433 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2438 Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2441 tie_t = (val << 28) >> 28;
2442 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2443 tie_t = (val << 26) >> 30;
2444 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2445 tie_t = (val << 24) >> 30;
2446 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2450 Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2453 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2454 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2455 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2460 Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2463 tie_t = (val << 28) >> 28;
2464 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2465 tie_t = (val << 26) >> 30;
2466 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2467 tie_t = (val << 24) >> 30;
2468 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2472 Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2475 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2476 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2477 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2482 Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2485 tie_t = (val << 28) >> 28;
2486 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2487 tie_t = (val << 26) >> 30;
2488 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2489 tie_t = (val << 24) >> 30;
2490 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2494 Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2497 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2498 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2499 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2504 Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2507 tie_t = (val << 28) >> 28;
2508 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2509 tie_t = (val << 26) >> 30;
2510 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2511 tie_t = (val << 24) >> 30;
2512 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2516 Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2519 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2520 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2521 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2526 Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2529 tie_t = (val << 28) >> 28;
2530 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2531 tie_t = (val << 26) >> 30;
2532 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2533 tie_t = (val << 24) >> 30;
2534 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2538 Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2541 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2542 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2543 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2548 Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2551 tie_t = (val << 28) >> 28;
2552 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2553 tie_t = (val << 26) >> 30;
2554 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2555 tie_t = (val << 24) >> 30;
2556 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2560 Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2563 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2564 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2565 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2570 Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2573 tie_t = (val << 28) >> 28;
2574 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2575 tie_t = (val << 26) >> 30;
2576 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2577 tie_t = (val << 24) >> 30;
2578 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2582 Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2585 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2586 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2587 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2592 Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2595 tie_t = (val << 28) >> 28;
2596 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2597 tie_t = (val << 26) >> 30;
2598 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2599 tie_t = (val << 24) >> 30;
2600 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2604 Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2607 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2608 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2609 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2614 Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2617 tie_t = (val << 28) >> 28;
2618 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2619 tie_t = (val << 26) >> 30;
2620 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2621 tie_t = (val << 24) >> 30;
2622 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2626 Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2629 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2630 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2631 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2636 Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2639 tie_t = (val << 28) >> 28;
2640 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2641 tie_t = (val << 26) >> 30;
2642 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2643 tie_t = (val << 24) >> 30;
2644 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2648 Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2651 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2652 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2653 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2658 Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2661 tie_t = (val << 28) >> 28;
2662 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2663 tie_t = (val << 26) >> 30;
2664 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2665 tie_t = (val << 24) >> 30;
2666 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2670 Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2673 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2674 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2675 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2680 Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2683 tie_t = (val << 28) >> 28;
2684 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2685 tie_t = (val << 26) >> 30;
2686 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2687 tie_t = (val << 24) >> 30;
2688 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2692 Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2695 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2696 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2697 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2702 Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2705 tie_t = (val << 28) >> 28;
2706 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2707 tie_t = (val << 26) >> 30;
2708 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2709 tie_t = (val << 24) >> 30;
2710 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2714 Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2717 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2718 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2719 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2724 Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2727 tie_t = (val << 28) >> 28;
2728 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2729 tie_t = (val << 26) >> 30;
2730 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2731 tie_t = (val << 24) >> 30;
2732 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2736 Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2739 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2740 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2741 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2746 Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2749 tie_t = (val << 28) >> 28;
2750 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2751 tie_t = (val << 26) >> 30;
2752 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2753 tie_t = (val << 24) >> 30;
2754 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2758 Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2761 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2762 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2763 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2768 Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2771 tie_t = (val << 28) >> 28;
2772 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2773 tie_t = (val << 26) >> 30;
2774 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2775 tie_t = (val << 24) >> 30;
2776 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2780 Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2783 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2784 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2785 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2790 Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2793 tie_t = (val << 28) >> 28;
2794 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2795 tie_t = (val << 26) >> 30;
2796 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2797 tie_t = (val << 24) >> 30;
2798 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2802 Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2805 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2810 Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2813 tie_t = (val << 31) >> 31;
2814 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2818 Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2821 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2822 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2823 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2828 Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2831 tie_t = (val << 28) >> 28;
2832 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2833 tie_t = (val << 26) >> 30;
2834 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2835 tie_t = (val << 25) >> 31;
2836 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2840 Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2843 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2844 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2845 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2850 Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2853 tie_t = (val << 28) >> 28;
2854 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2855 tie_t = (val << 26) >> 30;
2856 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2857 tie_t = (val << 24) >> 30;
2858 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2862 Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2865 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2866 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2867 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2872 Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2875 tie_t = (val << 28) >> 28;
2876 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2877 tie_t = (val << 26) >> 30;
2878 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2879 tie_t = (val << 24) >> 30;
2880 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2884 Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2887 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2888 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2889 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2894 Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2897 tie_t = (val << 28) >> 28;
2898 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2899 tie_t = (val << 26) >> 30;
2900 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2901 tie_t = (val << 24) >> 30;
2902 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2906 Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2909 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2910 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2911 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2916 Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2919 tie_t = (val << 28) >> 28;
2920 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2921 tie_t = (val << 26) >> 30;
2922 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2923 tie_t = (val << 24) >> 30;
2924 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2928 Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2931 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2932 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2933 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2938 Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2941 tie_t = (val << 28) >> 28;
2942 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2943 tie_t = (val << 26) >> 30;
2944 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2945 tie_t = (val << 24) >> 30;
2946 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2950 Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2953 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2954 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2955 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2960 Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2963 tie_t = (val << 28) >> 28;
2964 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2965 tie_t = (val << 26) >> 30;
2966 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2967 tie_t = (val << 24) >> 30;
2968 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2972 Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2975 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2976 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2977 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2982 Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
2985 tie_t = (val << 28) >> 28;
2986 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2987 tie_t = (val << 26) >> 30;
2988 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
2989 tie_t = (val << 24) >> 30;
2990 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2994 Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
2997 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2998 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
2999 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3004 Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3007 tie_t = (val << 28) >> 28;
3008 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3009 tie_t = (val << 26) >> 30;
3010 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3011 tie_t = (val << 24) >> 30;
3012 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3016 Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3019 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3020 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3021 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3026 Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3029 tie_t = (val << 28) >> 28;
3030 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3031 tie_t = (val << 26) >> 30;
3032 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3033 tie_t = (val << 24) >> 30;
3034 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3038 Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3041 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3042 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3043 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3048 Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3051 tie_t = (val << 28) >> 28;
3052 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3053 tie_t = (val << 26) >> 30;
3054 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3055 tie_t = (val << 24) >> 30;
3056 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3060 Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3063 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3064 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3065 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3070 Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3073 tie_t = (val << 28) >> 28;
3074 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3075 tie_t = (val << 26) >> 30;
3076 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3077 tie_t = (val << 24) >> 30;
3078 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3082 Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3085 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3086 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3087 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3092 Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3095 tie_t = (val << 28) >> 28;
3096 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3097 tie_t = (val << 26) >> 30;
3098 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3099 tie_t = (val << 24) >> 30;
3100 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3104 Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3107 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3108 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3109 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3114 Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3117 tie_t = (val << 28) >> 28;
3118 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3119 tie_t = (val << 26) >> 30;
3120 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3121 tie_t = (val << 24) >> 30;
3122 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3126 Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3129 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3130 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3131 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3136 Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3139 tie_t = (val << 28) >> 28;
3140 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3141 tie_t = (val << 26) >> 30;
3142 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3143 tie_t = (val << 24) >> 30;
3144 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3148 Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3151 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3152 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3153 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3158 Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3161 tie_t = (val << 28) >> 28;
3162 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3163 tie_t = (val << 26) >> 30;
3164 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3165 tie_t = (val << 24) >> 30;
3166 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3170 Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3173 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3174 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3175 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3180 Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3183 tie_t = (val << 28) >> 28;
3184 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3185 tie_t = (val << 26) >> 30;
3186 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3187 tie_t = (val << 24) >> 30;
3188 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3192 Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3195 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3196 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3197 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3202 Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3205 tie_t = (val << 28) >> 28;
3206 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3207 tie_t = (val << 26) >> 30;
3208 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3209 tie_t = (val << 24) >> 30;
3210 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3214 Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3217 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3218 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3219 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3224 Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3227 tie_t = (val << 28) >> 28;
3228 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3229 tie_t = (val << 26) >> 30;
3230 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3231 tie_t = (val << 24) >> 30;
3232 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3236 Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3239 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3240 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3241 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3246 Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3249 tie_t = (val << 28) >> 28;
3250 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3251 tie_t = (val << 26) >> 30;
3252 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3253 tie_t = (val << 24) >> 30;
3254 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3258 Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3261 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3262 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3263 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3268 Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3271 tie_t = (val << 28) >> 28;
3272 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3273 tie_t = (val << 26) >> 30;
3274 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3275 tie_t = (val << 24) >> 30;
3276 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3280 Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3283 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3284 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3285 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3290 Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3293 tie_t = (val << 28) >> 28;
3294 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3295 tie_t = (val << 26) >> 30;
3296 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3297 tie_t = (val << 24) >> 30;
3298 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3302 Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3305 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3306 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3307 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3312 Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3315 tie_t = (val << 28) >> 28;
3316 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3317 tie_t = (val << 26) >> 30;
3318 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3319 tie_t = (val << 24) >> 30;
3320 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3324 Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3327 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3328 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3329 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3334 Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3337 tie_t = (val << 28) >> 28;
3338 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3339 tie_t = (val << 26) >> 30;
3340 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3341 tie_t = (val << 24) >> 30;
3342 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3346 Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3349 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3350 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3351 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3356 Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3359 tie_t = (val << 28) >> 28;
3360 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3361 tie_t = (val << 26) >> 30;
3362 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3363 tie_t = (val << 24) >> 30;
3364 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3368 Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3371 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3372 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3373 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3378 Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3381 tie_t = (val << 28) >> 28;
3382 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3383 tie_t = (val << 26) >> 30;
3384 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3385 tie_t = (val << 24) >> 30;
3386 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3390 Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3393 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3394 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3395 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3400 Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3403 tie_t = (val << 28) >> 28;
3404 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3405 tie_t = (val << 26) >> 30;
3406 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3407 tie_t = (val << 24) >> 30;
3408 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3412 Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3415 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3416 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3417 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3422 Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3425 tie_t = (val << 28) >> 28;
3426 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3427 tie_t = (val << 26) >> 30;
3428 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3429 tie_t = (val << 24) >> 30;
3430 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3434 Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3437 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3438 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3439 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3444 Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3447 tie_t = (val << 28) >> 28;
3448 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3449 tie_t = (val << 26) >> 30;
3450 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3451 tie_t = (val << 24) >> 30;
3452 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3456 Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3459 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3460 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3461 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3466 Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3469 tie_t = (val << 28) >> 28;
3470 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3471 tie_t = (val << 26) >> 30;
3472 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3473 tie_t = (val << 24) >> 30;
3474 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3478 Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3481 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3482 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3483 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3488 Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3491 tie_t = (val << 28) >> 28;
3492 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3493 tie_t = (val << 26) >> 30;
3494 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
3495 tie_t = (val << 24) >> 30;
3496 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3500 Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3503 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3504 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3509 Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3512 tie_t = (val << 28) >> 28;
3513 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3514 tie_t = (val << 23) >> 27;
3515 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3519 Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3522 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3523 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3528 Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3531 tie_t = (val << 28) >> 28;
3532 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3533 tie_t = (val << 23) >> 27;
3534 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3538 Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3541 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3542 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3547 Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3550 tie_t = (val << 28) >> 28;
3551 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3552 tie_t = (val << 23) >> 27;
3553 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3557 Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3560 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3561 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3566 Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3569 tie_t = (val << 28) >> 28;
3570 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3571 tie_t = (val << 23) >> 27;
3572 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3576 Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3579 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3580 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3585 Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3588 tie_t = (val << 28) >> 28;
3589 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3590 tie_t = (val << 23) >> 27;
3591 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3595 Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3598 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3599 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3604 Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3607 tie_t = (val << 28) >> 28;
3608 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3609 tie_t = (val << 23) >> 27;
3610 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3614 Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3617 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3618 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3623 Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3626 tie_t = (val << 28) >> 28;
3627 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3628 tie_t = (val << 23) >> 27;
3629 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3633 Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3636 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3637 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3642 Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3645 tie_t = (val << 28) >> 28;
3646 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3647 tie_t = (val << 23) >> 27;
3648 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3652 Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3655 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3656 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3661 Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3664 tie_t = (val << 28) >> 28;
3665 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3666 tie_t = (val << 23) >> 27;
3667 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3671 Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3674 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3675 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3680 Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3683 tie_t = (val << 28) >> 28;
3684 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3685 tie_t = (val << 23) >> 27;
3686 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3690 Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3693 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3694 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3699 Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3702 tie_t = (val << 28) >> 28;
3703 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3704 tie_t = (val << 23) >> 27;
3705 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3709 Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3712 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3713 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3718 Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3721 tie_t = (val << 28) >> 28;
3722 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3723 tie_t = (val << 23) >> 27;
3724 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3728 Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3731 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3732 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3737 Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3740 tie_t = (val << 28) >> 28;
3741 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3742 tie_t = (val << 23) >> 27;
3743 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3747 Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3750 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3751 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3756 Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3759 tie_t = (val << 28) >> 28;
3760 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3761 tie_t = (val << 23) >> 27;
3762 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3766 Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3769 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3770 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3775 Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3778 tie_t = (val << 28) >> 28;
3779 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3780 tie_t = (val << 23) >> 27;
3781 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3785 Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3788 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3789 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3794 Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3797 tie_t = (val << 28) >> 28;
3798 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3799 tie_t = (val << 23) >> 27;
3800 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3804 Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3807 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3808 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3813 Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3816 tie_t = (val << 28) >> 28;
3817 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3818 tie_t = (val << 23) >> 27;
3819 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3823 Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3826 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3827 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3832 Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3835 tie_t = (val << 28) >> 28;
3836 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3837 tie_t = (val << 23) >> 27;
3838 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3842 Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3845 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3846 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3851 Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3854 tie_t = (val << 28) >> 28;
3855 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3856 tie_t = (val << 23) >> 27;
3857 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3861 Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3864 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3865 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3870 Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3873 tie_t = (val << 28) >> 28;
3874 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3875 tie_t = (val << 23) >> 27;
3876 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3880 Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3883 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3884 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
3889 Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3892 tie_t = (val << 31) >> 31;
3893 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
3894 tie_t = (val << 26) >> 27;
3895 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3899 Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3902 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3903 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
3908 Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3911 tie_t = (val << 31) >> 31;
3912 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
3913 tie_t = (val << 26) >> 27;
3914 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3918 Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3921 tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
3922 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3927 Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3930 tie_t = (val << 28) >> 28;
3931 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3932 tie_t = (val << 23) >> 27;
3933 insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
3937 Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3940 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
3945 Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3948 tie_t = (val << 28) >> 28;
3949 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
3953 Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3956 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3957 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3962 Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3965 tie_t = (val << 28) >> 28;
3966 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3967 tie_t = (val << 27) >> 31;
3968 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3972 Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3975 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3980 Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
3983 tie_t = (val << 28) >> 28;
3984 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3988 Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
3991 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3992 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
3993 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3998 Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4001 tie_t = (val << 28) >> 28;
4002 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4003 tie_t = (val << 26) >> 30;
4004 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4005 tie_t = (val << 24) >> 30;
4006 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4010 Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4013 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4014 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4015 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
4020 Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4023 tie_t = (val << 31) >> 31;
4024 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
4025 tie_t = (val << 29) >> 30;
4026 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4027 tie_t = (val << 27) >> 30;
4028 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4032 Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4035 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
4040 Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4043 tie_t = (val << 29) >> 29;
4044 insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
4048 Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4051 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4052 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4053 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4058 Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4061 tie_t = (val << 28) >> 28;
4062 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4063 tie_t = (val << 26) >> 30;
4064 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4065 tie_t = (val << 24) >> 30;
4066 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4070 Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4073 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4074 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4079 Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4082 tie_t = (val << 31) >> 31;
4083 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4084 tie_t = (val << 29) >> 30;
4085 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4089 Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4092 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4093 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4098 Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4101 tie_t = (val << 28) >> 28;
4102 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4103 tie_t = (val << 27) >> 31;
4104 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4108 Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4111 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4112 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4113 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4118 Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4121 tie_t = (val << 28) >> 28;
4122 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4123 tie_t = (val << 26) >> 30;
4124 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4125 tie_t = (val << 24) >> 30;
4126 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4130 Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4133 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4134 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4135 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4140 Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4143 tie_t = (val << 28) >> 28;
4144 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4145 tie_t = (val << 26) >> 30;
4146 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4147 tie_t = (val << 24) >> 30;
4148 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4152 Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4155 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4156 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4157 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4162 Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4165 tie_t = (val << 28) >> 28;
4166 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4167 tie_t = (val << 26) >> 30;
4168 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4169 tie_t = (val << 24) >> 30;
4170 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4174 Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4177 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4178 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4179 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4184 Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4187 tie_t = (val << 28) >> 28;
4188 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4189 tie_t = (val << 26) >> 30;
4190 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4191 tie_t = (val << 24) >> 30;
4192 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4196 Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4199 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4200 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4201 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4206 Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4209 tie_t = (val << 28) >> 28;
4210 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4211 tie_t = (val << 26) >> 30;
4212 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4213 tie_t = (val << 24) >> 30;
4214 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4218 Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4221 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4222 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4223 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4228 Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4231 tie_t = (val << 28) >> 28;
4232 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4233 tie_t = (val << 26) >> 30;
4234 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4235 tie_t = (val << 24) >> 30;
4236 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4240 Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4243 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4244 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4245 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4250 Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4253 tie_t = (val << 28) >> 28;
4254 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4255 tie_t = (val << 26) >> 30;
4256 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4257 tie_t = (val << 24) >> 30;
4258 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4262 Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4265 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4266 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4267 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4272 Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4275 tie_t = (val << 28) >> 28;
4276 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4277 tie_t = (val << 26) >> 30;
4278 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4279 tie_t = (val << 24) >> 30;
4280 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4284 Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4287 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4288 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4289 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4294 Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4297 tie_t = (val << 28) >> 28;
4298 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4299 tie_t = (val << 26) >> 30;
4300 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4301 tie_t = (val << 24) >> 30;
4302 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4306 Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4309 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4310 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4311 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4316 Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4319 tie_t = (val << 28) >> 28;
4320 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4321 tie_t = (val << 26) >> 30;
4322 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4323 tie_t = (val << 24) >> 30;
4324 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4328 Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4331 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4332 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4333 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4338 Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4341 tie_t = (val << 28) >> 28;
4342 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4343 tie_t = (val << 26) >> 30;
4344 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4345 tie_t = (val << 24) >> 30;
4346 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4350 Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4353 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4354 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4355 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
4360 Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4363 tie_t = (val << 31) >> 31;
4364 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
4365 tie_t = (val << 29) >> 30;
4366 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4367 tie_t = (val << 27) >> 30;
4368 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4372 Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4375 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4376 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4377 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4382 Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4385 tie_t = (val << 28) >> 28;
4386 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4387 tie_t = (val << 26) >> 30;
4388 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4389 tie_t = (val << 24) >> 30;
4390 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4394 Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4397 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4398 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4399 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4404 Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4407 tie_t = (val << 28) >> 28;
4408 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4409 tie_t = (val << 26) >> 30;
4410 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4411 tie_t = (val << 24) >> 30;
4412 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4416 Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4419 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4420 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4421 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4426 Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4429 tie_t = (val << 28) >> 28;
4430 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4431 tie_t = (val << 26) >> 30;
4432 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4433 tie_t = (val << 24) >> 30;
4434 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4438 Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4441 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4442 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4443 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4448 Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4451 tie_t = (val << 28) >> 28;
4452 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4453 tie_t = (val << 26) >> 30;
4454 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4455 tie_t = (val << 24) >> 30;
4456 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4460 Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4463 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4464 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4465 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4470 Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4473 tie_t = (val << 28) >> 28;
4474 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4475 tie_t = (val << 26) >> 30;
4476 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4477 tie_t = (val << 24) >> 30;
4478 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4482 Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4485 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4486 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4487 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4492 Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4495 tie_t = (val << 28) >> 28;
4496 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4497 tie_t = (val << 26) >> 30;
4498 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4499 tie_t = (val << 24) >> 30;
4500 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4504 Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4507 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4508 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4509 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4514 Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4517 tie_t = (val << 28) >> 28;
4518 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4519 tie_t = (val << 26) >> 30;
4520 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4521 tie_t = (val << 24) >> 30;
4522 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4526 Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4529 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4530 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4531 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4536 Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4539 tie_t = (val << 28) >> 28;
4540 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4541 tie_t = (val << 26) >> 30;
4542 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4543 tie_t = (val << 24) >> 30;
4544 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4548 Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4551 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4552 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4553 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4558 Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4561 tie_t = (val << 28) >> 28;
4562 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4563 tie_t = (val << 26) >> 30;
4564 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4565 tie_t = (val << 24) >> 30;
4566 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4570 Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4573 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4574 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4575 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4580 Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4583 tie_t = (val << 28) >> 28;
4584 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4585 tie_t = (val << 26) >> 30;
4586 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4587 tie_t = (val << 24) >> 30;
4588 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4592 Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4595 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4596 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4597 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4602 Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4605 tie_t = (val << 28) >> 28;
4606 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4607 tie_t = (val << 26) >> 30;
4608 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4609 tie_t = (val << 24) >> 30;
4610 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4614 Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4617 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4618 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4619 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4624 Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4627 tie_t = (val << 28) >> 28;
4628 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4629 tie_t = (val << 26) >> 30;
4630 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4631 tie_t = (val << 24) >> 30;
4632 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4636 Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4639 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4640 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4641 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4646 Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4649 tie_t = (val << 28) >> 28;
4650 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4651 tie_t = (val << 26) >> 30;
4652 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4653 tie_t = (val << 24) >> 30;
4654 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4658 Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4661 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4662 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4663 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4668 Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4671 tie_t = (val << 28) >> 28;
4672 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4673 tie_t = (val << 26) >> 30;
4674 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4675 tie_t = (val << 24) >> 30;
4676 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4680 Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4683 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4684 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4685 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4690 Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4693 tie_t = (val << 28) >> 28;
4694 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4695 tie_t = (val << 26) >> 30;
4696 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4697 tie_t = (val << 24) >> 30;
4698 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4702 Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
4705 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
4706 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
4707 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4712 Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
4715 tie_t = (val << 28) >> 28;
4716 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4717 tie_t = (val << 26) >> 30;
4718 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
4719 tie_t = (val << 24) >> 30;
4720 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
4724 Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4727 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
4732 Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4735 tie_t = (val << 28) >> 28;
4736 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
4740 Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4743 tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25);
4748 Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4751 tie_t = (val << 25) >> 25;
4752 insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20);
4756 Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4759 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4764 Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4767 tie_t = (val << 24) >> 24;
4768 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
4772 Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4775 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4780 Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4783 tie_t = (val << 28) >> 28;
4784 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4788 Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4791 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
4796 Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4799 tie_t = (val << 29) >> 29;
4800 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
4804 Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4807 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
4812 Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4815 tie_t = (val << 31) >> 31;
4816 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
4820 Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4823 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
4828 Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4831 tie_t = (val << 29) >> 29;
4832 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
4836 Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4839 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
4844 Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4847 tie_t = (val << 28) >> 28;
4848 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
4852 Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4855 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
4860 Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4863 tie_t = (val << 29) >> 29;
4864 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
4868 Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4871 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
4876 Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4879 tie_t = (val << 30) >> 30;
4880 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
4884 Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4887 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4888 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
4893 Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4896 tie_t = (val << 24) >> 24;
4897 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
4898 tie_t = (val << 16) >> 24;
4899 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
4903 Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4906 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4911 Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4914 tie_t = (val << 31) >> 31;
4915 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4919 Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4922 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4927 Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4930 tie_t = (val << 29) >> 29;
4931 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4935 Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4938 tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
4943 Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4946 tie_t = (val << 20) >> 20;
4947 insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
4951 Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4954 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4955 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4956 tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
4961 Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4964 tie_t = (val << 26) >> 26;
4965 insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
4966 tie_t = (val << 25) >> 31;
4967 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4968 tie_t = (val << 17) >> 24;
4969 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
4973 Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4976 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
4977 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
4982 Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
4985 tie_t = (val << 31) >> 31;
4986 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
4987 tie_t = (val << 27) >> 28;
4988 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4992 Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
4995 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
4996 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
5001 Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5004 tie_t = (val << 24) >> 24;
5005 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
5006 tie_t = (val << 16) >> 24;
5007 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5011 Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5014 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5015 tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29);
5020 Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5023 tie_t = (val << 29) >> 29;
5024 insn[0] = (insn[0] & ~0x38) | (tie_t << 3);
5025 tie_t = (val << 21) >> 24;
5026 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5030 Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5033 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
5034 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
5039 Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5042 tie_t = (val << 29) >> 29;
5043 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
5044 tie_t = (val << 27) >> 30;
5045 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
5049 Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5052 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5053 tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28);
5058 Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5061 tie_t = (val << 28) >> 28;
5062 insn[0] = (insn[0] & ~0x3c) | (tie_t << 2);
5063 tie_t = (val << 20) >> 24;
5064 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5068 Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5071 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
5072 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
5077 Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5080 tie_t = (val << 30) >> 30;
5081 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
5082 tie_t = (val << 28) >> 30;
5083 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
5087 Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5090 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5091 tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27);
5096 Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5099 tie_t = (val << 27) >> 27;
5100 insn[0] = (insn[0] & ~0x3e) | (tie_t << 1);
5101 tie_t = (val << 19) >> 24;
5102 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5106 Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5109 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
5110 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
5115 Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5118 tie_t = (val << 31) >> 31;
5119 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
5120 tie_t = (val << 29) >> 30;
5121 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
5125 Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5128 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5129 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5130 tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
5135 Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5138 tie_t = (val << 31) >> 31;
5139 insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
5140 tie_t = (val << 30) >> 31;
5141 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5142 tie_t = (val << 22) >> 24;
5143 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5147 Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5150 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
5151 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
5156 Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5159 tie_t = (val << 31) >> 31;
5160 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
5161 tie_t = (val << 27) >> 28;
5162 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
5166 Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5169 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5170 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5175 Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5178 tie_t = (val << 28) >> 28;
5179 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5180 tie_t = (val << 20) >> 24;
5181 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5185 Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5188 tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25);
5193 Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5196 tie_t = (val << 25) >> 25;
5197 insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13);
5201 Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5204 tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
5209 Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5212 tie_t = (val << 19) >> 19;
5213 insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
5217 Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5220 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
5225 Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5228 tie_t = (val << 31) >> 31;
5229 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
5233 Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5236 tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23);
5241 Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5244 tie_t = (val << 23) >> 23;
5245 insn[0] = (insn[0] & ~0xff800) | (tie_t << 11);
5249 Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5252 tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27);
5257 Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5260 tie_t = (val << 27) >> 27;
5261 insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6);
5265 Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5268 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5269 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
5274 Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5277 tie_t = (val << 29) >> 29;
5278 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
5279 tie_t = (val << 21) >> 24;
5280 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5284 Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5287 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
5292 Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5295 tie_t = (val << 28) >> 28;
5296 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
5300 Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5303 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5304 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
5309 Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5312 tie_t = (val << 29) >> 29;
5313 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
5314 tie_t = (val << 21) >> 24;
5315 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5319 Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5322 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
5327 Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5330 tie_t = (val << 29) >> 29;
5331 insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
5335 Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5338 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
5339 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
5344 Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5347 tie_t = (val << 31) >> 31;
5348 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
5349 tie_t = (val << 27) >> 28;
5350 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
5354 Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5357 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5358 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5363 Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5366 tie_t = (val << 31) >> 31;
5367 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5368 tie_t = (val << 23) >> 24;
5369 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5373 Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5376 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5377 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5382 Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5385 tie_t = (val << 31) >> 31;
5386 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5387 tie_t = (val << 23) >> 24;
5388 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5392 Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5395 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5396 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5401 Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5404 tie_t = (val << 31) >> 31;
5405 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5406 tie_t = (val << 23) >> 24;
5407 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5411 Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5414 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5415 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5420 Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5423 tie_t = (val << 31) >> 31;
5424 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5425 tie_t = (val << 23) >> 24;
5426 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5430 Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5433 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5434 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5439 Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5442 tie_t = (val << 31) >> 31;
5443 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5444 tie_t = (val << 23) >> 24;
5445 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5449 Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5452 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5453 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5458 Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5461 tie_t = (val << 31) >> 31;
5462 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5463 tie_t = (val << 23) >> 24;
5464 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5468 Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5471 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5472 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5477 Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5480 tie_t = (val << 31) >> 31;
5481 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5482 tie_t = (val << 23) >> 24;
5483 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5487 Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5490 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5491 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5496 Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5499 tie_t = (val << 31) >> 31;
5500 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5501 tie_t = (val << 23) >> 24;
5502 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5506 Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5509 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5510 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5515 Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5518 tie_t = (val << 31) >> 31;
5519 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5520 tie_t = (val << 23) >> 24;
5521 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5525 Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5528 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5529 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5534 Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5537 tie_t = (val << 31) >> 31;
5538 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5539 tie_t = (val << 23) >> 24;
5540 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5544 Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5547 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5548 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5553 Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5556 tie_t = (val << 31) >> 31;
5557 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5558 tie_t = (val << 23) >> 24;
5559 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5563 Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5566 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5567 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5572 Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5575 tie_t = (val << 31) >> 31;
5576 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5577 tie_t = (val << 23) >> 24;
5578 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5582 Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5585 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5586 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5591 Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5594 tie_t = (val << 31) >> 31;
5595 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5596 tie_t = (val << 23) >> 24;
5597 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5601 Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5604 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5605 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5610 Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5613 tie_t = (val << 31) >> 31;
5614 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5615 tie_t = (val << 23) >> 24;
5616 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5620 Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5623 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5624 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5629 Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5632 tie_t = (val << 31) >> 31;
5633 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5634 tie_t = (val << 23) >> 24;
5635 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5639 Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5642 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5643 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5648 Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5651 tie_t = (val << 31) >> 31;
5652 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5653 tie_t = (val << 23) >> 24;
5654 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5658 Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5661 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5662 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5667 Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5670 tie_t = (val << 31) >> 31;
5671 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5672 tie_t = (val << 23) >> 24;
5673 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5677 Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5680 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5681 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5686 Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5689 tie_t = (val << 31) >> 31;
5690 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5691 tie_t = (val << 23) >> 24;
5692 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5696 Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5699 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5700 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5705 Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5708 tie_t = (val << 31) >> 31;
5709 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5710 tie_t = (val << 23) >> 24;
5711 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5715 Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5718 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5719 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5724 Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5727 tie_t = (val << 31) >> 31;
5728 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5729 tie_t = (val << 23) >> 24;
5730 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5734 Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5737 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5738 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5743 Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5746 tie_t = (val << 31) >> 31;
5747 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5748 tie_t = (val << 23) >> 24;
5749 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5753 Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5756 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5757 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5762 Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5765 tie_t = (val << 31) >> 31;
5766 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5767 tie_t = (val << 23) >> 24;
5768 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5772 Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5775 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5776 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5781 Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5784 tie_t = (val << 31) >> 31;
5785 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5786 tie_t = (val << 23) >> 24;
5787 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5791 Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5794 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5795 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5800 Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5803 tie_t = (val << 31) >> 31;
5804 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5805 tie_t = (val << 23) >> 24;
5806 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5810 Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5813 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5814 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5819 Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5822 tie_t = (val << 31) >> 31;
5823 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5824 tie_t = (val << 23) >> 24;
5825 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5829 Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5832 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5833 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5838 Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5841 tie_t = (val << 31) >> 31;
5842 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5843 tie_t = (val << 23) >> 24;
5844 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5848 Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5851 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5852 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5857 Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5860 tie_t = (val << 31) >> 31;
5861 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5862 tie_t = (val << 23) >> 24;
5863 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5867 Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5870 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5871 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5876 Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5879 tie_t = (val << 31) >> 31;
5880 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5881 tie_t = (val << 23) >> 24;
5882 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5886 Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5889 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5890 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5895 Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5898 tie_t = (val << 31) >> 31;
5899 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5900 tie_t = (val << 23) >> 24;
5901 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5905 Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5908 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5909 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5914 Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5917 tie_t = (val << 31) >> 31;
5918 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5919 tie_t = (val << 23) >> 24;
5920 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5924 Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5927 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5928 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5933 Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5936 tie_t = (val << 31) >> 31;
5937 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5938 tie_t = (val << 23) >> 24;
5939 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5943 Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5946 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5947 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5952 Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5955 tie_t = (val << 31) >> 31;
5956 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5957 tie_t = (val << 23) >> 24;
5958 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5962 Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5965 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5966 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5971 Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5974 tie_t = (val << 31) >> 31;
5975 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5976 tie_t = (val << 23) >> 24;
5977 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
5981 Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
5984 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
5985 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
5990 Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
5993 tie_t = (val << 31) >> 31;
5994 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
5995 tie_t = (val << 23) >> 24;
5996 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6000 Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6003 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6004 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6009 Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6012 tie_t = (val << 31) >> 31;
6013 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6014 tie_t = (val << 23) >> 24;
6015 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6019 Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6022 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6023 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6028 Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6031 tie_t = (val << 31) >> 31;
6032 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6033 tie_t = (val << 23) >> 24;
6034 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6038 Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6041 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6042 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6047 Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6050 tie_t = (val << 31) >> 31;
6051 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6052 tie_t = (val << 23) >> 24;
6053 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6057 Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6060 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6061 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6066 Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6069 tie_t = (val << 31) >> 31;
6070 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6071 tie_t = (val << 23) >> 24;
6072 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6076 Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6079 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6080 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6085 Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6088 tie_t = (val << 31) >> 31;
6089 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6090 tie_t = (val << 23) >> 24;
6091 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6095 Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6098 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6099 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6104 Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6107 tie_t = (val << 31) >> 31;
6108 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6109 tie_t = (val << 23) >> 24;
6110 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6114 Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6117 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6118 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6123 Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6126 tie_t = (val << 31) >> 31;
6127 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6128 tie_t = (val << 23) >> 24;
6129 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6133 Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6136 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6137 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6142 Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6145 tie_t = (val << 31) >> 31;
6146 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6147 tie_t = (val << 23) >> 24;
6148 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6152 Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6155 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6156 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6161 Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6164 tie_t = (val << 31) >> 31;
6165 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6166 tie_t = (val << 23) >> 24;
6167 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6171 Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6174 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6175 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6180 Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6183 tie_t = (val << 31) >> 31;
6184 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6185 tie_t = (val << 23) >> 24;
6186 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6190 Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6193 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6194 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6199 Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6202 tie_t = (val << 31) >> 31;
6203 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6204 tie_t = (val << 23) >> 24;
6205 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6209 Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6212 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6213 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6218 Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6221 tie_t = (val << 31) >> 31;
6222 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6223 tie_t = (val << 23) >> 24;
6224 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6228 Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6231 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6232 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6237 Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6240 tie_t = (val << 31) >> 31;
6241 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6242 tie_t = (val << 23) >> 24;
6243 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6247 Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6250 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6251 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6256 Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6259 tie_t = (val << 31) >> 31;
6260 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6261 tie_t = (val << 23) >> 24;
6262 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6266 Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6269 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6270 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6275 Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6278 tie_t = (val << 30) >> 30;
6279 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6280 tie_t = (val << 22) >> 24;
6281 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6285 Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6288 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6289 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6294 Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6297 tie_t = (val << 30) >> 30;
6298 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6299 tie_t = (val << 22) >> 24;
6300 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6304 Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6307 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6308 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6313 Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6316 tie_t = (val << 30) >> 30;
6317 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6318 tie_t = (val << 22) >> 24;
6319 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6323 Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6326 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6327 tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
6332 Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6335 tie_t = (val << 31) >> 31;
6336 insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
6337 tie_t = (val << 23) >> 24;
6338 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6342 Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6345 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
6350 Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6353 tie_t = (val << 31) >> 31;
6354 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
6358 Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6361 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6362 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6367 Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6370 tie_t = (val << 30) >> 30;
6371 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6372 tie_t = (val << 22) >> 24;
6373 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6377 Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6380 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6381 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6386 Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6389 tie_t = (val << 30) >> 30;
6390 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6391 tie_t = (val << 22) >> 24;
6392 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6396 Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6399 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6400 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6405 Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6408 tie_t = (val << 30) >> 30;
6409 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6410 tie_t = (val << 22) >> 24;
6411 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6415 Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6418 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6419 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
6424 Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6427 tie_t = (val << 30) >> 30;
6428 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
6429 tie_t = (val << 22) >> 24;
6430 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6434 Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6437 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6438 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6443 Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6446 tie_t = (val << 30) >> 30;
6447 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6448 tie_t = (val << 22) >> 24;
6449 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6453 Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6456 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6457 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6462 Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6465 tie_t = (val << 30) >> 30;
6466 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6467 tie_t = (val << 22) >> 24;
6468 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6472 Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6475 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6476 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6481 Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6484 tie_t = (val << 30) >> 30;
6485 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6486 tie_t = (val << 22) >> 24;
6487 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6491 Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6494 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6495 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6500 Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6503 tie_t = (val << 30) >> 30;
6504 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6505 tie_t = (val << 22) >> 24;
6506 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6510 Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6513 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6514 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6519 Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6522 tie_t = (val << 30) >> 30;
6523 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6524 tie_t = (val << 22) >> 24;
6525 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6529 Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6532 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6533 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6538 Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6541 tie_t = (val << 30) >> 30;
6542 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6543 tie_t = (val << 22) >> 24;
6544 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6548 Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6551 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6556 Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6559 tie_t = (val << 30) >> 30;
6560 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6564 Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6567 tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27);
6572 Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6575 tie_t = (val << 27) >> 27;
6576 insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15);
6580 Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6583 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
6584 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
6589 Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6592 tie_t = (val << 30) >> 30;
6593 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
6594 tie_t = (val << 27) >> 29;
6595 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
6599 Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6602 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6603 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6608 Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6611 tie_t = (val << 31) >> 31;
6612 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6613 tie_t = (val << 23) >> 24;
6614 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6618 Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6621 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6622 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6627 Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6630 tie_t = (val << 31) >> 31;
6631 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6632 tie_t = (val << 23) >> 24;
6633 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6637 Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6640 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6641 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6642 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6647 Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6650 tie_t = (val << 28) >> 28;
6651 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6652 tie_t = (val << 27) >> 31;
6653 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6654 tie_t = (val << 19) >> 24;
6655 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6659 Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6662 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6663 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6664 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6669 Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6672 tie_t = (val << 28) >> 28;
6673 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6674 tie_t = (val << 27) >> 31;
6675 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6676 tie_t = (val << 19) >> 24;
6677 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6681 Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6684 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6685 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6690 Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6693 tie_t = (val << 31) >> 31;
6694 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6695 tie_t = (val << 23) >> 24;
6696 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6700 Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6703 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6704 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6709 Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6712 tie_t = (val << 31) >> 31;
6713 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6714 tie_t = (val << 23) >> 24;
6715 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6719 Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6722 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6723 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6728 Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6731 tie_t = (val << 31) >> 31;
6732 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6733 tie_t = (val << 23) >> 24;
6734 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6738 Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6741 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6742 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6747 Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6750 tie_t = (val << 31) >> 31;
6751 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6752 tie_t = (val << 23) >> 24;
6753 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6757 Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6760 tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
6761 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
6766 Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6769 tie_t = (val << 29) >> 29;
6770 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
6771 tie_t = (val << 17) >> 20;
6772 insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
6776 Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6779 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
6780 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6785 Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6788 tie_t = (val << 28) >> 28;
6789 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6790 tie_t = (val << 27) >> 31;
6791 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
6795 Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6798 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6799 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6804 Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6807 tie_t = (val << 28) >> 28;
6808 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6809 tie_t = (val << 20) >> 24;
6810 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6814 Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6817 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6818 tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
6823 Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6826 tie_t = (val << 26) >> 26;
6827 insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
6828 tie_t = (val << 18) >> 24;
6829 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6833 Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6836 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6837 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6838 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
6843 Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6846 tie_t = (val << 29) >> 29;
6847 insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
6848 tie_t = (val << 28) >> 31;
6849 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6850 tie_t = (val << 20) >> 24;
6851 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6855 Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6858 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
6859 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
6864 Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6867 tie_t = (val << 31) >> 31;
6868 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
6869 tie_t = (val << 30) >> 31;
6870 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
6874 Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6877 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6878 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6879 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6884 Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6887 tie_t = (val << 28) >> 28;
6888 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6889 tie_t = (val << 27) >> 31;
6890 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6891 tie_t = (val << 19) >> 24;
6892 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6896 Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6899 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6900 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6901 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6906 Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6909 tie_t = (val << 28) >> 28;
6910 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6911 tie_t = (val << 27) >> 31;
6912 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6913 tie_t = (val << 19) >> 24;
6914 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6918 Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6921 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6922 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6923 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
6928 Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6931 tie_t = (val << 28) >> 28;
6932 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
6933 tie_t = (val << 27) >> 31;
6934 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6935 tie_t = (val << 19) >> 24;
6936 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6940 Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6943 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
6944 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
6945 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
6950 Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6953 tie_t = (val << 31) >> 31;
6954 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
6955 tie_t = (val << 30) >> 31;
6956 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
6957 tie_t = (val << 22) >> 24;
6958 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
6962 Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6965 tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22);
6970 Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6973 tie_t = (val << 22) >> 22;
6974 insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10);
6978 Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6981 tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21);
6986 Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
6989 tie_t = (val << 21) >> 21;
6990 insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9);
6994 Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
6997 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
6998 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7003 Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7006 tie_t = (val << 28) >> 28;
7007 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7008 tie_t = (val << 27) >> 31;
7009 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
7013 Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7016 tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
7017 tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
7022 Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7025 tie_t = (val << 31) >> 31;
7026 insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
7027 tie_t = (val << 19) >> 20;
7028 insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
7032 Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7035 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
7036 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
7041 Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7044 tie_t = (val << 30) >> 30;
7045 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
7046 tie_t = (val << 29) >> 31;
7047 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
7051 Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7054 tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
7055 tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
7060 Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7063 tie_t = (val << 30) >> 30;
7064 insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
7065 tie_t = (val << 18) >> 20;
7066 insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
7070 Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7073 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
7074 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
7079 Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7082 tie_t = (val << 31) >> 31;
7083 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
7084 tie_t = (val << 30) >> 31;
7085 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
7089 Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7092 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7093 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7098 Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7101 tie_t = (val << 28) >> 28;
7102 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7103 tie_t = (val << 20) >> 24;
7104 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7108 Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7111 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7112 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
7117 Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7120 tie_t = (val << 31) >> 31;
7121 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
7122 tie_t = (val << 23) >> 24;
7123 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7127 Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7130 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7131 tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
7136 Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7139 tie_t = (val << 30) >> 30;
7140 insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
7141 tie_t = (val << 22) >> 24;
7142 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7146 Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7149 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
7154 Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7157 tie_t = (val << 30) >> 30;
7158 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
7162 Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7165 tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
7166 tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
7171 Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7174 tie_t = (val << 29) >> 29;
7175 insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
7176 tie_t = (val << 17) >> 20;
7177 insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
7181 Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7184 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7185 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7190 Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7193 tie_t = (val << 28) >> 28;
7194 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7195 tie_t = (val << 20) >> 24;
7196 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7200 Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7203 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
7204 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
7205 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7210 Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7213 tie_t = (val << 28) >> 28;
7214 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7215 tie_t = (val << 27) >> 31;
7216 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
7217 tie_t = (val << 19) >> 24;
7218 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
7222 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
7225 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7230 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7233 tie_t = (val << 28) >> 28;
7234 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7238 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
7241 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
7246 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7249 tie_t = (val << 31) >> 31;
7250 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
7254 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
7257 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
7258 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7263 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7266 tie_t = (val << 28) >> 28;
7267 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7268 tie_t = (val << 27) >> 31;
7269 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
7273 Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7276 tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
7281 Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7284 tie_t = (val << 27) >> 27;
7285 insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
7289 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
7292 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
7297 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7300 tie_t = (val << 20) >> 20;
7301 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
7305 Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7308 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7309 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
7314 Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7317 tie_t = (val << 24) >> 24;
7318 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
7319 tie_t = (val << 20) >> 28;
7320 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7324 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
7327 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
7332 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7335 tie_t = (val << 24) >> 24;
7336 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
7340 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
7343 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7348 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7351 tie_t = (val << 28) >> 28;
7352 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7356 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
7359 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7360 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
7365 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7368 tie_t = (val << 24) >> 24;
7369 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
7370 tie_t = (val << 20) >> 28;
7371 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7375 Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7378 tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
7383 Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7386 tie_t = (val << 20) >> 20;
7387 insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
7391 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
7394 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
7399 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7402 tie_t = (val << 16) >> 16;
7403 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
7407 Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7410 tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
7415 Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7418 tie_t = (val << 16) >> 16;
7419 insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
7423 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
7426 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
7431 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7434 tie_t = (val << 14) >> 14;
7435 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
7439 Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7442 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
7447 Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7450 tie_t = (val << 14) >> 14;
7451 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
7455 Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7458 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7463 Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7466 tie_t = (val << 28) >> 28;
7467 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7471 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
7474 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7479 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7482 tie_t = (val << 28) >> 28;
7483 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7487 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
7490 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
7495 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7498 tie_t = (val << 31) >> 31;
7499 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
7503 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
7506 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
7511 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7514 tie_t = (val << 31) >> 31;
7515 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
7519 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
7522 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
7523 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7528 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7531 tie_t = (val << 28) >> 28;
7532 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7533 tie_t = (val << 27) >> 31;
7534 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
7538 Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7541 tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
7546 Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7549 tie_t = (val << 27) >> 27;
7550 insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
7554 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
7557 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
7558 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7563 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7566 tie_t = (val << 28) >> 28;
7567 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7568 tie_t = (val << 27) >> 31;
7569 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
7573 Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7576 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
7577 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
7582 Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7585 tie_t = (val << 28) >> 28;
7586 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7587 tie_t = (val << 27) >> 31;
7588 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
7592 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
7595 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
7596 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7601 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7604 tie_t = (val << 28) >> 28;
7605 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7606 tie_t = (val << 27) >> 31;
7607 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
7611 Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7614 tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
7619 Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7622 tie_t = (val << 27) >> 27;
7623 insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
7627 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
7630 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
7635 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7638 tie_t = (val << 31) >> 31;
7639 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
7643 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
7646 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
7647 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7652 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7655 tie_t = (val << 28) >> 28;
7656 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7657 tie_t = (val << 27) >> 31;
7658 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
7662 Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
7665 tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
7670 Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
7673 tie_t = (val << 27) >> 27;
7674 insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
7678 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
7681 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7682 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7687 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7690 tie_t = (val << 28) >> 28;
7691 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7692 tie_t = (val << 24) >> 28;
7693 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7697 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
7700 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7701 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7706 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7709 tie_t = (val << 28) >> 28;
7710 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7711 tie_t = (val << 24) >> 28;
7712 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7716 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
7719 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7720 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7725 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7728 tie_t = (val << 28) >> 28;
7729 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7730 tie_t = (val << 24) >> 28;
7731 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7735 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
7738 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
7739 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
7744 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7747 tie_t = (val << 28) >> 28;
7748 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
7749 tie_t = (val << 24) >> 28;
7750 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
7754 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
7757 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7762 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7765 tie_t = (val << 28) >> 28;
7766 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7770 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
7773 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7778 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7781 tie_t = (val << 28) >> 28;
7782 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7786 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
7789 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7794 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7797 tie_t = (val << 28) >> 28;
7798 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7802 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
7805 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
7806 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7811 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
7814 tie_t = (val << 30) >> 30;
7815 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7816 tie_t = (val << 28) >> 30;
7817 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
7821 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
7824 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
7829 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7832 tie_t = (val << 31) >> 31;
7833 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
7837 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
7840 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7845 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7848 tie_t = (val << 28) >> 28;
7849 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7853 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
7856 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7861 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7864 tie_t = (val << 28) >> 28;
7865 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7869 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
7872 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7877 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7880 tie_t = (val << 30) >> 30;
7881 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7885 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
7888 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7893 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7896 tie_t = (val << 30) >> 30;
7897 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
7901 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
7904 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7909 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7912 tie_t = (val << 28) >> 28;
7913 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7917 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
7920 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7925 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7928 tie_t = (val << 28) >> 28;
7929 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7933 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
7936 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
7941 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7944 tie_t = (val << 29) >> 29;
7945 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
7949 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
7952 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
7957 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
7960 tie_t = (val << 29) >> 29;
7961 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
7965 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
7968 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
7973 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7976 tie_t = (val << 31) >> 31;
7977 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
7981 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
7984 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
7985 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
7990 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
7993 tie_t = (val << 28) >> 28;
7994 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
7995 tie_t = (val << 26) >> 30;
7996 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8000 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
8003 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8004 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
8009 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8012 tie_t = (val << 28) >> 28;
8013 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
8014 tie_t = (val << 26) >> 30;
8015 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8019 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
8022 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
8023 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
8028 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8031 tie_t = (val << 28) >> 28;
8032 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
8033 tie_t = (val << 25) >> 29;
8034 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
8038 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
8041 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
8042 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
8047 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8050 tie_t = (val << 28) >> 28;
8051 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
8052 tie_t = (val << 25) >> 29;
8053 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
8057 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
8060 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
8065 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8068 tie_t = (val << 29) >> 29;
8069 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
8073 Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
8076 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
8081 Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8084 tie_t = (val << 29) >> 29;
8085 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
8089 Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
8092 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
8097 Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8100 tie_t = (val << 29) >> 29;
8101 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
8105 Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
8108 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
8109 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
8114 Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
8117 tie_t = (val << 31) >> 31;
8118 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
8119 tie_t = (val << 29) >> 30;
8120 insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
8124 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
8127 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
8132 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8135 tie_t = (val << 29) >> 29;
8136 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
8140 Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
8143 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
8148 Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8151 tie_t = (val << 29) >> 29;
8152 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
8156 Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
8159 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
8164 Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8167 tie_t = (val << 29) >> 29;
8168 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
8172 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
8175 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
8180 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8183 tie_t = (val << 29) >> 29;
8184 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
8188 Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
8191 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
8196 Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8199 tie_t = (val << 29) >> 29;
8200 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
8204 Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
8207 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
8212 Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8215 tie_t = (val << 29) >> 29;
8216 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
8220 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
8223 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
8228 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8231 tie_t = (val << 30) >> 30;
8232 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
8236 Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
8239 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
8244 Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8247 tie_t = (val << 30) >> 30;
8248 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
8252 Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
8255 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
8260 Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8263 tie_t = (val << 30) >> 30;
8264 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
8268 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
8271 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
8276 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8279 tie_t = (val << 30) >> 30;
8280 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
8284 Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
8287 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
8292 Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8295 tie_t = (val << 30) >> 30;
8296 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
8300 Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
8303 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
8308 Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8311 tie_t = (val << 30) >> 30;
8312 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
8316 Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
8319 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8324 Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
8327 tie_t = (val << 30) >> 30;
8328 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8332 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
8335 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
8340 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8343 tie_t = (val << 30) >> 30;
8344 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
8348 Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
8351 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
8356 Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8359 tie_t = (val << 30) >> 30;
8360 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
8364 Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
8367 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
8372 Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8375 tie_t = (val << 30) >> 30;
8376 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
8380 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
8383 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
8388 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8391 tie_t = (val << 31) >> 31;
8392 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
8396 Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
8399 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
8404 Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8407 tie_t = (val << 31) >> 31;
8408 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
8412 Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
8415 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
8420 Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8423 tie_t = (val << 31) >> 31;
8424 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
8428 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
8431 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
8436 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8439 tie_t = (val << 31) >> 31;
8440 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
8444 Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
8447 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
8452 Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8455 tie_t = (val << 31) >> 31;
8456 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
8460 Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
8463 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
8468 Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8471 tie_t = (val << 31) >> 31;
8472 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
8476 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
8479 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
8484 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8487 tie_t = (val << 31) >> 31;
8488 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
8492 Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
8495 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
8500 Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
8503 tie_t = (val << 31) >> 31;
8504 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
8508 Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
8511 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
8516 Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
8519 tie_t = (val << 31) >> 31;
8520 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
8524 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
8527 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
8532 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8535 tie_t = (val << 17) >> 17;
8536 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
8540 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
8543 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
8548 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8551 tie_t = (val << 14) >> 14;
8552 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
8556 Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
8559 tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26);
8564 Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8567 tie_t = (val << 26) >> 26;
8568 insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4);
8572 Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
8575 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
8576 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
8581 Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
8584 tie_t = (val << 28) >> 28;
8585 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
8586 tie_t = (val << 26) >> 30;
8587 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
8591 Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
8594 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
8599 Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8602 tie_t = (val << 29) >> 29;
8603 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
8607 Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
8610 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8615 Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
8618 tie_t = (val << 30) >> 30;
8619 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8623 Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
8626 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
8631 Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8634 tie_t = (val << 29) >> 29;
8635 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
8639 Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
8642 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
8647 Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8650 tie_t = (val << 28) >> 28;
8651 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
8655 Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
8658 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
8663 Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8666 tie_t = (val << 28) >> 28;
8667 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
8671 Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
8674 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
8679 Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8682 tie_t = (val << 29) >> 29;
8683 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
8687 Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn)
8690 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
8695 Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8698 tie_t = (val << 30) >> 30;
8699 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
8703 Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn)
8706 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
8707 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
8712 Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
8715 tie_t = (val << 31) >> 31;
8716 insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
8717 tie_t = (val << 27) >> 28;
8718 insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
8722 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
8723 uint32 val ATTRIBUTE_UNUSED)
8729 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8735 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8741 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8747 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8753 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8759 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8765 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8771 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
8776 enum xtensa_field_id {
8824 FIELD_ae_s_non_samt,
8837 FIELD_ftsf21ae_slot1,
8838 FIELD_ftsf22ae_slot1,
8839 FIELD_ftsf23ae_slot1,
8840 FIELD_ftsf24ae_slot1,
8841 FIELD_ftsf25ae_slot1,
8842 FIELD_ftsf26ae_slot1,
8843 FIELD_ftsf27ae_slot1,
8844 FIELD_ftsf28ae_slot1,
8845 FIELD_ftsf29ae_slot1,
8846 FIELD_ftsf30ae_slot1,
8847 FIELD_ftsf31ae_slot1,
8848 FIELD_ftsf32ae_slot1,
8849 FIELD_ftsf33ae_slot1,
8850 FIELD_ftsf34ae_slot1,
8851 FIELD_ftsf35ae_slot1,
8852 FIELD_ftsf36ae_slot1,
8853 FIELD_ftsf37ae_slot1,
8854 FIELD_ftsf38ae_slot1,
8855 FIELD_ftsf39ae_slot1,
8856 FIELD_ftsf40ae_slot1,
8857 FIELD_ftsf41ae_slot1,
8858 FIELD_ftsf42ae_slot1,
8859 FIELD_ftsf43ae_slot1,
8860 FIELD_ftsf44ae_slot1,
8861 FIELD_ftsf45ae_slot1,
8862 FIELD_ftsf46ae_slot1,
8863 FIELD_ftsf47ae_slot1,
8864 FIELD_ftsf48ae_slot1,
8865 FIELD_ftsf49ae_slot1,
8866 FIELD_ftsf50ae_slot1,
8867 FIELD_ftsf51ae_slot1,
8868 FIELD_ftsf52ae_slot1,
8869 FIELD_ftsf53ae_slot1,
8870 FIELD_ftsf54ae_slot1,
8871 FIELD_ftsf55ae_slot1,
8872 FIELD_ftsf56ae_slot1,
8873 FIELD_ftsf57ae_slot1,
8874 FIELD_ftsf58ae_slot1,
8875 FIELD_ftsf59ae_slot1,
8876 FIELD_ftsf60ae_slot1,
8877 FIELD_ftsf61ae_slot1,
8878 FIELD_ftsf63ae_slot1,
8879 FIELD_ftsf64ae_slot1,
8880 FIELD_ftsf66ae_slot1,
8881 FIELD_ftsf67ae_slot1,
8882 FIELD_ftsf69ae_slot1,
8883 FIELD_ftsf71ae_slot1,
8884 FIELD_ftsf72ae_slot1,
8885 FIELD_ftsf73ae_slot1,
8886 FIELD_ftsf75ae_slot1,
8887 FIELD_ftsf76ae_slot1,
8888 FIELD_ftsf77ae_slot1,
8889 FIELD_ftsf78ae_slot1,
8890 FIELD_ftsf79ae_slot1,
8891 FIELD_ftsf80ae_slot1,
8892 FIELD_ftsf81ae_slot1,
8893 FIELD_ftsf82ae_slot1,
8894 FIELD_ftsf84ae_slot1,
8895 FIELD_ftsf86ae_slot1,
8896 FIELD_ftsf87ae_slot1,
8897 FIELD_ftsf88ae_slot1,
8898 FIELD_ftsf89ae_slot1,
8899 FIELD_ftsf90ae_slot1,
8900 FIELD_ftsf91ae_slot1,
8901 FIELD_ftsf92ae_slot1,
8902 FIELD_ftsf94ae_slot1,
8903 FIELD_ftsf96ae_slot1,
8904 FIELD_ftsf97ae_slot1,
8905 FIELD_ftsf98ae_slot1,
8906 FIELD_ftsf99ae_slot1,
8907 FIELD_ftsf100ae_slot1,
8908 FIELD_ftsf101ae_slot1,
8909 FIELD_ftsf103ae_slot1,
8910 FIELD_ftsf104ae_slot1,
8911 FIELD_ftsf105ae_slot1,
8912 FIELD_ftsf106ae_slot1,
8913 FIELD_ftsf107ae_slot1,
8914 FIELD_ftsf108ae_slot1,
8915 FIELD_ftsf109ae_slot1,
8916 FIELD_ftsf110ae_slot1,
8917 FIELD_ftsf111ae_slot1,
8918 FIELD_ftsf112ae_slot1,
8919 FIELD_ftsf113ae_slot1,
8920 FIELD_ftsf114ae_slot1,
8921 FIELD_ftsf115ae_slot1,
8922 FIELD_ftsf116ae_slot1,
8923 FIELD_ftsf118ae_slot1,
8924 FIELD_ftsf119ae_slot1,
8925 FIELD_ftsf120ae_slot1,
8926 FIELD_ftsf122ae_slot1,
8927 FIELD_ftsf124ae_slot1,
8928 FIELD_ftsf125ae_slot1,
8929 FIELD_ftsf126ae_slot1,
8930 FIELD_ftsf127ae_slot1,
8931 FIELD_ftsf128ae_slot1,
8932 FIELD_ftsf129ae_slot1,
8933 FIELD_ftsf130ae_slot1,
8934 FIELD_ftsf131ae_slot1,
8935 FIELD_ftsf132ae_slot1,
8936 FIELD_ftsf133ae_slot1,
8937 FIELD_ftsf134ae_slot1,
8938 FIELD_ftsf135ae_slot1,
8939 FIELD_ftsf136ae_slot1,
8940 FIELD_ftsf137ae_slot1,
8941 FIELD_ftsf138ae_slot1,
8942 FIELD_ftsf139ae_slot1,
8943 FIELD_ftsf140ae_slot1,
8944 FIELD_ftsf141ae_slot1,
8945 FIELD_ftsf142ae_slot1,
8946 FIELD_ftsf143ae_slot1,
8947 FIELD_ftsf144ae_slot1,
8948 FIELD_ftsf145ae_slot1,
8949 FIELD_ftsf146ae_slot1,
8950 FIELD_ftsf147ae_slot1,
8951 FIELD_ftsf148ae_slot1,
8952 FIELD_ftsf149ae_slot1,
8953 FIELD_ftsf150ae_slot1,
8954 FIELD_ftsf151ae_slot1,
8955 FIELD_ftsf152ae_slot1,
8956 FIELD_ftsf153ae_slot1,
8957 FIELD_ftsf154ae_slot1,
8958 FIELD_ftsf155ae_slot1,
8959 FIELD_ftsf156ae_slot1,
8960 FIELD_ftsf157ae_slot1,
8961 FIELD_ftsf158ae_slot1,
8962 FIELD_ftsf159ae_slot1,
8963 FIELD_ftsf160ae_slot1,
8964 FIELD_ftsf161ae_slot1,
8965 FIELD_ftsf162ae_slot1,
8966 FIELD_ftsf163ae_slot1,
8967 FIELD_ftsf164ae_slot1,
8968 FIELD_ftsf165ae_slot1,
8969 FIELD_ftsf166ae_slot1,
8970 FIELD_ftsf167ae_slot1,
8971 FIELD_ftsf168ae_slot1,
8972 FIELD_ftsf169ae_slot1,
8973 FIELD_ftsf170ae_slot1,
8974 FIELD_ftsf171ae_slot1,
8975 FIELD_ftsf172ae_slot1,
8976 FIELD_ftsf173ae_slot1,
8977 FIELD_ftsf174ae_slot1,
8978 FIELD_ftsf175ae_slot1,
8979 FIELD_ftsf176ae_slot1,
8980 FIELD_ftsf177ae_slot1,
8981 FIELD_ftsf178ae_slot1,
8982 FIELD_ftsf179ae_slot1,
8983 FIELD_ftsf180ae_slot1,
8984 FIELD_ftsf181ae_slot1,
8985 FIELD_ftsf182ae_slot1,
8986 FIELD_ftsf183ae_slot1,
8987 FIELD_ftsf184ae_slot1,
8988 FIELD_ftsf185ae_slot1,
8989 FIELD_ftsf186ae_slot1,
8990 FIELD_ftsf187ae_slot1,
8991 FIELD_ftsf188ae_slot1,
8992 FIELD_ftsf189ae_slot1,
8993 FIELD_ftsf190ae_slot1,
8994 FIELD_ftsf191ae_slot1,
8995 FIELD_ftsf192ae_slot1,
8996 FIELD_ftsf193ae_slot1,
8997 FIELD_ftsf194ae_slot1,
8998 FIELD_ftsf195ae_slot1,
8999 FIELD_ftsf196ae_slot1,
9000 FIELD_ftsf197ae_slot1,
9001 FIELD_ftsf198ae_slot1,
9002 FIELD_ftsf199ae_slot1,
9003 FIELD_ftsf200ae_slot1,
9004 FIELD_ftsf201ae_slot1,
9005 FIELD_ftsf202ae_slot1,
9006 FIELD_ftsf203ae_slot1,
9007 FIELD_ftsf204ae_slot1,
9008 FIELD_ftsf205ae_slot1,
9009 FIELD_ftsf206ae_slot1,
9010 FIELD_ftsf207ae_slot1,
9012 FIELD_ftsf209ae_slot1,
9013 FIELD_ftsf210ae_slot1,
9014 FIELD_ftsf211ae_slot1,
9015 FIELD_ftsf330ae_slot1,
9016 FIELD_ftsf332ae_slot1,
9017 FIELD_ftsf334ae_slot1,
9018 FIELD_ftsf336ae_slot1,
9019 FIELD_ftsf337ae_slot1,
9021 FIELD_ftsf339ae_slot1,
9023 FIELD_ftsf341ae_slot1,
9024 FIELD_ftsf342ae_slot1,
9025 FIELD_ftsf343ae_slot1,
9026 FIELD_ftsf344ae_slot1,
9027 FIELD_ftsf346ae_slot1,
9029 FIELD_ftsf348ae_slot1,
9030 FIELD_ftsf349ae_slot1,
9031 FIELD_ftsf350ae_slot1,
9033 FIELD_ftsf212ae_slot0,
9034 FIELD_ftsf213ae_slot0,
9035 FIELD_ftsf214ae_slot0,
9036 FIELD_ftsf215ae_slot0,
9037 FIELD_ftsf216ae_slot0,
9039 FIELD_ftsf218ae_slot0,
9040 FIELD_ftsf219ae_slot0,
9041 FIELD_ftsf220ae_slot0,
9042 FIELD_ftsf221ae_slot0,
9043 FIELD_ftsf222ae_slot0,
9044 FIELD_ftsf223ae_slot0,
9045 FIELD_ftsf224ae_slot0,
9046 FIELD_ftsf225ae_slot0,
9047 FIELD_ftsf226ae_slot0,
9048 FIELD_ftsf227ae_slot0,
9049 FIELD_ftsf228ae_slot0,
9050 FIELD_ftsf229ae_slot0,
9051 FIELD_ftsf230ae_slot0,
9052 FIELD_ftsf231ae_slot0,
9053 FIELD_ftsf232ae_slot0,
9054 FIELD_ftsf233ae_slot0,
9055 FIELD_ftsf234ae_slot0,
9056 FIELD_ftsf235ae_slot0,
9057 FIELD_ftsf236ae_slot0,
9058 FIELD_ftsf237ae_slot0,
9059 FIELD_ftsf238ae_slot0,
9060 FIELD_ftsf239ae_slot0,
9061 FIELD_ftsf240ae_slot0,
9062 FIELD_ftsf241ae_slot0,
9063 FIELD_ftsf242ae_slot0,
9064 FIELD_ftsf243ae_slot0,
9065 FIELD_ftsf244ae_slot0,
9066 FIELD_ftsf245ae_slot0,
9067 FIELD_ftsf246ae_slot0,
9068 FIELD_ftsf247ae_slot0,
9069 FIELD_ftsf248ae_slot0,
9070 FIELD_ftsf249ae_slot0,
9071 FIELD_ftsf250ae_slot0,
9072 FIELD_ftsf251ae_slot0,
9073 FIELD_ftsf252ae_slot0,
9074 FIELD_ftsf253ae_slot0,
9075 FIELD_ftsf254ae_slot0,
9076 FIELD_ftsf255ae_slot0,
9077 FIELD_ftsf256ae_slot0,
9078 FIELD_ftsf257ae_slot0,
9079 FIELD_ftsf258ae_slot0,
9080 FIELD_ftsf259ae_slot0,
9081 FIELD_ftsf260ae_slot0,
9082 FIELD_ftsf261ae_slot0,
9083 FIELD_ftsf262ae_slot0,
9084 FIELD_ftsf263ae_slot0,
9085 FIELD_ftsf264ae_slot0,
9086 FIELD_ftsf265ae_slot0,
9087 FIELD_ftsf266ae_slot0,
9088 FIELD_ftsf267ae_slot0,
9089 FIELD_ftsf268ae_slot0,
9090 FIELD_ftsf269ae_slot0,
9091 FIELD_ftsf270ae_slot0,
9092 FIELD_ftsf271ae_slot0,
9093 FIELD_ftsf272ae_slot0,
9094 FIELD_ftsf273ae_slot0,
9095 FIELD_ftsf274ae_slot0,
9096 FIELD_ftsf275ae_slot0,
9097 FIELD_ftsf276ae_slot0,
9098 FIELD_ftsf277ae_slot0,
9099 FIELD_ftsf278ae_slot0,
9100 FIELD_ftsf279ae_slot0,
9101 FIELD_ftsf281ae_slot0,
9102 FIELD_ftsf282ae_slot0,
9103 FIELD_ftsf283ae_slot0,
9104 FIELD_ftsf284ae_slot0,
9105 FIELD_ftsf286ae_slot0,
9106 FIELD_ftsf288ae_slot0,
9107 FIELD_ftsf290ae_slot0,
9108 FIELD_ftsf292ae_slot0,
9110 FIELD_ftsf294ae_slot0,
9111 FIELD_ftsf295ae_slot0,
9112 FIELD_ftsf296ae_slot0,
9113 FIELD_ftsf297ae_slot0,
9114 FIELD_ftsf298ae_slot0,
9115 FIELD_ftsf299ae_slot0,
9116 FIELD_ftsf300ae_slot0,
9117 FIELD_ftsf301ae_slot0,
9118 FIELD_ftsf302ae_slot0,
9119 FIELD_ftsf303ae_slot0,
9120 FIELD_ftsf304ae_slot0,
9121 FIELD_ftsf306ae_slot0,
9122 FIELD_ftsf308ae_slot0,
9123 FIELD_ftsf309ae_slot0,
9124 FIELD_ftsf310ae_slot0,
9125 FIELD_ftsf311ae_slot0,
9126 FIELD_ftsf312ae_slot0,
9127 FIELD_ftsf313ae_slot0,
9128 FIELD_ftsf314ae_slot0,
9129 FIELD_ftsf315ae_slot0,
9130 FIELD_ftsf316ae_slot0,
9131 FIELD_ftsf317ae_slot0,
9132 FIELD_ftsf318ae_slot0,
9134 FIELD_ftsf320ae_slot0,
9136 FIELD_ftsf322ae_slot0,
9137 FIELD_ftsf323ae_slot0,
9138 FIELD_ftsf324ae_slot0,
9139 FIELD_ftsf325ae_slot0,
9140 FIELD_ftsf326ae_slot0,
9141 FIELD_ftsf328ae_slot0,
9142 FIELD_ftsf329ae_slot0,
9143 FIELD_ftsf352ae_slot0,
9145 FIELD_ftsf354ae_slot0,
9146 FIELD_ftsf356ae_slot0,
9148 FIELD_ftsf358ae_slot0,
9149 FIELD_ftsf359ae_slot0,
9150 FIELD_ftsf360ae_slot0,
9151 FIELD_ftsf361ae_slot0,
9152 FIELD_ftsf362ae_slot0,
9153 FIELD_ftsf364ae_slot0,
9154 FIELD_ftsf365ae_slot0,
9155 FIELD_ftsf366ae_slot0,
9156 FIELD_ftsf368ae_slot0,
9157 FIELD_ftsf369ae_slot0,
9169 /* Functional units. */
9171 static xtensa_funcUnit_internal funcUnits[] = {
9173 { "ae_shift32x4", 1 },
9174 { "ae_shift32x5", 1 },
9175 { "ae_subshift", 1 }
9178 enum xtensa_funcUnit_id {
9180 FUNCUNIT_ae_shift32x4,
9181 FUNCUNIT_ae_shift32x5,
9182 FUNCUNIT_ae_subshift
9186 /* Register files. */
9188 enum xtensa_regfile_id {
9199 static xtensa_regfile_internal regfiles[] = {
9200 { "AR", "a", REGFILE_AR, 32, 32 },
9201 { "BR", "b", REGFILE_BR, 1, 16 },
9202 { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
9203 { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
9204 { "BR2", "b", REGFILE_BR, 2, 8 },
9205 { "BR4", "b", REGFILE_BR, 4, 4 },
9206 { "BR8", "b", REGFILE_BR, 8, 2 },
9207 { "BR16", "b", REGFILE_BR, 16, 1 }
9213 static xtensa_interface_internal interfaces[] = {
9214 { "RMPINT_Out", 12, 0, 0, 'o' },
9215 { "RMPINT_In", 32, 0, 1, 'i' }
9218 enum xtensa_interface_id {
9219 INTERFACE_RMPINT_Out,
9224 /* Constant tables. */
9226 /* constant table ai4c */
9227 static const unsigned CONST_TBL_ai4c_0[] = {
9247 /* constant table b4c */
9248 static const unsigned CONST_TBL_b4c_0[] = {
9268 /* constant table b4cu */
9269 static const unsigned CONST_TBL_b4cu_0[] = {
9290 /* Instruction operands. */
9293 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
9295 unsigned soffsetx4_out_0;
9296 unsigned soffsetx4_in_0;
9297 soffsetx4_in_0 = *valp & 0x3ffff;
9298 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
9299 *valp = soffsetx4_out_0;
9304 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
9306 unsigned soffsetx4_in_0;
9307 unsigned soffsetx4_out_0;
9308 soffsetx4_out_0 = *valp;
9309 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
9310 *valp = soffsetx4_in_0;
9315 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
9317 unsigned uimm12x8_out_0;
9318 unsigned uimm12x8_in_0;
9319 uimm12x8_in_0 = *valp & 0xfff;
9320 uimm12x8_out_0 = uimm12x8_in_0 << 3;
9321 *valp = uimm12x8_out_0;
9326 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
9328 unsigned uimm12x8_in_0;
9329 unsigned uimm12x8_out_0;
9330 uimm12x8_out_0 = *valp;
9331 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
9332 *valp = uimm12x8_in_0;
9337 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
9339 unsigned simm4_out_0;
9340 unsigned simm4_in_0;
9341 simm4_in_0 = *valp & 0xf;
9342 simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
9343 *valp = simm4_out_0;
9348 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
9350 unsigned simm4_in_0;
9351 unsigned simm4_out_0;
9352 simm4_out_0 = *valp;
9353 simm4_in_0 = (simm4_out_0 & 0xf);
9359 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
9365 OperandSem_opnd_sem_AR_encode (uint32 *valp)
9368 error = (*valp >= 32);
9373 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
9379 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
9382 error = (*valp >= 32);
9387 OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
9393 OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
9396 error = (*valp >= 32);
9401 OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
9407 OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
9410 error = (*valp >= 32);
9415 OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
9421 OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
9424 error = (*valp >= 32);
9429 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
9435 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
9438 error = (*valp >= 32);
9443 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
9445 unsigned immrx4_out_0;
9446 unsigned immrx4_in_0;
9447 immrx4_in_0 = *valp & 0xf;
9448 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
9449 *valp = immrx4_out_0;
9454 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
9456 unsigned immrx4_in_0;
9457 unsigned immrx4_out_0;
9458 immrx4_out_0 = *valp;
9459 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
9460 *valp = immrx4_in_0;
9465 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
9467 unsigned lsi4x4_out_0;
9468 unsigned lsi4x4_in_0;
9469 lsi4x4_in_0 = *valp & 0xf;
9470 lsi4x4_out_0 = lsi4x4_in_0 << 2;
9471 *valp = lsi4x4_out_0;
9476 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
9478 unsigned lsi4x4_in_0;
9479 unsigned lsi4x4_out_0;
9480 lsi4x4_out_0 = *valp;
9481 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
9482 *valp = lsi4x4_in_0;
9487 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
9489 unsigned simm7_out_0;
9490 unsigned simm7_in_0;
9491 simm7_in_0 = *valp & 0x7f;
9492 simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
9493 *valp = simm7_out_0;
9498 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
9500 unsigned simm7_in_0;
9501 unsigned simm7_out_0;
9502 simm7_out_0 = *valp;
9503 simm7_in_0 = (simm7_out_0 & 0x7f);
9509 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
9511 unsigned uimm6_out_0;
9512 unsigned uimm6_in_0;
9513 uimm6_in_0 = *valp & 0x3f;
9514 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
9515 *valp = uimm6_out_0;
9520 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
9522 unsigned uimm6_in_0;
9523 unsigned uimm6_out_0;
9524 uimm6_out_0 = *valp;
9525 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
9531 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
9533 unsigned ai4const_out_0;
9534 unsigned ai4const_in_0;
9535 ai4const_in_0 = *valp & 0xf;
9536 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
9537 *valp = ai4const_out_0;
9542 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
9544 unsigned ai4const_in_0;
9545 unsigned ai4const_out_0;
9546 ai4const_out_0 = *valp;
9547 switch (ai4const_out_0)
9549 case 0xffffffff: ai4const_in_0 = 0; break;
9550 case 0x1: ai4const_in_0 = 0x1; break;
9551 case 0x2: ai4const_in_0 = 0x2; break;
9552 case 0x3: ai4const_in_0 = 0x3; break;
9553 case 0x4: ai4const_in_0 = 0x4; break;
9554 case 0x5: ai4const_in_0 = 0x5; break;
9555 case 0x6: ai4const_in_0 = 0x6; break;
9556 case 0x7: ai4const_in_0 = 0x7; break;
9557 case 0x8: ai4const_in_0 = 0x8; break;
9558 case 0x9: ai4const_in_0 = 0x9; break;
9559 case 0xa: ai4const_in_0 = 0xa; break;
9560 case 0xb: ai4const_in_0 = 0xb; break;
9561 case 0xc: ai4const_in_0 = 0xc; break;
9562 case 0xd: ai4const_in_0 = 0xd; break;
9563 case 0xe: ai4const_in_0 = 0xe; break;
9564 default: ai4const_in_0 = 0xf; break;
9566 *valp = ai4const_in_0;
9571 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
9573 unsigned b4const_out_0;
9574 unsigned b4const_in_0;
9575 b4const_in_0 = *valp & 0xf;
9576 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
9577 *valp = b4const_out_0;
9582 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
9584 unsigned b4const_in_0;
9585 unsigned b4const_out_0;
9586 b4const_out_0 = *valp;
9587 switch (b4const_out_0)
9589 case 0xffffffff: b4const_in_0 = 0; break;
9590 case 0x1: b4const_in_0 = 0x1; break;
9591 case 0x2: b4const_in_0 = 0x2; break;
9592 case 0x3: b4const_in_0 = 0x3; break;
9593 case 0x4: b4const_in_0 = 0x4; break;
9594 case 0x5: b4const_in_0 = 0x5; break;
9595 case 0x6: b4const_in_0 = 0x6; break;
9596 case 0x7: b4const_in_0 = 0x7; break;
9597 case 0x8: b4const_in_0 = 0x8; break;
9598 case 0xa: b4const_in_0 = 0x9; break;
9599 case 0xc: b4const_in_0 = 0xa; break;
9600 case 0x10: b4const_in_0 = 0xb; break;
9601 case 0x20: b4const_in_0 = 0xc; break;
9602 case 0x40: b4const_in_0 = 0xd; break;
9603 case 0x80: b4const_in_0 = 0xe; break;
9604 default: b4const_in_0 = 0xf; break;
9606 *valp = b4const_in_0;
9611 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
9613 unsigned b4constu_out_0;
9614 unsigned b4constu_in_0;
9615 b4constu_in_0 = *valp & 0xf;
9616 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
9617 *valp = b4constu_out_0;
9622 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
9624 unsigned b4constu_in_0;
9625 unsigned b4constu_out_0;
9626 b4constu_out_0 = *valp;
9627 switch (b4constu_out_0)
9629 case 0x8000: b4constu_in_0 = 0; break;
9630 case 0x10000: b4constu_in_0 = 0x1; break;
9631 case 0x2: b4constu_in_0 = 0x2; break;
9632 case 0x3: b4constu_in_0 = 0x3; break;
9633 case 0x4: b4constu_in_0 = 0x4; break;
9634 case 0x5: b4constu_in_0 = 0x5; break;
9635 case 0x6: b4constu_in_0 = 0x6; break;
9636 case 0x7: b4constu_in_0 = 0x7; break;
9637 case 0x8: b4constu_in_0 = 0x8; break;
9638 case 0xa: b4constu_in_0 = 0x9; break;
9639 case 0xc: b4constu_in_0 = 0xa; break;
9640 case 0x10: b4constu_in_0 = 0xb; break;
9641 case 0x20: b4constu_in_0 = 0xc; break;
9642 case 0x40: b4constu_in_0 = 0xd; break;
9643 case 0x80: b4constu_in_0 = 0xe; break;
9644 default: b4constu_in_0 = 0xf; break;
9646 *valp = b4constu_in_0;
9651 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
9653 unsigned uimm8_out_0;
9654 unsigned uimm8_in_0;
9655 uimm8_in_0 = *valp & 0xff;
9656 uimm8_out_0 = uimm8_in_0;
9657 *valp = uimm8_out_0;
9662 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
9664 unsigned uimm8_in_0;
9665 unsigned uimm8_out_0;
9666 uimm8_out_0 = *valp;
9667 uimm8_in_0 = (uimm8_out_0 & 0xff);
9673 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
9675 unsigned uimm8x2_out_0;
9676 unsigned uimm8x2_in_0;
9677 uimm8x2_in_0 = *valp & 0xff;
9678 uimm8x2_out_0 = uimm8x2_in_0 << 1;
9679 *valp = uimm8x2_out_0;
9684 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
9686 unsigned uimm8x2_in_0;
9687 unsigned uimm8x2_out_0;
9688 uimm8x2_out_0 = *valp;
9689 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
9690 *valp = uimm8x2_in_0;
9695 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
9697 unsigned uimm8x4_out_0;
9698 unsigned uimm8x4_in_0;
9699 uimm8x4_in_0 = *valp & 0xff;
9700 uimm8x4_out_0 = uimm8x4_in_0 << 2;
9701 *valp = uimm8x4_out_0;
9706 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
9708 unsigned uimm8x4_in_0;
9709 unsigned uimm8x4_out_0;
9710 uimm8x4_out_0 = *valp;
9711 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
9712 *valp = uimm8x4_in_0;
9717 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
9719 unsigned uimm4x16_out_0;
9720 unsigned uimm4x16_in_0;
9721 uimm4x16_in_0 = *valp & 0xf;
9722 uimm4x16_out_0 = uimm4x16_in_0 << 4;
9723 *valp = uimm4x16_out_0;
9728 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
9730 unsigned uimm4x16_in_0;
9731 unsigned uimm4x16_out_0;
9732 uimm4x16_out_0 = *valp;
9733 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
9734 *valp = uimm4x16_in_0;
9739 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
9741 unsigned simm8_out_0;
9742 unsigned simm8_in_0;
9743 simm8_in_0 = *valp & 0xff;
9744 simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
9745 *valp = simm8_out_0;
9750 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
9752 unsigned simm8_in_0;
9753 unsigned simm8_out_0;
9754 simm8_out_0 = *valp;
9755 simm8_in_0 = (simm8_out_0 & 0xff);
9761 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
9763 unsigned simm8x256_out_0;
9764 unsigned simm8x256_in_0;
9765 simm8x256_in_0 = *valp & 0xff;
9766 simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
9767 *valp = simm8x256_out_0;
9772 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
9774 unsigned simm8x256_in_0;
9775 unsigned simm8x256_out_0;
9776 simm8x256_out_0 = *valp;
9777 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
9778 *valp = simm8x256_in_0;
9783 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
9785 unsigned simm12b_out_0;
9786 unsigned simm12b_in_0;
9787 simm12b_in_0 = *valp & 0xfff;
9788 simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
9789 *valp = simm12b_out_0;
9794 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
9796 unsigned simm12b_in_0;
9797 unsigned simm12b_out_0;
9798 simm12b_out_0 = *valp;
9799 simm12b_in_0 = (simm12b_out_0 & 0xfff);
9800 *valp = simm12b_in_0;
9805 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
9807 unsigned msalp32_out_0;
9808 unsigned msalp32_in_0;
9809 msalp32_in_0 = *valp & 0x1f;
9810 msalp32_out_0 = 0x20 - msalp32_in_0;
9811 *valp = msalp32_out_0;
9816 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
9818 unsigned msalp32_in_0;
9819 unsigned msalp32_out_0;
9820 msalp32_out_0 = *valp;
9821 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
9822 *valp = msalp32_in_0;
9827 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
9829 unsigned op2p1_out_0;
9830 unsigned op2p1_in_0;
9831 op2p1_in_0 = *valp & 0xf;
9832 op2p1_out_0 = op2p1_in_0 + 0x1;
9833 *valp = op2p1_out_0;
9838 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
9840 unsigned op2p1_in_0;
9841 unsigned op2p1_out_0;
9842 op2p1_out_0 = *valp;
9843 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
9849 OperandSem_opnd_sem_label8_decode (uint32 *valp)
9851 unsigned label8_out_0;
9852 unsigned label8_in_0;
9853 label8_in_0 = *valp & 0xff;
9854 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
9855 *valp = label8_out_0;
9860 OperandSem_opnd_sem_label8_encode (uint32 *valp)
9862 unsigned label8_in_0;
9863 unsigned label8_out_0;
9864 label8_out_0 = *valp;
9865 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
9866 *valp = label8_in_0;
9871 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
9873 unsigned ulabel8_out_0;
9874 unsigned ulabel8_in_0;
9875 ulabel8_in_0 = *valp & 0xff;
9876 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
9877 *valp = ulabel8_out_0;
9882 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
9884 unsigned ulabel8_in_0;
9885 unsigned ulabel8_out_0;
9886 ulabel8_out_0 = *valp;
9887 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
9888 *valp = ulabel8_in_0;
9893 OperandSem_opnd_sem_label12_decode (uint32 *valp)
9895 unsigned label12_out_0;
9896 unsigned label12_in_0;
9897 label12_in_0 = *valp & 0xfff;
9898 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
9899 *valp = label12_out_0;
9904 OperandSem_opnd_sem_label12_encode (uint32 *valp)
9906 unsigned label12_in_0;
9907 unsigned label12_out_0;
9908 label12_out_0 = *valp;
9909 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
9910 *valp = label12_in_0;
9915 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
9917 unsigned soffset_out_0;
9918 unsigned soffset_in_0;
9919 soffset_in_0 = *valp & 0x3ffff;
9920 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
9921 *valp = soffset_out_0;
9926 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
9928 unsigned soffset_in_0;
9929 unsigned soffset_out_0;
9930 soffset_out_0 = *valp;
9931 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
9932 *valp = soffset_in_0;
9937 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
9939 unsigned uimm16x4_out_0;
9940 unsigned uimm16x4_in_0;
9941 uimm16x4_in_0 = *valp & 0xffff;
9942 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
9943 *valp = uimm16x4_out_0;
9948 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
9950 unsigned uimm16x4_in_0;
9951 unsigned uimm16x4_out_0;
9952 uimm16x4_out_0 = *valp;
9953 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
9954 *valp = uimm16x4_in_0;
9959 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
9963 bbi_in_0 = *valp & 0x1f;
9964 bbi_out_0 = (0 << 5) | bbi_in_0;
9970 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
9975 bbi_in_0 = (bbi_out_0 & 0x1f);
9981 OperandSem_opnd_sem_s_decode (uint32 *valp)
9985 s_in_0 = *valp & 0xf;
9986 s_out_0 = (0 << 4) | s_in_0;
9992 OperandSem_opnd_sem_s_encode (uint32 *valp)
9997 s_in_0 = (s_out_0 & 0xf);
10003 OperandSem_opnd_sem_immt_decode (uint32 *valp)
10005 unsigned immt_out_0;
10006 unsigned immt_in_0;
10007 immt_in_0 = *valp & 0xf;
10008 immt_out_0 = immt_in_0;
10009 *valp = immt_out_0;
10014 OperandSem_opnd_sem_immt_encode (uint32 *valp)
10016 unsigned immt_in_0;
10017 unsigned immt_out_0;
10018 immt_out_0 = *valp;
10019 immt_in_0 = immt_out_0 & 0xf;
10025 OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10031 OperandSem_opnd_sem_BR_encode (uint32 *valp)
10034 error = (*valp >= 16);
10039 OperandSem_opnd_sem_BR2_decode (uint32 *valp)
10041 *valp = *valp << 1;
10046 OperandSem_opnd_sem_BR2_encode (uint32 *valp)
10049 error = (*valp >= 16) || ((*valp & 1) != 0);
10050 *valp = *valp >> 1;
10055 OperandSem_opnd_sem_BR4_decode (uint32 *valp)
10057 *valp = *valp << 2;
10062 OperandSem_opnd_sem_BR4_encode (uint32 *valp)
10065 error = (*valp >= 16) || ((*valp & 3) != 0);
10066 *valp = *valp >> 2;
10071 OperandSem_opnd_sem_BR8_decode (uint32 *valp)
10073 *valp = *valp << 3;
10078 OperandSem_opnd_sem_BR8_encode (uint32 *valp)
10081 error = (*valp >= 16) || ((*valp & 7) != 0);
10082 *valp = *valp >> 3;
10087 OperandSem_opnd_sem_BR16_decode (uint32 *valp)
10089 *valp = *valp << 4;
10094 OperandSem_opnd_sem_BR16_encode (uint32 *valp)
10097 error = (*valp >= 16) || ((*valp & 15) != 0);
10098 *valp = *valp >> 4;
10103 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
10105 unsigned tp7_out_0;
10107 tp7_in_0 = *valp & 0xf;
10108 tp7_out_0 = tp7_in_0 + 0x7;
10114 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
10117 unsigned tp7_out_0;
10119 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
10125 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
10127 unsigned xt_wbr15_label_out_0;
10128 unsigned xt_wbr15_label_in_0;
10129 xt_wbr15_label_in_0 = *valp & 0x7fff;
10130 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
10131 *valp = xt_wbr15_label_out_0;
10136 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
10138 unsigned xt_wbr15_label_in_0;
10139 unsigned xt_wbr15_label_out_0;
10140 xt_wbr15_label_out_0 = *valp;
10141 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
10142 *valp = xt_wbr15_label_in_0;
10147 OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
10149 unsigned ae_samt32_out_0;
10150 unsigned ae_samt32_in_0;
10151 ae_samt32_in_0 = *valp & 0x1f;
10152 ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
10153 *valp = ae_samt32_out_0;
10158 OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
10160 unsigned ae_samt32_in_0;
10161 unsigned ae_samt32_out_0;
10162 ae_samt32_out_0 = *valp;
10163 ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
10164 *valp = ae_samt32_in_0;
10169 OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10175 OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
10178 error = (*valp >= 8);
10183 OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10189 OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
10192 error = (*valp >= 4);
10197 OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
10199 unsigned ae_lsimm16_out_0;
10200 unsigned ae_lsimm16_in_0;
10201 ae_lsimm16_in_0 = *valp & 0xf;
10202 ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
10203 *valp = ae_lsimm16_out_0;
10208 OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
10210 unsigned ae_lsimm16_in_0;
10211 unsigned ae_lsimm16_out_0;
10212 ae_lsimm16_out_0 = *valp;
10213 ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
10214 *valp = ae_lsimm16_in_0;
10219 OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
10221 unsigned ae_lsimm32_out_0;
10222 unsigned ae_lsimm32_in_0;
10223 ae_lsimm32_in_0 = *valp & 0xf;
10224 ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
10225 *valp = ae_lsimm32_out_0;
10230 OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
10232 unsigned ae_lsimm32_in_0;
10233 unsigned ae_lsimm32_out_0;
10234 ae_lsimm32_out_0 = *valp;
10235 ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
10236 *valp = ae_lsimm32_in_0;
10241 OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
10243 unsigned ae_lsimm64_out_0;
10244 unsigned ae_lsimm64_in_0;
10245 ae_lsimm64_in_0 = *valp & 0xf;
10246 ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
10247 *valp = ae_lsimm64_out_0;
10252 OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
10254 unsigned ae_lsimm64_in_0;
10255 unsigned ae_lsimm64_out_0;
10256 ae_lsimm64_out_0 = *valp;
10257 ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
10258 *valp = ae_lsimm64_in_0;
10263 OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
10265 unsigned ae_samt64_out_0;
10266 unsigned ae_samt64_in_0;
10267 ae_samt64_in_0 = *valp & 0x3f;
10268 ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
10269 *valp = ae_samt64_out_0;
10274 OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
10276 unsigned ae_samt64_in_0;
10277 unsigned ae_samt64_out_0;
10278 ae_samt64_out_0 = *valp;
10279 ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
10280 *valp = ae_samt64_in_0;
10285 OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
10287 unsigned ae_ohba_out_0;
10288 unsigned ae_ohba_in_0;
10289 ae_ohba_in_0 = *valp & 0xf;
10290 ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
10291 *valp = ae_ohba_out_0;
10296 OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
10298 unsigned ae_ohba_in_0;
10299 unsigned ae_ohba_out_0;
10300 ae_ohba_out_0 = *valp;
10301 ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
10302 *valp = ae_ohba_in_0;
10307 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
10309 *valp -= (pc & ~0x3);
10314 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
10316 *valp += (pc & ~0x3);
10321 Operand_uimm6_ator (uint32 *valp, uint32 pc)
10328 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
10335 Operand_label8_ator (uint32 *valp, uint32 pc)
10342 Operand_label8_rtoa (uint32 *valp, uint32 pc)
10349 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
10356 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
10363 Operand_label12_ator (uint32 *valp, uint32 pc)
10370 Operand_label12_rtoa (uint32 *valp, uint32 pc)
10377 Operand_soffset_ator (uint32 *valp, uint32 pc)
10384 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
10391 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
10393 *valp -= ((pc + 3) & ~0x3);
10398 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
10400 *valp += ((pc + 3) & ~0x3);
10405 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
10412 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
10419 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
10426 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
10432 static xtensa_operand_internal operands[] = {
10433 { "soffsetx4", FIELD_offset, -1, 0,
10434 XTENSA_OPERAND_IS_PCRELATIVE,
10435 OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
10436 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
10437 { "uimm12x8", FIELD_imm12, -1, 0,
10439 OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
10441 { "simm4", FIELD_mn, -1, 0,
10443 OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
10445 { "arr", FIELD_r, REGFILE_AR, 1,
10446 XTENSA_OPERAND_IS_REGISTER,
10447 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10449 { "ars", FIELD_s, REGFILE_AR, 1,
10450 XTENSA_OPERAND_IS_REGISTER,
10451 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10453 { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
10454 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10455 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10457 { "art", FIELD_t, REGFILE_AR, 1,
10458 XTENSA_OPERAND_IS_REGISTER,
10459 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10461 { "ar0", FIELD__ar0, REGFILE_AR, 1,
10462 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10463 OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
10465 { "ar4", FIELD__ar4, REGFILE_AR, 1,
10466 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10467 OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
10469 { "ar8", FIELD__ar8, REGFILE_AR, 1,
10470 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10471 OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
10473 { "ar12", FIELD__ar12, REGFILE_AR, 1,
10474 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10475 OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
10477 { "ars_entry", FIELD_s, REGFILE_AR, 1,
10478 XTENSA_OPERAND_IS_REGISTER,
10479 OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
10481 { "immrx4", FIELD_r, -1, 0,
10483 OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
10485 { "lsi4x4", FIELD_r, -1, 0,
10487 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
10489 { "simm7", FIELD_imm7, -1, 0,
10491 OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
10493 { "uimm6", FIELD_imm6, -1, 0,
10494 XTENSA_OPERAND_IS_PCRELATIVE,
10495 OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
10496 Operand_uimm6_ator, Operand_uimm6_rtoa },
10497 { "ai4const", FIELD_t, -1, 0,
10499 OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
10501 { "b4const", FIELD_r, -1, 0,
10503 OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
10505 { "b4constu", FIELD_r, -1, 0,
10507 OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
10509 { "uimm8", FIELD_imm8, -1, 0,
10511 OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
10513 { "uimm8x2", FIELD_imm8, -1, 0,
10515 OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
10517 { "uimm8x4", FIELD_imm8, -1, 0,
10519 OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
10521 { "uimm4x16", FIELD_op2, -1, 0,
10523 OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
10525 { "uimmrx4", FIELD_r, -1, 0,
10527 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
10529 { "simm8", FIELD_imm8, -1, 0,
10531 OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
10533 { "simm8x256", FIELD_imm8, -1, 0,
10535 OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
10537 { "simm12b", FIELD_imm12b, -1, 0,
10539 OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
10541 { "msalp32", FIELD_sal, -1, 0,
10543 OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
10545 { "op2p1", FIELD_op2, -1, 0,
10547 OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
10549 { "label8", FIELD_imm8, -1, 0,
10550 XTENSA_OPERAND_IS_PCRELATIVE,
10551 OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
10552 Operand_label8_ator, Operand_label8_rtoa },
10553 { "ulabel8", FIELD_imm8, -1, 0,
10554 XTENSA_OPERAND_IS_PCRELATIVE,
10555 OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
10556 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
10557 { "label12", FIELD_imm12, -1, 0,
10558 XTENSA_OPERAND_IS_PCRELATIVE,
10559 OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
10560 Operand_label12_ator, Operand_label12_rtoa },
10561 { "soffset", FIELD_offset, -1, 0,
10562 XTENSA_OPERAND_IS_PCRELATIVE,
10563 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
10564 Operand_soffset_ator, Operand_soffset_rtoa },
10565 { "uimm16x4", FIELD_imm16, -1, 0,
10566 XTENSA_OPERAND_IS_PCRELATIVE,
10567 OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
10568 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
10569 { "bbi", FIELD_bbi, -1, 0,
10571 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10573 { "sae", FIELD_sae, -1, 0,
10575 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10577 { "sas", FIELD_sas, -1, 0,
10579 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10581 { "sargt", FIELD_sargt, -1, 0,
10583 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10585 { "s", FIELD_s, -1, 0,
10587 OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
10589 { "immt", FIELD_t, -1, 0,
10591 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
10593 { "imms", FIELD_s, -1, 0,
10595 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
10597 { "bt", FIELD_t, REGFILE_BR, 1,
10598 XTENSA_OPERAND_IS_REGISTER,
10599 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10601 { "bs", FIELD_s, REGFILE_BR, 1,
10602 XTENSA_OPERAND_IS_REGISTER,
10603 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10605 { "br", FIELD_r, REGFILE_BR, 1,
10606 XTENSA_OPERAND_IS_REGISTER,
10607 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10609 { "bt2", FIELD_t2, REGFILE_BR, 2,
10610 XTENSA_OPERAND_IS_REGISTER,
10611 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10613 { "bs2", FIELD_s2, REGFILE_BR, 2,
10614 XTENSA_OPERAND_IS_REGISTER,
10615 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10617 { "br2", FIELD_r2, REGFILE_BR, 2,
10618 XTENSA_OPERAND_IS_REGISTER,
10619 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10621 { "bt4", FIELD_t4, REGFILE_BR, 4,
10622 XTENSA_OPERAND_IS_REGISTER,
10623 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10625 { "bs4", FIELD_s4, REGFILE_BR, 4,
10626 XTENSA_OPERAND_IS_REGISTER,
10627 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10629 { "br4", FIELD_r4, REGFILE_BR, 4,
10630 XTENSA_OPERAND_IS_REGISTER,
10631 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10633 { "bt8", FIELD_t8, REGFILE_BR, 8,
10634 XTENSA_OPERAND_IS_REGISTER,
10635 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10637 { "bs8", FIELD_s8, REGFILE_BR, 8,
10638 XTENSA_OPERAND_IS_REGISTER,
10639 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10641 { "br8", FIELD_r8, REGFILE_BR, 8,
10642 XTENSA_OPERAND_IS_REGISTER,
10643 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10645 { "bt16", FIELD__bt16, REGFILE_BR, 16,
10646 XTENSA_OPERAND_IS_REGISTER,
10647 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10649 { "bs16", FIELD__bs16, REGFILE_BR, 16,
10650 XTENSA_OPERAND_IS_REGISTER,
10651 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10653 { "br16", FIELD__br16, REGFILE_BR, 16,
10654 XTENSA_OPERAND_IS_REGISTER,
10655 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10657 { "brall", FIELD__brall, REGFILE_BR, 16,
10658 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10659 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10661 { "tp7", FIELD_t, -1, 0,
10663 OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
10665 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
10666 XTENSA_OPERAND_IS_PCRELATIVE,
10667 OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
10668 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
10669 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
10670 XTENSA_OPERAND_IS_PCRELATIVE,
10671 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
10672 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
10673 { "ae_samt32", FIELD_ftsf14, -1, 0,
10675 OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
10677 { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
10678 XTENSA_OPERAND_IS_REGISTER,
10679 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10681 { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
10682 XTENSA_OPERAND_IS_REGISTER,
10683 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10685 { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
10686 XTENSA_OPERAND_IS_REGISTER,
10687 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10689 { "ae_lsimm16", FIELD_t, -1, 0,
10691 OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
10693 { "ae_lsimm32", FIELD_t, -1, 0,
10695 OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
10697 { "ae_lsimm64", FIELD_t, -1, 0,
10699 OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
10701 { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
10703 OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
10705 { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
10707 OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
10709 { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
10711 OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
10713 { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
10714 XTENSA_OPERAND_IS_REGISTER,
10715 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10717 { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
10718 XTENSA_OPERAND_IS_REGISTER,
10719 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10721 { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
10722 XTENSA_OPERAND_IS_REGISTER,
10723 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10725 { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
10726 XTENSA_OPERAND_IS_REGISTER,
10727 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10729 { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
10730 XTENSA_OPERAND_IS_REGISTER,
10731 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10733 { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
10734 XTENSA_OPERAND_IS_REGISTER,
10735 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10737 { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
10738 XTENSA_OPERAND_IS_REGISTER,
10739 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10741 { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
10742 XTENSA_OPERAND_IS_REGISTER,
10743 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10745 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
10746 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
10747 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
10748 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
10749 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
10750 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
10751 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
10752 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
10753 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
10754 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
10755 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
10756 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
10757 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
10758 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
10759 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
10760 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
10761 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
10762 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
10763 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
10764 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
10765 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
10766 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
10767 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
10768 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
10769 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
10770 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
10771 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
10772 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
10773 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
10774 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
10775 { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
10776 { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
10777 { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
10778 { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
10779 { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
10780 { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
10781 { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
10782 { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
10783 { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
10784 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
10785 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
10786 { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
10787 { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
10788 { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
10789 { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
10790 { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
10791 { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
10792 { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
10793 { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
10794 { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
10795 { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
10796 { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
10797 { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
10798 { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
10799 { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 },
10800 { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10801 { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10802 { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10803 { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10804 { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10805 { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10806 { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10807 { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10808 { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10809 { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10810 { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10811 { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10812 { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10813 { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10814 { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10815 { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10816 { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10817 { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10818 { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10819 { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10820 { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10821 { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10822 { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10823 { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10824 { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10825 { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10826 { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10827 { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10828 { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10829 { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10830 { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10831 { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10832 { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10833 { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10834 { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10835 { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10836 { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10837 { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10838 { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10839 { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10840 { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10841 { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10842 { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10843 { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10844 { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10845 { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10846 { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10847 { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10848 { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10849 { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10850 { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10851 { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10852 { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10853 { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10854 { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10855 { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10856 { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10857 { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10858 { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10859 { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10860 { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10861 { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10862 { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10863 { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10864 { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10865 { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10866 { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10867 { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10868 { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10869 { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10870 { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10871 { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10872 { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10873 { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10874 { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10875 { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10876 { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10877 { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10878 { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10879 { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10880 { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10881 { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10882 { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10883 { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10884 { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10885 { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10886 { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10887 { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10888 { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10889 { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10890 { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10891 { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10892 { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10893 { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10894 { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10895 { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10896 { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10897 { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10898 { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10899 { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10900 { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10901 { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10902 { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10903 { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10904 { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10905 { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10906 { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10907 { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10908 { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10909 { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10910 { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10911 { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10912 { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10913 { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10914 { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10915 { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10916 { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10917 { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10918 { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10919 { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10920 { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10921 { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10922 { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10923 { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10924 { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10925 { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10926 { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10927 { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10928 { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10929 { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10930 { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10931 { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10932 { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10933 { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10934 { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10935 { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10936 { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10937 { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10938 { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10939 { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10940 { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10941 { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10942 { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10943 { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10944 { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10945 { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10946 { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10947 { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10948 { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10949 { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10950 { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10951 { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10952 { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10953 { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10954 { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10955 { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10956 { "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10957 { "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10958 { "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10959 { "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10960 { "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10961 { "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10962 { "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10963 { "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10964 { "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10965 { "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10966 { "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10967 { "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10968 { "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10969 { "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10970 { "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10971 { "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10972 { "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10973 { "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10974 { "ftsf208", FIELD_ftsf208, -1, 0, 0, 0, 0, 0, 0 },
10975 { "ftsf209ae_slot1", FIELD_ftsf209ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10976 { "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10977 { "ftsf211ae_slot1", FIELD_ftsf211ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10978 { "ftsf330ae_slot1", FIELD_ftsf330ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10979 { "ftsf332ae_slot1", FIELD_ftsf332ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10980 { "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10981 { "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10982 { "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10983 { "ftsf338", FIELD_ftsf338, -1, 0, 0, 0, 0, 0, 0 },
10984 { "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10985 { "ftsf340", FIELD_ftsf340, -1, 0, 0, 0, 0, 0, 0 },
10986 { "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10987 { "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10988 { "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10989 { "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10990 { "ftsf346ae_slot1", FIELD_ftsf346ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10991 { "ftsf347", FIELD_ftsf347, -1, 0, 0, 0, 0, 0, 0 },
10992 { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10993 { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10994 { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
10995 { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 },
10996 { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
10997 { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
10998 { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
10999 { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11000 { "ftsf216ae_slot0", FIELD_ftsf216ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11001 { "ftsf217", FIELD_ftsf217, -1, 0, 0, 0, 0, 0, 0 },
11002 { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11003 { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11004 { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11005 { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11006 { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11007 { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11008 { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11009 { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11010 { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11011 { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11012 { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11013 { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11014 { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11015 { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11016 { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11017 { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11018 { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11019 { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11020 { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11021 { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11022 { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11023 { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11024 { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11025 { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11026 { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11027 { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11028 { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11029 { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11030 { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11031 { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11032 { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11033 { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11034 { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11035 { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11036 { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11037 { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11038 { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11039 { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11040 { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11041 { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11042 { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11043 { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11044 { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11045 { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11046 { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11047 { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11048 { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11049 { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11050 { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11051 { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11052 { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11053 { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11054 { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11055 { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11056 { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11057 { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11058 { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11059 { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11060 { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11061 { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11062 { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11063 { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11064 { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11065 { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11066 { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11067 { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11068 { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11069 { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11070 { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11071 { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11072 { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 },
11073 { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11074 { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11075 { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11076 { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11077 { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11078 { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11079 { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11080 { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11081 { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11082 { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11083 { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11084 { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11085 { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11086 { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11087 { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11088 { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11089 { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11090 { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11091 { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11092 { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11093 { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11094 { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11095 { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11096 { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 },
11097 { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11098 { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 },
11099 { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11100 { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11101 { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11102 { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11103 { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11104 { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11105 { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11106 { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11107 { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 },
11108 { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11109 { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11110 { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 },
11111 { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11112 { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11113 { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11114 { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11115 { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11116 { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11117 { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11118 { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11119 { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
11120 { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }
11123 enum xtensa_operand_id {
11129 OPERAND__ars_invisible,
11182 OPERAND_xt_wbr15_label,
11183 OPERAND_xt_wbr18_label,
11188 OPERAND_ae_lsimm16,
11189 OPERAND_ae_lsimm32,
11190 OPERAND_ae_lsimm64,
11197 OPERAND_mac_qr0_rw,
11201 OPERAND_alupppb_ps,
11241 OPERAND_xt_wbr15_imm,
11242 OPERAND_xt_wbr18_imm,
11244 OPERAND_ae_s_non_samt,
11247 OPERAND_ae_samt_s_t,
11251 OPERAND_ae_fld_ohba,
11252 OPERAND_ae_fld_ohba2,
11257 OPERAND_ftsf21ae_slot1,
11258 OPERAND_ftsf22ae_slot1,
11259 OPERAND_ftsf23ae_slot1,
11260 OPERAND_ftsf24ae_slot1,
11261 OPERAND_ftsf25ae_slot1,
11262 OPERAND_ftsf26ae_slot1,
11263 OPERAND_ftsf27ae_slot1,
11264 OPERAND_ftsf28ae_slot1,
11265 OPERAND_ftsf29ae_slot1,
11266 OPERAND_ftsf30ae_slot1,
11267 OPERAND_ftsf31ae_slot1,
11268 OPERAND_ftsf32ae_slot1,
11269 OPERAND_ftsf33ae_slot1,
11270 OPERAND_ftsf34ae_slot1,
11271 OPERAND_ftsf35ae_slot1,
11272 OPERAND_ftsf36ae_slot1,
11273 OPERAND_ftsf37ae_slot1,
11274 OPERAND_ftsf38ae_slot1,
11275 OPERAND_ftsf39ae_slot1,
11276 OPERAND_ftsf40ae_slot1,
11277 OPERAND_ftsf41ae_slot1,
11278 OPERAND_ftsf42ae_slot1,
11279 OPERAND_ftsf43ae_slot1,
11280 OPERAND_ftsf44ae_slot1,
11281 OPERAND_ftsf45ae_slot1,
11282 OPERAND_ftsf46ae_slot1,
11283 OPERAND_ftsf47ae_slot1,
11284 OPERAND_ftsf48ae_slot1,
11285 OPERAND_ftsf49ae_slot1,
11286 OPERAND_ftsf50ae_slot1,
11287 OPERAND_ftsf51ae_slot1,
11288 OPERAND_ftsf52ae_slot1,
11289 OPERAND_ftsf53ae_slot1,
11290 OPERAND_ftsf54ae_slot1,
11291 OPERAND_ftsf55ae_slot1,
11292 OPERAND_ftsf56ae_slot1,
11293 OPERAND_ftsf57ae_slot1,
11294 OPERAND_ftsf58ae_slot1,
11295 OPERAND_ftsf59ae_slot1,
11296 OPERAND_ftsf60ae_slot1,
11297 OPERAND_ftsf61ae_slot1,
11298 OPERAND_ftsf63ae_slot1,
11299 OPERAND_ftsf64ae_slot1,
11300 OPERAND_ftsf66ae_slot1,
11301 OPERAND_ftsf67ae_slot1,
11302 OPERAND_ftsf69ae_slot1,
11303 OPERAND_ftsf71ae_slot1,
11304 OPERAND_ftsf72ae_slot1,
11305 OPERAND_ftsf73ae_slot1,
11306 OPERAND_ftsf75ae_slot1,
11307 OPERAND_ftsf76ae_slot1,
11308 OPERAND_ftsf77ae_slot1,
11309 OPERAND_ftsf78ae_slot1,
11310 OPERAND_ftsf79ae_slot1,
11311 OPERAND_ftsf80ae_slot1,
11312 OPERAND_ftsf81ae_slot1,
11313 OPERAND_ftsf82ae_slot1,
11314 OPERAND_ftsf84ae_slot1,
11315 OPERAND_ftsf86ae_slot1,
11316 OPERAND_ftsf87ae_slot1,
11317 OPERAND_ftsf88ae_slot1,
11318 OPERAND_ftsf89ae_slot1,
11319 OPERAND_ftsf90ae_slot1,
11320 OPERAND_ftsf91ae_slot1,
11321 OPERAND_ftsf92ae_slot1,
11322 OPERAND_ftsf94ae_slot1,
11323 OPERAND_ftsf96ae_slot1,
11324 OPERAND_ftsf97ae_slot1,
11325 OPERAND_ftsf98ae_slot1,
11326 OPERAND_ftsf99ae_slot1,
11327 OPERAND_ftsf100ae_slot1,
11328 OPERAND_ftsf101ae_slot1,
11329 OPERAND_ftsf103ae_slot1,
11330 OPERAND_ftsf104ae_slot1,
11331 OPERAND_ftsf105ae_slot1,
11332 OPERAND_ftsf106ae_slot1,
11333 OPERAND_ftsf107ae_slot1,
11334 OPERAND_ftsf108ae_slot1,
11335 OPERAND_ftsf109ae_slot1,
11336 OPERAND_ftsf110ae_slot1,
11337 OPERAND_ftsf111ae_slot1,
11338 OPERAND_ftsf112ae_slot1,
11339 OPERAND_ftsf113ae_slot1,
11340 OPERAND_ftsf114ae_slot1,
11341 OPERAND_ftsf115ae_slot1,
11342 OPERAND_ftsf116ae_slot1,
11343 OPERAND_ftsf118ae_slot1,
11344 OPERAND_ftsf119ae_slot1,
11345 OPERAND_ftsf120ae_slot1,
11346 OPERAND_ftsf122ae_slot1,
11347 OPERAND_ftsf124ae_slot1,
11348 OPERAND_ftsf125ae_slot1,
11349 OPERAND_ftsf126ae_slot1,
11350 OPERAND_ftsf127ae_slot1,
11351 OPERAND_ftsf128ae_slot1,
11352 OPERAND_ftsf129ae_slot1,
11353 OPERAND_ftsf130ae_slot1,
11354 OPERAND_ftsf131ae_slot1,
11355 OPERAND_ftsf132ae_slot1,
11356 OPERAND_ftsf133ae_slot1,
11357 OPERAND_ftsf134ae_slot1,
11358 OPERAND_ftsf135ae_slot1,
11359 OPERAND_ftsf136ae_slot1,
11360 OPERAND_ftsf137ae_slot1,
11361 OPERAND_ftsf138ae_slot1,
11362 OPERAND_ftsf139ae_slot1,
11363 OPERAND_ftsf140ae_slot1,
11364 OPERAND_ftsf141ae_slot1,
11365 OPERAND_ftsf142ae_slot1,
11366 OPERAND_ftsf143ae_slot1,
11367 OPERAND_ftsf144ae_slot1,
11368 OPERAND_ftsf145ae_slot1,
11369 OPERAND_ftsf146ae_slot1,
11370 OPERAND_ftsf147ae_slot1,
11371 OPERAND_ftsf148ae_slot1,
11372 OPERAND_ftsf149ae_slot1,
11373 OPERAND_ftsf150ae_slot1,
11374 OPERAND_ftsf151ae_slot1,
11375 OPERAND_ftsf152ae_slot1,
11376 OPERAND_ftsf153ae_slot1,
11377 OPERAND_ftsf154ae_slot1,
11378 OPERAND_ftsf155ae_slot1,
11379 OPERAND_ftsf156ae_slot1,
11380 OPERAND_ftsf157ae_slot1,
11381 OPERAND_ftsf158ae_slot1,
11382 OPERAND_ftsf159ae_slot1,
11383 OPERAND_ftsf160ae_slot1,
11384 OPERAND_ftsf161ae_slot1,
11385 OPERAND_ftsf162ae_slot1,
11386 OPERAND_ftsf163ae_slot1,
11387 OPERAND_ftsf164ae_slot1,
11388 OPERAND_ftsf165ae_slot1,
11389 OPERAND_ftsf166ae_slot1,
11390 OPERAND_ftsf167ae_slot1,
11391 OPERAND_ftsf168ae_slot1,
11392 OPERAND_ftsf169ae_slot1,
11393 OPERAND_ftsf170ae_slot1,
11394 OPERAND_ftsf171ae_slot1,
11395 OPERAND_ftsf172ae_slot1,
11396 OPERAND_ftsf173ae_slot1,
11397 OPERAND_ftsf174ae_slot1,
11398 OPERAND_ftsf175ae_slot1,
11399 OPERAND_ftsf176ae_slot1,
11400 OPERAND_ftsf177ae_slot1,
11401 OPERAND_ftsf178ae_slot1,
11402 OPERAND_ftsf179ae_slot1,
11403 OPERAND_ftsf180ae_slot1,
11404 OPERAND_ftsf181ae_slot1,
11405 OPERAND_ftsf182ae_slot1,
11406 OPERAND_ftsf183ae_slot1,
11407 OPERAND_ftsf184ae_slot1,
11408 OPERAND_ftsf185ae_slot1,
11409 OPERAND_ftsf186ae_slot1,
11410 OPERAND_ftsf187ae_slot1,
11411 OPERAND_ftsf188ae_slot1,
11412 OPERAND_ftsf189ae_slot1,
11413 OPERAND_ftsf190ae_slot1,
11414 OPERAND_ftsf191ae_slot1,
11415 OPERAND_ftsf192ae_slot1,
11416 OPERAND_ftsf193ae_slot1,
11417 OPERAND_ftsf194ae_slot1,
11418 OPERAND_ftsf195ae_slot1,
11419 OPERAND_ftsf196ae_slot1,
11420 OPERAND_ftsf197ae_slot1,
11421 OPERAND_ftsf198ae_slot1,
11422 OPERAND_ftsf199ae_slot1,
11423 OPERAND_ftsf200ae_slot1,
11424 OPERAND_ftsf201ae_slot1,
11425 OPERAND_ftsf202ae_slot1,
11426 OPERAND_ftsf203ae_slot1,
11427 OPERAND_ftsf204ae_slot1,
11428 OPERAND_ftsf205ae_slot1,
11429 OPERAND_ftsf206ae_slot1,
11430 OPERAND_ftsf207ae_slot1,
11432 OPERAND_ftsf209ae_slot1,
11433 OPERAND_ftsf210ae_slot1,
11434 OPERAND_ftsf211ae_slot1,
11435 OPERAND_ftsf330ae_slot1,
11436 OPERAND_ftsf332ae_slot1,
11437 OPERAND_ftsf334ae_slot1,
11438 OPERAND_ftsf336ae_slot1,
11439 OPERAND_ftsf337ae_slot1,
11441 OPERAND_ftsf339ae_slot1,
11443 OPERAND_ftsf341ae_slot1,
11444 OPERAND_ftsf342ae_slot1,
11445 OPERAND_ftsf343ae_slot1,
11446 OPERAND_ftsf344ae_slot1,
11447 OPERAND_ftsf346ae_slot1,
11449 OPERAND_ftsf348ae_slot1,
11450 OPERAND_ftsf349ae_slot1,
11451 OPERAND_ftsf350ae_slot1,
11453 OPERAND_ftsf212ae_slot0,
11454 OPERAND_ftsf213ae_slot0,
11455 OPERAND_ftsf214ae_slot0,
11456 OPERAND_ftsf215ae_slot0,
11457 OPERAND_ftsf216ae_slot0,
11459 OPERAND_ftsf218ae_slot0,
11460 OPERAND_ftsf219ae_slot0,
11461 OPERAND_ftsf220ae_slot0,
11462 OPERAND_ftsf221ae_slot0,
11463 OPERAND_ftsf222ae_slot0,
11464 OPERAND_ftsf223ae_slot0,
11465 OPERAND_ftsf224ae_slot0,
11466 OPERAND_ftsf225ae_slot0,
11467 OPERAND_ftsf226ae_slot0,
11468 OPERAND_ftsf227ae_slot0,
11469 OPERAND_ftsf228ae_slot0,
11470 OPERAND_ftsf229ae_slot0,
11471 OPERAND_ftsf230ae_slot0,
11472 OPERAND_ftsf231ae_slot0,
11473 OPERAND_ftsf232ae_slot0,
11474 OPERAND_ftsf233ae_slot0,
11475 OPERAND_ftsf234ae_slot0,
11476 OPERAND_ftsf235ae_slot0,
11477 OPERAND_ftsf236ae_slot0,
11478 OPERAND_ftsf237ae_slot0,
11479 OPERAND_ftsf238ae_slot0,
11480 OPERAND_ftsf239ae_slot0,
11481 OPERAND_ftsf240ae_slot0,
11482 OPERAND_ftsf241ae_slot0,
11483 OPERAND_ftsf242ae_slot0,
11484 OPERAND_ftsf243ae_slot0,
11485 OPERAND_ftsf244ae_slot0,
11486 OPERAND_ftsf245ae_slot0,
11487 OPERAND_ftsf246ae_slot0,
11488 OPERAND_ftsf247ae_slot0,
11489 OPERAND_ftsf248ae_slot0,
11490 OPERAND_ftsf249ae_slot0,
11491 OPERAND_ftsf250ae_slot0,
11492 OPERAND_ftsf251ae_slot0,
11493 OPERAND_ftsf252ae_slot0,
11494 OPERAND_ftsf253ae_slot0,
11495 OPERAND_ftsf254ae_slot0,
11496 OPERAND_ftsf255ae_slot0,
11497 OPERAND_ftsf256ae_slot0,
11498 OPERAND_ftsf257ae_slot0,
11499 OPERAND_ftsf258ae_slot0,
11500 OPERAND_ftsf259ae_slot0,
11501 OPERAND_ftsf260ae_slot0,
11502 OPERAND_ftsf261ae_slot0,
11503 OPERAND_ftsf262ae_slot0,
11504 OPERAND_ftsf263ae_slot0,
11505 OPERAND_ftsf264ae_slot0,
11506 OPERAND_ftsf265ae_slot0,
11507 OPERAND_ftsf266ae_slot0,
11508 OPERAND_ftsf267ae_slot0,
11509 OPERAND_ftsf268ae_slot0,
11510 OPERAND_ftsf269ae_slot0,
11511 OPERAND_ftsf270ae_slot0,
11512 OPERAND_ftsf271ae_slot0,
11513 OPERAND_ftsf272ae_slot0,
11514 OPERAND_ftsf273ae_slot0,
11515 OPERAND_ftsf274ae_slot0,
11516 OPERAND_ftsf275ae_slot0,
11517 OPERAND_ftsf276ae_slot0,
11518 OPERAND_ftsf277ae_slot0,
11519 OPERAND_ftsf278ae_slot0,
11520 OPERAND_ftsf279ae_slot0,
11521 OPERAND_ftsf281ae_slot0,
11522 OPERAND_ftsf282ae_slot0,
11523 OPERAND_ftsf283ae_slot0,
11524 OPERAND_ftsf284ae_slot0,
11525 OPERAND_ftsf286ae_slot0,
11526 OPERAND_ftsf288ae_slot0,
11527 OPERAND_ftsf290ae_slot0,
11528 OPERAND_ftsf292ae_slot0,
11530 OPERAND_ftsf294ae_slot0,
11531 OPERAND_ftsf295ae_slot0,
11532 OPERAND_ftsf296ae_slot0,
11533 OPERAND_ftsf297ae_slot0,
11534 OPERAND_ftsf298ae_slot0,
11535 OPERAND_ftsf299ae_slot0,
11536 OPERAND_ftsf300ae_slot0,
11537 OPERAND_ftsf301ae_slot0,
11538 OPERAND_ftsf302ae_slot0,
11539 OPERAND_ftsf303ae_slot0,
11540 OPERAND_ftsf304ae_slot0,
11541 OPERAND_ftsf306ae_slot0,
11542 OPERAND_ftsf308ae_slot0,
11543 OPERAND_ftsf309ae_slot0,
11544 OPERAND_ftsf310ae_slot0,
11545 OPERAND_ftsf311ae_slot0,
11546 OPERAND_ftsf312ae_slot0,
11547 OPERAND_ftsf313ae_slot0,
11548 OPERAND_ftsf314ae_slot0,
11549 OPERAND_ftsf315ae_slot0,
11550 OPERAND_ftsf316ae_slot0,
11551 OPERAND_ftsf317ae_slot0,
11552 OPERAND_ftsf318ae_slot0,
11554 OPERAND_ftsf320ae_slot0,
11556 OPERAND_ftsf322ae_slot0,
11557 OPERAND_ftsf323ae_slot0,
11558 OPERAND_ftsf324ae_slot0,
11559 OPERAND_ftsf325ae_slot0,
11560 OPERAND_ftsf326ae_slot0,
11561 OPERAND_ftsf328ae_slot0,
11562 OPERAND_ftsf329ae_slot0,
11563 OPERAND_ftsf352ae_slot0,
11565 OPERAND_ftsf354ae_slot0,
11566 OPERAND_ftsf356ae_slot0,
11568 OPERAND_ftsf358ae_slot0,
11569 OPERAND_ftsf359ae_slot0,
11570 OPERAND_ftsf360ae_slot0,
11571 OPERAND_ftsf361ae_slot0,
11572 OPERAND_ftsf362ae_slot0,
11573 OPERAND_ftsf364ae_slot0,
11574 OPERAND_ftsf365ae_slot0,
11575 OPERAND_ftsf366ae_slot0,
11576 OPERAND_ftsf368ae_slot0,
11577 OPERAND_ftsf369ae_slot0
11581 /* Iclass table. */
11583 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
11584 { { STATE_PSRING }, 'i' },
11585 { { STATE_PSEXCM }, 'm' },
11586 { { STATE_EPC1 }, 'i' }
11589 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
11590 { { STATE_PSEXCM }, 'i' },
11591 { { STATE_PSRING }, 'i' },
11592 { { STATE_DEPC }, 'i' }
11595 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
11596 { { OPERAND_soffsetx4 }, 'i' },
11597 { { OPERAND_ar12 }, 'o' }
11600 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
11601 { { STATE_PSCALLINC }, 'o' }
11604 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
11605 { { OPERAND_soffsetx4 }, 'i' },
11606 { { OPERAND_ar8 }, 'o' }
11609 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
11610 { { STATE_PSCALLINC }, 'o' }
11613 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
11614 { { OPERAND_soffsetx4 }, 'i' },
11615 { { OPERAND_ar4 }, 'o' }
11618 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
11619 { { STATE_PSCALLINC }, 'o' }
11622 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
11623 { { OPERAND_ars }, 'i' },
11624 { { OPERAND_ar12 }, 'o' }
11627 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
11628 { { STATE_PSCALLINC }, 'o' }
11631 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
11632 { { OPERAND_ars }, 'i' },
11633 { { OPERAND_ar8 }, 'o' }
11636 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
11637 { { STATE_PSCALLINC }, 'o' }
11640 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
11641 { { OPERAND_ars }, 'i' },
11642 { { OPERAND_ar4 }, 'o' }
11645 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
11646 { { STATE_PSCALLINC }, 'o' }
11649 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
11650 { { OPERAND_ars_entry }, 's' },
11651 { { OPERAND_ars }, 'i' },
11652 { { OPERAND_uimm12x8 }, 'i' }
11655 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
11656 { { STATE_PSCALLINC }, 'i' },
11657 { { STATE_PSEXCM }, 'i' },
11658 { { STATE_PSWOE }, 'i' },
11659 { { STATE_WindowBase }, 'm' },
11660 { { STATE_WindowStart }, 'm' }
11663 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
11664 { { OPERAND_art }, 'o' },
11665 { { OPERAND_ars }, 'i' }
11668 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
11669 { { STATE_WindowBase }, 'i' },
11670 { { STATE_WindowStart }, 'i' }
11673 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
11674 { { OPERAND_simm4 }, 'i' }
11677 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
11678 { { STATE_PSEXCM }, 'i' },
11679 { { STATE_PSRING }, 'i' },
11680 { { STATE_WindowBase }, 'm' }
11683 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
11684 { { OPERAND__ars_invisible }, 'i' }
11687 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
11688 { { STATE_WindowBase }, 'm' },
11689 { { STATE_WindowStart }, 'm' },
11690 { { STATE_PSEXCM }, 'i' },
11691 { { STATE_PSWOE }, 'i' }
11694 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
11695 { { STATE_EPC1 }, 'i' },
11696 { { STATE_PSEXCM }, 'm' },
11697 { { STATE_PSRING }, 'i' },
11698 { { STATE_WindowBase }, 'm' },
11699 { { STATE_WindowStart }, 'm' },
11700 { { STATE_PSOWB }, 'i' }
11703 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
11704 { { OPERAND_art }, 'o' },
11705 { { OPERAND_ars }, 'i' },
11706 { { OPERAND_immrx4 }, 'i' }
11709 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
11710 { { STATE_PSEXCM }, 'i' },
11711 { { STATE_PSRING }, 'i' }
11714 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
11715 { { OPERAND_art }, 'i' },
11716 { { OPERAND_ars }, 'i' },
11717 { { OPERAND_immrx4 }, 'i' }
11720 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
11721 { { STATE_PSEXCM }, 'i' },
11722 { { STATE_PSRING }, 'i' }
11725 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
11726 { { OPERAND_art }, 'o' }
11729 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
11730 { { STATE_PSEXCM }, 'i' },
11731 { { STATE_PSRING }, 'i' },
11732 { { STATE_WindowBase }, 'i' }
11735 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
11736 { { OPERAND_art }, 'i' }
11739 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
11740 { { STATE_PSEXCM }, 'i' },
11741 { { STATE_PSRING }, 'i' },
11742 { { STATE_WindowBase }, 'o' }
11745 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
11746 { { OPERAND_art }, 'm' }
11749 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
11750 { { STATE_PSEXCM }, 'i' },
11751 { { STATE_PSRING }, 'i' },
11752 { { STATE_WindowBase }, 'm' }
11755 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
11756 { { OPERAND_art }, 'o' }
11759 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
11760 { { STATE_PSEXCM }, 'i' },
11761 { { STATE_PSRING }, 'i' },
11762 { { STATE_WindowStart }, 'i' }
11765 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
11766 { { OPERAND_art }, 'i' }
11769 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
11770 { { STATE_PSEXCM }, 'i' },
11771 { { STATE_PSRING }, 'i' },
11772 { { STATE_WindowStart }, 'o' }
11775 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
11776 { { OPERAND_art }, 'm' }
11779 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
11780 { { STATE_PSEXCM }, 'i' },
11781 { { STATE_PSRING }, 'i' },
11782 { { STATE_WindowStart }, 'm' }
11785 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
11786 { { OPERAND_arr }, 'o' },
11787 { { OPERAND_ars }, 'i' },
11788 { { OPERAND_art }, 'i' }
11791 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
11792 { { OPERAND_arr }, 'o' },
11793 { { OPERAND_ars }, 'i' },
11794 { { OPERAND_ai4const }, 'i' }
11797 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
11798 { { OPERAND_ars }, 'i' },
11799 { { OPERAND_uimm6 }, 'i' }
11802 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
11803 { { OPERAND_art }, 'o' },
11804 { { OPERAND_ars }, 'i' },
11805 { { OPERAND_lsi4x4 }, 'i' }
11808 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
11809 { { OPERAND_art }, 'o' },
11810 { { OPERAND_ars }, 'i' }
11813 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
11814 { { OPERAND_ars }, 'o' },
11815 { { OPERAND_simm7 }, 'i' }
11818 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
11819 { { OPERAND__ars_invisible }, 'i' }
11822 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
11823 { { OPERAND_art }, 'i' },
11824 { { OPERAND_ars }, 'i' },
11825 { { OPERAND_lsi4x4 }, 'i' }
11828 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
11829 { { OPERAND_arr }, 'o' }
11832 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
11833 { { STATE_THREADPTR }, 'i' }
11836 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
11837 { { OPERAND_art }, 'i' }
11840 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
11841 { { STATE_THREADPTR }, 'o' }
11844 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
11845 { { OPERAND_art }, 'o' },
11846 { { OPERAND_ars }, 'i' },
11847 { { OPERAND_simm8 }, 'i' }
11850 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
11851 { { OPERAND_art }, 'o' },
11852 { { OPERAND_ars }, 'i' },
11853 { { OPERAND_simm8x256 }, 'i' }
11856 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
11857 { { OPERAND_arr }, 'o' },
11858 { { OPERAND_ars }, 'i' },
11859 { { OPERAND_art }, 'i' }
11862 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
11863 { { OPERAND_arr }, 'o' },
11864 { { OPERAND_ars }, 'i' },
11865 { { OPERAND_art }, 'i' }
11868 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
11869 { { OPERAND_ars }, 'i' },
11870 { { OPERAND_b4const }, 'i' },
11871 { { OPERAND_label8 }, 'i' }
11874 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
11875 { { OPERAND_ars }, 'i' },
11876 { { OPERAND_bbi }, 'i' },
11877 { { OPERAND_label8 }, 'i' }
11880 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
11881 { { OPERAND_ars }, 'i' },
11882 { { OPERAND_b4constu }, 'i' },
11883 { { OPERAND_label8 }, 'i' }
11886 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
11887 { { OPERAND_ars }, 'i' },
11888 { { OPERAND_art }, 'i' },
11889 { { OPERAND_label8 }, 'i' }
11892 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
11893 { { OPERAND_ars }, 'i' },
11894 { { OPERAND_label12 }, 'i' }
11897 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
11898 { { OPERAND_soffsetx4 }, 'i' },
11899 { { OPERAND_ar0 }, 'o' }
11902 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
11903 { { OPERAND_ars }, 'i' },
11904 { { OPERAND_ar0 }, 'o' }
11907 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
11908 { { OPERAND_arr }, 'o' },
11909 { { OPERAND_art }, 'i' },
11910 { { OPERAND_sae }, 'i' },
11911 { { OPERAND_op2p1 }, 'i' }
11914 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
11915 { { OPERAND_soffset }, 'i' }
11918 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
11919 { { OPERAND_ars }, 'i' }
11922 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
11923 { { OPERAND_art }, 'o' },
11924 { { OPERAND_ars }, 'i' },
11925 { { OPERAND_uimm8x2 }, 'i' }
11928 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
11929 { { OPERAND_art }, 'o' },
11930 { { OPERAND_ars }, 'i' },
11931 { { OPERAND_uimm8x2 }, 'i' }
11934 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
11935 { { OPERAND_art }, 'o' },
11936 { { OPERAND_ars }, 'i' },
11937 { { OPERAND_uimm8x4 }, 'i' }
11940 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
11941 { { OPERAND_art }, 'o' },
11942 { { OPERAND_uimm16x4 }, 'i' }
11945 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
11946 { { STATE_LITBADDR }, 'i' },
11947 { { STATE_LITBEN }, 'i' }
11950 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
11951 { { OPERAND_art }, 'o' },
11952 { { OPERAND_ars }, 'i' },
11953 { { OPERAND_uimm8 }, 'i' }
11956 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
11957 { { OPERAND_ars }, 'i' },
11958 { { OPERAND_ulabel8 }, 'i' }
11961 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
11962 { { STATE_LBEG }, 'o' },
11963 { { STATE_LEND }, 'o' },
11964 { { STATE_LCOUNT }, 'o' }
11967 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
11968 { { OPERAND_ars }, 'i' },
11969 { { OPERAND_ulabel8 }, 'i' }
11972 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
11973 { { STATE_LBEG }, 'o' },
11974 { { STATE_LEND }, 'o' },
11975 { { STATE_LCOUNT }, 'o' }
11978 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
11979 { { OPERAND_art }, 'o' },
11980 { { OPERAND_simm12b }, 'i' }
11983 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
11984 { { OPERAND_arr }, 'm' },
11985 { { OPERAND_ars }, 'i' },
11986 { { OPERAND_art }, 'i' }
11989 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
11990 { { OPERAND_arr }, 'o' },
11991 { { OPERAND_art }, 'i' }
11994 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
11995 { { OPERAND__ars_invisible }, 'i' }
11998 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
11999 { { OPERAND_art }, 'i' },
12000 { { OPERAND_ars }, 'i' },
12001 { { OPERAND_uimm8x2 }, 'i' }
12004 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
12005 { { OPERAND_art }, 'i' },
12006 { { OPERAND_ars }, 'i' },
12007 { { OPERAND_uimm8x4 }, 'i' }
12010 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
12011 { { OPERAND_art }, 'i' },
12012 { { OPERAND_ars }, 'i' },
12013 { { OPERAND_uimm8 }, 'i' }
12016 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
12017 { { OPERAND_ars }, 'i' }
12020 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
12021 { { STATE_SAR }, 'o' }
12024 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
12025 { { OPERAND_sas }, 'i' }
12028 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
12029 { { STATE_SAR }, 'o' }
12032 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
12033 { { OPERAND_arr }, 'o' },
12034 { { OPERAND_ars }, 'i' }
12037 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
12038 { { STATE_SAR }, 'i' }
12041 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
12042 { { OPERAND_arr }, 'o' },
12043 { { OPERAND_ars }, 'i' },
12044 { { OPERAND_art }, 'i' }
12047 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
12048 { { STATE_SAR }, 'i' }
12051 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
12052 { { OPERAND_arr }, 'o' },
12053 { { OPERAND_art }, 'i' }
12056 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
12057 { { STATE_SAR }, 'i' }
12060 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
12061 { { OPERAND_arr }, 'o' },
12062 { { OPERAND_ars }, 'i' },
12063 { { OPERAND_msalp32 }, 'i' }
12066 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
12067 { { OPERAND_arr }, 'o' },
12068 { { OPERAND_art }, 'i' },
12069 { { OPERAND_sargt }, 'i' }
12072 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
12073 { { OPERAND_arr }, 'o' },
12074 { { OPERAND_art }, 'i' },
12075 { { OPERAND_s }, 'i' }
12078 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
12079 { { STATE_XTSYNC }, 'i' }
12082 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
12083 { { OPERAND_art }, 'o' },
12084 { { OPERAND_s }, 'i' }
12087 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
12088 { { STATE_PSWOE }, 'i' },
12089 { { STATE_PSCALLINC }, 'i' },
12090 { { STATE_PSOWB }, 'i' },
12091 { { STATE_PSRING }, 'i' },
12092 { { STATE_PSUM }, 'i' },
12093 { { STATE_PSEXCM }, 'i' },
12094 { { STATE_PSINTLEVEL }, 'm' }
12097 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
12098 { { OPERAND_art }, 'o' }
12101 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
12102 { { STATE_LEND }, 'i' }
12105 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
12106 { { OPERAND_art }, 'i' }
12109 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
12110 { { STATE_LEND }, 'o' }
12113 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
12114 { { OPERAND_art }, 'm' }
12117 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
12118 { { STATE_LEND }, 'm' }
12121 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
12122 { { OPERAND_art }, 'o' }
12125 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
12126 { { STATE_LCOUNT }, 'i' }
12129 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
12130 { { OPERAND_art }, 'i' }
12133 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
12134 { { STATE_XTSYNC }, 'o' },
12135 { { STATE_LCOUNT }, 'o' }
12138 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
12139 { { OPERAND_art }, 'm' }
12142 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
12143 { { STATE_XTSYNC }, 'o' },
12144 { { STATE_LCOUNT }, 'm' }
12147 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
12148 { { OPERAND_art }, 'o' }
12151 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
12152 { { STATE_LBEG }, 'i' }
12155 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
12156 { { OPERAND_art }, 'i' }
12159 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
12160 { { STATE_LBEG }, 'o' }
12163 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
12164 { { OPERAND_art }, 'm' }
12167 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
12168 { { STATE_LBEG }, 'm' }
12171 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
12172 { { OPERAND_art }, 'o' }
12175 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
12176 { { STATE_SAR }, 'i' }
12179 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
12180 { { OPERAND_art }, 'i' }
12183 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
12184 { { STATE_SAR }, 'o' },
12185 { { STATE_XTSYNC }, 'o' }
12188 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
12189 { { OPERAND_art }, 'm' }
12192 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
12193 { { STATE_SAR }, 'm' }
12196 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
12197 { { OPERAND_art }, 'o' }
12200 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
12201 { { STATE_LITBADDR }, 'i' },
12202 { { STATE_LITBEN }, 'i' }
12205 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
12206 { { OPERAND_art }, 'i' }
12209 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
12210 { { STATE_LITBADDR }, 'o' },
12211 { { STATE_LITBEN }, 'o' }
12214 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
12215 { { OPERAND_art }, 'm' }
12218 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
12219 { { STATE_LITBADDR }, 'm' },
12220 { { STATE_LITBEN }, 'm' }
12223 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
12224 { { OPERAND_art }, 'o' }
12227 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
12228 { { STATE_PSEXCM }, 'i' },
12229 { { STATE_PSRING }, 'i' }
12232 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
12233 { { OPERAND_art }, 'i' }
12236 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
12237 { { STATE_PSEXCM }, 'i' },
12238 { { STATE_PSRING }, 'i' }
12241 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
12242 { { OPERAND_art }, 'o' }
12245 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
12246 { { STATE_PSEXCM }, 'i' },
12247 { { STATE_PSRING }, 'i' }
12250 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
12251 { { OPERAND_art }, 'o' }
12254 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
12255 { { STATE_PSWOE }, 'i' },
12256 { { STATE_PSCALLINC }, 'i' },
12257 { { STATE_PSOWB }, 'i' },
12258 { { STATE_PSRING }, 'i' },
12259 { { STATE_PSUM }, 'i' },
12260 { { STATE_PSEXCM }, 'i' },
12261 { { STATE_PSINTLEVEL }, 'i' }
12264 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
12265 { { OPERAND_art }, 'i' }
12268 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
12269 { { STATE_PSWOE }, 'o' },
12270 { { STATE_PSCALLINC }, 'o' },
12271 { { STATE_PSOWB }, 'o' },
12272 { { STATE_PSRING }, 'm' },
12273 { { STATE_PSUM }, 'o' },
12274 { { STATE_PSEXCM }, 'm' },
12275 { { STATE_PSINTLEVEL }, 'o' }
12278 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
12279 { { OPERAND_art }, 'm' }
12282 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
12283 { { STATE_PSWOE }, 'm' },
12284 { { STATE_PSCALLINC }, 'm' },
12285 { { STATE_PSOWB }, 'm' },
12286 { { STATE_PSRING }, 'm' },
12287 { { STATE_PSUM }, 'm' },
12288 { { STATE_PSEXCM }, 'm' },
12289 { { STATE_PSINTLEVEL }, 'm' }
12292 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
12293 { { OPERAND_art }, 'o' }
12296 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
12297 { { STATE_PSEXCM }, 'i' },
12298 { { STATE_PSRING }, 'i' },
12299 { { STATE_EPC1 }, 'i' }
12302 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
12303 { { OPERAND_art }, 'i' }
12306 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
12307 { { STATE_PSEXCM }, 'i' },
12308 { { STATE_PSRING }, 'i' },
12309 { { STATE_EPC1 }, 'o' }
12312 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
12313 { { OPERAND_art }, 'm' }
12316 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
12317 { { STATE_PSEXCM }, 'i' },
12318 { { STATE_PSRING }, 'i' },
12319 { { STATE_EPC1 }, 'm' }
12322 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
12323 { { OPERAND_art }, 'o' }
12326 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
12327 { { STATE_PSEXCM }, 'i' },
12328 { { STATE_PSRING }, 'i' },
12329 { { STATE_EXCSAVE1 }, 'i' }
12332 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
12333 { { OPERAND_art }, 'i' }
12336 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
12337 { { STATE_PSEXCM }, 'i' },
12338 { { STATE_PSRING }, 'i' },
12339 { { STATE_EXCSAVE1 }, 'o' }
12342 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
12343 { { OPERAND_art }, 'm' }
12346 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
12347 { { STATE_PSEXCM }, 'i' },
12348 { { STATE_PSRING }, 'i' },
12349 { { STATE_EXCSAVE1 }, 'm' }
12352 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
12353 { { OPERAND_art }, 'o' }
12356 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
12357 { { STATE_PSEXCM }, 'i' },
12358 { { STATE_PSRING }, 'i' },
12359 { { STATE_EPC2 }, 'i' }
12362 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
12363 { { OPERAND_art }, 'i' }
12366 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
12367 { { STATE_PSEXCM }, 'i' },
12368 { { STATE_PSRING }, 'i' },
12369 { { STATE_EPC2 }, 'o' }
12372 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
12373 { { OPERAND_art }, 'm' }
12376 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
12377 { { STATE_PSEXCM }, 'i' },
12378 { { STATE_PSRING }, 'i' },
12379 { { STATE_EPC2 }, 'm' }
12382 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
12383 { { OPERAND_art }, 'o' }
12386 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
12387 { { STATE_PSEXCM }, 'i' },
12388 { { STATE_PSRING }, 'i' },
12389 { { STATE_EXCSAVE2 }, 'i' }
12392 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
12393 { { OPERAND_art }, 'i' }
12396 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
12397 { { STATE_PSEXCM }, 'i' },
12398 { { STATE_PSRING }, 'i' },
12399 { { STATE_EXCSAVE2 }, 'o' }
12402 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
12403 { { OPERAND_art }, 'm' }
12406 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
12407 { { STATE_PSEXCM }, 'i' },
12408 { { STATE_PSRING }, 'i' },
12409 { { STATE_EXCSAVE2 }, 'm' }
12412 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
12413 { { OPERAND_art }, 'o' }
12416 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
12417 { { STATE_PSEXCM }, 'i' },
12418 { { STATE_PSRING }, 'i' },
12419 { { STATE_EPS2 }, 'i' }
12422 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
12423 { { OPERAND_art }, 'i' }
12426 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
12427 { { STATE_PSEXCM }, 'i' },
12428 { { STATE_PSRING }, 'i' },
12429 { { STATE_EPS2 }, 'o' }
12432 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
12433 { { OPERAND_art }, 'm' }
12436 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
12437 { { STATE_PSEXCM }, 'i' },
12438 { { STATE_PSRING }, 'i' },
12439 { { STATE_EPS2 }, 'm' }
12442 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
12443 { { OPERAND_art }, 'o' }
12446 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
12447 { { STATE_PSEXCM }, 'i' },
12448 { { STATE_PSRING }, 'i' },
12449 { { STATE_EXCVADDR }, 'i' }
12452 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
12453 { { OPERAND_art }, 'i' }
12456 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
12457 { { STATE_PSEXCM }, 'i' },
12458 { { STATE_PSRING }, 'i' },
12459 { { STATE_EXCVADDR }, 'o' }
12462 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
12463 { { OPERAND_art }, 'm' }
12466 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
12467 { { STATE_PSEXCM }, 'i' },
12468 { { STATE_PSRING }, 'i' },
12469 { { STATE_EXCVADDR }, 'm' }
12472 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
12473 { { OPERAND_art }, 'o' }
12476 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
12477 { { STATE_PSEXCM }, 'i' },
12478 { { STATE_PSRING }, 'i' },
12479 { { STATE_DEPC }, 'i' }
12482 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
12483 { { OPERAND_art }, 'i' }
12486 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
12487 { { STATE_PSEXCM }, 'i' },
12488 { { STATE_PSRING }, 'i' },
12489 { { STATE_DEPC }, 'o' }
12492 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
12493 { { OPERAND_art }, 'm' }
12496 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
12497 { { STATE_PSEXCM }, 'i' },
12498 { { STATE_PSRING }, 'i' },
12499 { { STATE_DEPC }, 'm' }
12502 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
12503 { { OPERAND_art }, 'o' }
12506 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
12507 { { STATE_PSEXCM }, 'i' },
12508 { { STATE_PSRING }, 'i' },
12509 { { STATE_EXCCAUSE }, 'i' },
12510 { { STATE_XTSYNC }, 'i' }
12513 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
12514 { { OPERAND_art }, 'i' }
12517 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
12518 { { STATE_PSEXCM }, 'i' },
12519 { { STATE_PSRING }, 'i' },
12520 { { STATE_EXCCAUSE }, 'o' }
12523 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
12524 { { OPERAND_art }, 'm' }
12527 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
12528 { { STATE_PSEXCM }, 'i' },
12529 { { STATE_PSRING }, 'i' },
12530 { { STATE_EXCCAUSE }, 'm' }
12533 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
12534 { { OPERAND_art }, 'o' }
12537 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
12538 { { STATE_PSEXCM }, 'i' },
12539 { { STATE_PSRING }, 'i' },
12540 { { STATE_MISC0 }, 'i' }
12543 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
12544 { { OPERAND_art }, 'i' }
12547 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
12548 { { STATE_PSEXCM }, 'i' },
12549 { { STATE_PSRING }, 'i' },
12550 { { STATE_MISC0 }, 'o' }
12553 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
12554 { { OPERAND_art }, 'm' }
12557 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
12558 { { STATE_PSEXCM }, 'i' },
12559 { { STATE_PSRING }, 'i' },
12560 { { STATE_MISC0 }, 'm' }
12563 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
12564 { { OPERAND_art }, 'o' }
12567 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
12568 { { STATE_PSEXCM }, 'i' },
12569 { { STATE_PSRING }, 'i' },
12570 { { STATE_MISC1 }, 'i' }
12573 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
12574 { { OPERAND_art }, 'i' }
12577 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
12578 { { STATE_PSEXCM }, 'i' },
12579 { { STATE_PSRING }, 'i' },
12580 { { STATE_MISC1 }, 'o' }
12583 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
12584 { { OPERAND_art }, 'm' }
12587 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
12588 { { STATE_PSEXCM }, 'i' },
12589 { { STATE_PSRING }, 'i' },
12590 { { STATE_MISC1 }, 'm' }
12593 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
12594 { { OPERAND_art }, 'o' }
12597 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
12598 { { STATE_PSEXCM }, 'i' },
12599 { { STATE_PSRING }, 'i' }
12602 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
12603 { { OPERAND_art }, 'o' }
12606 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
12607 { { STATE_PSEXCM }, 'i' },
12608 { { STATE_PSRING }, 'i' },
12609 { { STATE_VECBASE }, 'i' }
12612 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
12613 { { OPERAND_art }, 'i' }
12616 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
12617 { { STATE_PSEXCM }, 'i' },
12618 { { STATE_PSRING }, 'i' },
12619 { { STATE_VECBASE }, 'o' }
12622 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
12623 { { OPERAND_art }, 'm' }
12626 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
12627 { { STATE_PSEXCM }, 'i' },
12628 { { STATE_PSRING }, 'i' },
12629 { { STATE_VECBASE }, 'm' }
12632 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
12633 { { OPERAND_arr }, 'o' },
12634 { { OPERAND_ars }, 'i' },
12635 { { OPERAND_art }, 'i' }
12638 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
12639 { { OPERAND_arr }, 'o' },
12640 { { OPERAND_ars }, 'i' },
12641 { { OPERAND_art }, 'i' }
12644 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
12645 { { OPERAND_s }, 'i' }
12648 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
12649 { { STATE_PSWOE }, 'o' },
12650 { { STATE_PSCALLINC }, 'o' },
12651 { { STATE_PSOWB }, 'o' },
12652 { { STATE_PSRING }, 'm' },
12653 { { STATE_PSUM }, 'o' },
12654 { { STATE_PSEXCM }, 'm' },
12655 { { STATE_PSINTLEVEL }, 'o' },
12656 { { STATE_EPC1 }, 'i' },
12657 { { STATE_EPC2 }, 'i' },
12658 { { STATE_EPS2 }, 'i' },
12659 { { STATE_InOCDMode }, 'm' }
12662 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
12663 { { OPERAND_s }, 'i' }
12666 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
12667 { { STATE_PSEXCM }, 'i' },
12668 { { STATE_PSRING }, 'i' },
12669 { { STATE_PSINTLEVEL }, 'o' }
12672 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
12673 { { OPERAND_art }, 'o' }
12676 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
12677 { { STATE_PSEXCM }, 'i' },
12678 { { STATE_PSRING }, 'i' },
12679 { { STATE_INTERRUPT }, 'i' }
12682 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
12683 { { OPERAND_art }, 'i' }
12686 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
12687 { { STATE_PSEXCM }, 'i' },
12688 { { STATE_PSRING }, 'i' },
12689 { { STATE_XTSYNC }, 'o' },
12690 { { STATE_INTERRUPT }, 'm' }
12693 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
12694 { { OPERAND_art }, 'i' }
12697 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
12698 { { STATE_PSEXCM }, 'i' },
12699 { { STATE_PSRING }, 'i' },
12700 { { STATE_XTSYNC }, 'o' },
12701 { { STATE_INTERRUPT }, 'm' }
12704 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
12705 { { OPERAND_art }, 'o' }
12708 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
12709 { { STATE_PSEXCM }, 'i' },
12710 { { STATE_PSRING }, 'i' },
12711 { { STATE_INTENABLE }, 'i' }
12714 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
12715 { { OPERAND_art }, 'i' }
12718 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
12719 { { STATE_PSEXCM }, 'i' },
12720 { { STATE_PSRING }, 'i' },
12721 { { STATE_INTENABLE }, 'o' }
12724 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
12725 { { OPERAND_art }, 'm' }
12728 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
12729 { { STATE_PSEXCM }, 'i' },
12730 { { STATE_PSRING }, 'i' },
12731 { { STATE_INTENABLE }, 'm' }
12734 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
12735 { { OPERAND_imms }, 'i' },
12736 { { OPERAND_immt }, 'i' }
12739 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
12740 { { STATE_PSEXCM }, 'i' },
12741 { { STATE_PSINTLEVEL }, 'i' }
12744 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
12745 { { OPERAND_imms }, 'i' }
12748 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
12749 { { STATE_PSEXCM }, 'i' },
12750 { { STATE_PSINTLEVEL }, 'i' }
12753 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
12754 { { OPERAND_art }, 'o' }
12757 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
12758 { { STATE_PSEXCM }, 'i' },
12759 { { STATE_PSRING }, 'i' },
12760 { { STATE_DEBUGCAUSE }, 'i' },
12761 { { STATE_DBNUM }, 'i' }
12764 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
12765 { { OPERAND_art }, 'i' }
12768 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
12769 { { STATE_PSEXCM }, 'i' },
12770 { { STATE_PSRING }, 'i' },
12771 { { STATE_DEBUGCAUSE }, 'o' },
12772 { { STATE_DBNUM }, 'o' }
12775 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
12776 { { OPERAND_art }, 'm' }
12779 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
12780 { { STATE_PSEXCM }, 'i' },
12781 { { STATE_PSRING }, 'i' },
12782 { { STATE_DEBUGCAUSE }, 'm' },
12783 { { STATE_DBNUM }, 'm' }
12786 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
12787 { { OPERAND_art }, 'o' }
12790 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
12791 { { STATE_PSEXCM }, 'i' },
12792 { { STATE_PSRING }, 'i' },
12793 { { STATE_ICOUNT }, 'i' }
12796 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
12797 { { OPERAND_art }, 'i' }
12800 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
12801 { { STATE_PSEXCM }, 'i' },
12802 { { STATE_PSRING }, 'i' },
12803 { { STATE_XTSYNC }, 'o' },
12804 { { STATE_ICOUNT }, 'o' }
12807 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
12808 { { OPERAND_art }, 'm' }
12811 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
12812 { { STATE_PSEXCM }, 'i' },
12813 { { STATE_PSRING }, 'i' },
12814 { { STATE_XTSYNC }, 'o' },
12815 { { STATE_ICOUNT }, 'm' }
12818 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
12819 { { OPERAND_art }, 'o' }
12822 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
12823 { { STATE_PSEXCM }, 'i' },
12824 { { STATE_PSRING }, 'i' },
12825 { { STATE_ICOUNTLEVEL }, 'i' }
12828 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
12829 { { OPERAND_art }, 'i' }
12832 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
12833 { { STATE_PSEXCM }, 'i' },
12834 { { STATE_PSRING }, 'i' },
12835 { { STATE_ICOUNTLEVEL }, 'o' }
12838 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
12839 { { OPERAND_art }, 'm' }
12842 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
12843 { { STATE_PSEXCM }, 'i' },
12844 { { STATE_PSRING }, 'i' },
12845 { { STATE_ICOUNTLEVEL }, 'm' }
12848 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
12849 { { OPERAND_art }, 'o' }
12852 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
12853 { { STATE_PSEXCM }, 'i' },
12854 { { STATE_PSRING }, 'i' },
12855 { { STATE_DDR }, 'i' }
12858 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
12859 { { OPERAND_art }, 'i' }
12862 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
12863 { { STATE_PSEXCM }, 'i' },
12864 { { STATE_PSRING }, 'i' },
12865 { { STATE_XTSYNC }, 'o' },
12866 { { STATE_DDR }, 'o' }
12869 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
12870 { { OPERAND_art }, 'm' }
12873 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
12874 { { STATE_PSEXCM }, 'i' },
12875 { { STATE_PSRING }, 'i' },
12876 { { STATE_XTSYNC }, 'o' },
12877 { { STATE_DDR }, 'm' }
12880 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
12881 { { OPERAND_imms }, 'i' }
12884 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
12885 { { STATE_InOCDMode }, 'm' },
12886 { { STATE_EPC2 }, 'i' },
12887 { { STATE_PSWOE }, 'o' },
12888 { { STATE_PSCALLINC }, 'o' },
12889 { { STATE_PSOWB }, 'o' },
12890 { { STATE_PSRING }, 'o' },
12891 { { STATE_PSUM }, 'o' },
12892 { { STATE_PSEXCM }, 'o' },
12893 { { STATE_PSINTLEVEL }, 'o' },
12894 { { STATE_EPS2 }, 'i' }
12897 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
12898 { { STATE_InOCDMode }, 'm' }
12901 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
12902 { { OPERAND_br }, 'o' },
12903 { { OPERAND_bs }, 'i' },
12904 { { OPERAND_bt }, 'i' }
12907 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
12908 { { OPERAND_bt }, 'o' },
12909 { { OPERAND_bs4 }, 'i' }
12912 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
12913 { { OPERAND_bt }, 'o' },
12914 { { OPERAND_bs8 }, 'i' }
12917 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
12918 { { OPERAND_bs }, 'i' },
12919 { { OPERAND_label8 }, 'i' }
12922 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
12923 { { OPERAND_arr }, 'm' },
12924 { { OPERAND_ars }, 'i' },
12925 { { OPERAND_bt }, 'i' }
12928 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
12929 { { OPERAND_art }, 'o' },
12930 { { OPERAND_brall }, 'i' }
12933 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
12934 { { OPERAND_art }, 'i' },
12935 { { OPERAND_brall }, 'o' }
12938 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
12939 { { OPERAND_art }, 'm' },
12940 { { OPERAND_brall }, 'm' }
12943 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
12944 { { OPERAND_art }, 'o' }
12947 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
12948 { { STATE_PSEXCM }, 'i' },
12949 { { STATE_PSRING }, 'i' },
12950 { { STATE_CCOUNT }, 'i' }
12953 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
12954 { { OPERAND_art }, 'i' }
12957 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
12958 { { STATE_PSEXCM }, 'i' },
12959 { { STATE_PSRING }, 'i' },
12960 { { STATE_XTSYNC }, 'o' },
12961 { { STATE_CCOUNT }, 'o' }
12964 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
12965 { { OPERAND_art }, 'm' }
12968 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
12969 { { STATE_PSEXCM }, 'i' },
12970 { { STATE_PSRING }, 'i' },
12971 { { STATE_XTSYNC }, 'o' },
12972 { { STATE_CCOUNT }, 'm' }
12975 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
12976 { { OPERAND_art }, 'o' }
12979 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
12980 { { STATE_PSEXCM }, 'i' },
12981 { { STATE_PSRING }, 'i' },
12982 { { STATE_CCOMPARE0 }, 'i' }
12985 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
12986 { { OPERAND_art }, 'i' }
12989 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
12990 { { STATE_PSEXCM }, 'i' },
12991 { { STATE_PSRING }, 'i' },
12992 { { STATE_CCOMPARE0 }, 'o' },
12993 { { STATE_INTERRUPT }, 'm' }
12996 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
12997 { { OPERAND_art }, 'm' }
13000 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
13001 { { STATE_PSEXCM }, 'i' },
13002 { { STATE_PSRING }, 'i' },
13003 { { STATE_CCOMPARE0 }, 'm' },
13004 { { STATE_INTERRUPT }, 'm' }
13007 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
13008 { { OPERAND_art }, 'o' }
13011 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
13012 { { STATE_PSEXCM }, 'i' },
13013 { { STATE_PSRING }, 'i' },
13014 { { STATE_CCOMPARE1 }, 'i' }
13017 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
13018 { { OPERAND_art }, 'i' }
13021 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
13022 { { STATE_PSEXCM }, 'i' },
13023 { { STATE_PSRING }, 'i' },
13024 { { STATE_CCOMPARE1 }, 'o' },
13025 { { STATE_INTERRUPT }, 'm' }
13028 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
13029 { { OPERAND_art }, 'm' }
13032 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
13033 { { STATE_PSEXCM }, 'i' },
13034 { { STATE_PSRING }, 'i' },
13035 { { STATE_CCOMPARE1 }, 'm' },
13036 { { STATE_INTERRUPT }, 'm' }
13039 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
13040 { { OPERAND_ars }, 'i' },
13041 { { OPERAND_uimm8x4 }, 'i' }
13044 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
13045 { { OPERAND_ars }, 'i' },
13046 { { OPERAND_uimm8x4 }, 'i' }
13049 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
13050 { { STATE_PSEXCM }, 'i' },
13051 { { STATE_PSRING }, 'i' }
13054 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
13055 { { OPERAND_art }, 'o' },
13056 { { OPERAND_ars }, 'i' }
13059 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
13060 { { STATE_PSEXCM }, 'i' },
13061 { { STATE_PSRING }, 'i' }
13064 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
13065 { { OPERAND_art }, 'i' },
13066 { { OPERAND_ars }, 'i' }
13069 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
13070 { { STATE_PSEXCM }, 'i' },
13071 { { STATE_PSRING }, 'i' }
13074 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
13075 { { OPERAND_ars }, 'i' },
13076 { { OPERAND_uimm8x4 }, 'i' }
13079 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
13080 { { OPERAND_ars }, 'i' },
13081 { { OPERAND_uimm4x16 }, 'i' }
13084 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
13085 { { STATE_PSEXCM }, 'i' },
13086 { { STATE_PSRING }, 'i' }
13089 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
13090 { { OPERAND_ars }, 'i' },
13091 { { OPERAND_uimm8x4 }, 'i' }
13094 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
13095 { { STATE_PSEXCM }, 'i' },
13096 { { STATE_PSRING }, 'i' }
13099 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
13100 { { OPERAND_ars }, 'i' },
13101 { { OPERAND_uimm8x4 }, 'i' }
13104 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
13105 { { OPERAND_art }, 'i' },
13106 { { OPERAND_ars }, 'i' }
13109 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
13110 { { STATE_PSEXCM }, 'i' },
13111 { { STATE_PSRING }, 'i' }
13114 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
13115 { { OPERAND_art }, 'o' },
13116 { { OPERAND_ars }, 'i' }
13119 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
13120 { { STATE_PSEXCM }, 'i' },
13121 { { STATE_PSRING }, 'i' }
13124 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
13125 { { OPERAND_art }, 'i' }
13128 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
13129 { { STATE_PSEXCM }, 'i' },
13130 { { STATE_PSRING }, 'i' },
13131 { { STATE_PTBASE }, 'o' },
13132 { { STATE_XTSYNC }, 'o' }
13135 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
13136 { { OPERAND_art }, 'o' }
13139 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
13140 { { STATE_PSEXCM }, 'i' },
13141 { { STATE_PSRING }, 'i' },
13142 { { STATE_PTBASE }, 'i' },
13143 { { STATE_EXCVADDR }, 'i' }
13146 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
13147 { { OPERAND_art }, 'm' }
13150 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
13151 { { STATE_PSEXCM }, 'i' },
13152 { { STATE_PSRING }, 'i' },
13153 { { STATE_PTBASE }, 'm' },
13154 { { STATE_EXCVADDR }, 'i' },
13155 { { STATE_XTSYNC }, 'o' }
13158 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
13159 { { OPERAND_art }, 'o' }
13162 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
13163 { { STATE_PSEXCM }, 'i' },
13164 { { STATE_PSRING }, 'i' },
13165 { { STATE_ASID3 }, 'i' },
13166 { { STATE_ASID2 }, 'i' },
13167 { { STATE_ASID1 }, 'i' }
13170 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
13171 { { OPERAND_art }, 'i' }
13174 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
13175 { { STATE_XTSYNC }, 'o' },
13176 { { STATE_PSEXCM }, 'i' },
13177 { { STATE_PSRING }, 'i' },
13178 { { STATE_ASID3 }, 'o' },
13179 { { STATE_ASID2 }, 'o' },
13180 { { STATE_ASID1 }, 'o' }
13183 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
13184 { { OPERAND_art }, 'm' }
13187 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
13188 { { STATE_XTSYNC }, 'o' },
13189 { { STATE_PSEXCM }, 'i' },
13190 { { STATE_PSRING }, 'i' },
13191 { { STATE_ASID3 }, 'm' },
13192 { { STATE_ASID2 }, 'm' },
13193 { { STATE_ASID1 }, 'm' }
13196 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
13197 { { OPERAND_art }, 'o' }
13200 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
13201 { { STATE_PSEXCM }, 'i' },
13202 { { STATE_PSRING }, 'i' },
13203 { { STATE_INSTPGSZID4 }, 'i' }
13206 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
13207 { { OPERAND_art }, 'i' }
13210 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
13211 { { STATE_XTSYNC }, 'o' },
13212 { { STATE_PSEXCM }, 'i' },
13213 { { STATE_PSRING }, 'i' },
13214 { { STATE_INSTPGSZID4 }, 'o' }
13217 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
13218 { { OPERAND_art }, 'm' }
13221 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
13222 { { STATE_XTSYNC }, 'o' },
13223 { { STATE_PSEXCM }, 'i' },
13224 { { STATE_PSRING }, 'i' },
13225 { { STATE_INSTPGSZID4 }, 'm' }
13228 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
13229 { { OPERAND_art }, 'o' }
13232 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
13233 { { STATE_PSEXCM }, 'i' },
13234 { { STATE_PSRING }, 'i' },
13235 { { STATE_DATAPGSZID4 }, 'i' }
13238 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
13239 { { OPERAND_art }, 'i' }
13242 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
13243 { { STATE_XTSYNC }, 'o' },
13244 { { STATE_PSEXCM }, 'i' },
13245 { { STATE_PSRING }, 'i' },
13246 { { STATE_DATAPGSZID4 }, 'o' }
13249 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
13250 { { OPERAND_art }, 'm' }
13253 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
13254 { { STATE_XTSYNC }, 'o' },
13255 { { STATE_PSEXCM }, 'i' },
13256 { { STATE_PSRING }, 'i' },
13257 { { STATE_DATAPGSZID4 }, 'm' }
13260 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
13261 { { OPERAND_ars }, 'i' }
13264 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
13265 { { STATE_PSEXCM }, 'i' },
13266 { { STATE_PSRING }, 'i' },
13267 { { STATE_XTSYNC }, 'o' }
13270 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
13271 { { OPERAND_art }, 'o' },
13272 { { OPERAND_ars }, 'i' }
13275 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
13276 { { STATE_PSEXCM }, 'i' },
13277 { { STATE_PSRING }, 'i' }
13280 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
13281 { { OPERAND_art }, 'i' },
13282 { { OPERAND_ars }, 'i' }
13285 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
13286 { { STATE_PSEXCM }, 'i' },
13287 { { STATE_PSRING }, 'i' },
13288 { { STATE_XTSYNC }, 'o' }
13291 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
13292 { { OPERAND_ars }, 'i' }
13295 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
13296 { { STATE_PSEXCM }, 'i' },
13297 { { STATE_PSRING }, 'i' }
13300 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
13301 { { OPERAND_art }, 'o' },
13302 { { OPERAND_ars }, 'i' }
13305 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
13306 { { STATE_PSEXCM }, 'i' },
13307 { { STATE_PSRING }, 'i' }
13310 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
13311 { { OPERAND_art }, 'i' },
13312 { { OPERAND_ars }, 'i' }
13315 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
13316 { { STATE_PSEXCM }, 'i' },
13317 { { STATE_PSRING }, 'i' }
13320 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
13321 { { STATE_PTBASE }, 'i' },
13322 { { STATE_EXCVADDR }, 'i' }
13325 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
13326 { { STATE_EXCVADDR }, 'i' }
13329 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
13330 { { STATE_EXCVADDR }, 'i' }
13333 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
13334 { { OPERAND_art }, 'o' }
13337 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
13338 { { STATE_PSEXCM }, 'i' },
13339 { { STATE_PSRING }, 'i' },
13340 { { STATE_CPENABLE }, 'i' }
13343 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
13344 { { OPERAND_art }, 'i' }
13347 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
13348 { { STATE_PSEXCM }, 'i' },
13349 { { STATE_PSRING }, 'i' },
13350 { { STATE_CPENABLE }, 'o' }
13353 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
13354 { { OPERAND_art }, 'm' }
13357 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
13358 { { STATE_PSEXCM }, 'i' },
13359 { { STATE_PSRING }, 'i' },
13360 { { STATE_CPENABLE }, 'm' }
13363 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
13364 { { OPERAND_arr }, 'o' },
13365 { { OPERAND_ars }, 'i' },
13366 { { OPERAND_tp7 }, 'i' }
13369 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
13370 { { OPERAND_arr }, 'o' },
13371 { { OPERAND_ars }, 'i' },
13372 { { OPERAND_art }, 'i' }
13375 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
13376 { { OPERAND_art }, 'o' },
13377 { { OPERAND_ars }, 'i' }
13380 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
13381 { { OPERAND_arr }, 'o' },
13382 { { OPERAND_ars }, 'i' },
13383 { { OPERAND_tp7 }, 'i' }
13386 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
13387 { { OPERAND_art }, 'o' },
13388 { { OPERAND_ars }, 'i' },
13389 { { OPERAND_uimm8x4 }, 'i' }
13392 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
13393 { { OPERAND_art }, 'i' },
13394 { { OPERAND_ars }, 'i' },
13395 { { OPERAND_uimm8x4 }, 'i' }
13398 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
13399 { { OPERAND_art }, 'm' },
13400 { { OPERAND_ars }, 'i' },
13401 { { OPERAND_uimm8x4 }, 'i' }
13404 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
13405 { { STATE_SCOMPARE1 }, 'i' },
13406 { { STATE_XTSYNC }, 'i' },
13407 { { STATE_SCOMPARE1 }, 'i' }
13410 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
13411 { { OPERAND_art }, 'o' }
13414 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
13415 { { STATE_SCOMPARE1 }, 'i' }
13418 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
13419 { { OPERAND_art }, 'i' }
13422 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
13423 { { STATE_SCOMPARE1 }, 'o' }
13426 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
13427 { { OPERAND_art }, 'm' }
13430 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
13431 { { STATE_SCOMPARE1 }, 'm' }
13434 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
13435 { { OPERAND_art }, 'o' }
13438 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
13439 { { STATE_PSEXCM }, 'i' },
13440 { { STATE_PSRING }, 'i' },
13441 { { STATE_ATOMCTL }, 'i' }
13444 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
13445 { { OPERAND_art }, 'i' }
13448 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
13449 { { STATE_PSEXCM }, 'i' },
13450 { { STATE_PSRING }, 'i' },
13451 { { STATE_ATOMCTL }, 'o' },
13452 { { STATE_XTSYNC }, 'o' }
13455 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
13456 { { OPERAND_art }, 'm' }
13459 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
13460 { { STATE_PSEXCM }, 'i' },
13461 { { STATE_PSRING }, 'i' },
13462 { { STATE_ATOMCTL }, 'm' },
13463 { { STATE_XTSYNC }, 'o' }
13466 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
13467 { { OPERAND_art }, 'o' },
13468 { { OPERAND_ars }, 'i' }
13471 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
13472 { { STATE_CCON }, 'i' },
13473 { { STATE_PSEXCM }, 'i' },
13474 { { STATE_PSRING }, 'i' },
13475 { { STATE_MPSCORE }, 'i' }
13478 static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
13479 INTERFACE_RMPINT_Out,
13480 INTERFACE_RMPINT_In
13483 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
13484 { { OPERAND_art }, 'i' },
13485 { { OPERAND_ars }, 'i' }
13488 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
13489 { { STATE_CCON }, 'm' },
13490 { { STATE_PSEXCM }, 'i' },
13491 { { STATE_PSRING }, 'i' },
13492 { { STATE_WMPINT_DATA }, 'o' },
13493 { { STATE_WMPINT_ADDR }, 'o' },
13494 { { STATE_MPSCORE }, 'm' },
13495 { { STATE_WMPINT_TOGGLEEN }, 'm' }
13498 static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
13499 { { OPERAND_arr }, 'o' }
13502 static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
13503 { { STATE_AE_OVERFLOW }, 'i' },
13504 { { STATE_AE_SAR }, 'i' },
13505 { { STATE_CPENABLE }, 'i' }
13508 static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
13509 { { OPERAND_art }, 'i' }
13512 static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
13513 { { STATE_AE_OVERFLOW }, 'o' },
13514 { { STATE_AE_SAR }, 'o' },
13515 { { STATE_CPENABLE }, 'i' }
13518 static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
13519 { { OPERAND_arr }, 'o' }
13522 static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
13523 { { STATE_AE_BITHEAD }, 'i' },
13524 { { STATE_CPENABLE }, 'i' }
13527 static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
13528 { { OPERAND_art }, 'i' }
13531 static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
13532 { { STATE_AE_BITHEAD }, 'o' },
13533 { { STATE_CPENABLE }, 'i' }
13536 static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
13537 { { OPERAND_arr }, 'o' }
13540 static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
13541 { { STATE_AE_BITPTR }, 'i' },
13542 { { STATE_AE_BITSUSED }, 'i' },
13543 { { STATE_AE_TABLESIZE }, 'i' },
13544 { { STATE_AE_FIRST_TS }, 'i' },
13545 { { STATE_CPENABLE }, 'i' }
13548 static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
13549 { { OPERAND_art }, 'i' }
13552 static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
13553 { { STATE_AE_BITPTR }, 'o' },
13554 { { STATE_AE_BITSUSED }, 'o' },
13555 { { STATE_AE_TABLESIZE }, 'o' },
13556 { { STATE_AE_FIRST_TS }, 'o' },
13557 { { STATE_CPENABLE }, 'i' }
13560 static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
13561 { { OPERAND_arr }, 'o' }
13564 static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
13565 { { STATE_AE_NEXTOFFSET }, 'i' },
13566 { { STATE_AE_SEARCHDONE }, 'i' },
13567 { { STATE_CPENABLE }, 'i' }
13570 static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
13571 { { OPERAND_art }, 'i' }
13574 static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
13575 { { STATE_AE_NEXTOFFSET }, 'o' },
13576 { { STATE_AE_SEARCHDONE }, 'o' },
13577 { { STATE_CPENABLE }, 'i' }
13580 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
13581 { { OPERAND_arr }, 'o' }
13584 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
13585 { { STATE_AE_OVERFLOW }, 'i' },
13586 { { STATE_CPENABLE }, 'i' }
13589 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
13590 { { OPERAND_art }, 'i' }
13593 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
13594 { { STATE_AE_OVERFLOW }, 'o' },
13595 { { STATE_CPENABLE }, 'i' }
13598 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
13599 { { OPERAND_arr }, 'o' }
13602 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
13603 { { STATE_AE_SAR }, 'i' },
13604 { { STATE_CPENABLE }, 'i' }
13607 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
13608 { { OPERAND_art }, 'i' }
13611 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
13612 { { STATE_AE_SAR }, 'o' },
13613 { { STATE_CPENABLE }, 'i' }
13616 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
13617 { { OPERAND_arr }, 'o' }
13620 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
13621 { { STATE_AE_BITPTR }, 'i' },
13622 { { STATE_CPENABLE }, 'i' }
13625 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
13626 { { OPERAND_art }, 'i' }
13629 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
13630 { { STATE_AE_BITPTR }, 'o' },
13631 { { STATE_CPENABLE }, 'i' }
13634 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
13635 { { OPERAND_arr }, 'o' }
13638 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
13639 { { STATE_AE_BITSUSED }, 'i' },
13640 { { STATE_CPENABLE }, 'i' }
13643 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
13644 { { OPERAND_art }, 'i' }
13647 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
13648 { { STATE_AE_BITSUSED }, 'o' },
13649 { { STATE_CPENABLE }, 'i' }
13652 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
13653 { { OPERAND_arr }, 'o' }
13656 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
13657 { { STATE_AE_TABLESIZE }, 'i' },
13658 { { STATE_CPENABLE }, 'i' }
13661 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
13662 { { OPERAND_art }, 'i' }
13665 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
13666 { { STATE_AE_TABLESIZE }, 'o' },
13667 { { STATE_CPENABLE }, 'i' }
13670 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
13671 { { OPERAND_arr }, 'o' }
13674 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
13675 { { STATE_AE_FIRST_TS }, 'i' },
13676 { { STATE_CPENABLE }, 'i' }
13679 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
13680 { { OPERAND_art }, 'i' }
13683 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
13684 { { STATE_AE_FIRST_TS }, 'o' },
13685 { { STATE_CPENABLE }, 'i' }
13688 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
13689 { { OPERAND_arr }, 'o' }
13692 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
13693 { { STATE_AE_NEXTOFFSET }, 'i' },
13694 { { STATE_CPENABLE }, 'i' }
13697 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
13698 { { OPERAND_art }, 'i' }
13701 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
13702 { { STATE_AE_NEXTOFFSET }, 'o' },
13703 { { STATE_CPENABLE }, 'i' }
13706 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
13707 { { OPERAND_arr }, 'o' }
13710 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
13711 { { STATE_AE_SEARCHDONE }, 'i' },
13712 { { STATE_CPENABLE }, 'i' }
13715 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
13716 { { OPERAND_art }, 'i' }
13719 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
13720 { { STATE_AE_SEARCHDONE }, 'o' },
13721 { { STATE_CPENABLE }, 'i' }
13724 static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
13725 { { OPERAND_pr }, 'o' },
13726 { { OPERAND_ars }, 'i' },
13727 { { OPERAND_ae_lsimm16 }, 'i' }
13730 static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
13731 { { STATE_CPENABLE }, 'i' }
13734 static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
13735 { { OPERAND_pr }, 'o' },
13736 { { OPERAND_ars }, 'm' },
13737 { { OPERAND_ae_lsimm16 }, 'i' }
13740 static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
13741 { { STATE_CPENABLE }, 'i' }
13744 static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
13745 { { OPERAND_pr }, 'o' },
13746 { { OPERAND_ars }, 'i' },
13747 { { OPERAND_art }, 'i' }
13750 static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
13751 { { STATE_CPENABLE }, 'i' }
13754 static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
13755 { { OPERAND_pr }, 'o' },
13756 { { OPERAND_ars }, 'm' },
13757 { { OPERAND_art }, 'i' }
13760 static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
13761 { { STATE_CPENABLE }, 'i' }
13764 static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
13765 { { OPERAND_pr }, 'o' },
13766 { { OPERAND_ars }, 'i' },
13767 { { OPERAND_ae_lsimm32 }, 'i' }
13770 static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
13771 { { STATE_CPENABLE }, 'i' }
13774 static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
13775 { { OPERAND_pr }, 'o' },
13776 { { OPERAND_ars }, 'm' },
13777 { { OPERAND_ae_lsimm32 }, 'i' }
13780 static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
13781 { { STATE_CPENABLE }, 'i' }
13784 static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
13785 { { OPERAND_pr }, 'o' },
13786 { { OPERAND_ars }, 'i' },
13787 { { OPERAND_art }, 'i' }
13790 static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
13791 { { STATE_CPENABLE }, 'i' }
13794 static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
13795 { { OPERAND_pr }, 'o' },
13796 { { OPERAND_ars }, 'm' },
13797 { { OPERAND_art }, 'i' }
13800 static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
13801 { { STATE_CPENABLE }, 'i' }
13804 static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
13805 { { OPERAND_pr }, 'o' },
13806 { { OPERAND_ars }, 'i' },
13807 { { OPERAND_ae_lsimm32 }, 'i' }
13810 static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
13811 { { STATE_CPENABLE }, 'i' }
13814 static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
13815 { { OPERAND_pr }, 'o' },
13816 { { OPERAND_ars }, 'm' },
13817 { { OPERAND_ae_lsimm32 }, 'i' }
13820 static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
13821 { { STATE_CPENABLE }, 'i' }
13824 static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
13825 { { OPERAND_pr }, 'o' },
13826 { { OPERAND_ars }, 'i' },
13827 { { OPERAND_art }, 'i' }
13830 static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
13831 { { STATE_CPENABLE }, 'i' }
13834 static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
13835 { { OPERAND_pr }, 'o' },
13836 { { OPERAND_ars }, 'm' },
13837 { { OPERAND_art }, 'i' }
13840 static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
13841 { { STATE_CPENABLE }, 'i' }
13844 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
13845 { { OPERAND_pr }, 'o' },
13846 { { OPERAND_ars }, 'i' },
13847 { { OPERAND_ae_lsimm32 }, 'i' }
13850 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
13851 { { STATE_CPENABLE }, 'i' }
13854 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
13855 { { OPERAND_pr }, 'o' },
13856 { { OPERAND_ars }, 'm' },
13857 { { OPERAND_ae_lsimm32 }, 'i' }
13860 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
13861 { { STATE_CPENABLE }, 'i' }
13864 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
13865 { { OPERAND_pr }, 'o' },
13866 { { OPERAND_ars }, 'i' },
13867 { { OPERAND_art }, 'i' }
13870 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
13871 { { STATE_CPENABLE }, 'i' }
13874 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
13875 { { OPERAND_pr }, 'o' },
13876 { { OPERAND_ars }, 'm' },
13877 { { OPERAND_art }, 'i' }
13880 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
13881 { { STATE_CPENABLE }, 'i' }
13884 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
13885 { { OPERAND_pr }, 'o' },
13886 { { OPERAND_ars }, 'i' },
13887 { { OPERAND_ae_lsimm64 }, 'i' }
13890 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
13891 { { STATE_CPENABLE }, 'i' }
13894 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
13895 { { OPERAND_pr }, 'o' },
13896 { { OPERAND_ars }, 'm' },
13897 { { OPERAND_ae_lsimm64 }, 'i' }
13900 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
13901 { { STATE_CPENABLE }, 'i' }
13904 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
13905 { { OPERAND_pr }, 'o' },
13906 { { OPERAND_ars }, 'i' },
13907 { { OPERAND_art }, 'i' }
13910 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
13911 { { STATE_CPENABLE }, 'i' }
13914 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
13915 { { OPERAND_pr }, 'o' },
13916 { { OPERAND_ars }, 'm' },
13917 { { OPERAND_art }, 'i' }
13920 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
13921 { { STATE_CPENABLE }, 'i' }
13924 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
13925 { { OPERAND_pr }, 'o' },
13926 { { OPERAND_ars }, 'i' },
13927 { { OPERAND_ae_lsimm64 }, 'i' }
13930 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
13931 { { STATE_CPENABLE }, 'i' }
13934 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
13935 { { OPERAND_pr }, 'o' },
13936 { { OPERAND_ars }, 'm' },
13937 { { OPERAND_ae_lsimm64 }, 'i' }
13940 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
13941 { { STATE_CPENABLE }, 'i' }
13944 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
13945 { { OPERAND_pr }, 'o' },
13946 { { OPERAND_ars }, 'i' },
13947 { { OPERAND_art }, 'i' }
13950 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
13951 { { STATE_CPENABLE }, 'i' }
13954 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
13955 { { OPERAND_pr }, 'o' },
13956 { { OPERAND_ars }, 'm' },
13957 { { OPERAND_art }, 'i' }
13960 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
13961 { { STATE_CPENABLE }, 'i' }
13964 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
13965 { { OPERAND_pr }, 'i' },
13966 { { OPERAND_ars }, 'i' },
13967 { { OPERAND_ae_lsimm32 }, 'i' }
13970 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
13971 { { STATE_CPENABLE }, 'i' }
13974 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
13975 { { OPERAND_pr }, 'i' },
13976 { { OPERAND_ars }, 'm' },
13977 { { OPERAND_ae_lsimm32 }, 'i' }
13980 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
13981 { { STATE_CPENABLE }, 'i' }
13984 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
13985 { { OPERAND_pr }, 'i' },
13986 { { OPERAND_ars }, 'i' },
13987 { { OPERAND_art }, 'i' }
13990 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
13991 { { STATE_CPENABLE }, 'i' }
13994 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
13995 { { OPERAND_pr }, 'i' },
13996 { { OPERAND_ars }, 'm' },
13997 { { OPERAND_art }, 'i' }
14000 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
14001 { { STATE_CPENABLE }, 'i' }
14004 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
14005 { { OPERAND_pr }, 'i' },
14006 { { OPERAND_ars }, 'i' },
14007 { { OPERAND_ae_lsimm64 }, 'i' }
14010 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
14011 { { STATE_CPENABLE }, 'i' }
14014 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
14015 { { OPERAND_pr }, 'i' },
14016 { { OPERAND_ars }, 'm' },
14017 { { OPERAND_ae_lsimm64 }, 'i' }
14020 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
14021 { { STATE_CPENABLE }, 'i' }
14024 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
14025 { { OPERAND_pr }, 'i' },
14026 { { OPERAND_ars }, 'i' },
14027 { { OPERAND_art }, 'i' }
14030 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
14031 { { STATE_CPENABLE }, 'i' }
14034 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
14035 { { OPERAND_pr }, 'i' },
14036 { { OPERAND_ars }, 'm' },
14037 { { OPERAND_art }, 'i' }
14040 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
14041 { { STATE_CPENABLE }, 'i' }
14044 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
14045 { { OPERAND_pr }, 'i' },
14046 { { OPERAND_ars }, 'i' },
14047 { { OPERAND_ae_lsimm64 }, 'i' }
14050 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
14051 { { STATE_CPENABLE }, 'i' }
14054 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
14055 { { OPERAND_pr }, 'i' },
14056 { { OPERAND_ars }, 'm' },
14057 { { OPERAND_ae_lsimm64 }, 'i' }
14060 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
14061 { { STATE_CPENABLE }, 'i' }
14064 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
14065 { { OPERAND_pr }, 'i' },
14066 { { OPERAND_ars }, 'i' },
14067 { { OPERAND_art }, 'i' }
14070 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
14071 { { STATE_CPENABLE }, 'i' }
14074 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
14075 { { OPERAND_pr }, 'i' },
14076 { { OPERAND_ars }, 'm' },
14077 { { OPERAND_art }, 'i' }
14080 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
14081 { { STATE_CPENABLE }, 'i' }
14084 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
14085 { { OPERAND_pr }, 'i' },
14086 { { OPERAND_ars }, 'i' },
14087 { { OPERAND_ae_lsimm16 }, 'i' }
14090 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
14091 { { STATE_CPENABLE }, 'i' }
14094 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
14095 { { OPERAND_pr }, 'i' },
14096 { { OPERAND_ars }, 'm' },
14097 { { OPERAND_ae_lsimm16 }, 'i' }
14100 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
14101 { { STATE_CPENABLE }, 'i' }
14104 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
14105 { { OPERAND_pr }, 'i' },
14106 { { OPERAND_ars }, 'i' },
14107 { { OPERAND_art }, 'i' }
14110 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
14111 { { STATE_CPENABLE }, 'i' }
14114 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
14115 { { OPERAND_pr }, 'i' },
14116 { { OPERAND_ars }, 'm' },
14117 { { OPERAND_art }, 'i' }
14120 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
14121 { { STATE_CPENABLE }, 'i' }
14124 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
14125 { { OPERAND_pr }, 'i' },
14126 { { OPERAND_ars }, 'i' },
14127 { { OPERAND_ae_lsimm32 }, 'i' }
14130 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
14131 { { STATE_CPENABLE }, 'i' }
14134 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
14135 { { OPERAND_pr }, 'i' },
14136 { { OPERAND_ars }, 'm' },
14137 { { OPERAND_ae_lsimm32 }, 'i' }
14140 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
14141 { { STATE_CPENABLE }, 'i' }
14144 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
14145 { { OPERAND_pr }, 'i' },
14146 { { OPERAND_ars }, 'i' },
14147 { { OPERAND_art }, 'i' }
14150 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
14151 { { STATE_CPENABLE }, 'i' }
14154 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
14155 { { OPERAND_pr }, 'i' },
14156 { { OPERAND_ars }, 'm' },
14157 { { OPERAND_art }, 'i' }
14160 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
14161 { { STATE_CPENABLE }, 'i' }
14164 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
14165 { { OPERAND_pr }, 'i' },
14166 { { OPERAND_ars }, 'i' },
14167 { { OPERAND_ae_lsimm32 }, 'i' }
14170 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
14171 { { STATE_CPENABLE }, 'i' }
14174 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
14175 { { OPERAND_pr }, 'i' },
14176 { { OPERAND_ars }, 'm' },
14177 { { OPERAND_ae_lsimm32 }, 'i' }
14180 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
14181 { { STATE_CPENABLE }, 'i' }
14184 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
14185 { { OPERAND_pr }, 'i' },
14186 { { OPERAND_ars }, 'i' },
14187 { { OPERAND_art }, 'i' }
14190 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
14191 { { STATE_CPENABLE }, 'i' }
14194 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
14195 { { OPERAND_pr }, 'i' },
14196 { { OPERAND_ars }, 'm' },
14197 { { OPERAND_art }, 'i' }
14200 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
14201 { { STATE_CPENABLE }, 'i' }
14204 static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
14205 { { OPERAND_qr1_w }, 'o' },
14206 { { OPERAND_ars }, 'i' },
14207 { { OPERAND_ae_lsimm64 }, 'i' }
14210 static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
14211 { { STATE_CPENABLE }, 'i' }
14214 static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
14215 { { OPERAND_qr1_w }, 'o' },
14216 { { OPERAND_ars }, 'm' },
14217 { { OPERAND_ae_lsimm64 }, 'i' }
14220 static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
14221 { { STATE_CPENABLE }, 'i' }
14224 static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
14225 { { OPERAND_qr1_w }, 'o' },
14226 { { OPERAND_ars }, 'i' },
14227 { { OPERAND_art }, 'i' }
14230 static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
14231 { { STATE_CPENABLE }, 'i' }
14234 static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
14235 { { OPERAND_qr1_w }, 'o' },
14236 { { OPERAND_ars }, 'm' },
14237 { { OPERAND_art }, 'i' }
14240 static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
14241 { { STATE_CPENABLE }, 'i' }
14244 static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
14245 { { OPERAND_qr1_w }, 'o' },
14246 { { OPERAND_ars }, 'i' },
14247 { { OPERAND_ae_lsimm32 }, 'i' }
14250 static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
14251 { { STATE_CPENABLE }, 'i' }
14254 static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
14255 { { OPERAND_qr1_w }, 'o' },
14256 { { OPERAND_ars }, 'm' },
14257 { { OPERAND_ae_lsimm32 }, 'i' }
14260 static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
14261 { { STATE_CPENABLE }, 'i' }
14264 static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
14265 { { OPERAND_qr1_w }, 'o' },
14266 { { OPERAND_ars }, 'i' },
14267 { { OPERAND_art }, 'i' }
14270 static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
14271 { { STATE_CPENABLE }, 'i' }
14274 static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
14275 { { OPERAND_qr1_w }, 'o' },
14276 { { OPERAND_ars }, 'm' },
14277 { { OPERAND_art }, 'i' }
14280 static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
14281 { { STATE_CPENABLE }, 'i' }
14284 static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
14285 { { OPERAND_qr0_rw }, 'i' },
14286 { { OPERAND_ars }, 'i' },
14287 { { OPERAND_ae_lsimm64 }, 'i' }
14290 static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
14291 { { STATE_CPENABLE }, 'i' }
14294 static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
14295 { { OPERAND_qr0_rw }, 'i' },
14296 { { OPERAND_ars }, 'm' },
14297 { { OPERAND_ae_lsimm64 }, 'i' }
14300 static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
14301 { { STATE_CPENABLE }, 'i' }
14304 static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
14305 { { OPERAND_qr0_rw }, 'i' },
14306 { { OPERAND_ars }, 'i' },
14307 { { OPERAND_art }, 'i' }
14310 static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
14311 { { STATE_CPENABLE }, 'i' }
14314 static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
14315 { { OPERAND_qr0_rw }, 'i' },
14316 { { OPERAND_ars }, 'm' },
14317 { { OPERAND_art }, 'i' }
14320 static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
14321 { { STATE_CPENABLE }, 'i' }
14324 static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
14325 { { OPERAND_qr0_rw }, 'i' },
14326 { { OPERAND_ars }, 'i' },
14327 { { OPERAND_ae_lsimm32 }, 'i' }
14330 static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
14331 { { STATE_CPENABLE }, 'i' }
14334 static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
14335 { { OPERAND_qr0_rw }, 'i' },
14336 { { OPERAND_ars }, 'm' },
14337 { { OPERAND_ae_lsimm32 }, 'i' }
14340 static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
14341 { { STATE_CPENABLE }, 'i' }
14344 static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
14345 { { OPERAND_qr0_rw }, 'i' },
14346 { { OPERAND_ars }, 'i' },
14347 { { OPERAND_art }, 'i' }
14350 static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
14351 { { STATE_CPENABLE }, 'i' }
14354 static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
14355 { { OPERAND_qr0_rw }, 'i' },
14356 { { OPERAND_ars }, 'm' },
14357 { { OPERAND_art }, 'i' }
14360 static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
14361 { { STATE_CPENABLE }, 'i' }
14364 static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
14365 { { OPERAND_ps }, 'o' }
14368 static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
14369 { { STATE_CPENABLE }, 'i' }
14372 static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
14373 { { OPERAND_ps }, 'o' },
14374 { { OPERAND_pr }, 'i' }
14377 static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
14378 { { STATE_CPENABLE }, 'i' }
14381 static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
14382 { { OPERAND_ps }, 'o' },
14383 { { OPERAND_pr }, 'i' },
14384 { { OPERAND_pr0 }, 'i' }
14387 static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
14388 { { STATE_CPENABLE }, 'i' }
14391 static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
14392 { { OPERAND_ps }, 'o' },
14393 { { OPERAND_pr }, 'i' },
14394 { { OPERAND_pr0 }, 'i' }
14397 static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
14398 { { STATE_CPENABLE }, 'i' }
14401 static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
14402 { { OPERAND_ps }, 'o' },
14403 { { OPERAND_pr }, 'i' },
14404 { { OPERAND_pr0 }, 'i' }
14407 static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
14408 { { STATE_CPENABLE }, 'i' }
14411 static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
14412 { { OPERAND_ps }, 'o' },
14413 { { OPERAND_pr }, 'i' },
14414 { { OPERAND_pr0 }, 'i' }
14417 static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
14418 { { STATE_CPENABLE }, 'i' }
14421 static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
14422 { { OPERAND_pr }, 'm' },
14423 { { OPERAND_pr0 }, 'i' },
14424 { { OPERAND_bt2 }, 'i' }
14427 static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
14428 { { STATE_CPENABLE }, 'i' }
14431 static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
14432 { { OPERAND_pr }, 'm' },
14433 { { OPERAND_pr0 }, 'i' },
14434 { { OPERAND_bt2 }, 'i' }
14437 static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
14438 { { STATE_CPENABLE }, 'i' }
14441 static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
14442 { { OPERAND_pr }, 'm' },
14443 { { OPERAND_pr0 }, 'i' },
14444 { { OPERAND_bt }, 'i' }
14447 static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
14448 { { STATE_CPENABLE }, 'i' }
14451 static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
14452 { { OPERAND_pr }, 'm' },
14453 { { OPERAND_pr0 }, 'i' },
14454 { { OPERAND_bt }, 'i' }
14457 static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
14458 { { STATE_CPENABLE }, 'i' }
14461 static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
14462 { { OPERAND_pr }, 'o' },
14463 { { OPERAND_ars }, 'i' },
14464 { { OPERAND_art }, 'i' }
14467 static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
14468 { { STATE_CPENABLE }, 'i' }
14471 static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
14472 { { OPERAND_pr }, 'o' },
14473 { { OPERAND_ars }, 'i' },
14474 { { OPERAND_art }, 'i' }
14477 static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
14478 { { STATE_CPENABLE }, 'i' }
14481 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
14482 { { OPERAND_ars }, 'o' },
14483 { { OPERAND_pr }, 'i' }
14486 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
14487 { { STATE_CPENABLE }, 'i' }
14490 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
14491 { { OPERAND_ars }, 'o' },
14492 { { OPERAND_pr }, 'i' }
14495 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
14496 { { STATE_CPENABLE }, 'i' }
14499 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
14500 { { OPERAND_pr }, 'o' },
14501 { { OPERAND_ars }, 'i' },
14502 { { OPERAND_art }, 'i' }
14505 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
14506 { { STATE_CPENABLE }, 'i' }
14509 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
14510 { { OPERAND_pr }, 'o' },
14511 { { OPERAND_ars }, 'i' },
14512 { { OPERAND_art }, 'i' }
14515 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
14516 { { STATE_CPENABLE }, 'i' }
14519 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
14520 { { OPERAND_pr }, 'o' },
14521 { { OPERAND_ars }, 'i' },
14522 { { OPERAND_art }, 'i' }
14525 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
14526 { { STATE_CPENABLE }, 'i' }
14529 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
14530 { { OPERAND_pr }, 'o' },
14531 { { OPERAND_ars }, 'i' },
14532 { { OPERAND_art }, 'i' }
14535 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
14536 { { STATE_CPENABLE }, 'i' }
14539 static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
14540 { { OPERAND_ps }, 'o' },
14541 { { OPERAND_qr0_rw }, 'i' },
14542 { { OPERAND_qr0 }, 'i' }
14545 static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
14546 { { STATE_CPENABLE }, 'i' }
14549 static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
14550 { { OPERAND_ps }, 'o' },
14551 { { OPERAND_pr }, 'i' }
14554 static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
14555 { { STATE_CPENABLE }, 'i' }
14558 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
14559 { { OPERAND_ps }, 'o' },
14560 { { OPERAND_qr0_rw }, 'i' }
14563 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
14564 { { STATE_AE_OVERFLOW }, 'm' },
14565 { { STATE_CPENABLE }, 'i' }
14568 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
14569 { { OPERAND_ps }, 'o' },
14570 { { OPERAND_qr0_rw }, 'i' }
14573 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
14574 { { STATE_AE_OVERFLOW }, 'm' },
14575 { { STATE_CPENABLE }, 'i' }
14578 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
14579 { { OPERAND_ps }, 'o' },
14580 { { OPERAND_qr0_rw }, 'i' }
14583 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
14584 { { STATE_AE_OVERFLOW }, 'm' },
14585 { { STATE_CPENABLE }, 'i' }
14588 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
14589 { { OPERAND_ps }, 'o' },
14590 { { OPERAND_qr0_rw }, 'i' }
14593 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
14594 { { STATE_AE_OVERFLOW }, 'm' },
14595 { { STATE_CPENABLE }, 'i' }
14598 static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
14599 { { OPERAND_ps }, 'o' },
14600 { { OPERAND_pr }, 'i' }
14603 static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
14604 { { STATE_AE_OVERFLOW }, 'm' },
14605 { { STATE_CPENABLE }, 'i' }
14608 static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
14609 { { OPERAND_ps }, 'o' },
14610 { { OPERAND_pr }, 'i' }
14613 static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
14614 { { STATE_AE_OVERFLOW }, 'm' },
14615 { { STATE_CPENABLE }, 'i' }
14618 static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
14619 { { OPERAND_qr1_w }, 'o' }
14622 static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
14623 { { STATE_CPENABLE }, 'i' }
14626 static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
14627 { { OPERAND_qr1_w }, 'o' },
14628 { { OPERAND_qr0_rw }, 'i' }
14631 static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
14632 { { STATE_CPENABLE }, 'i' }
14635 static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
14636 { { OPERAND_qr1_w }, 'm' },
14637 { { OPERAND_qr0_rw }, 'i' },
14638 { { OPERAND_bs }, 'i' }
14641 static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
14642 { { STATE_CPENABLE }, 'i' }
14645 static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
14646 { { OPERAND_qr1_w }, 'm' },
14647 { { OPERAND_qr0_rw }, 'i' },
14648 { { OPERAND_bs }, 'i' }
14651 static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
14652 { { STATE_CPENABLE }, 'i' }
14655 static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
14656 { { OPERAND_qr1_w }, 'o' },
14657 { { OPERAND_ars }, 'i' }
14660 static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
14661 { { STATE_CPENABLE }, 'i' }
14664 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
14665 { { OPERAND_qr1_w }, 'o' },
14666 { { OPERAND_cvt_pr }, 'i' }
14669 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
14670 { { STATE_CPENABLE }, 'i' }
14673 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
14674 { { OPERAND_qr1_w }, 'o' },
14675 { { OPERAND_cvt_pr }, 'i' }
14678 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
14679 { { STATE_CPENABLE }, 'i' }
14682 static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
14683 { { OPERAND_qr1_w }, 'o' },
14684 { { OPERAND_qr0 }, 'i' }
14687 static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
14688 { { STATE_AE_OVERFLOW }, 'm' },
14689 { { STATE_CPENABLE }, 'i' }
14692 static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
14693 { { OPERAND_qr1_w }, 'o' },
14694 { { OPERAND_qr0_rw }, 'i' }
14697 static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
14698 { { STATE_CPENABLE }, 'i' }
14701 static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
14702 { { OPERAND_qr1_w }, 'o' },
14703 { { OPERAND_qr0_rw }, 'i' }
14706 static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
14707 { { STATE_AE_OVERFLOW }, 'm' },
14708 { { STATE_CPENABLE }, 'i' }
14711 static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
14712 { { OPERAND_qr1_w }, 'o' },
14713 { { OPERAND_qr0_rw }, 'i' }
14716 static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
14717 { { STATE_AE_OVERFLOW }, 'm' },
14718 { { STATE_CPENABLE }, 'i' }
14721 static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
14722 { { OPERAND_ars }, 'o' },
14723 { { OPERAND_qr0_rw }, 'i' }
14726 static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
14727 { { STATE_CPENABLE }, 'i' }
14730 static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
14731 { { OPERAND_ars }, 'o' },
14732 { { OPERAND_pr }, 'i' }
14735 static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
14736 { { STATE_CPENABLE }, 'i' }
14739 static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
14740 { { OPERAND_ars }, 'o' },
14741 { { OPERAND_pr }, 'i' }
14744 static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
14745 { { STATE_CPENABLE }, 'i' }
14748 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
14749 { { OPERAND_ars }, 'o' },
14750 { { OPERAND_pr }, 'i' }
14753 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
14754 { { STATE_CPENABLE }, 'i' }
14757 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
14758 { { OPERAND_ars }, 'o' },
14759 { { OPERAND_pr }, 'i' }
14762 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
14763 { { STATE_CPENABLE }, 'i' }
14766 static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
14767 { { OPERAND_ps }, 'o' },
14768 { { OPERAND_pr }, 'i' },
14769 { { OPERAND_pr0 }, 'i' }
14772 static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
14773 { { STATE_CPENABLE }, 'i' }
14776 static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
14777 { { OPERAND_ps }, 'o' },
14778 { { OPERAND_pr }, 'i' },
14779 { { OPERAND_pr0 }, 'i' }
14782 static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
14783 { { STATE_CPENABLE }, 'i' }
14786 static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
14787 { { OPERAND_ps }, 'o' },
14788 { { OPERAND_pr0 }, 'i' }
14791 static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
14792 { { STATE_CPENABLE }, 'i' }
14795 static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
14796 { { OPERAND_ps }, 'o' },
14797 { { OPERAND_pr0 }, 'i' }
14800 static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
14801 { { STATE_CPENABLE }, 'i' }
14804 static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
14805 { { OPERAND_ps }, 'o' },
14806 { { OPERAND_pr }, 'i' },
14807 { { OPERAND_pr0 }, 'i' }
14810 static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
14811 { { STATE_CPENABLE }, 'i' }
14814 static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
14815 { { OPERAND_ps }, 'o' },
14816 { { OPERAND_pr }, 'i' },
14817 { { OPERAND_pr0 }, 'i' }
14820 static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
14821 { { STATE_CPENABLE }, 'i' }
14824 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
14825 { { OPERAND_alupppb_ps }, 'o' },
14826 { { OPERAND_pr }, 'i' },
14827 { { OPERAND_pr0 }, 'i' },
14828 { { OPERAND_bt2 }, 'o' }
14831 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
14832 { { STATE_CPENABLE }, 'i' }
14835 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
14836 { { OPERAND_alupppb_ps }, 'o' },
14837 { { OPERAND_pr }, 'i' },
14838 { { OPERAND_pr0 }, 'i' },
14839 { { OPERAND_bt2 }, 'o' }
14842 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
14843 { { STATE_CPENABLE }, 'i' }
14846 static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
14847 { { OPERAND_ps }, 'o' },
14848 { { OPERAND_pr }, 'i' },
14849 { { OPERAND_pr0 }, 'i' }
14852 static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
14853 { { STATE_AE_OVERFLOW }, 'm' },
14854 { { STATE_CPENABLE }, 'i' }
14857 static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
14858 { { OPERAND_ps }, 'o' },
14859 { { OPERAND_pr }, 'i' },
14860 { { OPERAND_pr0 }, 'i' }
14863 static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
14864 { { STATE_AE_OVERFLOW }, 'm' },
14865 { { STATE_CPENABLE }, 'i' }
14868 static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
14869 { { OPERAND_ps }, 'o' },
14870 { { OPERAND_pr0 }, 'i' }
14873 static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
14874 { { STATE_AE_OVERFLOW }, 'm' },
14875 { { STATE_CPENABLE }, 'i' }
14878 static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
14879 { { OPERAND_ps }, 'o' },
14880 { { OPERAND_pr0 }, 'i' }
14883 static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
14884 { { STATE_AE_OVERFLOW }, 'm' },
14885 { { STATE_CPENABLE }, 'i' }
14888 static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
14889 { { OPERAND_ps }, 'o' },
14890 { { OPERAND_pr }, 'i' },
14891 { { OPERAND_pr0 }, 'i' }
14894 static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
14895 { { STATE_CPENABLE }, 'i' }
14898 static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
14899 { { OPERAND_ps }, 'o' },
14900 { { OPERAND_pr }, 'i' },
14901 { { OPERAND_pr0 }, 'i' }
14904 static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
14905 { { STATE_CPENABLE }, 'i' }
14908 static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
14909 { { OPERAND_ps }, 'o' },
14910 { { OPERAND_pr }, 'i' },
14911 { { OPERAND_pr0 }, 'i' }
14914 static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
14915 { { STATE_CPENABLE }, 'i' }
14918 static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
14919 { { OPERAND_ps }, 'o' },
14920 { { OPERAND_pr }, 'i' },
14921 { { OPERAND_pr0 }, 'i' }
14924 static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
14925 { { STATE_CPENABLE }, 'i' }
14928 static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
14929 { { OPERAND_bt2 }, 'o' },
14930 { { OPERAND_pr }, 'i' },
14931 { { OPERAND_pr0 }, 'i' }
14934 static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
14935 { { STATE_CPENABLE }, 'i' }
14938 static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
14939 { { OPERAND_bt2 }, 'o' },
14940 { { OPERAND_pr }, 'i' },
14941 { { OPERAND_pr0 }, 'i' }
14944 static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
14945 { { STATE_CPENABLE }, 'i' }
14948 static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
14949 { { OPERAND_bt2 }, 'o' },
14950 { { OPERAND_pr }, 'i' },
14951 { { OPERAND_pr0 }, 'i' }
14954 static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
14955 { { STATE_CPENABLE }, 'i' }
14958 static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
14959 { { OPERAND_qr1_w }, 'o' },
14960 { { OPERAND_qr0_rw }, 'i' },
14961 { { OPERAND_qr0 }, 'i' }
14964 static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
14965 { { STATE_CPENABLE }, 'i' }
14968 static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
14969 { { OPERAND_qr1_w }, 'o' },
14970 { { OPERAND_qr0_rw }, 'i' },
14971 { { OPERAND_qr0 }, 'i' }
14974 static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
14975 { { STATE_CPENABLE }, 'i' }
14978 static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
14979 { { OPERAND_qr1_w }, 'o' },
14980 { { OPERAND_qr0 }, 'i' }
14983 static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
14984 { { STATE_CPENABLE }, 'i' }
14987 static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
14988 { { OPERAND_qr1_w }, 'o' },
14989 { { OPERAND_qr0 }, 'i' }
14992 static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
14993 { { STATE_CPENABLE }, 'i' }
14996 static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
14997 { { OPERAND_qr1_w }, 'o' },
14998 { { OPERAND_qr0 }, 'i' },
14999 { { OPERAND_qr0_rw }, 'i' }
15002 static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
15003 { { STATE_CPENABLE }, 'i' }
15006 static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
15007 { { OPERAND_qr1_w }, 'o' },
15008 { { OPERAND_qr0 }, 'i' },
15009 { { OPERAND_qr0_rw }, 'i' }
15012 static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
15013 { { STATE_CPENABLE }, 'i' }
15016 static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
15017 { { OPERAND_qr1_w }, 'o' },
15018 { { OPERAND_qr0 }, 'i' },
15019 { { OPERAND_qr0_rw }, 'i' },
15020 { { OPERAND_bt }, 'o' }
15023 static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
15024 { { STATE_CPENABLE }, 'i' }
15027 static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
15028 { { OPERAND_qr1_w }, 'o' },
15029 { { OPERAND_qr0 }, 'i' },
15030 { { OPERAND_qr0_rw }, 'i' },
15031 { { OPERAND_bt }, 'o' }
15034 static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
15035 { { STATE_CPENABLE }, 'i' }
15038 static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
15039 { { OPERAND_qr1_w }, 'o' },
15040 { { OPERAND_qr0_rw }, 'i' },
15041 { { OPERAND_qr0 }, 'i' }
15044 static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
15045 { { STATE_AE_OVERFLOW }, 'm' },
15046 { { STATE_CPENABLE }, 'i' }
15049 static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
15050 { { OPERAND_qr1_w }, 'o' },
15051 { { OPERAND_qr0_rw }, 'i' },
15052 { { OPERAND_qr0 }, 'i' }
15055 static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
15056 { { STATE_AE_OVERFLOW }, 'm' },
15057 { { STATE_CPENABLE }, 'i' }
15060 static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
15061 { { OPERAND_qr1_w }, 'o' },
15062 { { OPERAND_qr0 }, 'i' }
15065 static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
15066 { { STATE_AE_OVERFLOW }, 'm' },
15067 { { STATE_CPENABLE }, 'i' }
15070 static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
15071 { { OPERAND_qr1_w }, 'o' },
15072 { { OPERAND_qr0 }, 'i' }
15075 static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
15076 { { STATE_AE_OVERFLOW }, 'm' },
15077 { { STATE_CPENABLE }, 'i' }
15080 static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
15081 { { OPERAND_qr1_w }, 'o' },
15082 { { OPERAND_qr0 }, 'i' },
15083 { { OPERAND_qr0_rw }, 'i' }
15086 static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
15087 { { STATE_CPENABLE }, 'i' }
15090 static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
15091 { { OPERAND_qr1_w }, 'o' },
15092 { { OPERAND_qr0 }, 'i' },
15093 { { OPERAND_qr0_rw }, 'i' }
15096 static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
15097 { { STATE_CPENABLE }, 'i' }
15100 static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
15101 { { OPERAND_qr1_w }, 'o' },
15102 { { OPERAND_qr0 }, 'i' },
15103 { { OPERAND_qr0_rw }, 'i' }
15106 static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
15107 { { STATE_CPENABLE }, 'i' }
15110 static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
15111 { { OPERAND_qr1_w }, 'o' },
15112 { { OPERAND_qr0 }, 'i' },
15113 { { OPERAND_qr0_rw }, 'i' }
15116 static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
15117 { { STATE_CPENABLE }, 'i' }
15120 static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
15121 { { OPERAND_ps }, 'o' },
15122 { { OPERAND_pr }, 'i' },
15123 { { OPERAND_ae_samt32 }, 'i' }
15126 static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
15127 { { STATE_CPENABLE }, 'i' }
15130 static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
15131 { { OPERAND_ps }, 'o' },
15132 { { OPERAND_pr }, 'i' },
15133 { { OPERAND_ae_samt32 }, 'i' }
15136 static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
15137 { { STATE_CPENABLE }, 'i' }
15140 static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
15141 { { OPERAND_ps }, 'o' },
15142 { { OPERAND_pr }, 'i' },
15143 { { OPERAND_ae_samt32 }, 'i' }
15146 static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
15147 { { STATE_CPENABLE }, 'i' }
15150 static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
15151 { { OPERAND_ps }, 'o' },
15152 { { OPERAND_pr }, 'i' }
15155 static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
15156 { { STATE_AE_SAR }, 'i' },
15157 { { STATE_CPENABLE }, 'i' }
15160 static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
15161 { { OPERAND_ps }, 'o' },
15162 { { OPERAND_pr }, 'i' }
15165 static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
15166 { { STATE_AE_SAR }, 'i' },
15167 { { STATE_CPENABLE }, 'i' }
15170 static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
15171 { { OPERAND_ps }, 'o' },
15172 { { OPERAND_pr }, 'i' }
15175 static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
15176 { { STATE_AE_SAR }, 'i' },
15177 { { STATE_CPENABLE }, 'i' }
15180 static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
15181 { { OPERAND_ps }, 'o' },
15182 { { OPERAND_pr }, 'i' },
15183 { { OPERAND_ae_samt32 }, 'i' }
15186 static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
15187 { { STATE_AE_OVERFLOW }, 'm' },
15188 { { STATE_CPENABLE }, 'i' }
15191 static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
15192 { { OPERAND_ps }, 'o' },
15193 { { OPERAND_pr }, 'i' }
15196 static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
15197 { { STATE_AE_OVERFLOW }, 'm' },
15198 { { STATE_AE_SAR }, 'i' },
15199 { { STATE_CPENABLE }, 'i' }
15202 static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
15203 { { OPERAND_qr1_w }, 'o' },
15204 { { OPERAND_qr0_rw }, 'i' },
15205 { { OPERAND_ae_samt64 }, 'i' }
15208 static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
15209 { { STATE_CPENABLE }, 'i' }
15212 static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
15213 { { OPERAND_qr1_w }, 'o' },
15214 { { OPERAND_qr0_rw }, 'i' },
15215 { { OPERAND_ae_samt64 }, 'i' }
15218 static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
15219 { { STATE_CPENABLE }, 'i' }
15222 static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
15223 { { OPERAND_qr1_w }, 'o' },
15224 { { OPERAND_qr0_rw }, 'i' },
15225 { { OPERAND_ae_samt64 }, 'i' }
15228 static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
15229 { { STATE_CPENABLE }, 'i' }
15232 static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
15233 { { OPERAND_qr1_w }, 'o' },
15234 { { OPERAND_qr0_rw }, 'i' }
15237 static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
15238 { { STATE_AE_SAR }, 'i' },
15239 { { STATE_CPENABLE }, 'i' }
15242 static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
15243 { { OPERAND_qr1_w }, 'o' },
15244 { { OPERAND_qr0_rw }, 'i' }
15247 static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
15248 { { STATE_AE_SAR }, 'i' },
15249 { { STATE_CPENABLE }, 'i' }
15252 static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
15253 { { OPERAND_qr1_w }, 'o' },
15254 { { OPERAND_qr0_rw }, 'i' }
15257 static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
15258 { { STATE_AE_SAR }, 'i' },
15259 { { STATE_CPENABLE }, 'i' }
15262 static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
15263 { { OPERAND_qr1_w }, 'o' },
15264 { { OPERAND_qr0_rw }, 'i' },
15265 { { OPERAND_ars }, 'i' }
15268 static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
15269 { { STATE_CPENABLE }, 'i' }
15272 static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
15273 { { OPERAND_qr1_w }, 'o' },
15274 { { OPERAND_qr0_rw }, 'i' },
15275 { { OPERAND_ars }, 'i' }
15278 static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
15279 { { STATE_CPENABLE }, 'i' }
15282 static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
15283 { { OPERAND_qr1_w }, 'o' },
15284 { { OPERAND_qr0_rw }, 'i' },
15285 { { OPERAND_ars }, 'i' }
15288 static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
15289 { { STATE_CPENABLE }, 'i' }
15292 static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
15293 { { OPERAND_qr1_w }, 'o' },
15294 { { OPERAND_qr0_rw }, 'i' },
15295 { { OPERAND_ae_samt64 }, 'i' }
15298 static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
15299 { { STATE_AE_OVERFLOW }, 'm' },
15300 { { STATE_CPENABLE }, 'i' }
15303 static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
15304 { { OPERAND_qr1_w }, 'o' },
15305 { { OPERAND_qr0_rw }, 'i' }
15308 static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
15309 { { STATE_AE_OVERFLOW }, 'm' },
15310 { { STATE_AE_SAR }, 'i' },
15311 { { STATE_CPENABLE }, 'i' }
15314 static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
15315 { { OPERAND_qr1_w }, 'o' },
15316 { { OPERAND_qr0_rw }, 'i' },
15317 { { OPERAND_ars }, 'i' }
15320 static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
15321 { { STATE_AE_OVERFLOW }, 'm' },
15322 { { STATE_CPENABLE }, 'i' }
15325 static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
15326 { { OPERAND_bt }, 'o' },
15327 { { OPERAND_qr0 }, 'i' },
15328 { { OPERAND_qr0_rw }, 'i' }
15331 static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
15332 { { STATE_CPENABLE }, 'i' }
15335 static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
15336 { { OPERAND_bt }, 'o' },
15337 { { OPERAND_qr0 }, 'i' },
15338 { { OPERAND_qr0_rw }, 'i' }
15341 static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
15342 { { STATE_CPENABLE }, 'i' }
15345 static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
15346 { { OPERAND_bt }, 'o' },
15347 { { OPERAND_qr0 }, 'i' },
15348 { { OPERAND_qr0_rw }, 'i' }
15351 static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
15352 { { STATE_CPENABLE }, 'i' }
15355 static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
15356 { { OPERAND_ars }, 'o' },
15357 { { OPERAND_qr0_rw }, 'i' }
15360 static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
15361 { { STATE_CPENABLE }, 'i' }
15364 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
15365 { { OPERAND_mac_qr1_w }, 'o' },
15366 { { OPERAND_pr }, 'i' },
15367 { { OPERAND_pr0 }, 'i' }
15370 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
15371 { { STATE_AE_OVERFLOW }, 'm' },
15372 { { STATE_CPENABLE }, 'i' }
15375 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
15376 { { OPERAND_mac_qr1_w }, 'o' },
15377 { { OPERAND_pr }, 'i' },
15378 { { OPERAND_pr0 }, 'i' }
15381 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
15382 { { STATE_CPENABLE }, 'i' }
15385 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
15386 { { OPERAND_mac_qr1_w }, 'o' },
15387 { { OPERAND_pr }, 'i' },
15388 { { OPERAND_pr0 }, 'i' }
15391 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
15392 { { STATE_CPENABLE }, 'i' }
15395 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
15396 { { OPERAND_mac_qr1_w }, 'o' },
15397 { { OPERAND_pr }, 'i' },
15398 { { OPERAND_pr0 }, 'i' }
15401 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
15402 { { STATE_AE_OVERFLOW }, 'm' },
15403 { { STATE_CPENABLE }, 'i' }
15406 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
15407 { { OPERAND_mac_qr1_w }, 'o' },
15408 { { OPERAND_pr }, 'i' },
15409 { { OPERAND_pr0 }, 'i' }
15412 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
15413 { { STATE_CPENABLE }, 'i' }
15416 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
15417 { { OPERAND_mac_qr1_w }, 'o' },
15418 { { OPERAND_pr }, 'i' },
15419 { { OPERAND_pr0 }, 'i' }
15422 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
15423 { { STATE_CPENABLE }, 'i' }
15426 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
15427 { { OPERAND_mac_qr1_w }, 'o' },
15428 { { OPERAND_pr }, 'i' },
15429 { { OPERAND_pr0 }, 'i' }
15432 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
15433 { { STATE_AE_OVERFLOW }, 'm' },
15434 { { STATE_CPENABLE }, 'i' }
15437 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
15438 { { OPERAND_mac_qr1_w }, 'o' },
15439 { { OPERAND_pr }, 'i' },
15440 { { OPERAND_pr0 }, 'i' }
15443 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
15444 { { STATE_CPENABLE }, 'i' }
15447 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
15448 { { OPERAND_mac_qr1_w }, 'o' },
15449 { { OPERAND_pr }, 'i' },
15450 { { OPERAND_pr0 }, 'i' }
15453 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
15454 { { STATE_CPENABLE }, 'i' }
15457 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
15458 { { OPERAND_mac_qr1_w }, 'o' },
15459 { { OPERAND_pr }, 'i' },
15460 { { OPERAND_pr0 }, 'i' }
15463 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
15464 { { STATE_AE_OVERFLOW }, 'm' },
15465 { { STATE_CPENABLE }, 'i' }
15468 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
15469 { { OPERAND_mac_qr1_w }, 'o' },
15470 { { OPERAND_pr }, 'i' },
15471 { { OPERAND_pr0 }, 'i' }
15474 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
15475 { { STATE_CPENABLE }, 'i' }
15478 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
15479 { { OPERAND_mac_qr1_w }, 'o' },
15480 { { OPERAND_pr }, 'i' },
15481 { { OPERAND_pr0 }, 'i' }
15484 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
15485 { { STATE_CPENABLE }, 'i' }
15488 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
15489 { { OPERAND_mac_qr1_w }, 'm' },
15490 { { OPERAND_pr }, 'i' },
15491 { { OPERAND_pr0 }, 'i' }
15494 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
15495 { { STATE_AE_OVERFLOW }, 'm' },
15496 { { STATE_CPENABLE }, 'i' }
15499 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
15500 { { OPERAND_mac_qr1_w }, 'm' },
15501 { { OPERAND_pr }, 'i' },
15502 { { OPERAND_pr0 }, 'i' }
15505 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
15506 { { STATE_CPENABLE }, 'i' }
15509 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
15510 { { OPERAND_mac_qr1_w }, 'm' },
15511 { { OPERAND_pr }, 'i' },
15512 { { OPERAND_pr0 }, 'i' }
15515 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
15516 { { STATE_CPENABLE }, 'i' }
15519 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
15520 { { OPERAND_mac_qr1_w }, 'm' },
15521 { { OPERAND_pr }, 'i' },
15522 { { OPERAND_pr0 }, 'i' }
15525 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
15526 { { STATE_AE_OVERFLOW }, 'm' },
15527 { { STATE_CPENABLE }, 'i' }
15530 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
15531 { { OPERAND_mac_qr1_w }, 'm' },
15532 { { OPERAND_pr }, 'i' },
15533 { { OPERAND_pr0 }, 'i' }
15536 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
15537 { { STATE_CPENABLE }, 'i' }
15540 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
15541 { { OPERAND_mac_qr1_w }, 'm' },
15542 { { OPERAND_pr }, 'i' },
15543 { { OPERAND_pr0 }, 'i' }
15546 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
15547 { { STATE_CPENABLE }, 'i' }
15550 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
15551 { { OPERAND_mac_qr1_w }, 'm' },
15552 { { OPERAND_pr }, 'i' },
15553 { { OPERAND_pr0 }, 'i' }
15556 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
15557 { { STATE_AE_OVERFLOW }, 'm' },
15558 { { STATE_CPENABLE }, 'i' }
15561 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
15562 { { OPERAND_mac_qr1_w }, 'm' },
15563 { { OPERAND_pr }, 'i' },
15564 { { OPERAND_pr0 }, 'i' }
15567 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
15568 { { STATE_CPENABLE }, 'i' }
15571 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
15572 { { OPERAND_mac_qr1_w }, 'm' },
15573 { { OPERAND_pr }, 'i' },
15574 { { OPERAND_pr0 }, 'i' }
15577 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
15578 { { STATE_CPENABLE }, 'i' }
15581 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
15582 { { OPERAND_mac_qr1_w }, 'm' },
15583 { { OPERAND_pr }, 'i' },
15584 { { OPERAND_pr0 }, 'i' }
15587 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
15588 { { STATE_AE_OVERFLOW }, 'm' },
15589 { { STATE_CPENABLE }, 'i' }
15592 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
15593 { { OPERAND_mac_qr1_w }, 'm' },
15594 { { OPERAND_pr }, 'i' },
15595 { { OPERAND_pr0 }, 'i' }
15598 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
15599 { { STATE_CPENABLE }, 'i' }
15602 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
15603 { { OPERAND_mac_qr1_w }, 'm' },
15604 { { OPERAND_pr }, 'i' },
15605 { { OPERAND_pr0 }, 'i' }
15608 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
15609 { { STATE_CPENABLE }, 'i' }
15612 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
15613 { { OPERAND_mac_qr1_w }, 'm' },
15614 { { OPERAND_pr }, 'i' },
15615 { { OPERAND_pr0 }, 'i' }
15618 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
15619 { { STATE_AE_OVERFLOW }, 'm' },
15620 { { STATE_CPENABLE }, 'i' }
15623 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
15624 { { OPERAND_mac_qr1_w }, 'm' },
15625 { { OPERAND_pr }, 'i' },
15626 { { OPERAND_pr0 }, 'i' }
15629 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
15630 { { STATE_CPENABLE }, 'i' }
15633 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
15634 { { OPERAND_mac_qr1_w }, 'm' },
15635 { { OPERAND_pr }, 'i' },
15636 { { OPERAND_pr0 }, 'i' }
15639 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
15640 { { STATE_CPENABLE }, 'i' }
15643 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
15644 { { OPERAND_mac_qr1_w }, 'm' },
15645 { { OPERAND_pr }, 'i' },
15646 { { OPERAND_pr0 }, 'i' }
15649 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
15650 { { STATE_AE_OVERFLOW }, 'm' },
15651 { { STATE_CPENABLE }, 'i' }
15654 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
15655 { { OPERAND_mac_qr1_w }, 'm' },
15656 { { OPERAND_pr }, 'i' },
15657 { { OPERAND_pr0 }, 'i' }
15660 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
15661 { { STATE_CPENABLE }, 'i' }
15664 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
15665 { { OPERAND_mac_qr1_w }, 'm' },
15666 { { OPERAND_pr }, 'i' },
15667 { { OPERAND_pr0 }, 'i' }
15670 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
15671 { { STATE_CPENABLE }, 'i' }
15674 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
15675 { { OPERAND_mac_qr1_w }, 'm' },
15676 { { OPERAND_pr }, 'i' },
15677 { { OPERAND_pr0 }, 'i' }
15680 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
15681 { { STATE_AE_OVERFLOW }, 'm' },
15682 { { STATE_CPENABLE }, 'i' }
15685 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
15686 { { OPERAND_mac_qr1_w }, 'm' },
15687 { { OPERAND_pr }, 'i' },
15688 { { OPERAND_pr0 }, 'i' }
15691 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
15692 { { STATE_CPENABLE }, 'i' }
15695 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
15696 { { OPERAND_mac_qr1_w }, 'm' },
15697 { { OPERAND_pr }, 'i' },
15698 { { OPERAND_pr0 }, 'i' }
15701 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
15702 { { STATE_CPENABLE }, 'i' }
15705 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
15706 { { OPERAND_mac_qr1_w }, 'm' },
15707 { { OPERAND_pr }, 'i' },
15708 { { OPERAND_pr0 }, 'i' }
15711 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
15712 { { STATE_AE_OVERFLOW }, 'm' },
15713 { { STATE_CPENABLE }, 'i' }
15716 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
15717 { { OPERAND_mac_qr1_w }, 'm' },
15718 { { OPERAND_pr }, 'i' },
15719 { { OPERAND_pr0 }, 'i' }
15722 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
15723 { { STATE_CPENABLE }, 'i' }
15726 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
15727 { { OPERAND_mac_qr1_w }, 'm' },
15728 { { OPERAND_pr }, 'i' },
15729 { { OPERAND_pr0 }, 'i' }
15732 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
15733 { { STATE_CPENABLE }, 'i' }
15736 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
15737 { { OPERAND_mac_qr1_w }, 'm' },
15738 { { OPERAND_pr }, 'i' },
15739 { { OPERAND_pr0 }, 'i' }
15742 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
15743 { { STATE_AE_OVERFLOW }, 'm' },
15744 { { STATE_CPENABLE }, 'i' }
15747 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
15748 { { OPERAND_mac_qr1_w }, 'm' },
15749 { { OPERAND_pr }, 'i' },
15750 { { OPERAND_pr0 }, 'i' }
15753 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
15754 { { STATE_AE_OVERFLOW }, 'm' },
15755 { { STATE_CPENABLE }, 'i' }
15758 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
15759 { { OPERAND_mac_qr1_w }, 'm' },
15760 { { OPERAND_pr }, 'i' },
15761 { { OPERAND_pr0 }, 'i' }
15764 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
15765 { { STATE_AE_OVERFLOW }, 'm' },
15766 { { STATE_CPENABLE }, 'i' }
15769 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
15770 { { OPERAND_mac_qr1_w }, 'm' },
15771 { { OPERAND_pr }, 'i' },
15772 { { OPERAND_pr0 }, 'i' }
15775 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
15776 { { STATE_AE_OVERFLOW }, 'm' },
15777 { { STATE_CPENABLE }, 'i' }
15780 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
15781 { { OPERAND_mac_qr1_w }, 'm' },
15782 { { OPERAND_pr }, 'i' },
15783 { { OPERAND_pr0 }, 'i' }
15786 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
15787 { { STATE_AE_OVERFLOW }, 'm' },
15788 { { STATE_CPENABLE }, 'i' }
15791 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
15792 { { OPERAND_mac_qr1_w }, 'm' },
15793 { { OPERAND_pr }, 'i' },
15794 { { OPERAND_pr0 }, 'i' }
15797 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
15798 { { STATE_AE_OVERFLOW }, 'm' },
15799 { { STATE_CPENABLE }, 'i' }
15802 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
15803 { { OPERAND_mac_qr1_w }, 'm' },
15804 { { OPERAND_pr }, 'i' },
15805 { { OPERAND_pr0 }, 'i' }
15808 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
15809 { { STATE_AE_OVERFLOW }, 'm' },
15810 { { STATE_CPENABLE }, 'i' }
15813 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
15814 { { OPERAND_mac_qr1_w }, 'm' },
15815 { { OPERAND_pr }, 'i' },
15816 { { OPERAND_pr0 }, 'i' }
15819 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
15820 { { STATE_AE_OVERFLOW }, 'm' },
15821 { { STATE_CPENABLE }, 'i' }
15824 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
15825 { { OPERAND_mac_qr1_w }, 'm' },
15826 { { OPERAND_pr }, 'i' },
15827 { { OPERAND_pr0 }, 'i' }
15830 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
15831 { { STATE_AE_OVERFLOW }, 'm' },
15832 { { STATE_CPENABLE }, 'i' }
15835 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
15836 { { OPERAND_mac_qr1_w }, 'm' },
15837 { { OPERAND_pr }, 'i' },
15838 { { OPERAND_pr0 }, 'i' }
15841 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
15842 { { STATE_AE_OVERFLOW }, 'm' },
15843 { { STATE_CPENABLE }, 'i' }
15846 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
15847 { { OPERAND_mac_qr1_w }, 'm' },
15848 { { OPERAND_pr }, 'i' },
15849 { { OPERAND_pr0 }, 'i' }
15852 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
15853 { { STATE_AE_OVERFLOW }, 'm' },
15854 { { STATE_CPENABLE }, 'i' }
15857 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
15858 { { OPERAND_mac_qr1_w }, 'm' },
15859 { { OPERAND_pr }, 'i' },
15860 { { OPERAND_pr0 }, 'i' }
15863 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
15864 { { STATE_AE_OVERFLOW }, 'm' },
15865 { { STATE_CPENABLE }, 'i' }
15868 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
15869 { { OPERAND_mac_qr1_w }, 'm' },
15870 { { OPERAND_pr }, 'i' },
15871 { { OPERAND_pr0 }, 'i' }
15874 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
15875 { { STATE_AE_OVERFLOW }, 'm' },
15876 { { STATE_CPENABLE }, 'i' }
15879 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
15880 { { OPERAND_mac_qr1_w }, 'm' },
15881 { { OPERAND_pr }, 'i' },
15882 { { OPERAND_pr0 }, 'i' }
15885 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
15886 { { STATE_AE_OVERFLOW }, 'm' },
15887 { { STATE_CPENABLE }, 'i' }
15890 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
15891 { { OPERAND_mac_qr1_w }, 'm' },
15892 { { OPERAND_pr }, 'i' },
15893 { { OPERAND_pr0 }, 'i' }
15896 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
15897 { { STATE_AE_OVERFLOW }, 'm' },
15898 { { STATE_CPENABLE }, 'i' }
15901 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
15902 { { OPERAND_mac_qr1_w }, 'm' },
15903 { { OPERAND_pr }, 'i' },
15904 { { OPERAND_pr0 }, 'i' }
15907 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
15908 { { STATE_AE_OVERFLOW }, 'm' },
15909 { { STATE_CPENABLE }, 'i' }
15912 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
15913 { { OPERAND_mac_qr1_w }, 'o' },
15914 { { OPERAND_mac_qr0_rw }, 'i' },
15915 { { OPERAND_pr }, 'i' }
15918 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
15919 { { STATE_CPENABLE }, 'i' }
15922 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
15923 { { OPERAND_mac_qr1_w }, 'o' },
15924 { { OPERAND_mac_qr0_rw }, 'i' },
15925 { { OPERAND_pr }, 'i' }
15928 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
15929 { { STATE_CPENABLE }, 'i' }
15932 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
15933 { { OPERAND_mac_qr1_w }, 'o' },
15934 { { OPERAND_mac_qr0_rw }, 'i' },
15935 { { OPERAND_pr }, 'i' }
15938 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
15939 { { STATE_CPENABLE }, 'i' }
15942 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
15943 { { OPERAND_mac_qr1_w }, 'o' },
15944 { { OPERAND_mac_qr0_rw }, 'i' },
15945 { { OPERAND_pr }, 'i' }
15948 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
15949 { { STATE_CPENABLE }, 'i' }
15952 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
15953 { { OPERAND_mac_qr1_w }, 'o' },
15954 { { OPERAND_mac_qr0_rw }, 'i' },
15955 { { OPERAND_pr }, 'i' }
15958 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
15959 { { STATE_CPENABLE }, 'i' }
15962 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
15963 { { OPERAND_mac_qr1_w }, 'o' },
15964 { { OPERAND_mac_qr0_rw }, 'i' },
15965 { { OPERAND_pr }, 'i' }
15968 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
15969 { { STATE_CPENABLE }, 'i' }
15972 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
15973 { { OPERAND_mac_qr1_w }, 'o' },
15974 { { OPERAND_mac_qr0_rw }, 'i' },
15975 { { OPERAND_pr }, 'i' }
15978 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
15979 { { STATE_CPENABLE }, 'i' }
15982 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
15983 { { OPERAND_mac_qr1_w }, 'o' },
15984 { { OPERAND_mac_qr0_rw }, 'i' },
15985 { { OPERAND_pr }, 'i' }
15988 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
15989 { { STATE_CPENABLE }, 'i' }
15992 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
15993 { { OPERAND_mac_qr1_w }, 'm' },
15994 { { OPERAND_mac_qr0_rw }, 'i' },
15995 { { OPERAND_pr }, 'i' }
15998 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
15999 { { STATE_CPENABLE }, 'i' }
16002 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
16003 { { OPERAND_mac_qr1_w }, 'm' },
16004 { { OPERAND_mac_qr0_rw }, 'i' },
16005 { { OPERAND_pr }, 'i' }
16008 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
16009 { { STATE_CPENABLE }, 'i' }
16012 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
16013 { { OPERAND_mac_qr1_w }, 'm' },
16014 { { OPERAND_mac_qr0_rw }, 'i' },
16015 { { OPERAND_pr }, 'i' }
16018 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
16019 { { STATE_CPENABLE }, 'i' }
16022 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
16023 { { OPERAND_mac_qr1_w }, 'm' },
16024 { { OPERAND_mac_qr0_rw }, 'i' },
16025 { { OPERAND_pr }, 'i' }
16028 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
16029 { { STATE_CPENABLE }, 'i' }
16032 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
16033 { { OPERAND_mac_qr1_w }, 'm' },
16034 { { OPERAND_mac_qr0_rw }, 'i' },
16035 { { OPERAND_pr }, 'i' }
16038 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
16039 { { STATE_CPENABLE }, 'i' }
16042 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
16043 { { OPERAND_mac_qr1_w }, 'm' },
16044 { { OPERAND_mac_qr0_rw }, 'i' },
16045 { { OPERAND_pr }, 'i' }
16048 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
16049 { { STATE_CPENABLE }, 'i' }
16052 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
16053 { { OPERAND_mac_qr1_w }, 'm' },
16054 { { OPERAND_mac_qr0_rw }, 'i' },
16055 { { OPERAND_pr }, 'i' }
16058 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
16059 { { STATE_CPENABLE }, 'i' }
16062 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
16063 { { OPERAND_mac_qr1_w }, 'm' },
16064 { { OPERAND_mac_qr0_rw }, 'i' },
16065 { { OPERAND_pr }, 'i' }
16068 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
16069 { { STATE_CPENABLE }, 'i' }
16072 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
16073 { { OPERAND_mac_qr1_w }, 'm' },
16074 { { OPERAND_mac_qr0_rw }, 'i' },
16075 { { OPERAND_pr }, 'i' }
16078 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
16079 { { STATE_CPENABLE }, 'i' }
16082 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
16083 { { OPERAND_mac_qr1_w }, 'm' },
16084 { { OPERAND_mac_qr0_rw }, 'i' },
16085 { { OPERAND_pr }, 'i' }
16088 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
16089 { { STATE_CPENABLE }, 'i' }
16092 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
16093 { { OPERAND_mac_qr1_w }, 'm' },
16094 { { OPERAND_mac_qr0_rw }, 'i' },
16095 { { OPERAND_pr }, 'i' }
16098 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
16099 { { STATE_CPENABLE }, 'i' }
16102 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
16103 { { OPERAND_mac_qr1_w }, 'm' },
16104 { { OPERAND_mac_qr0_rw }, 'i' },
16105 { { OPERAND_pr }, 'i' }
16108 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
16109 { { STATE_CPENABLE }, 'i' }
16112 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
16113 { { OPERAND_mac_qr1_w }, 'm' },
16114 { { OPERAND_mac_qr0_rw }, 'i' },
16115 { { OPERAND_pr }, 'i' }
16118 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
16119 { { STATE_CPENABLE }, 'i' }
16122 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
16123 { { OPERAND_mac_qr1_w }, 'm' },
16124 { { OPERAND_mac_qr0_rw }, 'i' },
16125 { { OPERAND_pr }, 'i' }
16128 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
16129 { { STATE_CPENABLE }, 'i' }
16132 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
16133 { { OPERAND_mac_qr1_w }, 'm' },
16134 { { OPERAND_mac_qr0_rw }, 'i' },
16135 { { OPERAND_pr }, 'i' }
16138 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
16139 { { STATE_CPENABLE }, 'i' }
16142 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
16143 { { OPERAND_mac_qr1_w }, 'm' },
16144 { { OPERAND_mac_qr0_rw }, 'i' },
16145 { { OPERAND_pr }, 'i' }
16148 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
16149 { { STATE_CPENABLE }, 'i' }
16152 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
16153 { { OPERAND_mac_qr1_w }, 'o' },
16154 { { OPERAND_mac_qr0_rw }, 'i' },
16155 { { OPERAND_pr }, 'i' },
16156 { { OPERAND_mac_qr0 }, 'i' },
16157 { { OPERAND_pr0 }, 'i' }
16160 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
16161 { { STATE_CPENABLE }, 'i' }
16164 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
16165 { { OPERAND_mac_qr1_w }, 'o' },
16166 { { OPERAND_mac_qr0_rw }, 'i' },
16167 { { OPERAND_pr }, 'i' },
16168 { { OPERAND_mac_qr0 }, 'i' },
16169 { { OPERAND_pr0 }, 'i' }
16172 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
16173 { { STATE_CPENABLE }, 'i' }
16176 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
16177 { { OPERAND_mac_qr1_w }, 'o' },
16178 { { OPERAND_mac_qr0_rw }, 'i' },
16179 { { OPERAND_pr }, 'i' },
16180 { { OPERAND_mac_qr0 }, 'i' },
16181 { { OPERAND_pr0 }, 'i' }
16184 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
16185 { { STATE_CPENABLE }, 'i' }
16188 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
16189 { { OPERAND_mac_qr1_w }, 'o' },
16190 { { OPERAND_mac_qr0_rw }, 'i' },
16191 { { OPERAND_pr }, 'i' },
16192 { { OPERAND_mac_qr0 }, 'i' },
16193 { { OPERAND_pr0 }, 'i' }
16196 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
16197 { { STATE_CPENABLE }, 'i' }
16200 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
16201 { { OPERAND_mac_qr1_w }, 'o' },
16202 { { OPERAND_mac_qr0_rw }, 'i' },
16203 { { OPERAND_pr }, 'i' },
16204 { { OPERAND_mac_qr0 }, 'i' },
16205 { { OPERAND_pr0 }, 'i' }
16208 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
16209 { { STATE_CPENABLE }, 'i' }
16212 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
16213 { { OPERAND_mac_qr1_w }, 'o' },
16214 { { OPERAND_mac_qr0_rw }, 'i' },
16215 { { OPERAND_pr }, 'i' },
16216 { { OPERAND_mac_qr0 }, 'i' },
16217 { { OPERAND_pr0 }, 'i' }
16220 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
16221 { { STATE_CPENABLE }, 'i' }
16224 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
16225 { { OPERAND_mac_qr1_w }, 'o' },
16226 { { OPERAND_mac_qr0_rw }, 'i' },
16227 { { OPERAND_pr }, 'i' },
16228 { { OPERAND_mac_qr0 }, 'i' },
16229 { { OPERAND_pr0 }, 'i' }
16232 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
16233 { { STATE_CPENABLE }, 'i' }
16236 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
16237 { { OPERAND_mac_qr1_w }, 'o' },
16238 { { OPERAND_mac_qr0_rw }, 'i' },
16239 { { OPERAND_pr }, 'i' },
16240 { { OPERAND_mac_qr0 }, 'i' },
16241 { { OPERAND_pr0 }, 'i' }
16244 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
16245 { { STATE_CPENABLE }, 'i' }
16248 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
16249 { { OPERAND_mac_qr1_w }, 'o' },
16250 { { OPERAND_mac_qr0_rw }, 'i' },
16251 { { OPERAND_pr }, 'i' },
16252 { { OPERAND_mac_qr0 }, 'i' },
16253 { { OPERAND_pr0 }, 'i' }
16256 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
16257 { { STATE_CPENABLE }, 'i' }
16260 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
16261 { { OPERAND_mac_qr1_w }, 'o' },
16262 { { OPERAND_mac_qr0_rw }, 'i' },
16263 { { OPERAND_pr }, 'i' },
16264 { { OPERAND_mac_qr0 }, 'i' },
16265 { { OPERAND_pr0 }, 'i' }
16268 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
16269 { { STATE_CPENABLE }, 'i' }
16272 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
16273 { { OPERAND_mac_qr1_w }, 'o' },
16274 { { OPERAND_mac_qr0_rw }, 'i' },
16275 { { OPERAND_pr }, 'i' },
16276 { { OPERAND_mac_qr0 }, 'i' },
16277 { { OPERAND_pr0 }, 'i' }
16280 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
16281 { { STATE_CPENABLE }, 'i' }
16284 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
16285 { { OPERAND_mac_qr1_w }, 'o' },
16286 { { OPERAND_mac_qr0_rw }, 'i' },
16287 { { OPERAND_pr }, 'i' },
16288 { { OPERAND_mac_qr0 }, 'i' },
16289 { { OPERAND_pr0 }, 'i' }
16292 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
16293 { { STATE_CPENABLE }, 'i' }
16296 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
16297 { { OPERAND_mac_qr1_w }, 'o' },
16298 { { OPERAND_mac_qr0_rw }, 'i' },
16299 { { OPERAND_pr }, 'i' },
16300 { { OPERAND_mac_qr0 }, 'i' },
16301 { { OPERAND_pr0 }, 'i' }
16304 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
16305 { { STATE_CPENABLE }, 'i' }
16308 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
16309 { { OPERAND_mac_qr1_w }, 'o' },
16310 { { OPERAND_mac_qr0_rw }, 'i' },
16311 { { OPERAND_pr }, 'i' },
16312 { { OPERAND_mac_qr0 }, 'i' },
16313 { { OPERAND_pr0 }, 'i' }
16316 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
16317 { { STATE_CPENABLE }, 'i' }
16320 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
16321 { { OPERAND_mac_qr1_w }, 'o' },
16322 { { OPERAND_mac_qr0_rw }, 'i' },
16323 { { OPERAND_pr }, 'i' },
16324 { { OPERAND_mac_qr0 }, 'i' },
16325 { { OPERAND_pr0 }, 'i' }
16328 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
16329 { { STATE_CPENABLE }, 'i' }
16332 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
16333 { { OPERAND_mac_qr1_w }, 'o' },
16334 { { OPERAND_mac_qr0_rw }, 'i' },
16335 { { OPERAND_pr }, 'i' },
16336 { { OPERAND_mac_qr0 }, 'i' },
16337 { { OPERAND_pr0 }, 'i' }
16340 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
16341 { { STATE_CPENABLE }, 'i' }
16344 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
16345 { { OPERAND_mac_qr1_w }, 'o' },
16346 { { OPERAND_mac_qr0_rw }, 'i' },
16347 { { OPERAND_pr }, 'i' },
16348 { { OPERAND_mac_qr0 }, 'i' },
16349 { { OPERAND_pr0 }, 'i' }
16352 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
16353 { { STATE_CPENABLE }, 'i' }
16356 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
16357 { { OPERAND_mac_qr1_w }, 'o' },
16358 { { OPERAND_mac_qr0_rw }, 'i' },
16359 { { OPERAND_pr }, 'i' },
16360 { { OPERAND_mac_qr0 }, 'i' },
16361 { { OPERAND_pr0 }, 'i' }
16364 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
16365 { { STATE_CPENABLE }, 'i' }
16368 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
16369 { { OPERAND_mac_qr1_w }, 'o' },
16370 { { OPERAND_mac_qr0_rw }, 'i' },
16371 { { OPERAND_pr }, 'i' },
16372 { { OPERAND_mac_qr0 }, 'i' },
16373 { { OPERAND_pr0 }, 'i' }
16376 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
16377 { { STATE_CPENABLE }, 'i' }
16380 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
16381 { { OPERAND_mac_qr1_w }, 'o' },
16382 { { OPERAND_mac_qr0_rw }, 'i' },
16383 { { OPERAND_pr }, 'i' },
16384 { { OPERAND_mac_qr0 }, 'i' },
16385 { { OPERAND_pr0 }, 'i' }
16388 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
16389 { { STATE_CPENABLE }, 'i' }
16392 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
16393 { { OPERAND_mac_qr1_w }, 'o' },
16394 { { OPERAND_mac_qr0_rw }, 'i' },
16395 { { OPERAND_pr }, 'i' },
16396 { { OPERAND_mac_qr0 }, 'i' },
16397 { { OPERAND_pr0 }, 'i' }
16400 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
16401 { { STATE_CPENABLE }, 'i' }
16404 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
16405 { { OPERAND_mac_qr1_w }, 'o' },
16406 { { OPERAND_mac_qr0_rw }, 'i' },
16407 { { OPERAND_pr }, 'i' },
16408 { { OPERAND_mac_qr0 }, 'i' },
16409 { { OPERAND_pr0 }, 'i' }
16412 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
16413 { { STATE_CPENABLE }, 'i' }
16416 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
16417 { { OPERAND_mac_qr1_w }, 'o' },
16418 { { OPERAND_mac_qr0_rw }, 'i' },
16419 { { OPERAND_pr }, 'i' },
16420 { { OPERAND_mac_qr0 }, 'i' },
16421 { { OPERAND_pr0 }, 'i' }
16424 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
16425 { { STATE_CPENABLE }, 'i' }
16428 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
16429 { { OPERAND_mac_qr1_w }, 'o' },
16430 { { OPERAND_mac_qr0_rw }, 'i' },
16431 { { OPERAND_pr }, 'i' },
16432 { { OPERAND_mac_qr0 }, 'i' },
16433 { { OPERAND_pr0 }, 'i' }
16436 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
16437 { { STATE_CPENABLE }, 'i' }
16440 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
16441 { { OPERAND_mac_qr1_w }, 'o' },
16442 { { OPERAND_mac_qr0_rw }, 'i' },
16443 { { OPERAND_pr }, 'i' },
16444 { { OPERAND_mac_qr0 }, 'i' },
16445 { { OPERAND_pr0 }, 'i' }
16448 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
16449 { { STATE_CPENABLE }, 'i' }
16452 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
16453 { { OPERAND_mac_qr1_w }, 'o' },
16454 { { OPERAND_mac_qr0_rw }, 'i' },
16455 { { OPERAND_pr }, 'i' },
16456 { { OPERAND_mac_qr0 }, 'i' },
16457 { { OPERAND_pr0 }, 'i' }
16460 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
16461 { { STATE_CPENABLE }, 'i' }
16464 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
16465 { { OPERAND_mac_qr1_w }, 'o' },
16466 { { OPERAND_mac_qr0_rw }, 'i' },
16467 { { OPERAND_pr }, 'i' },
16468 { { OPERAND_mac_qr0 }, 'i' },
16469 { { OPERAND_pr0 }, 'i' }
16472 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
16473 { { STATE_CPENABLE }, 'i' }
16476 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
16477 { { OPERAND_mac_qr1_w }, 'o' },
16478 { { OPERAND_mac_qr0_rw }, 'i' },
16479 { { OPERAND_pr }, 'i' },
16480 { { OPERAND_mac_qr0 }, 'i' },
16481 { { OPERAND_pr0 }, 'i' }
16484 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
16485 { { STATE_CPENABLE }, 'i' }
16488 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
16489 { { OPERAND_mac_qr1_w }, 'o' },
16490 { { OPERAND_mac_qr0_rw }, 'i' },
16491 { { OPERAND_pr }, 'i' },
16492 { { OPERAND_mac_qr0 }, 'i' },
16493 { { OPERAND_pr0 }, 'i' }
16496 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
16497 { { STATE_CPENABLE }, 'i' }
16500 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
16501 { { OPERAND_mac_qr1_w }, 'o' },
16502 { { OPERAND_mac_qr0_rw }, 'i' },
16503 { { OPERAND_pr }, 'i' },
16504 { { OPERAND_mac_qr0 }, 'i' },
16505 { { OPERAND_pr0 }, 'i' }
16508 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
16509 { { STATE_CPENABLE }, 'i' }
16512 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
16513 { { OPERAND_mac_qr1_w }, 'o' },
16514 { { OPERAND_mac_qr0_rw }, 'i' },
16515 { { OPERAND_pr }, 'i' },
16516 { { OPERAND_mac_qr0 }, 'i' },
16517 { { OPERAND_pr0 }, 'i' }
16520 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
16521 { { STATE_CPENABLE }, 'i' }
16524 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
16525 { { OPERAND_mac_qr1_w }, 'o' },
16526 { { OPERAND_mac_qr0_rw }, 'i' },
16527 { { OPERAND_pr }, 'i' },
16528 { { OPERAND_mac_qr0 }, 'i' },
16529 { { OPERAND_pr0 }, 'i' }
16532 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
16533 { { STATE_CPENABLE }, 'i' }
16536 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
16537 { { OPERAND_mac_qr1_w }, 'o' },
16538 { { OPERAND_mac_qr0_rw }, 'i' },
16539 { { OPERAND_pr }, 'i' },
16540 { { OPERAND_mac_qr0 }, 'i' },
16541 { { OPERAND_pr0 }, 'i' }
16544 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
16545 { { STATE_CPENABLE }, 'i' }
16548 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
16549 { { OPERAND_mac_qr1_w }, 'o' },
16550 { { OPERAND_mac_qr0_rw }, 'i' },
16551 { { OPERAND_pr }, 'i' },
16552 { { OPERAND_mac_qr0 }, 'i' },
16553 { { OPERAND_pr0 }, 'i' }
16556 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
16557 { { STATE_CPENABLE }, 'i' }
16560 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
16561 { { OPERAND_mac_qr1_w }, 'o' },
16562 { { OPERAND_mac_qr0_rw }, 'i' },
16563 { { OPERAND_pr }, 'i' },
16564 { { OPERAND_mac_qr0 }, 'i' },
16565 { { OPERAND_pr0 }, 'i' }
16568 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
16569 { { STATE_CPENABLE }, 'i' }
16572 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
16573 { { OPERAND_mac_qr1_w }, 'o' },
16574 { { OPERAND_mac_qr0_rw }, 'i' },
16575 { { OPERAND_pr }, 'i' },
16576 { { OPERAND_mac_qr0 }, 'i' },
16577 { { OPERAND_pr0 }, 'i' }
16580 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
16581 { { STATE_CPENABLE }, 'i' }
16584 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
16585 { { OPERAND_mac_qr1_w }, 'o' },
16586 { { OPERAND_mac_qr0_rw }, 'i' },
16587 { { OPERAND_pr }, 'i' },
16588 { { OPERAND_mac_qr0 }, 'i' },
16589 { { OPERAND_pr0 }, 'i' }
16592 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
16593 { { STATE_CPENABLE }, 'i' }
16596 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
16597 { { OPERAND_mac_qr1_w }, 'o' },
16598 { { OPERAND_mac_qr0_rw }, 'i' },
16599 { { OPERAND_pr }, 'i' },
16600 { { OPERAND_mac_qr0 }, 'i' },
16601 { { OPERAND_pr0 }, 'i' }
16604 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
16605 { { STATE_CPENABLE }, 'i' }
16608 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
16609 { { OPERAND_mac_qr1_w }, 'o' },
16610 { { OPERAND_mac_qr0_rw }, 'i' },
16611 { { OPERAND_pr }, 'i' },
16612 { { OPERAND_mac_qr0 }, 'i' },
16613 { { OPERAND_pr0 }, 'i' }
16616 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
16617 { { STATE_CPENABLE }, 'i' }
16620 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
16621 { { OPERAND_mac_qr1_w }, 'o' },
16622 { { OPERAND_mac_qr0_rw }, 'i' },
16623 { { OPERAND_pr }, 'i' },
16624 { { OPERAND_mac_qr0 }, 'i' },
16625 { { OPERAND_pr0 }, 'i' }
16628 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
16629 { { STATE_CPENABLE }, 'i' }
16632 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
16633 { { OPERAND_mac_qr1_w }, 'o' },
16634 { { OPERAND_mac_qr0_rw }, 'i' },
16635 { { OPERAND_pr }, 'i' },
16636 { { OPERAND_mac_qr0 }, 'i' },
16637 { { OPERAND_pr0 }, 'i' }
16640 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
16641 { { STATE_CPENABLE }, 'i' }
16644 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
16645 { { OPERAND_mac_qr1_w }, 'o' },
16646 { { OPERAND_mac_qr0_rw }, 'i' },
16647 { { OPERAND_pr }, 'i' },
16648 { { OPERAND_mac_qr0 }, 'i' },
16649 { { OPERAND_pr0 }, 'i' }
16652 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
16653 { { STATE_CPENABLE }, 'i' }
16656 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
16657 { { OPERAND_mac_qr1_w }, 'o' },
16658 { { OPERAND_mac_qr0_rw }, 'i' },
16659 { { OPERAND_pr }, 'i' },
16660 { { OPERAND_mac_qr0 }, 'i' },
16661 { { OPERAND_pr0 }, 'i' }
16664 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
16665 { { STATE_CPENABLE }, 'i' }
16668 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
16669 { { OPERAND_mac_qr1_w }, 'o' },
16670 { { OPERAND_mac_qr0_rw }, 'i' },
16671 { { OPERAND_pr }, 'i' },
16672 { { OPERAND_mac_qr0 }, 'i' },
16673 { { OPERAND_pr0 }, 'i' }
16676 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
16677 { { STATE_CPENABLE }, 'i' }
16680 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
16681 { { OPERAND_mac_qr1_w }, 'o' },
16682 { { OPERAND_mac_qr0_rw }, 'i' },
16683 { { OPERAND_pr }, 'i' },
16684 { { OPERAND_mac_qr0 }, 'i' },
16685 { { OPERAND_pr0 }, 'i' }
16688 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
16689 { { STATE_CPENABLE }, 'i' }
16692 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
16693 { { OPERAND_mac_qr1_w }, 'o' },
16694 { { OPERAND_mac_qr0_rw }, 'i' },
16695 { { OPERAND_pr }, 'i' },
16696 { { OPERAND_mac_qr0 }, 'i' },
16697 { { OPERAND_pr0 }, 'i' }
16700 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
16701 { { STATE_CPENABLE }, 'i' }
16704 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
16705 { { OPERAND_mac_qr1_w }, 'o' },
16706 { { OPERAND_mac_qr0_rw }, 'i' },
16707 { { OPERAND_pr }, 'i' },
16708 { { OPERAND_mac_qr0 }, 'i' },
16709 { { OPERAND_pr0 }, 'i' }
16712 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
16713 { { STATE_CPENABLE }, 'i' }
16716 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
16717 { { OPERAND_mac_qr1_w }, 'o' },
16718 { { OPERAND_mac_qr0_rw }, 'i' },
16719 { { OPERAND_pr }, 'i' },
16720 { { OPERAND_mac_qr0 }, 'i' },
16721 { { OPERAND_pr0 }, 'i' }
16724 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
16725 { { STATE_CPENABLE }, 'i' }
16728 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
16729 { { OPERAND_mac_qr1_w }, 'o' },
16730 { { OPERAND_pr }, 'i' },
16731 { { OPERAND_pr0 }, 'i' }
16734 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
16735 { { STATE_CPENABLE }, 'i' }
16738 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
16739 { { OPERAND_mac_qr1_w }, 'o' },
16740 { { OPERAND_pr }, 'i' },
16741 { { OPERAND_pr0 }, 'i' }
16744 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
16745 { { STATE_CPENABLE }, 'i' }
16748 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
16749 { { OPERAND_mac_qr1_w }, 'o' },
16750 { { OPERAND_pr }, 'i' },
16751 { { OPERAND_pr0 }, 'i' }
16754 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
16755 { { STATE_CPENABLE }, 'i' }
16758 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
16759 { { OPERAND_mac_qr1_w }, 'o' },
16760 { { OPERAND_pr }, 'i' },
16761 { { OPERAND_pr0 }, 'i' }
16764 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
16765 { { STATE_CPENABLE }, 'i' }
16768 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
16769 { { OPERAND_mac_qr1_w }, 'o' },
16770 { { OPERAND_pr }, 'i' },
16771 { { OPERAND_pr0 }, 'i' }
16774 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
16775 { { STATE_CPENABLE }, 'i' }
16778 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
16779 { { OPERAND_mac_qr1_w }, 'o' },
16780 { { OPERAND_pr }, 'i' },
16781 { { OPERAND_pr0 }, 'i' }
16784 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
16785 { { STATE_CPENABLE }, 'i' }
16788 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
16789 { { OPERAND_mac_qr1_w }, 'o' },
16790 { { OPERAND_pr }, 'i' },
16791 { { OPERAND_pr0 }, 'i' }
16794 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
16795 { { STATE_CPENABLE }, 'i' }
16798 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
16799 { { OPERAND_mac_qr1_w }, 'o' },
16800 { { OPERAND_pr }, 'i' },
16801 { { OPERAND_pr0 }, 'i' }
16804 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
16805 { { STATE_CPENABLE }, 'i' }
16808 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
16809 { { OPERAND_mac_qr1_w }, 'o' },
16810 { { OPERAND_pr }, 'i' },
16811 { { OPERAND_pr0 }, 'i' }
16814 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
16815 { { STATE_CPENABLE }, 'i' }
16818 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
16819 { { OPERAND_mac_qr1_w }, 'o' },
16820 { { OPERAND_pr }, 'i' },
16821 { { OPERAND_pr0 }, 'i' }
16824 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
16825 { { STATE_CPENABLE }, 'i' }
16828 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
16829 { { OPERAND_mac_qr1_w }, 'o' },
16830 { { OPERAND_pr }, 'i' },
16831 { { OPERAND_pr0 }, 'i' }
16834 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
16835 { { STATE_CPENABLE }, 'i' }
16838 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
16839 { { OPERAND_mac_qr1_w }, 'o' },
16840 { { OPERAND_pr }, 'i' },
16841 { { OPERAND_pr0 }, 'i' }
16844 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
16845 { { STATE_CPENABLE }, 'i' }
16848 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
16849 { { OPERAND_mac_qr1_w }, 'o' },
16850 { { OPERAND_pr }, 'i' },
16851 { { OPERAND_pr0 }, 'i' }
16854 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
16855 { { STATE_CPENABLE }, 'i' }
16858 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
16859 { { OPERAND_mac_qr1_w }, 'o' },
16860 { { OPERAND_pr }, 'i' },
16861 { { OPERAND_pr0 }, 'i' }
16864 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
16865 { { STATE_CPENABLE }, 'i' }
16868 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
16869 { { OPERAND_mac_qr1_w }, 'o' },
16870 { { OPERAND_pr }, 'i' },
16871 { { OPERAND_pr0 }, 'i' }
16874 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
16875 { { STATE_CPENABLE }, 'i' }
16878 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
16879 { { OPERAND_mac_qr1_w }, 'o' },
16880 { { OPERAND_pr }, 'i' },
16881 { { OPERAND_pr0 }, 'i' }
16884 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
16885 { { STATE_CPENABLE }, 'i' }
16888 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
16889 { { OPERAND_mac_qr1_w }, 'm' },
16890 { { OPERAND_pr }, 'i' },
16891 { { OPERAND_pr0 }, 'i' }
16894 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
16895 { { STATE_CPENABLE }, 'i' }
16898 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
16899 { { OPERAND_mac_qr1_w }, 'm' },
16900 { { OPERAND_pr }, 'i' },
16901 { { OPERAND_pr0 }, 'i' }
16904 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
16905 { { STATE_CPENABLE }, 'i' }
16908 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
16909 { { OPERAND_mac_qr1_w }, 'm' },
16910 { { OPERAND_pr }, 'i' },
16911 { { OPERAND_pr0 }, 'i' }
16914 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
16915 { { STATE_CPENABLE }, 'i' }
16918 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
16919 { { OPERAND_mac_qr1_w }, 'm' },
16920 { { OPERAND_pr }, 'i' },
16921 { { OPERAND_pr0 }, 'i' }
16924 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
16925 { { STATE_CPENABLE }, 'i' }
16928 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
16929 { { OPERAND_mac_qr1_w }, 'm' },
16930 { { OPERAND_pr }, 'i' },
16931 { { OPERAND_pr0 }, 'i' }
16934 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
16935 { { STATE_CPENABLE }, 'i' }
16938 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
16939 { { OPERAND_mac_qr1_w }, 'm' },
16940 { { OPERAND_pr }, 'i' },
16941 { { OPERAND_pr0 }, 'i' }
16944 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
16945 { { STATE_CPENABLE }, 'i' }
16948 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
16949 { { OPERAND_mac_qr1_w }, 'm' },
16950 { { OPERAND_pr }, 'i' },
16951 { { OPERAND_pr0 }, 'i' }
16954 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
16955 { { STATE_CPENABLE }, 'i' }
16958 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
16959 { { OPERAND_mac_qr1_w }, 'm' },
16960 { { OPERAND_pr }, 'i' },
16961 { { OPERAND_pr0 }, 'i' }
16964 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
16965 { { STATE_CPENABLE }, 'i' }
16968 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
16969 { { OPERAND_mac_qr1_w }, 'm' },
16970 { { OPERAND_pr }, 'i' },
16971 { { OPERAND_pr0 }, 'i' }
16974 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
16975 { { STATE_CPENABLE }, 'i' }
16978 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
16979 { { OPERAND_mac_qr1_w }, 'm' },
16980 { { OPERAND_pr }, 'i' },
16981 { { OPERAND_pr0 }, 'i' }
16984 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
16985 { { STATE_CPENABLE }, 'i' }
16988 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
16989 { { OPERAND_mac_qr1_w }, 'm' },
16990 { { OPERAND_pr }, 'i' },
16991 { { OPERAND_pr0 }, 'i' }
16994 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
16995 { { STATE_CPENABLE }, 'i' }
16998 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
16999 { { OPERAND_mac_qr1_w }, 'm' },
17000 { { OPERAND_pr }, 'i' },
17001 { { OPERAND_pr0 }, 'i' }
17004 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
17005 { { STATE_CPENABLE }, 'i' }
17008 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
17009 { { OPERAND_mac_qr1_w }, 'm' },
17010 { { OPERAND_pr }, 'i' },
17011 { { OPERAND_pr0 }, 'i' }
17014 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
17015 { { STATE_CPENABLE }, 'i' }
17018 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
17019 { { OPERAND_mac_qr1_w }, 'm' },
17020 { { OPERAND_pr }, 'i' },
17021 { { OPERAND_pr0 }, 'i' }
17024 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
17025 { { STATE_CPENABLE }, 'i' }
17028 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
17029 { { OPERAND_mac_qr1_w }, 'm' },
17030 { { OPERAND_pr }, 'i' },
17031 { { OPERAND_pr0 }, 'i' }
17034 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
17035 { { STATE_CPENABLE }, 'i' }
17038 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
17039 { { OPERAND_mac_qr1_w }, 'm' },
17040 { { OPERAND_pr }, 'i' },
17041 { { OPERAND_pr0 }, 'i' }
17044 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
17045 { { STATE_CPENABLE }, 'i' }
17048 static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
17049 { { OPERAND_arr }, 'o' },
17050 { { OPERAND_ars }, 'i' }
17053 static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
17054 { { OPERAND_br }, 'o' },
17055 { { OPERAND_art }, 'o' },
17056 { { OPERAND_ars }, 'i' }
17059 static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
17060 { { STATE_AE_TABLESIZE }, 'm' },
17061 { { STATE_AE_BITSUSED }, 'o' },
17062 { { STATE_AE_NEXTOFFSET }, 'm' },
17063 { { STATE_AE_SEARCHDONE }, 'o' },
17064 { { STATE_CPENABLE }, 'i' }
17067 static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
17068 { { OPERAND_br }, 'o' },
17069 { { OPERAND_art }, 'o' },
17070 { { OPERAND_ars }, 'i' }
17073 static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
17074 { { STATE_AE_TABLESIZE }, 'm' },
17075 { { STATE_AE_BITSUSED }, 'o' },
17076 { { STATE_AE_NEXTOFFSET }, 'm' },
17077 { { STATE_AE_SEARCHDONE }, 'o' },
17078 { { STATE_CPENABLE }, 'i' }
17081 static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
17082 { { OPERAND_ars }, 'm' }
17085 static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
17086 { { STATE_AE_NEXTOFFSET }, 'm' },
17087 { { STATE_AE_TABLESIZE }, 'm' },
17088 { { STATE_AE_BITPTR }, 'm' },
17089 { { STATE_AE_BITHEAD }, 'm' },
17090 { { STATE_AE_FIRST_TS }, 'i' },
17091 { { STATE_AE_BITSUSED }, 'i' },
17092 { { STATE_AE_SEARCHDONE }, 'i' },
17093 { { STATE_CPENABLE }, 'i' }
17096 static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
17097 { { OPERAND_art }, 'i' }
17100 static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
17101 { { STATE_AE_BITPTR }, 'i' },
17102 { { STATE_AE_BITHEAD }, 'i' },
17103 { { STATE_AE_FIRST_TS }, 'o' },
17104 { { STATE_AE_NEXTOFFSET }, 'o' },
17105 { { STATE_AE_TABLESIZE }, 'o' },
17106 { { STATE_CPENABLE }, 'i' }
17109 static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
17110 { { OPERAND_arr }, 'o' },
17111 { { OPERAND_art }, 'i' }
17114 static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
17115 { { STATE_AE_BITPTR }, 'i' },
17116 { { STATE_AE_BITHEAD }, 'i' },
17117 { { STATE_CPENABLE }, 'i' }
17120 static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
17121 { { OPERAND_arr }, 'o' },
17122 { { OPERAND_ae_ohba2 }, 'i' }
17125 static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
17126 { { STATE_AE_BITPTR }, 'i' },
17127 { { STATE_AE_BITHEAD }, 'i' },
17128 { { STATE_CPENABLE }, 'i' }
17131 static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
17132 { { OPERAND_arr }, 'o' },
17133 { { OPERAND_ars }, 'i' },
17134 { { OPERAND_art }, 'i' }
17137 static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
17138 { { STATE_AE_BITPTR }, 'i' },
17139 { { STATE_AE_BITHEAD }, 'i' },
17140 { { STATE_CPENABLE }, 'i' }
17143 static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
17144 { { OPERAND_arr }, 'o' },
17145 { { OPERAND_ars }, 'i' },
17146 { { OPERAND_ae_ohba2 }, 'i' }
17149 static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
17150 { { STATE_AE_BITPTR }, 'i' },
17151 { { STATE_AE_BITHEAD }, 'i' },
17152 { { STATE_CPENABLE }, 'i' }
17155 static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
17156 { { OPERAND_ars }, 'm' },
17157 { { OPERAND_art }, 'i' }
17160 static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
17161 { { STATE_AE_BITPTR }, 'm' },
17162 { { STATE_AE_BITHEAD }, 'm' },
17163 { { STATE_CPENABLE }, 'i' }
17166 static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
17167 { { OPERAND_ars }, 'm' },
17168 { { OPERAND_ae_ohba }, 'i' }
17171 static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
17172 { { STATE_AE_BITPTR }, 'm' },
17173 { { STATE_AE_BITHEAD }, 'm' },
17174 { { STATE_CPENABLE }, 'i' }
17177 static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
17178 { { OPERAND_br }, 'o' },
17179 { { OPERAND_art }, 'm' },
17180 { { OPERAND_ars }, 'i' }
17183 static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
17184 { { STATE_AE_BITSUSED }, 'o' },
17185 { { STATE_AE_NEXTOFFSET }, 'o' },
17186 { { STATE_CPENABLE }, 'i' }
17189 static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
17190 { { OPERAND_br }, 'o' },
17191 { { OPERAND_art }, 'm' },
17192 { { OPERAND_ars }, 'i' }
17195 static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
17196 { { STATE_AE_BITSUSED }, 'o' },
17197 { { STATE_AE_NEXTOFFSET }, 'o' },
17198 { { STATE_CPENABLE }, 'i' }
17201 static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
17202 { { OPERAND_ars }, 'm' },
17203 { { OPERAND_art }, 'i' }
17206 static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
17207 { { STATE_AE_BITSUSED }, 'i' },
17208 { { STATE_AE_BITPTR }, 'm' },
17209 { { STATE_AE_BITHEAD }, 'm' },
17210 { { STATE_CPENABLE }, 'i' }
17213 static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
17214 { { OPERAND_ars }, 'm' },
17215 { { OPERAND_art }, 'i' },
17216 { { OPERAND_ae_ohba }, 'i' }
17219 static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
17220 { { STATE_AE_BITPTR }, 'm' },
17221 { { STATE_AE_BITHEAD }, 'm' },
17222 { { STATE_CPENABLE }, 'i' }
17225 static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
17226 { { OPERAND_ars }, 'm' }
17229 static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
17230 { { STATE_AE_BITPTR }, 'm' },
17231 { { STATE_AE_BITHEAD }, 'm' },
17232 { { STATE_AE_BITSUSED }, 'i' },
17233 { { STATE_AE_NEXTOFFSET }, 'i' },
17234 { { STATE_CPENABLE }, 'i' }
17237 static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
17238 { { OPERAND_ars }, 'm' }
17241 static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
17242 { { STATE_AE_BITPTR }, 'i' },
17243 { { STATE_AE_BITHEAD }, 'm' },
17244 { { STATE_CPENABLE }, 'i' }
17247 static xtensa_iclass_internal iclasses[] = {
17248 { 0, 0 /* xt_iclass_excw */,
17250 { 0, 0 /* xt_iclass_rfe */,
17251 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
17252 { 0, 0 /* xt_iclass_rfde */,
17253 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
17254 { 0, 0 /* xt_iclass_syscall */,
17256 { 2, Iclass_xt_iclass_call12_args,
17257 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
17258 { 2, Iclass_xt_iclass_call8_args,
17259 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
17260 { 2, Iclass_xt_iclass_call4_args,
17261 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
17262 { 2, Iclass_xt_iclass_callx12_args,
17263 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
17264 { 2, Iclass_xt_iclass_callx8_args,
17265 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
17266 { 2, Iclass_xt_iclass_callx4_args,
17267 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
17268 { 3, Iclass_xt_iclass_entry_args,
17269 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
17270 { 2, Iclass_xt_iclass_movsp_args,
17271 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
17272 { 1, Iclass_xt_iclass_rotw_args,
17273 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
17274 { 1, Iclass_xt_iclass_retw_args,
17275 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
17276 { 0, 0 /* xt_iclass_rfwou */,
17277 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
17278 { 3, Iclass_xt_iclass_l32e_args,
17279 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
17280 { 3, Iclass_xt_iclass_s32e_args,
17281 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
17282 { 1, Iclass_xt_iclass_rsr_windowbase_args,
17283 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
17284 { 1, Iclass_xt_iclass_wsr_windowbase_args,
17285 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
17286 { 1, Iclass_xt_iclass_xsr_windowbase_args,
17287 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
17288 { 1, Iclass_xt_iclass_rsr_windowstart_args,
17289 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
17290 { 1, Iclass_xt_iclass_wsr_windowstart_args,
17291 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
17292 { 1, Iclass_xt_iclass_xsr_windowstart_args,
17293 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
17294 { 3, Iclass_xt_iclass_add_n_args,
17296 { 3, Iclass_xt_iclass_addi_n_args,
17298 { 2, Iclass_xt_iclass_bz6_args,
17300 { 0, 0 /* xt_iclass_ill_n */,
17302 { 3, Iclass_xt_iclass_loadi4_args,
17304 { 2, Iclass_xt_iclass_mov_n_args,
17306 { 2, Iclass_xt_iclass_movi_n_args,
17308 { 0, 0 /* xt_iclass_nopn */,
17310 { 1, Iclass_xt_iclass_retn_args,
17312 { 3, Iclass_xt_iclass_storei4_args,
17314 { 1, Iclass_rur_threadptr_args,
17315 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
17316 { 1, Iclass_wur_threadptr_args,
17317 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
17318 { 3, Iclass_xt_iclass_addi_args,
17320 { 3, Iclass_xt_iclass_addmi_args,
17322 { 3, Iclass_xt_iclass_addsub_args,
17324 { 3, Iclass_xt_iclass_bit_args,
17326 { 3, Iclass_xt_iclass_bsi8_args,
17328 { 3, Iclass_xt_iclass_bsi8b_args,
17330 { 3, Iclass_xt_iclass_bsi8u_args,
17332 { 3, Iclass_xt_iclass_bst8_args,
17334 { 2, Iclass_xt_iclass_bsz12_args,
17336 { 2, Iclass_xt_iclass_call0_args,
17338 { 2, Iclass_xt_iclass_callx0_args,
17340 { 4, Iclass_xt_iclass_exti_args,
17342 { 0, 0 /* xt_iclass_ill */,
17344 { 1, Iclass_xt_iclass_jump_args,
17346 { 1, Iclass_xt_iclass_jumpx_args,
17348 { 3, Iclass_xt_iclass_l16ui_args,
17350 { 3, Iclass_xt_iclass_l16si_args,
17352 { 3, Iclass_xt_iclass_l32i_args,
17354 { 2, Iclass_xt_iclass_l32r_args,
17355 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
17356 { 3, Iclass_xt_iclass_l8i_args,
17358 { 2, Iclass_xt_iclass_loop_args,
17359 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
17360 { 2, Iclass_xt_iclass_loopz_args,
17361 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
17362 { 2, Iclass_xt_iclass_movi_args,
17364 { 3, Iclass_xt_iclass_movz_args,
17366 { 2, Iclass_xt_iclass_neg_args,
17368 { 0, 0 /* xt_iclass_nop */,
17370 { 1, Iclass_xt_iclass_return_args,
17372 { 0, 0 /* xt_iclass_simcall */,
17374 { 3, Iclass_xt_iclass_s16i_args,
17376 { 3, Iclass_xt_iclass_s32i_args,
17378 { 3, Iclass_xt_iclass_s8i_args,
17380 { 1, Iclass_xt_iclass_sar_args,
17381 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
17382 { 1, Iclass_xt_iclass_sari_args,
17383 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
17384 { 2, Iclass_xt_iclass_shifts_args,
17385 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
17386 { 3, Iclass_xt_iclass_shiftst_args,
17387 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
17388 { 2, Iclass_xt_iclass_shiftt_args,
17389 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
17390 { 3, Iclass_xt_iclass_slli_args,
17392 { 3, Iclass_xt_iclass_srai_args,
17394 { 3, Iclass_xt_iclass_srli_args,
17396 { 0, 0 /* xt_iclass_memw */,
17398 { 0, 0 /* xt_iclass_extw */,
17400 { 0, 0 /* xt_iclass_isync */,
17402 { 0, 0 /* xt_iclass_sync */,
17403 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
17404 { 2, Iclass_xt_iclass_rsil_args,
17405 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
17406 { 1, Iclass_xt_iclass_rsr_lend_args,
17407 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
17408 { 1, Iclass_xt_iclass_wsr_lend_args,
17409 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
17410 { 1, Iclass_xt_iclass_xsr_lend_args,
17411 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
17412 { 1, Iclass_xt_iclass_rsr_lcount_args,
17413 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
17414 { 1, Iclass_xt_iclass_wsr_lcount_args,
17415 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
17416 { 1, Iclass_xt_iclass_xsr_lcount_args,
17417 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
17418 { 1, Iclass_xt_iclass_rsr_lbeg_args,
17419 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
17420 { 1, Iclass_xt_iclass_wsr_lbeg_args,
17421 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
17422 { 1, Iclass_xt_iclass_xsr_lbeg_args,
17423 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
17424 { 1, Iclass_xt_iclass_rsr_sar_args,
17425 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
17426 { 1, Iclass_xt_iclass_wsr_sar_args,
17427 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
17428 { 1, Iclass_xt_iclass_xsr_sar_args,
17429 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
17430 { 1, Iclass_xt_iclass_rsr_litbase_args,
17431 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
17432 { 1, Iclass_xt_iclass_wsr_litbase_args,
17433 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
17434 { 1, Iclass_xt_iclass_xsr_litbase_args,
17435 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
17436 { 1, Iclass_xt_iclass_rsr_configid0_args,
17437 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
17438 { 1, Iclass_xt_iclass_wsr_configid0_args,
17439 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
17440 { 1, Iclass_xt_iclass_rsr_configid1_args,
17441 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
17442 { 1, Iclass_xt_iclass_rsr_ps_args,
17443 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
17444 { 1, Iclass_xt_iclass_wsr_ps_args,
17445 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
17446 { 1, Iclass_xt_iclass_xsr_ps_args,
17447 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
17448 { 1, Iclass_xt_iclass_rsr_epc1_args,
17449 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
17450 { 1, Iclass_xt_iclass_wsr_epc1_args,
17451 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
17452 { 1, Iclass_xt_iclass_xsr_epc1_args,
17453 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
17454 { 1, Iclass_xt_iclass_rsr_excsave1_args,
17455 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
17456 { 1, Iclass_xt_iclass_wsr_excsave1_args,
17457 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
17458 { 1, Iclass_xt_iclass_xsr_excsave1_args,
17459 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
17460 { 1, Iclass_xt_iclass_rsr_epc2_args,
17461 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
17462 { 1, Iclass_xt_iclass_wsr_epc2_args,
17463 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
17464 { 1, Iclass_xt_iclass_xsr_epc2_args,
17465 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
17466 { 1, Iclass_xt_iclass_rsr_excsave2_args,
17467 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
17468 { 1, Iclass_xt_iclass_wsr_excsave2_args,
17469 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
17470 { 1, Iclass_xt_iclass_xsr_excsave2_args,
17471 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
17472 { 1, Iclass_xt_iclass_rsr_eps2_args,
17473 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
17474 { 1, Iclass_xt_iclass_wsr_eps2_args,
17475 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
17476 { 1, Iclass_xt_iclass_xsr_eps2_args,
17477 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
17478 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
17479 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
17480 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
17481 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
17482 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
17483 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
17484 { 1, Iclass_xt_iclass_rsr_depc_args,
17485 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
17486 { 1, Iclass_xt_iclass_wsr_depc_args,
17487 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
17488 { 1, Iclass_xt_iclass_xsr_depc_args,
17489 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
17490 { 1, Iclass_xt_iclass_rsr_exccause_args,
17491 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
17492 { 1, Iclass_xt_iclass_wsr_exccause_args,
17493 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
17494 { 1, Iclass_xt_iclass_xsr_exccause_args,
17495 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
17496 { 1, Iclass_xt_iclass_rsr_misc0_args,
17497 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
17498 { 1, Iclass_xt_iclass_wsr_misc0_args,
17499 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
17500 { 1, Iclass_xt_iclass_xsr_misc0_args,
17501 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
17502 { 1, Iclass_xt_iclass_rsr_misc1_args,
17503 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
17504 { 1, Iclass_xt_iclass_wsr_misc1_args,
17505 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
17506 { 1, Iclass_xt_iclass_xsr_misc1_args,
17507 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
17508 { 1, Iclass_xt_iclass_rsr_prid_args,
17509 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
17510 { 1, Iclass_xt_iclass_rsr_vecbase_args,
17511 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
17512 { 1, Iclass_xt_iclass_wsr_vecbase_args,
17513 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
17514 { 1, Iclass_xt_iclass_xsr_vecbase_args,
17515 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
17516 { 3, Iclass_xt_mul16_args,
17518 { 3, Iclass_xt_mul32_args,
17520 { 1, Iclass_xt_iclass_rfi_args,
17521 11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
17522 { 1, Iclass_xt_iclass_wait_args,
17523 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
17524 { 1, Iclass_xt_iclass_rsr_interrupt_args,
17525 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
17526 { 1, Iclass_xt_iclass_wsr_intset_args,
17527 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
17528 { 1, Iclass_xt_iclass_wsr_intclear_args,
17529 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
17530 { 1, Iclass_xt_iclass_rsr_intenable_args,
17531 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
17532 { 1, Iclass_xt_iclass_wsr_intenable_args,
17533 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
17534 { 1, Iclass_xt_iclass_xsr_intenable_args,
17535 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
17536 { 2, Iclass_xt_iclass_break_args,
17537 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
17538 { 1, Iclass_xt_iclass_break_n_args,
17539 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
17540 { 1, Iclass_xt_iclass_rsr_debugcause_args,
17541 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
17542 { 1, Iclass_xt_iclass_wsr_debugcause_args,
17543 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
17544 { 1, Iclass_xt_iclass_xsr_debugcause_args,
17545 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
17546 { 1, Iclass_xt_iclass_rsr_icount_args,
17547 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
17548 { 1, Iclass_xt_iclass_wsr_icount_args,
17549 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
17550 { 1, Iclass_xt_iclass_xsr_icount_args,
17551 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
17552 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
17553 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
17554 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
17555 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
17556 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
17557 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
17558 { 1, Iclass_xt_iclass_rsr_ddr_args,
17559 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
17560 { 1, Iclass_xt_iclass_wsr_ddr_args,
17561 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
17562 { 1, Iclass_xt_iclass_xsr_ddr_args,
17563 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
17564 { 1, Iclass_xt_iclass_rfdo_args,
17565 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
17566 { 0, 0 /* xt_iclass_rfdd */,
17567 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
17568 { 3, Iclass_xt_iclass_bbool1_args,
17570 { 2, Iclass_xt_iclass_bbool4_args,
17572 { 2, Iclass_xt_iclass_bbool8_args,
17574 { 2, Iclass_xt_iclass_bbranch_args,
17576 { 3, Iclass_xt_iclass_bmove_args,
17578 { 2, Iclass_xt_iclass_RSR_BR_args,
17580 { 2, Iclass_xt_iclass_WSR_BR_args,
17582 { 2, Iclass_xt_iclass_XSR_BR_args,
17584 { 1, Iclass_xt_iclass_rsr_ccount_args,
17585 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
17586 { 1, Iclass_xt_iclass_wsr_ccount_args,
17587 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
17588 { 1, Iclass_xt_iclass_xsr_ccount_args,
17589 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
17590 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
17591 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
17592 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
17593 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
17594 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
17595 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
17596 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
17597 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
17598 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
17599 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
17600 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
17601 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
17602 { 2, Iclass_xt_iclass_icache_args,
17604 { 2, Iclass_xt_iclass_icache_inv_args,
17605 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
17606 { 2, Iclass_xt_iclass_licx_args,
17607 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
17608 { 2, Iclass_xt_iclass_sicx_args,
17609 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
17610 { 2, Iclass_xt_iclass_dcache_args,
17612 { 2, Iclass_xt_iclass_dcache_ind_args,
17613 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
17614 { 2, Iclass_xt_iclass_dcache_inv_args,
17615 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
17616 { 2, Iclass_xt_iclass_dpf_args,
17618 { 2, Iclass_xt_iclass_sdct_args,
17619 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
17620 { 2, Iclass_xt_iclass_ldct_args,
17621 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
17622 { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
17623 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
17624 { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
17625 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
17626 { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
17627 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
17628 { 1, Iclass_xt_iclass_rsr_rasid_args,
17629 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
17630 { 1, Iclass_xt_iclass_wsr_rasid_args,
17631 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
17632 { 1, Iclass_xt_iclass_xsr_rasid_args,
17633 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
17634 { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
17635 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
17636 { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
17637 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
17638 { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
17639 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
17640 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
17641 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
17642 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
17643 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
17644 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
17645 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
17646 { 1, Iclass_xt_iclass_idtlb_args,
17647 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
17648 { 2, Iclass_xt_iclass_rdtlb_args,
17649 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
17650 { 2, Iclass_xt_iclass_wdtlb_args,
17651 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
17652 { 1, Iclass_xt_iclass_iitlb_args,
17653 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
17654 { 2, Iclass_xt_iclass_ritlb_args,
17655 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
17656 { 2, Iclass_xt_iclass_witlb_args,
17657 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
17658 { 0, 0 /* xt_iclass_ldpte */,
17659 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
17660 { 0, 0 /* xt_iclass_hwwitlba */,
17661 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
17662 { 0, 0 /* xt_iclass_hwwdtlba */,
17663 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
17664 { 1, Iclass_xt_iclass_rsr_cpenable_args,
17665 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
17666 { 1, Iclass_xt_iclass_wsr_cpenable_args,
17667 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
17668 { 1, Iclass_xt_iclass_xsr_cpenable_args,
17669 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
17670 { 3, Iclass_xt_iclass_clamp_args,
17672 { 3, Iclass_xt_iclass_minmax_args,
17674 { 2, Iclass_xt_iclass_nsa_args,
17676 { 3, Iclass_xt_iclass_sx_args,
17678 { 3, Iclass_xt_iclass_l32ai_args,
17680 { 3, Iclass_xt_iclass_s32ri_args,
17682 { 3, Iclass_xt_iclass_s32c1i_args,
17683 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
17684 { 1, Iclass_xt_iclass_rsr_scompare1_args,
17685 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
17686 { 1, Iclass_xt_iclass_wsr_scompare1_args,
17687 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
17688 { 1, Iclass_xt_iclass_xsr_scompare1_args,
17689 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
17690 { 1, Iclass_xt_iclass_rsr_atomctl_args,
17691 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
17692 { 1, Iclass_xt_iclass_wsr_atomctl_args,
17693 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
17694 { 1, Iclass_xt_iclass_xsr_atomctl_args,
17695 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
17696 { 2, Iclass_xt_iclass_rer_args,
17697 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
17698 { 2, Iclass_xt_iclass_wer_args,
17699 7, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
17700 { 1, Iclass_rur_ae_ovf_sar_args,
17701 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 },
17702 { 1, Iclass_wur_ae_ovf_sar_args,
17703 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 },
17704 { 1, Iclass_rur_ae_bithead_args,
17705 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 },
17706 { 1, Iclass_wur_ae_bithead_args,
17707 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 },
17708 { 1, Iclass_rur_ae_ts_fts_bu_bp_args,
17709 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
17710 { 1, Iclass_wur_ae_ts_fts_bu_bp_args,
17711 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
17712 { 1, Iclass_rur_ae_sd_no_args,
17713 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 },
17714 { 1, Iclass_wur_ae_sd_no_args,
17715 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 },
17716 { 1, Iclass_ae_iclass_rur_ae_overflow_args,
17717 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 },
17718 { 1, Iclass_ae_iclass_wur_ae_overflow_args,
17719 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 },
17720 { 1, Iclass_ae_iclass_rur_ae_sar_args,
17721 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 },
17722 { 1, Iclass_ae_iclass_wur_ae_sar_args,
17723 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 },
17724 { 1, Iclass_ae_iclass_rur_ae_bitptr_args,
17725 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 },
17726 { 1, Iclass_ae_iclass_wur_ae_bitptr_args,
17727 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 },
17728 { 1, Iclass_ae_iclass_rur_ae_bitsused_args,
17729 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 },
17730 { 1, Iclass_ae_iclass_wur_ae_bitsused_args,
17731 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 },
17732 { 1, Iclass_ae_iclass_rur_ae_tablesize_args,
17733 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 },
17734 { 1, Iclass_ae_iclass_wur_ae_tablesize_args,
17735 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 },
17736 { 1, Iclass_ae_iclass_rur_ae_first_ts_args,
17737 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 },
17738 { 1, Iclass_ae_iclass_wur_ae_first_ts_args,
17739 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 },
17740 { 1, Iclass_ae_iclass_rur_ae_nextoffset_args,
17741 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 },
17742 { 1, Iclass_ae_iclass_wur_ae_nextoffset_args,
17743 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 },
17744 { 1, Iclass_ae_iclass_rur_ae_searchdone_args,
17745 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 },
17746 { 1, Iclass_ae_iclass_wur_ae_searchdone_args,
17747 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 },
17748 { 3, Iclass_ae_iclass_lp16f_i_args,
17749 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 },
17750 { 3, Iclass_ae_iclass_lp16f_iu_args,
17751 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 },
17752 { 3, Iclass_ae_iclass_lp16f_x_args,
17753 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 },
17754 { 3, Iclass_ae_iclass_lp16f_xu_args,
17755 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 },
17756 { 3, Iclass_ae_iclass_lp24_i_args,
17757 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 },
17758 { 3, Iclass_ae_iclass_lp24_iu_args,
17759 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 },
17760 { 3, Iclass_ae_iclass_lp24_x_args,
17761 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 },
17762 { 3, Iclass_ae_iclass_lp24_xu_args,
17763 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 },
17764 { 3, Iclass_ae_iclass_lp24f_i_args,
17765 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 },
17766 { 3, Iclass_ae_iclass_lp24f_iu_args,
17767 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 },
17768 { 3, Iclass_ae_iclass_lp24f_x_args,
17769 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 },
17770 { 3, Iclass_ae_iclass_lp24f_xu_args,
17771 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 },
17772 { 3, Iclass_ae_iclass_lp16x2f_i_args,
17773 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 },
17774 { 3, Iclass_ae_iclass_lp16x2f_iu_args,
17775 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 },
17776 { 3, Iclass_ae_iclass_lp16x2f_x_args,
17777 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 },
17778 { 3, Iclass_ae_iclass_lp16x2f_xu_args,
17779 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 },
17780 { 3, Iclass_ae_iclass_lp24x2f_i_args,
17781 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 },
17782 { 3, Iclass_ae_iclass_lp24x2f_iu_args,
17783 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 },
17784 { 3, Iclass_ae_iclass_lp24x2f_x_args,
17785 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 },
17786 { 3, Iclass_ae_iclass_lp24x2f_xu_args,
17787 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 },
17788 { 3, Iclass_ae_iclass_lp24x2_i_args,
17789 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 },
17790 { 3, Iclass_ae_iclass_lp24x2_iu_args,
17791 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 },
17792 { 3, Iclass_ae_iclass_lp24x2_x_args,
17793 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 },
17794 { 3, Iclass_ae_iclass_lp24x2_xu_args,
17795 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 },
17796 { 3, Iclass_ae_iclass_sp16x2f_i_args,
17797 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 },
17798 { 3, Iclass_ae_iclass_sp16x2f_iu_args,
17799 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 },
17800 { 3, Iclass_ae_iclass_sp16x2f_x_args,
17801 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 },
17802 { 3, Iclass_ae_iclass_sp16x2f_xu_args,
17803 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 },
17804 { 3, Iclass_ae_iclass_sp24x2s_i_args,
17805 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 },
17806 { 3, Iclass_ae_iclass_sp24x2s_iu_args,
17807 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 },
17808 { 3, Iclass_ae_iclass_sp24x2s_x_args,
17809 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 },
17810 { 3, Iclass_ae_iclass_sp24x2s_xu_args,
17811 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 },
17812 { 3, Iclass_ae_iclass_sp24x2f_i_args,
17813 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 },
17814 { 3, Iclass_ae_iclass_sp24x2f_iu_args,
17815 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 },
17816 { 3, Iclass_ae_iclass_sp24x2f_x_args,
17817 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 },
17818 { 3, Iclass_ae_iclass_sp24x2f_xu_args,
17819 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 },
17820 { 3, Iclass_ae_iclass_sp16f_l_i_args,
17821 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 },
17822 { 3, Iclass_ae_iclass_sp16f_l_iu_args,
17823 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 },
17824 { 3, Iclass_ae_iclass_sp16f_l_x_args,
17825 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 },
17826 { 3, Iclass_ae_iclass_sp16f_l_xu_args,
17827 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 },
17828 { 3, Iclass_ae_iclass_sp24s_l_i_args,
17829 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 },
17830 { 3, Iclass_ae_iclass_sp24s_l_iu_args,
17831 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 },
17832 { 3, Iclass_ae_iclass_sp24s_l_x_args,
17833 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 },
17834 { 3, Iclass_ae_iclass_sp24s_l_xu_args,
17835 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 },
17836 { 3, Iclass_ae_iclass_sp24f_l_i_args,
17837 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 },
17838 { 3, Iclass_ae_iclass_sp24f_l_iu_args,
17839 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 },
17840 { 3, Iclass_ae_iclass_sp24f_l_x_args,
17841 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 },
17842 { 3, Iclass_ae_iclass_sp24f_l_xu_args,
17843 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 },
17844 { 3, Iclass_ae_iclass_lq56_i_args,
17845 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 },
17846 { 3, Iclass_ae_iclass_lq56_iu_args,
17847 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 },
17848 { 3, Iclass_ae_iclass_lq56_x_args,
17849 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 },
17850 { 3, Iclass_ae_iclass_lq56_xu_args,
17851 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 },
17852 { 3, Iclass_ae_iclass_lq32f_i_args,
17853 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 },
17854 { 3, Iclass_ae_iclass_lq32f_iu_args,
17855 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 },
17856 { 3, Iclass_ae_iclass_lq32f_x_args,
17857 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 },
17858 { 3, Iclass_ae_iclass_lq32f_xu_args,
17859 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 },
17860 { 3, Iclass_ae_iclass_sq56s_i_args,
17861 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 },
17862 { 3, Iclass_ae_iclass_sq56s_iu_args,
17863 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 },
17864 { 3, Iclass_ae_iclass_sq56s_x_args,
17865 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 },
17866 { 3, Iclass_ae_iclass_sq56s_xu_args,
17867 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 },
17868 { 3, Iclass_ae_iclass_sq32f_i_args,
17869 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 },
17870 { 3, Iclass_ae_iclass_sq32f_iu_args,
17871 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 },
17872 { 3, Iclass_ae_iclass_sq32f_x_args,
17873 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 },
17874 { 3, Iclass_ae_iclass_sq32f_xu_args,
17875 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 },
17876 { 1, Iclass_ae_iclass_zerop48_args,
17877 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 },
17878 { 2, Iclass_ae_iclass_movp48_args,
17879 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 },
17880 { 3, Iclass_ae_iclass_selp24_ll_args,
17881 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 },
17882 { 3, Iclass_ae_iclass_selp24_lh_args,
17883 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 },
17884 { 3, Iclass_ae_iclass_selp24_hl_args,
17885 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 },
17886 { 3, Iclass_ae_iclass_selp24_hh_args,
17887 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 },
17888 { 3, Iclass_ae_iclass_movtp24x2_args,
17889 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 },
17890 { 3, Iclass_ae_iclass_movfp24x2_args,
17891 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 },
17892 { 3, Iclass_ae_iclass_movtp48_args,
17893 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 },
17894 { 3, Iclass_ae_iclass_movfp48_args,
17895 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 },
17896 { 3, Iclass_ae_iclass_movpa24x2_args,
17897 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 },
17898 { 3, Iclass_ae_iclass_truncp24a32x2_args,
17899 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 },
17900 { 2, Iclass_ae_iclass_cvta32p24_l_args,
17901 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 },
17902 { 2, Iclass_ae_iclass_cvta32p24_h_args,
17903 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 },
17904 { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args,
17905 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 },
17906 { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args,
17907 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 },
17908 { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args,
17909 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 },
17910 { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args,
17911 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 },
17912 { 3, Iclass_ae_iclass_truncp24q48x2_args,
17913 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 },
17914 { 2, Iclass_ae_iclass_truncp16_args,
17915 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 },
17916 { 2, Iclass_ae_iclass_roundsp24q48sym_args,
17917 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 },
17918 { 2, Iclass_ae_iclass_roundsp24q48asym_args,
17919 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 },
17920 { 2, Iclass_ae_iclass_roundsp16q48sym_args,
17921 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 },
17922 { 2, Iclass_ae_iclass_roundsp16q48asym_args,
17923 2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 },
17924 { 2, Iclass_ae_iclass_roundsp16sym_args,
17925 2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 },
17926 { 2, Iclass_ae_iclass_roundsp16asym_args,
17927 2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 },
17928 { 1, Iclass_ae_iclass_zeroq56_args,
17929 1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 },
17930 { 2, Iclass_ae_iclass_movq56_args,
17931 1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 },
17932 { 3, Iclass_ae_iclass_movtq56_args,
17933 1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 },
17934 { 3, Iclass_ae_iclass_movfq56_args,
17935 1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 },
17936 { 2, Iclass_ae_iclass_cvtq48a32s_args,
17937 1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 },
17938 { 2, Iclass_ae_iclass_cvtq48p24s_l_args,
17939 1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 },
17940 { 2, Iclass_ae_iclass_cvtq48p24s_h_args,
17941 1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 },
17942 { 2, Iclass_ae_iclass_satq48s_args,
17943 2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 },
17944 { 2, Iclass_ae_iclass_truncq32_args,
17945 1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 },
17946 { 2, Iclass_ae_iclass_roundsq32sym_args,
17947 2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 },
17948 { 2, Iclass_ae_iclass_roundsq32asym_args,
17949 2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 },
17950 { 2, Iclass_ae_iclass_trunca32q48_args,
17951 1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 },
17952 { 2, Iclass_ae_iclass_movap24s_l_args,
17953 1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 },
17954 { 2, Iclass_ae_iclass_movap24s_h_args,
17955 1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 },
17956 { 2, Iclass_ae_iclass_trunca16p24s_l_args,
17957 1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 },
17958 { 2, Iclass_ae_iclass_trunca16p24s_h_args,
17959 1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 },
17960 { 3, Iclass_ae_iclass_addp24_args,
17961 1, Iclass_ae_iclass_addp24_stateArgs, 0, 0 },
17962 { 3, Iclass_ae_iclass_subp24_args,
17963 1, Iclass_ae_iclass_subp24_stateArgs, 0, 0 },
17964 { 2, Iclass_ae_iclass_negp24_args,
17965 1, Iclass_ae_iclass_negp24_stateArgs, 0, 0 },
17966 { 2, Iclass_ae_iclass_absp24_args,
17967 1, Iclass_ae_iclass_absp24_stateArgs, 0, 0 },
17968 { 3, Iclass_ae_iclass_maxp24s_args,
17969 1, Iclass_ae_iclass_maxp24s_stateArgs, 0, 0 },
17970 { 3, Iclass_ae_iclass_minp24s_args,
17971 1, Iclass_ae_iclass_minp24s_stateArgs, 0, 0 },
17972 { 4, Iclass_ae_iclass_maxbp24s_args,
17973 1, Iclass_ae_iclass_maxbp24s_stateArgs, 0, 0 },
17974 { 4, Iclass_ae_iclass_minbp24s_args,
17975 1, Iclass_ae_iclass_minbp24s_stateArgs, 0, 0 },
17976 { 3, Iclass_ae_iclass_addsp24s_args,
17977 2, Iclass_ae_iclass_addsp24s_stateArgs, 0, 0 },
17978 { 3, Iclass_ae_iclass_subsp24s_args,
17979 2, Iclass_ae_iclass_subsp24s_stateArgs, 0, 0 },
17980 { 2, Iclass_ae_iclass_negsp24s_args,
17981 2, Iclass_ae_iclass_negsp24s_stateArgs, 0, 0 },
17982 { 2, Iclass_ae_iclass_abssp24s_args,
17983 2, Iclass_ae_iclass_abssp24s_stateArgs, 0, 0 },
17984 { 3, Iclass_ae_iclass_andp48_args,
17985 1, Iclass_ae_iclass_andp48_stateArgs, 0, 0 },
17986 { 3, Iclass_ae_iclass_nandp48_args,
17987 1, Iclass_ae_iclass_nandp48_stateArgs, 0, 0 },
17988 { 3, Iclass_ae_iclass_orp48_args,
17989 1, Iclass_ae_iclass_orp48_stateArgs, 0, 0 },
17990 { 3, Iclass_ae_iclass_xorp48_args,
17991 1, Iclass_ae_iclass_xorp48_stateArgs, 0, 0 },
17992 { 3, Iclass_ae_iclass_ltp24s_args,
17993 1, Iclass_ae_iclass_ltp24s_stateArgs, 0, 0 },
17994 { 3, Iclass_ae_iclass_lep24s_args,
17995 1, Iclass_ae_iclass_lep24s_stateArgs, 0, 0 },
17996 { 3, Iclass_ae_iclass_eqp24_args,
17997 1, Iclass_ae_iclass_eqp24_stateArgs, 0, 0 },
17998 { 3, Iclass_ae_iclass_addq56_args,
17999 1, Iclass_ae_iclass_addq56_stateArgs, 0, 0 },
18000 { 3, Iclass_ae_iclass_subq56_args,
18001 1, Iclass_ae_iclass_subq56_stateArgs, 0, 0 },
18002 { 2, Iclass_ae_iclass_negq56_args,
18003 1, Iclass_ae_iclass_negq56_stateArgs, 0, 0 },
18004 { 2, Iclass_ae_iclass_absq56_args,
18005 1, Iclass_ae_iclass_absq56_stateArgs, 0, 0 },
18006 { 3, Iclass_ae_iclass_maxq56s_args,
18007 1, Iclass_ae_iclass_maxq56s_stateArgs, 0, 0 },
18008 { 3, Iclass_ae_iclass_minq56s_args,
18009 1, Iclass_ae_iclass_minq56s_stateArgs, 0, 0 },
18010 { 4, Iclass_ae_iclass_maxbq56s_args,
18011 1, Iclass_ae_iclass_maxbq56s_stateArgs, 0, 0 },
18012 { 4, Iclass_ae_iclass_minbq56s_args,
18013 1, Iclass_ae_iclass_minbq56s_stateArgs, 0, 0 },
18014 { 3, Iclass_ae_iclass_addsq56s_args,
18015 2, Iclass_ae_iclass_addsq56s_stateArgs, 0, 0 },
18016 { 3, Iclass_ae_iclass_subsq56s_args,
18017 2, Iclass_ae_iclass_subsq56s_stateArgs, 0, 0 },
18018 { 2, Iclass_ae_iclass_negsq56s_args,
18019 2, Iclass_ae_iclass_negsq56s_stateArgs, 0, 0 },
18020 { 2, Iclass_ae_iclass_abssq56s_args,
18021 2, Iclass_ae_iclass_abssq56s_stateArgs, 0, 0 },
18022 { 3, Iclass_ae_iclass_andq56_args,
18023 1, Iclass_ae_iclass_andq56_stateArgs, 0, 0 },
18024 { 3, Iclass_ae_iclass_nandq56_args,
18025 1, Iclass_ae_iclass_nandq56_stateArgs, 0, 0 },
18026 { 3, Iclass_ae_iclass_orq56_args,
18027 1, Iclass_ae_iclass_orq56_stateArgs, 0, 0 },
18028 { 3, Iclass_ae_iclass_xorq56_args,
18029 1, Iclass_ae_iclass_xorq56_stateArgs, 0, 0 },
18030 { 3, Iclass_ae_iclass_sllip24_args,
18031 1, Iclass_ae_iclass_sllip24_stateArgs, 0, 0 },
18032 { 3, Iclass_ae_iclass_srlip24_args,
18033 1, Iclass_ae_iclass_srlip24_stateArgs, 0, 0 },
18034 { 3, Iclass_ae_iclass_sraip24_args,
18035 1, Iclass_ae_iclass_sraip24_stateArgs, 0, 0 },
18036 { 2, Iclass_ae_iclass_sllsp24_args,
18037 2, Iclass_ae_iclass_sllsp24_stateArgs, 0, 0 },
18038 { 2, Iclass_ae_iclass_srlsp24_args,
18039 2, Iclass_ae_iclass_srlsp24_stateArgs, 0, 0 },
18040 { 2, Iclass_ae_iclass_srasp24_args,
18041 2, Iclass_ae_iclass_srasp24_stateArgs, 0, 0 },
18042 { 3, Iclass_ae_iclass_sllisp24s_args,
18043 2, Iclass_ae_iclass_sllisp24s_stateArgs, 0, 0 },
18044 { 2, Iclass_ae_iclass_sllssp24s_args,
18045 3, Iclass_ae_iclass_sllssp24s_stateArgs, 0, 0 },
18046 { 3, Iclass_ae_iclass_slliq56_args,
18047 1, Iclass_ae_iclass_slliq56_stateArgs, 0, 0 },
18048 { 3, Iclass_ae_iclass_srliq56_args,
18049 1, Iclass_ae_iclass_srliq56_stateArgs, 0, 0 },
18050 { 3, Iclass_ae_iclass_sraiq56_args,
18051 1, Iclass_ae_iclass_sraiq56_stateArgs, 0, 0 },
18052 { 2, Iclass_ae_iclass_sllsq56_args,
18053 2, Iclass_ae_iclass_sllsq56_stateArgs, 0, 0 },
18054 { 2, Iclass_ae_iclass_srlsq56_args,
18055 2, Iclass_ae_iclass_srlsq56_stateArgs, 0, 0 },
18056 { 2, Iclass_ae_iclass_srasq56_args,
18057 2, Iclass_ae_iclass_srasq56_stateArgs, 0, 0 },
18058 { 3, Iclass_ae_iclass_sllaq56_args,
18059 1, Iclass_ae_iclass_sllaq56_stateArgs, 0, 0 },
18060 { 3, Iclass_ae_iclass_srlaq56_args,
18061 1, Iclass_ae_iclass_srlaq56_stateArgs, 0, 0 },
18062 { 3, Iclass_ae_iclass_sraaq56_args,
18063 1, Iclass_ae_iclass_sraaq56_stateArgs, 0, 0 },
18064 { 3, Iclass_ae_iclass_sllisq56s_args,
18065 2, Iclass_ae_iclass_sllisq56s_stateArgs, 0, 0 },
18066 { 2, Iclass_ae_iclass_sllssq56s_args,
18067 3, Iclass_ae_iclass_sllssq56s_stateArgs, 0, 0 },
18068 { 3, Iclass_ae_iclass_sllasq56s_args,
18069 2, Iclass_ae_iclass_sllasq56s_stateArgs, 0, 0 },
18070 { 3, Iclass_ae_iclass_ltq56s_args,
18071 1, Iclass_ae_iclass_ltq56s_stateArgs, 0, 0 },
18072 { 3, Iclass_ae_iclass_leq56s_args,
18073 1, Iclass_ae_iclass_leq56s_stateArgs, 0, 0 },
18074 { 3, Iclass_ae_iclass_eqq56_args,
18075 1, Iclass_ae_iclass_eqq56_stateArgs, 0, 0 },
18076 { 2, Iclass_ae_iclass_nsaq56s_args,
18077 1, Iclass_ae_iclass_nsaq56s_stateArgs, 0, 0 },
18078 { 3, Iclass_ae_iclass_mulfs32p16s_ll_args,
18079 2, Iclass_ae_iclass_mulfs32p16s_ll_stateArgs, 0, 0 },
18080 { 3, Iclass_ae_iclass_mulfp24s_ll_args,
18081 1, Iclass_ae_iclass_mulfp24s_ll_stateArgs, 0, 0 },
18082 { 3, Iclass_ae_iclass_mulp24s_ll_args,
18083 1, Iclass_ae_iclass_mulp24s_ll_stateArgs, 0, 0 },
18084 { 3, Iclass_ae_iclass_mulfs32p16s_lh_args,
18085 2, Iclass_ae_iclass_mulfs32p16s_lh_stateArgs, 0, 0 },
18086 { 3, Iclass_ae_iclass_mulfp24s_lh_args,
18087 1, Iclass_ae_iclass_mulfp24s_lh_stateArgs, 0, 0 },
18088 { 3, Iclass_ae_iclass_mulp24s_lh_args,
18089 1, Iclass_ae_iclass_mulp24s_lh_stateArgs, 0, 0 },
18090 { 3, Iclass_ae_iclass_mulfs32p16s_hl_args,
18091 2, Iclass_ae_iclass_mulfs32p16s_hl_stateArgs, 0, 0 },
18092 { 3, Iclass_ae_iclass_mulfp24s_hl_args,
18093 1, Iclass_ae_iclass_mulfp24s_hl_stateArgs, 0, 0 },
18094 { 3, Iclass_ae_iclass_mulp24s_hl_args,
18095 1, Iclass_ae_iclass_mulp24s_hl_stateArgs, 0, 0 },
18096 { 3, Iclass_ae_iclass_mulfs32p16s_hh_args,
18097 2, Iclass_ae_iclass_mulfs32p16s_hh_stateArgs, 0, 0 },
18098 { 3, Iclass_ae_iclass_mulfp24s_hh_args,
18099 1, Iclass_ae_iclass_mulfp24s_hh_stateArgs, 0, 0 },
18100 { 3, Iclass_ae_iclass_mulp24s_hh_args,
18101 1, Iclass_ae_iclass_mulp24s_hh_stateArgs, 0, 0 },
18102 { 3, Iclass_ae_iclass_mulafs32p16s_ll_args,
18103 2, Iclass_ae_iclass_mulafs32p16s_ll_stateArgs, 0, 0 },
18104 { 3, Iclass_ae_iclass_mulafp24s_ll_args,
18105 1, Iclass_ae_iclass_mulafp24s_ll_stateArgs, 0, 0 },
18106 { 3, Iclass_ae_iclass_mulap24s_ll_args,
18107 1, Iclass_ae_iclass_mulap24s_ll_stateArgs, 0, 0 },
18108 { 3, Iclass_ae_iclass_mulafs32p16s_lh_args,
18109 2, Iclass_ae_iclass_mulafs32p16s_lh_stateArgs, 0, 0 },
18110 { 3, Iclass_ae_iclass_mulafp24s_lh_args,
18111 1, Iclass_ae_iclass_mulafp24s_lh_stateArgs, 0, 0 },
18112 { 3, Iclass_ae_iclass_mulap24s_lh_args,
18113 1, Iclass_ae_iclass_mulap24s_lh_stateArgs, 0, 0 },
18114 { 3, Iclass_ae_iclass_mulafs32p16s_hl_args,
18115 2, Iclass_ae_iclass_mulafs32p16s_hl_stateArgs, 0, 0 },
18116 { 3, Iclass_ae_iclass_mulafp24s_hl_args,
18117 1, Iclass_ae_iclass_mulafp24s_hl_stateArgs, 0, 0 },
18118 { 3, Iclass_ae_iclass_mulap24s_hl_args,
18119 1, Iclass_ae_iclass_mulap24s_hl_stateArgs, 0, 0 },
18120 { 3, Iclass_ae_iclass_mulafs32p16s_hh_args,
18121 2, Iclass_ae_iclass_mulafs32p16s_hh_stateArgs, 0, 0 },
18122 { 3, Iclass_ae_iclass_mulafp24s_hh_args,
18123 1, Iclass_ae_iclass_mulafp24s_hh_stateArgs, 0, 0 },
18124 { 3, Iclass_ae_iclass_mulap24s_hh_args,
18125 1, Iclass_ae_iclass_mulap24s_hh_stateArgs, 0, 0 },
18126 { 3, Iclass_ae_iclass_mulsfs32p16s_ll_args,
18127 2, Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs, 0, 0 },
18128 { 3, Iclass_ae_iclass_mulsfp24s_ll_args,
18129 1, Iclass_ae_iclass_mulsfp24s_ll_stateArgs, 0, 0 },
18130 { 3, Iclass_ae_iclass_mulsp24s_ll_args,
18131 1, Iclass_ae_iclass_mulsp24s_ll_stateArgs, 0, 0 },
18132 { 3, Iclass_ae_iclass_mulsfs32p16s_lh_args,
18133 2, Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs, 0, 0 },
18134 { 3, Iclass_ae_iclass_mulsfp24s_lh_args,
18135 1, Iclass_ae_iclass_mulsfp24s_lh_stateArgs, 0, 0 },
18136 { 3, Iclass_ae_iclass_mulsp24s_lh_args,
18137 1, Iclass_ae_iclass_mulsp24s_lh_stateArgs, 0, 0 },
18138 { 3, Iclass_ae_iclass_mulsfs32p16s_hl_args,
18139 2, Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs, 0, 0 },
18140 { 3, Iclass_ae_iclass_mulsfp24s_hl_args,
18141 1, Iclass_ae_iclass_mulsfp24s_hl_stateArgs, 0, 0 },
18142 { 3, Iclass_ae_iclass_mulsp24s_hl_args,
18143 1, Iclass_ae_iclass_mulsp24s_hl_stateArgs, 0, 0 },
18144 { 3, Iclass_ae_iclass_mulsfs32p16s_hh_args,
18145 2, Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs, 0, 0 },
18146 { 3, Iclass_ae_iclass_mulsfp24s_hh_args,
18147 1, Iclass_ae_iclass_mulsfp24s_hh_stateArgs, 0, 0 },
18148 { 3, Iclass_ae_iclass_mulsp24s_hh_args,
18149 1, Iclass_ae_iclass_mulsp24s_hh_stateArgs, 0, 0 },
18150 { 3, Iclass_ae_iclass_mulafs56p24s_ll_args,
18151 2, Iclass_ae_iclass_mulafs56p24s_ll_stateArgs, 0, 0 },
18152 { 3, Iclass_ae_iclass_mulas56p24s_ll_args,
18153 2, Iclass_ae_iclass_mulas56p24s_ll_stateArgs, 0, 0 },
18154 { 3, Iclass_ae_iclass_mulafs56p24s_lh_args,
18155 2, Iclass_ae_iclass_mulafs56p24s_lh_stateArgs, 0, 0 },
18156 { 3, Iclass_ae_iclass_mulas56p24s_lh_args,
18157 2, Iclass_ae_iclass_mulas56p24s_lh_stateArgs, 0, 0 },
18158 { 3, Iclass_ae_iclass_mulafs56p24s_hl_args,
18159 2, Iclass_ae_iclass_mulafs56p24s_hl_stateArgs, 0, 0 },
18160 { 3, Iclass_ae_iclass_mulas56p24s_hl_args,
18161 2, Iclass_ae_iclass_mulas56p24s_hl_stateArgs, 0, 0 },
18162 { 3, Iclass_ae_iclass_mulafs56p24s_hh_args,
18163 2, Iclass_ae_iclass_mulafs56p24s_hh_stateArgs, 0, 0 },
18164 { 3, Iclass_ae_iclass_mulas56p24s_hh_args,
18165 2, Iclass_ae_iclass_mulas56p24s_hh_stateArgs, 0, 0 },
18166 { 3, Iclass_ae_iclass_mulsfs56p24s_ll_args,
18167 2, Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs, 0, 0 },
18168 { 3, Iclass_ae_iclass_mulss56p24s_ll_args,
18169 2, Iclass_ae_iclass_mulss56p24s_ll_stateArgs, 0, 0 },
18170 { 3, Iclass_ae_iclass_mulsfs56p24s_lh_args,
18171 2, Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs, 0, 0 },
18172 { 3, Iclass_ae_iclass_mulss56p24s_lh_args,
18173 2, Iclass_ae_iclass_mulss56p24s_lh_stateArgs, 0, 0 },
18174 { 3, Iclass_ae_iclass_mulsfs56p24s_hl_args,
18175 2, Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs, 0, 0 },
18176 { 3, Iclass_ae_iclass_mulss56p24s_hl_args,
18177 2, Iclass_ae_iclass_mulss56p24s_hl_stateArgs, 0, 0 },
18178 { 3, Iclass_ae_iclass_mulsfs56p24s_hh_args,
18179 2, Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs, 0, 0 },
18180 { 3, Iclass_ae_iclass_mulss56p24s_hh_args,
18181 2, Iclass_ae_iclass_mulss56p24s_hh_stateArgs, 0, 0 },
18182 { 3, Iclass_ae_iclass_mulfq32sp16s_l_args,
18183 1, Iclass_ae_iclass_mulfq32sp16s_l_stateArgs, 0, 0 },
18184 { 3, Iclass_ae_iclass_mulfq32sp16s_h_args,
18185 1, Iclass_ae_iclass_mulfq32sp16s_h_stateArgs, 0, 0 },
18186 { 3, Iclass_ae_iclass_mulfq32sp16u_l_args,
18187 1, Iclass_ae_iclass_mulfq32sp16u_l_stateArgs, 0, 0 },
18188 { 3, Iclass_ae_iclass_mulfq32sp16u_h_args,
18189 1, Iclass_ae_iclass_mulfq32sp16u_h_stateArgs, 0, 0 },
18190 { 3, Iclass_ae_iclass_mulq32sp16s_l_args,
18191 1, Iclass_ae_iclass_mulq32sp16s_l_stateArgs, 0, 0 },
18192 { 3, Iclass_ae_iclass_mulq32sp16s_h_args,
18193 1, Iclass_ae_iclass_mulq32sp16s_h_stateArgs, 0, 0 },
18194 { 3, Iclass_ae_iclass_mulq32sp16u_l_args,
18195 1, Iclass_ae_iclass_mulq32sp16u_l_stateArgs, 0, 0 },
18196 { 3, Iclass_ae_iclass_mulq32sp16u_h_args,
18197 1, Iclass_ae_iclass_mulq32sp16u_h_stateArgs, 0, 0 },
18198 { 3, Iclass_ae_iclass_mulafq32sp16s_l_args,
18199 1, Iclass_ae_iclass_mulafq32sp16s_l_stateArgs, 0, 0 },
18200 { 3, Iclass_ae_iclass_mulafq32sp16s_h_args,
18201 1, Iclass_ae_iclass_mulafq32sp16s_h_stateArgs, 0, 0 },
18202 { 3, Iclass_ae_iclass_mulafq32sp16u_l_args,
18203 1, Iclass_ae_iclass_mulafq32sp16u_l_stateArgs, 0, 0 },
18204 { 3, Iclass_ae_iclass_mulafq32sp16u_h_args,
18205 1, Iclass_ae_iclass_mulafq32sp16u_h_stateArgs, 0, 0 },
18206 { 3, Iclass_ae_iclass_mulaq32sp16s_l_args,
18207 1, Iclass_ae_iclass_mulaq32sp16s_l_stateArgs, 0, 0 },
18208 { 3, Iclass_ae_iclass_mulaq32sp16s_h_args,
18209 1, Iclass_ae_iclass_mulaq32sp16s_h_stateArgs, 0, 0 },
18210 { 3, Iclass_ae_iclass_mulaq32sp16u_l_args,
18211 1, Iclass_ae_iclass_mulaq32sp16u_l_stateArgs, 0, 0 },
18212 { 3, Iclass_ae_iclass_mulaq32sp16u_h_args,
18213 1, Iclass_ae_iclass_mulaq32sp16u_h_stateArgs, 0, 0 },
18214 { 3, Iclass_ae_iclass_mulsfq32sp16s_l_args,
18215 1, Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs, 0, 0 },
18216 { 3, Iclass_ae_iclass_mulsfq32sp16s_h_args,
18217 1, Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs, 0, 0 },
18218 { 3, Iclass_ae_iclass_mulsfq32sp16u_l_args,
18219 1, Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs, 0, 0 },
18220 { 3, Iclass_ae_iclass_mulsfq32sp16u_h_args,
18221 1, Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs, 0, 0 },
18222 { 3, Iclass_ae_iclass_mulsq32sp16s_l_args,
18223 1, Iclass_ae_iclass_mulsq32sp16s_l_stateArgs, 0, 0 },
18224 { 3, Iclass_ae_iclass_mulsq32sp16s_h_args,
18225 1, Iclass_ae_iclass_mulsq32sp16s_h_stateArgs, 0, 0 },
18226 { 3, Iclass_ae_iclass_mulsq32sp16u_l_args,
18227 1, Iclass_ae_iclass_mulsq32sp16u_l_stateArgs, 0, 0 },
18228 { 3, Iclass_ae_iclass_mulsq32sp16u_h_args,
18229 1, Iclass_ae_iclass_mulsq32sp16u_h_stateArgs, 0, 0 },
18230 { 5, Iclass_ae_iclass_mulzaaq32sp16s_ll_args,
18231 1, Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs, 0, 0 },
18232 { 5, Iclass_ae_iclass_mulzaafq32sp16s_ll_args,
18233 1, Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs, 0, 0 },
18234 { 5, Iclass_ae_iclass_mulzaaq32sp16u_ll_args,
18235 1, Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs, 0, 0 },
18236 { 5, Iclass_ae_iclass_mulzaafq32sp16u_ll_args,
18237 1, Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs, 0, 0 },
18238 { 5, Iclass_ae_iclass_mulzaaq32sp16s_hh_args,
18239 1, Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs, 0, 0 },
18240 { 5, Iclass_ae_iclass_mulzaafq32sp16s_hh_args,
18241 1, Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs, 0, 0 },
18242 { 5, Iclass_ae_iclass_mulzaaq32sp16u_hh_args,
18243 1, Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs, 0, 0 },
18244 { 5, Iclass_ae_iclass_mulzaafq32sp16u_hh_args,
18245 1, Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs, 0, 0 },
18246 { 5, Iclass_ae_iclass_mulzaaq32sp16s_lh_args,
18247 1, Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs, 0, 0 },
18248 { 5, Iclass_ae_iclass_mulzaafq32sp16s_lh_args,
18249 1, Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs, 0, 0 },
18250 { 5, Iclass_ae_iclass_mulzaaq32sp16u_lh_args,
18251 1, Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 },
18252 { 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args,
18253 1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 },
18254 { 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args,
18255 1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 },
18256 { 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args,
18257 1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 },
18258 { 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args,
18259 1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 },
18260 { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args,
18261 1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 },
18262 { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args,
18263 1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 },
18264 { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args,
18265 1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 },
18266 { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args,
18267 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 },
18268 { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args,
18269 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 },
18270 { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args,
18271 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 },
18272 { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args,
18273 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 },
18274 { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args,
18275 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 },
18276 { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args,
18277 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 },
18278 { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args,
18279 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 },
18280 { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args,
18281 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 },
18282 { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args,
18283 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 },
18284 { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args,
18285 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 },
18286 { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args,
18287 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 },
18288 { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args,
18289 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 },
18290 { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args,
18291 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 },
18292 { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args,
18293 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 },
18294 { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args,
18295 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 },
18296 { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args,
18297 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 },
18298 { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args,
18299 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 },
18300 { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args,
18301 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 },
18302 { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args,
18303 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 },
18304 { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args,
18305 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 },
18306 { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args,
18307 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 },
18308 { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args,
18309 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 },
18310 { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args,
18311 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 },
18312 { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args,
18313 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 },
18314 { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args,
18315 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 },
18316 { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args,
18317 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 },
18318 { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args,
18319 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 },
18320 { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args,
18321 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 },
18322 { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args,
18323 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 },
18324 { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args,
18325 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 },
18326 { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args,
18327 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 },
18328 { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
18329 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
18330 { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
18331 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
18332 { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
18333 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
18334 { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
18335 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
18336 { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
18337 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
18338 { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
18339 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
18340 { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
18341 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
18342 { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
18343 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
18344 { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
18345 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
18346 { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
18347 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
18348 { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
18349 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
18350 { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
18351 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
18352 { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
18353 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
18354 { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
18355 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
18356 { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
18357 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
18358 { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
18359 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
18360 { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
18361 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
18362 { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
18363 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
18364 { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
18365 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
18366 { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
18367 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
18368 { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
18369 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
18370 { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
18371 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
18372 { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
18373 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
18374 { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
18375 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
18376 { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
18377 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
18378 { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
18379 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
18380 { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
18381 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
18382 { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
18383 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
18384 { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
18385 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
18386 { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
18387 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
18388 { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
18389 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
18390 { 2, Iclass_ae_iclass_sha32_args,
18392 { 3, Iclass_ae_iclass_vldl32t_args,
18393 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
18394 { 3, Iclass_ae_iclass_vldl16t_args,
18395 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
18396 { 1, Iclass_ae_iclass_vldl16c_args,
18397 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
18398 { 1, Iclass_ae_iclass_vldsht_args,
18399 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
18400 { 2, Iclass_ae_iclass_lb_args,
18401 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
18402 { 2, Iclass_ae_iclass_lbi_args,
18403 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
18404 { 3, Iclass_ae_iclass_lbk_args,
18405 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
18406 { 3, Iclass_ae_iclass_lbki_args,
18407 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
18408 { 2, Iclass_ae_iclass_db_args,
18409 3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
18410 { 2, Iclass_ae_iclass_dbi_args,
18411 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
18412 { 3, Iclass_ae_iclass_vlel32t_args,
18413 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
18414 { 3, Iclass_ae_iclass_vlel16t_args,
18415 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
18416 { 2, Iclass_ae_iclass_sb_args,
18417 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
18418 { 3, Iclass_ae_iclass_sbi_args,
18419 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
18420 { 1, Iclass_ae_iclass_vles16c_args,
18421 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
18422 { 1, Iclass_ae_iclass_sbf_args,
18423 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }
18426 enum xtensa_iclass_id {
18427 ICLASS_xt_iclass_excw,
18428 ICLASS_xt_iclass_rfe,
18429 ICLASS_xt_iclass_rfde,
18430 ICLASS_xt_iclass_syscall,
18431 ICLASS_xt_iclass_call12,
18432 ICLASS_xt_iclass_call8,
18433 ICLASS_xt_iclass_call4,
18434 ICLASS_xt_iclass_callx12,
18435 ICLASS_xt_iclass_callx8,
18436 ICLASS_xt_iclass_callx4,
18437 ICLASS_xt_iclass_entry,
18438 ICLASS_xt_iclass_movsp,
18439 ICLASS_xt_iclass_rotw,
18440 ICLASS_xt_iclass_retw,
18441 ICLASS_xt_iclass_rfwou,
18442 ICLASS_xt_iclass_l32e,
18443 ICLASS_xt_iclass_s32e,
18444 ICLASS_xt_iclass_rsr_windowbase,
18445 ICLASS_xt_iclass_wsr_windowbase,
18446 ICLASS_xt_iclass_xsr_windowbase,
18447 ICLASS_xt_iclass_rsr_windowstart,
18448 ICLASS_xt_iclass_wsr_windowstart,
18449 ICLASS_xt_iclass_xsr_windowstart,
18450 ICLASS_xt_iclass_add_n,
18451 ICLASS_xt_iclass_addi_n,
18452 ICLASS_xt_iclass_bz6,
18453 ICLASS_xt_iclass_ill_n,
18454 ICLASS_xt_iclass_loadi4,
18455 ICLASS_xt_iclass_mov_n,
18456 ICLASS_xt_iclass_movi_n,
18457 ICLASS_xt_iclass_nopn,
18458 ICLASS_xt_iclass_retn,
18459 ICLASS_xt_iclass_storei4,
18460 ICLASS_rur_threadptr,
18461 ICLASS_wur_threadptr,
18462 ICLASS_xt_iclass_addi,
18463 ICLASS_xt_iclass_addmi,
18464 ICLASS_xt_iclass_addsub,
18465 ICLASS_xt_iclass_bit,
18466 ICLASS_xt_iclass_bsi8,
18467 ICLASS_xt_iclass_bsi8b,
18468 ICLASS_xt_iclass_bsi8u,
18469 ICLASS_xt_iclass_bst8,
18470 ICLASS_xt_iclass_bsz12,
18471 ICLASS_xt_iclass_call0,
18472 ICLASS_xt_iclass_callx0,
18473 ICLASS_xt_iclass_exti,
18474 ICLASS_xt_iclass_ill,
18475 ICLASS_xt_iclass_jump,
18476 ICLASS_xt_iclass_jumpx,
18477 ICLASS_xt_iclass_l16ui,
18478 ICLASS_xt_iclass_l16si,
18479 ICLASS_xt_iclass_l32i,
18480 ICLASS_xt_iclass_l32r,
18481 ICLASS_xt_iclass_l8i,
18482 ICLASS_xt_iclass_loop,
18483 ICLASS_xt_iclass_loopz,
18484 ICLASS_xt_iclass_movi,
18485 ICLASS_xt_iclass_movz,
18486 ICLASS_xt_iclass_neg,
18487 ICLASS_xt_iclass_nop,
18488 ICLASS_xt_iclass_return,
18489 ICLASS_xt_iclass_simcall,
18490 ICLASS_xt_iclass_s16i,
18491 ICLASS_xt_iclass_s32i,
18492 ICLASS_xt_iclass_s8i,
18493 ICLASS_xt_iclass_sar,
18494 ICLASS_xt_iclass_sari,
18495 ICLASS_xt_iclass_shifts,
18496 ICLASS_xt_iclass_shiftst,
18497 ICLASS_xt_iclass_shiftt,
18498 ICLASS_xt_iclass_slli,
18499 ICLASS_xt_iclass_srai,
18500 ICLASS_xt_iclass_srli,
18501 ICLASS_xt_iclass_memw,
18502 ICLASS_xt_iclass_extw,
18503 ICLASS_xt_iclass_isync,
18504 ICLASS_xt_iclass_sync,
18505 ICLASS_xt_iclass_rsil,
18506 ICLASS_xt_iclass_rsr_lend,
18507 ICLASS_xt_iclass_wsr_lend,
18508 ICLASS_xt_iclass_xsr_lend,
18509 ICLASS_xt_iclass_rsr_lcount,
18510 ICLASS_xt_iclass_wsr_lcount,
18511 ICLASS_xt_iclass_xsr_lcount,
18512 ICLASS_xt_iclass_rsr_lbeg,
18513 ICLASS_xt_iclass_wsr_lbeg,
18514 ICLASS_xt_iclass_xsr_lbeg,
18515 ICLASS_xt_iclass_rsr_sar,
18516 ICLASS_xt_iclass_wsr_sar,
18517 ICLASS_xt_iclass_xsr_sar,
18518 ICLASS_xt_iclass_rsr_litbase,
18519 ICLASS_xt_iclass_wsr_litbase,
18520 ICLASS_xt_iclass_xsr_litbase,
18521 ICLASS_xt_iclass_rsr_configid0,
18522 ICLASS_xt_iclass_wsr_configid0,
18523 ICLASS_xt_iclass_rsr_configid1,
18524 ICLASS_xt_iclass_rsr_ps,
18525 ICLASS_xt_iclass_wsr_ps,
18526 ICLASS_xt_iclass_xsr_ps,
18527 ICLASS_xt_iclass_rsr_epc1,
18528 ICLASS_xt_iclass_wsr_epc1,
18529 ICLASS_xt_iclass_xsr_epc1,
18530 ICLASS_xt_iclass_rsr_excsave1,
18531 ICLASS_xt_iclass_wsr_excsave1,
18532 ICLASS_xt_iclass_xsr_excsave1,
18533 ICLASS_xt_iclass_rsr_epc2,
18534 ICLASS_xt_iclass_wsr_epc2,
18535 ICLASS_xt_iclass_xsr_epc2,
18536 ICLASS_xt_iclass_rsr_excsave2,
18537 ICLASS_xt_iclass_wsr_excsave2,
18538 ICLASS_xt_iclass_xsr_excsave2,
18539 ICLASS_xt_iclass_rsr_eps2,
18540 ICLASS_xt_iclass_wsr_eps2,
18541 ICLASS_xt_iclass_xsr_eps2,
18542 ICLASS_xt_iclass_rsr_excvaddr,
18543 ICLASS_xt_iclass_wsr_excvaddr,
18544 ICLASS_xt_iclass_xsr_excvaddr,
18545 ICLASS_xt_iclass_rsr_depc,
18546 ICLASS_xt_iclass_wsr_depc,
18547 ICLASS_xt_iclass_xsr_depc,
18548 ICLASS_xt_iclass_rsr_exccause,
18549 ICLASS_xt_iclass_wsr_exccause,
18550 ICLASS_xt_iclass_xsr_exccause,
18551 ICLASS_xt_iclass_rsr_misc0,
18552 ICLASS_xt_iclass_wsr_misc0,
18553 ICLASS_xt_iclass_xsr_misc0,
18554 ICLASS_xt_iclass_rsr_misc1,
18555 ICLASS_xt_iclass_wsr_misc1,
18556 ICLASS_xt_iclass_xsr_misc1,
18557 ICLASS_xt_iclass_rsr_prid,
18558 ICLASS_xt_iclass_rsr_vecbase,
18559 ICLASS_xt_iclass_wsr_vecbase,
18560 ICLASS_xt_iclass_xsr_vecbase,
18563 ICLASS_xt_iclass_rfi,
18564 ICLASS_xt_iclass_wait,
18565 ICLASS_xt_iclass_rsr_interrupt,
18566 ICLASS_xt_iclass_wsr_intset,
18567 ICLASS_xt_iclass_wsr_intclear,
18568 ICLASS_xt_iclass_rsr_intenable,
18569 ICLASS_xt_iclass_wsr_intenable,
18570 ICLASS_xt_iclass_xsr_intenable,
18571 ICLASS_xt_iclass_break,
18572 ICLASS_xt_iclass_break_n,
18573 ICLASS_xt_iclass_rsr_debugcause,
18574 ICLASS_xt_iclass_wsr_debugcause,
18575 ICLASS_xt_iclass_xsr_debugcause,
18576 ICLASS_xt_iclass_rsr_icount,
18577 ICLASS_xt_iclass_wsr_icount,
18578 ICLASS_xt_iclass_xsr_icount,
18579 ICLASS_xt_iclass_rsr_icountlevel,
18580 ICLASS_xt_iclass_wsr_icountlevel,
18581 ICLASS_xt_iclass_xsr_icountlevel,
18582 ICLASS_xt_iclass_rsr_ddr,
18583 ICLASS_xt_iclass_wsr_ddr,
18584 ICLASS_xt_iclass_xsr_ddr,
18585 ICLASS_xt_iclass_rfdo,
18586 ICLASS_xt_iclass_rfdd,
18587 ICLASS_xt_iclass_bbool1,
18588 ICLASS_xt_iclass_bbool4,
18589 ICLASS_xt_iclass_bbool8,
18590 ICLASS_xt_iclass_bbranch,
18591 ICLASS_xt_iclass_bmove,
18592 ICLASS_xt_iclass_RSR_BR,
18593 ICLASS_xt_iclass_WSR_BR,
18594 ICLASS_xt_iclass_XSR_BR,
18595 ICLASS_xt_iclass_rsr_ccount,
18596 ICLASS_xt_iclass_wsr_ccount,
18597 ICLASS_xt_iclass_xsr_ccount,
18598 ICLASS_xt_iclass_rsr_ccompare0,
18599 ICLASS_xt_iclass_wsr_ccompare0,
18600 ICLASS_xt_iclass_xsr_ccompare0,
18601 ICLASS_xt_iclass_rsr_ccompare1,
18602 ICLASS_xt_iclass_wsr_ccompare1,
18603 ICLASS_xt_iclass_xsr_ccompare1,
18604 ICLASS_xt_iclass_icache,
18605 ICLASS_xt_iclass_icache_inv,
18606 ICLASS_xt_iclass_licx,
18607 ICLASS_xt_iclass_sicx,
18608 ICLASS_xt_iclass_dcache,
18609 ICLASS_xt_iclass_dcache_ind,
18610 ICLASS_xt_iclass_dcache_inv,
18611 ICLASS_xt_iclass_dpf,
18612 ICLASS_xt_iclass_sdct,
18613 ICLASS_xt_iclass_ldct,
18614 ICLASS_xt_iclass_wsr_ptevaddr,
18615 ICLASS_xt_iclass_rsr_ptevaddr,
18616 ICLASS_xt_iclass_xsr_ptevaddr,
18617 ICLASS_xt_iclass_rsr_rasid,
18618 ICLASS_xt_iclass_wsr_rasid,
18619 ICLASS_xt_iclass_xsr_rasid,
18620 ICLASS_xt_iclass_rsr_itlbcfg,
18621 ICLASS_xt_iclass_wsr_itlbcfg,
18622 ICLASS_xt_iclass_xsr_itlbcfg,
18623 ICLASS_xt_iclass_rsr_dtlbcfg,
18624 ICLASS_xt_iclass_wsr_dtlbcfg,
18625 ICLASS_xt_iclass_xsr_dtlbcfg,
18626 ICLASS_xt_iclass_idtlb,
18627 ICLASS_xt_iclass_rdtlb,
18628 ICLASS_xt_iclass_wdtlb,
18629 ICLASS_xt_iclass_iitlb,
18630 ICLASS_xt_iclass_ritlb,
18631 ICLASS_xt_iclass_witlb,
18632 ICLASS_xt_iclass_ldpte,
18633 ICLASS_xt_iclass_hwwitlba,
18634 ICLASS_xt_iclass_hwwdtlba,
18635 ICLASS_xt_iclass_rsr_cpenable,
18636 ICLASS_xt_iclass_wsr_cpenable,
18637 ICLASS_xt_iclass_xsr_cpenable,
18638 ICLASS_xt_iclass_clamp,
18639 ICLASS_xt_iclass_minmax,
18640 ICLASS_xt_iclass_nsa,
18641 ICLASS_xt_iclass_sx,
18642 ICLASS_xt_iclass_l32ai,
18643 ICLASS_xt_iclass_s32ri,
18644 ICLASS_xt_iclass_s32c1i,
18645 ICLASS_xt_iclass_rsr_scompare1,
18646 ICLASS_xt_iclass_wsr_scompare1,
18647 ICLASS_xt_iclass_xsr_scompare1,
18648 ICLASS_xt_iclass_rsr_atomctl,
18649 ICLASS_xt_iclass_wsr_atomctl,
18650 ICLASS_xt_iclass_xsr_atomctl,
18651 ICLASS_xt_iclass_rer,
18652 ICLASS_xt_iclass_wer,
18653 ICLASS_rur_ae_ovf_sar,
18654 ICLASS_wur_ae_ovf_sar,
18655 ICLASS_rur_ae_bithead,
18656 ICLASS_wur_ae_bithead,
18657 ICLASS_rur_ae_ts_fts_bu_bp,
18658 ICLASS_wur_ae_ts_fts_bu_bp,
18659 ICLASS_rur_ae_sd_no,
18660 ICLASS_wur_ae_sd_no,
18661 ICLASS_ae_iclass_rur_ae_overflow,
18662 ICLASS_ae_iclass_wur_ae_overflow,
18663 ICLASS_ae_iclass_rur_ae_sar,
18664 ICLASS_ae_iclass_wur_ae_sar,
18665 ICLASS_ae_iclass_rur_ae_bitptr,
18666 ICLASS_ae_iclass_wur_ae_bitptr,
18667 ICLASS_ae_iclass_rur_ae_bitsused,
18668 ICLASS_ae_iclass_wur_ae_bitsused,
18669 ICLASS_ae_iclass_rur_ae_tablesize,
18670 ICLASS_ae_iclass_wur_ae_tablesize,
18671 ICLASS_ae_iclass_rur_ae_first_ts,
18672 ICLASS_ae_iclass_wur_ae_first_ts,
18673 ICLASS_ae_iclass_rur_ae_nextoffset,
18674 ICLASS_ae_iclass_wur_ae_nextoffset,
18675 ICLASS_ae_iclass_rur_ae_searchdone,
18676 ICLASS_ae_iclass_wur_ae_searchdone,
18677 ICLASS_ae_iclass_lp16f_i,
18678 ICLASS_ae_iclass_lp16f_iu,
18679 ICLASS_ae_iclass_lp16f_x,
18680 ICLASS_ae_iclass_lp16f_xu,
18681 ICLASS_ae_iclass_lp24_i,
18682 ICLASS_ae_iclass_lp24_iu,
18683 ICLASS_ae_iclass_lp24_x,
18684 ICLASS_ae_iclass_lp24_xu,
18685 ICLASS_ae_iclass_lp24f_i,
18686 ICLASS_ae_iclass_lp24f_iu,
18687 ICLASS_ae_iclass_lp24f_x,
18688 ICLASS_ae_iclass_lp24f_xu,
18689 ICLASS_ae_iclass_lp16x2f_i,
18690 ICLASS_ae_iclass_lp16x2f_iu,
18691 ICLASS_ae_iclass_lp16x2f_x,
18692 ICLASS_ae_iclass_lp16x2f_xu,
18693 ICLASS_ae_iclass_lp24x2f_i,
18694 ICLASS_ae_iclass_lp24x2f_iu,
18695 ICLASS_ae_iclass_lp24x2f_x,
18696 ICLASS_ae_iclass_lp24x2f_xu,
18697 ICLASS_ae_iclass_lp24x2_i,
18698 ICLASS_ae_iclass_lp24x2_iu,
18699 ICLASS_ae_iclass_lp24x2_x,
18700 ICLASS_ae_iclass_lp24x2_xu,
18701 ICLASS_ae_iclass_sp16x2f_i,
18702 ICLASS_ae_iclass_sp16x2f_iu,
18703 ICLASS_ae_iclass_sp16x2f_x,
18704 ICLASS_ae_iclass_sp16x2f_xu,
18705 ICLASS_ae_iclass_sp24x2s_i,
18706 ICLASS_ae_iclass_sp24x2s_iu,
18707 ICLASS_ae_iclass_sp24x2s_x,
18708 ICLASS_ae_iclass_sp24x2s_xu,
18709 ICLASS_ae_iclass_sp24x2f_i,
18710 ICLASS_ae_iclass_sp24x2f_iu,
18711 ICLASS_ae_iclass_sp24x2f_x,
18712 ICLASS_ae_iclass_sp24x2f_xu,
18713 ICLASS_ae_iclass_sp16f_l_i,
18714 ICLASS_ae_iclass_sp16f_l_iu,
18715 ICLASS_ae_iclass_sp16f_l_x,
18716 ICLASS_ae_iclass_sp16f_l_xu,
18717 ICLASS_ae_iclass_sp24s_l_i,
18718 ICLASS_ae_iclass_sp24s_l_iu,
18719 ICLASS_ae_iclass_sp24s_l_x,
18720 ICLASS_ae_iclass_sp24s_l_xu,
18721 ICLASS_ae_iclass_sp24f_l_i,
18722 ICLASS_ae_iclass_sp24f_l_iu,
18723 ICLASS_ae_iclass_sp24f_l_x,
18724 ICLASS_ae_iclass_sp24f_l_xu,
18725 ICLASS_ae_iclass_lq56_i,
18726 ICLASS_ae_iclass_lq56_iu,
18727 ICLASS_ae_iclass_lq56_x,
18728 ICLASS_ae_iclass_lq56_xu,
18729 ICLASS_ae_iclass_lq32f_i,
18730 ICLASS_ae_iclass_lq32f_iu,
18731 ICLASS_ae_iclass_lq32f_x,
18732 ICLASS_ae_iclass_lq32f_xu,
18733 ICLASS_ae_iclass_sq56s_i,
18734 ICLASS_ae_iclass_sq56s_iu,
18735 ICLASS_ae_iclass_sq56s_x,
18736 ICLASS_ae_iclass_sq56s_xu,
18737 ICLASS_ae_iclass_sq32f_i,
18738 ICLASS_ae_iclass_sq32f_iu,
18739 ICLASS_ae_iclass_sq32f_x,
18740 ICLASS_ae_iclass_sq32f_xu,
18741 ICLASS_ae_iclass_zerop48,
18742 ICLASS_ae_iclass_movp48,
18743 ICLASS_ae_iclass_selp24_ll,
18744 ICLASS_ae_iclass_selp24_lh,
18745 ICLASS_ae_iclass_selp24_hl,
18746 ICLASS_ae_iclass_selp24_hh,
18747 ICLASS_ae_iclass_movtp24x2,
18748 ICLASS_ae_iclass_movfp24x2,
18749 ICLASS_ae_iclass_movtp48,
18750 ICLASS_ae_iclass_movfp48,
18751 ICLASS_ae_iclass_movpa24x2,
18752 ICLASS_ae_iclass_truncp24a32x2,
18753 ICLASS_ae_iclass_cvta32p24_l,
18754 ICLASS_ae_iclass_cvta32p24_h,
18755 ICLASS_ae_iclass_cvtp24a16x2_ll,
18756 ICLASS_ae_iclass_cvtp24a16x2_lh,
18757 ICLASS_ae_iclass_cvtp24a16x2_hl,
18758 ICLASS_ae_iclass_cvtp24a16x2_hh,
18759 ICLASS_ae_iclass_truncp24q48x2,
18760 ICLASS_ae_iclass_truncp16,
18761 ICLASS_ae_iclass_roundsp24q48sym,
18762 ICLASS_ae_iclass_roundsp24q48asym,
18763 ICLASS_ae_iclass_roundsp16q48sym,
18764 ICLASS_ae_iclass_roundsp16q48asym,
18765 ICLASS_ae_iclass_roundsp16sym,
18766 ICLASS_ae_iclass_roundsp16asym,
18767 ICLASS_ae_iclass_zeroq56,
18768 ICLASS_ae_iclass_movq56,
18769 ICLASS_ae_iclass_movtq56,
18770 ICLASS_ae_iclass_movfq56,
18771 ICLASS_ae_iclass_cvtq48a32s,
18772 ICLASS_ae_iclass_cvtq48p24s_l,
18773 ICLASS_ae_iclass_cvtq48p24s_h,
18774 ICLASS_ae_iclass_satq48s,
18775 ICLASS_ae_iclass_truncq32,
18776 ICLASS_ae_iclass_roundsq32sym,
18777 ICLASS_ae_iclass_roundsq32asym,
18778 ICLASS_ae_iclass_trunca32q48,
18779 ICLASS_ae_iclass_movap24s_l,
18780 ICLASS_ae_iclass_movap24s_h,
18781 ICLASS_ae_iclass_trunca16p24s_l,
18782 ICLASS_ae_iclass_trunca16p24s_h,
18783 ICLASS_ae_iclass_addp24,
18784 ICLASS_ae_iclass_subp24,
18785 ICLASS_ae_iclass_negp24,
18786 ICLASS_ae_iclass_absp24,
18787 ICLASS_ae_iclass_maxp24s,
18788 ICLASS_ae_iclass_minp24s,
18789 ICLASS_ae_iclass_maxbp24s,
18790 ICLASS_ae_iclass_minbp24s,
18791 ICLASS_ae_iclass_addsp24s,
18792 ICLASS_ae_iclass_subsp24s,
18793 ICLASS_ae_iclass_negsp24s,
18794 ICLASS_ae_iclass_abssp24s,
18795 ICLASS_ae_iclass_andp48,
18796 ICLASS_ae_iclass_nandp48,
18797 ICLASS_ae_iclass_orp48,
18798 ICLASS_ae_iclass_xorp48,
18799 ICLASS_ae_iclass_ltp24s,
18800 ICLASS_ae_iclass_lep24s,
18801 ICLASS_ae_iclass_eqp24,
18802 ICLASS_ae_iclass_addq56,
18803 ICLASS_ae_iclass_subq56,
18804 ICLASS_ae_iclass_negq56,
18805 ICLASS_ae_iclass_absq56,
18806 ICLASS_ae_iclass_maxq56s,
18807 ICLASS_ae_iclass_minq56s,
18808 ICLASS_ae_iclass_maxbq56s,
18809 ICLASS_ae_iclass_minbq56s,
18810 ICLASS_ae_iclass_addsq56s,
18811 ICLASS_ae_iclass_subsq56s,
18812 ICLASS_ae_iclass_negsq56s,
18813 ICLASS_ae_iclass_abssq56s,
18814 ICLASS_ae_iclass_andq56,
18815 ICLASS_ae_iclass_nandq56,
18816 ICLASS_ae_iclass_orq56,
18817 ICLASS_ae_iclass_xorq56,
18818 ICLASS_ae_iclass_sllip24,
18819 ICLASS_ae_iclass_srlip24,
18820 ICLASS_ae_iclass_sraip24,
18821 ICLASS_ae_iclass_sllsp24,
18822 ICLASS_ae_iclass_srlsp24,
18823 ICLASS_ae_iclass_srasp24,
18824 ICLASS_ae_iclass_sllisp24s,
18825 ICLASS_ae_iclass_sllssp24s,
18826 ICLASS_ae_iclass_slliq56,
18827 ICLASS_ae_iclass_srliq56,
18828 ICLASS_ae_iclass_sraiq56,
18829 ICLASS_ae_iclass_sllsq56,
18830 ICLASS_ae_iclass_srlsq56,
18831 ICLASS_ae_iclass_srasq56,
18832 ICLASS_ae_iclass_sllaq56,
18833 ICLASS_ae_iclass_srlaq56,
18834 ICLASS_ae_iclass_sraaq56,
18835 ICLASS_ae_iclass_sllisq56s,
18836 ICLASS_ae_iclass_sllssq56s,
18837 ICLASS_ae_iclass_sllasq56s,
18838 ICLASS_ae_iclass_ltq56s,
18839 ICLASS_ae_iclass_leq56s,
18840 ICLASS_ae_iclass_eqq56,
18841 ICLASS_ae_iclass_nsaq56s,
18842 ICLASS_ae_iclass_mulfs32p16s_ll,
18843 ICLASS_ae_iclass_mulfp24s_ll,
18844 ICLASS_ae_iclass_mulp24s_ll,
18845 ICLASS_ae_iclass_mulfs32p16s_lh,
18846 ICLASS_ae_iclass_mulfp24s_lh,
18847 ICLASS_ae_iclass_mulp24s_lh,
18848 ICLASS_ae_iclass_mulfs32p16s_hl,
18849 ICLASS_ae_iclass_mulfp24s_hl,
18850 ICLASS_ae_iclass_mulp24s_hl,
18851 ICLASS_ae_iclass_mulfs32p16s_hh,
18852 ICLASS_ae_iclass_mulfp24s_hh,
18853 ICLASS_ae_iclass_mulp24s_hh,
18854 ICLASS_ae_iclass_mulafs32p16s_ll,
18855 ICLASS_ae_iclass_mulafp24s_ll,
18856 ICLASS_ae_iclass_mulap24s_ll,
18857 ICLASS_ae_iclass_mulafs32p16s_lh,
18858 ICLASS_ae_iclass_mulafp24s_lh,
18859 ICLASS_ae_iclass_mulap24s_lh,
18860 ICLASS_ae_iclass_mulafs32p16s_hl,
18861 ICLASS_ae_iclass_mulafp24s_hl,
18862 ICLASS_ae_iclass_mulap24s_hl,
18863 ICLASS_ae_iclass_mulafs32p16s_hh,
18864 ICLASS_ae_iclass_mulafp24s_hh,
18865 ICLASS_ae_iclass_mulap24s_hh,
18866 ICLASS_ae_iclass_mulsfs32p16s_ll,
18867 ICLASS_ae_iclass_mulsfp24s_ll,
18868 ICLASS_ae_iclass_mulsp24s_ll,
18869 ICLASS_ae_iclass_mulsfs32p16s_lh,
18870 ICLASS_ae_iclass_mulsfp24s_lh,
18871 ICLASS_ae_iclass_mulsp24s_lh,
18872 ICLASS_ae_iclass_mulsfs32p16s_hl,
18873 ICLASS_ae_iclass_mulsfp24s_hl,
18874 ICLASS_ae_iclass_mulsp24s_hl,
18875 ICLASS_ae_iclass_mulsfs32p16s_hh,
18876 ICLASS_ae_iclass_mulsfp24s_hh,
18877 ICLASS_ae_iclass_mulsp24s_hh,
18878 ICLASS_ae_iclass_mulafs56p24s_ll,
18879 ICLASS_ae_iclass_mulas56p24s_ll,
18880 ICLASS_ae_iclass_mulafs56p24s_lh,
18881 ICLASS_ae_iclass_mulas56p24s_lh,
18882 ICLASS_ae_iclass_mulafs56p24s_hl,
18883 ICLASS_ae_iclass_mulas56p24s_hl,
18884 ICLASS_ae_iclass_mulafs56p24s_hh,
18885 ICLASS_ae_iclass_mulas56p24s_hh,
18886 ICLASS_ae_iclass_mulsfs56p24s_ll,
18887 ICLASS_ae_iclass_mulss56p24s_ll,
18888 ICLASS_ae_iclass_mulsfs56p24s_lh,
18889 ICLASS_ae_iclass_mulss56p24s_lh,
18890 ICLASS_ae_iclass_mulsfs56p24s_hl,
18891 ICLASS_ae_iclass_mulss56p24s_hl,
18892 ICLASS_ae_iclass_mulsfs56p24s_hh,
18893 ICLASS_ae_iclass_mulss56p24s_hh,
18894 ICLASS_ae_iclass_mulfq32sp16s_l,
18895 ICLASS_ae_iclass_mulfq32sp16s_h,
18896 ICLASS_ae_iclass_mulfq32sp16u_l,
18897 ICLASS_ae_iclass_mulfq32sp16u_h,
18898 ICLASS_ae_iclass_mulq32sp16s_l,
18899 ICLASS_ae_iclass_mulq32sp16s_h,
18900 ICLASS_ae_iclass_mulq32sp16u_l,
18901 ICLASS_ae_iclass_mulq32sp16u_h,
18902 ICLASS_ae_iclass_mulafq32sp16s_l,
18903 ICLASS_ae_iclass_mulafq32sp16s_h,
18904 ICLASS_ae_iclass_mulafq32sp16u_l,
18905 ICLASS_ae_iclass_mulafq32sp16u_h,
18906 ICLASS_ae_iclass_mulaq32sp16s_l,
18907 ICLASS_ae_iclass_mulaq32sp16s_h,
18908 ICLASS_ae_iclass_mulaq32sp16u_l,
18909 ICLASS_ae_iclass_mulaq32sp16u_h,
18910 ICLASS_ae_iclass_mulsfq32sp16s_l,
18911 ICLASS_ae_iclass_mulsfq32sp16s_h,
18912 ICLASS_ae_iclass_mulsfq32sp16u_l,
18913 ICLASS_ae_iclass_mulsfq32sp16u_h,
18914 ICLASS_ae_iclass_mulsq32sp16s_l,
18915 ICLASS_ae_iclass_mulsq32sp16s_h,
18916 ICLASS_ae_iclass_mulsq32sp16u_l,
18917 ICLASS_ae_iclass_mulsq32sp16u_h,
18918 ICLASS_ae_iclass_mulzaaq32sp16s_ll,
18919 ICLASS_ae_iclass_mulzaafq32sp16s_ll,
18920 ICLASS_ae_iclass_mulzaaq32sp16u_ll,
18921 ICLASS_ae_iclass_mulzaafq32sp16u_ll,
18922 ICLASS_ae_iclass_mulzaaq32sp16s_hh,
18923 ICLASS_ae_iclass_mulzaafq32sp16s_hh,
18924 ICLASS_ae_iclass_mulzaaq32sp16u_hh,
18925 ICLASS_ae_iclass_mulzaafq32sp16u_hh,
18926 ICLASS_ae_iclass_mulzaaq32sp16s_lh,
18927 ICLASS_ae_iclass_mulzaafq32sp16s_lh,
18928 ICLASS_ae_iclass_mulzaaq32sp16u_lh,
18929 ICLASS_ae_iclass_mulzaafq32sp16u_lh,
18930 ICLASS_ae_iclass_mulzasq32sp16s_ll,
18931 ICLASS_ae_iclass_mulzasfq32sp16s_ll,
18932 ICLASS_ae_iclass_mulzasq32sp16u_ll,
18933 ICLASS_ae_iclass_mulzasfq32sp16u_ll,
18934 ICLASS_ae_iclass_mulzasq32sp16s_hh,
18935 ICLASS_ae_iclass_mulzasfq32sp16s_hh,
18936 ICLASS_ae_iclass_mulzasq32sp16u_hh,
18937 ICLASS_ae_iclass_mulzasfq32sp16u_hh,
18938 ICLASS_ae_iclass_mulzasq32sp16s_lh,
18939 ICLASS_ae_iclass_mulzasfq32sp16s_lh,
18940 ICLASS_ae_iclass_mulzasq32sp16u_lh,
18941 ICLASS_ae_iclass_mulzasfq32sp16u_lh,
18942 ICLASS_ae_iclass_mulzsaq32sp16s_ll,
18943 ICLASS_ae_iclass_mulzsafq32sp16s_ll,
18944 ICLASS_ae_iclass_mulzsaq32sp16u_ll,
18945 ICLASS_ae_iclass_mulzsafq32sp16u_ll,
18946 ICLASS_ae_iclass_mulzsaq32sp16s_hh,
18947 ICLASS_ae_iclass_mulzsafq32sp16s_hh,
18948 ICLASS_ae_iclass_mulzsaq32sp16u_hh,
18949 ICLASS_ae_iclass_mulzsafq32sp16u_hh,
18950 ICLASS_ae_iclass_mulzsaq32sp16s_lh,
18951 ICLASS_ae_iclass_mulzsafq32sp16s_lh,
18952 ICLASS_ae_iclass_mulzsaq32sp16u_lh,
18953 ICLASS_ae_iclass_mulzsafq32sp16u_lh,
18954 ICLASS_ae_iclass_mulzssq32sp16s_ll,
18955 ICLASS_ae_iclass_mulzssfq32sp16s_ll,
18956 ICLASS_ae_iclass_mulzssq32sp16u_ll,
18957 ICLASS_ae_iclass_mulzssfq32sp16u_ll,
18958 ICLASS_ae_iclass_mulzssq32sp16s_hh,
18959 ICLASS_ae_iclass_mulzssfq32sp16s_hh,
18960 ICLASS_ae_iclass_mulzssq32sp16u_hh,
18961 ICLASS_ae_iclass_mulzssfq32sp16u_hh,
18962 ICLASS_ae_iclass_mulzssq32sp16s_lh,
18963 ICLASS_ae_iclass_mulzssfq32sp16s_lh,
18964 ICLASS_ae_iclass_mulzssq32sp16u_lh,
18965 ICLASS_ae_iclass_mulzssfq32sp16u_lh,
18966 ICLASS_ae_iclass_mulzaafp24s_hh_ll,
18967 ICLASS_ae_iclass_mulzaap24s_hh_ll,
18968 ICLASS_ae_iclass_mulzaafp24s_hl_lh,
18969 ICLASS_ae_iclass_mulzaap24s_hl_lh,
18970 ICLASS_ae_iclass_mulzasfp24s_hh_ll,
18971 ICLASS_ae_iclass_mulzasp24s_hh_ll,
18972 ICLASS_ae_iclass_mulzasfp24s_hl_lh,
18973 ICLASS_ae_iclass_mulzasp24s_hl_lh,
18974 ICLASS_ae_iclass_mulzsafp24s_hh_ll,
18975 ICLASS_ae_iclass_mulzsap24s_hh_ll,
18976 ICLASS_ae_iclass_mulzsafp24s_hl_lh,
18977 ICLASS_ae_iclass_mulzsap24s_hl_lh,
18978 ICLASS_ae_iclass_mulzssfp24s_hh_ll,
18979 ICLASS_ae_iclass_mulzssp24s_hh_ll,
18980 ICLASS_ae_iclass_mulzssfp24s_hl_lh,
18981 ICLASS_ae_iclass_mulzssp24s_hl_lh,
18982 ICLASS_ae_iclass_mulaafp24s_hh_ll,
18983 ICLASS_ae_iclass_mulaap24s_hh_ll,
18984 ICLASS_ae_iclass_mulaafp24s_hl_lh,
18985 ICLASS_ae_iclass_mulaap24s_hl_lh,
18986 ICLASS_ae_iclass_mulasfp24s_hh_ll,
18987 ICLASS_ae_iclass_mulasp24s_hh_ll,
18988 ICLASS_ae_iclass_mulasfp24s_hl_lh,
18989 ICLASS_ae_iclass_mulasp24s_hl_lh,
18990 ICLASS_ae_iclass_mulsafp24s_hh_ll,
18991 ICLASS_ae_iclass_mulsap24s_hh_ll,
18992 ICLASS_ae_iclass_mulsafp24s_hl_lh,
18993 ICLASS_ae_iclass_mulsap24s_hl_lh,
18994 ICLASS_ae_iclass_mulssfp24s_hh_ll,
18995 ICLASS_ae_iclass_mulssp24s_hh_ll,
18996 ICLASS_ae_iclass_mulssfp24s_hl_lh,
18997 ICLASS_ae_iclass_mulssp24s_hl_lh,
18998 ICLASS_ae_iclass_sha32,
18999 ICLASS_ae_iclass_vldl32t,
19000 ICLASS_ae_iclass_vldl16t,
19001 ICLASS_ae_iclass_vldl16c,
19002 ICLASS_ae_iclass_vldsht,
19003 ICLASS_ae_iclass_lb,
19004 ICLASS_ae_iclass_lbi,
19005 ICLASS_ae_iclass_lbk,
19006 ICLASS_ae_iclass_lbki,
19007 ICLASS_ae_iclass_db,
19008 ICLASS_ae_iclass_dbi,
19009 ICLASS_ae_iclass_vlel32t,
19010 ICLASS_ae_iclass_vlel16t,
19011 ICLASS_ae_iclass_sb,
19012 ICLASS_ae_iclass_sbi,
19013 ICLASS_ae_iclass_vles16c,
19014 ICLASS_ae_iclass_sbf
19018 /* Opcode encodings. */
19021 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
19023 slotbuf[0] = 0x2080;
19027 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
19029 slotbuf[0] = 0x3000;
19033 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
19035 slotbuf[0] = 0x3200;
19039 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19041 slotbuf[0] = 0x5000;
19045 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
19051 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19057 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19063 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
19069 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19075 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19081 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
19087 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
19089 slotbuf[0] = 0x1000;
19093 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
19095 slotbuf[0] = 0x408000;
19099 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
19105 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19107 slotbuf[0] = 0xf01d;
19111 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
19113 slotbuf[0] = 0x3400;
19117 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
19119 slotbuf[0] = 0x3500;
19123 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
19125 slotbuf[0] = 0x90000;
19129 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
19131 slotbuf[0] = 0x490000;
19135 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
19137 slotbuf[0] = 0x34800;
19141 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
19143 slotbuf[0] = 0x134800;
19147 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
19149 slotbuf[0] = 0x614800;
19153 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
19155 slotbuf[0] = 0x34900;
19159 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
19161 slotbuf[0] = 0x134900;
19165 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
19167 slotbuf[0] = 0x614900;
19171 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19177 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19183 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19189 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19195 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19197 slotbuf[0] = 0xf06d;
19201 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19207 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19213 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19219 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19221 slotbuf[0] = 0xf03d;
19225 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
19227 slotbuf[0] = 0xf00d;
19231 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
19237 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
19239 slotbuf[0] = 0xe30e70;
19243 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
19245 slotbuf[0] = 0xf3e700;
19249 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19251 slotbuf[0] = 0xc002;
19255 Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19257 slotbuf[0] = 0x200040;
19261 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19263 slotbuf[0] = 0xd002;
19267 Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19269 slotbuf[0] = 0x200080;
19273 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
19275 slotbuf[0] = 0x800000;
19279 Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19281 slotbuf[0] = 0x1b2000;
19285 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
19287 slotbuf[0] = 0xc00000;
19291 Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19293 slotbuf[0] = 0x1ca000;
19297 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
19299 slotbuf[0] = 0x900000;
19303 Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19305 slotbuf[0] = 0x1b4000;
19309 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19311 slotbuf[0] = 0xa00000;
19315 Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19317 slotbuf[0] = 0x1b8000;
19321 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19323 slotbuf[0] = 0xb00000;
19327 Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19329 slotbuf[0] = 0x1b3000;
19333 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
19335 slotbuf[0] = 0xd00000;
19339 Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19341 slotbuf[0] = 0x1cc000;
19345 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
19347 slotbuf[0] = 0xe00000;
19351 Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19353 slotbuf[0] = 0x1cb000;
19357 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
19359 slotbuf[0] = 0xf00000;
19363 Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19365 slotbuf[0] = 0x1cd000;
19369 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
19371 slotbuf[0] = 0x100000;
19375 Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19377 slotbuf[0] = 0x1b5000;
19381 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
19383 slotbuf[0] = 0x200000;
19387 Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19389 slotbuf[0] = 0x1e0000;
19393 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
19395 slotbuf[0] = 0x300000;
19399 Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19401 slotbuf[0] = 0x1ce000;
19405 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19411 Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19413 slotbuf[0] = 0x300000;
19417 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
19423 Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19425 slotbuf[0] = 0x300003;
19429 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
19435 Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19437 slotbuf[0] = 0x300001;
19441 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
19447 Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19449 slotbuf[0] = 0x300004;
19453 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
19455 slotbuf[0] = 0x6007;
19459 Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19461 slotbuf[0] = 0x200000;
19465 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19467 slotbuf[0] = 0xe007;
19471 Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19473 slotbuf[0] = 0x200020;
19477 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19483 Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19485 slotbuf[0] = 0x300002;
19489 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19495 Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19497 slotbuf[0] = 0x300008;
19501 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
19503 slotbuf[0] = 0x1007;
19507 Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19509 slotbuf[0] = 0x2000a0;
19513 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
19515 slotbuf[0] = 0x9007;
19519 Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19521 slotbuf[0] = 0x400000;
19525 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
19527 slotbuf[0] = 0xa007;
19531 Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19533 slotbuf[0] = 0x2000c0;
19537 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
19539 slotbuf[0] = 0x2007;
19543 Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19545 slotbuf[0] = 0x2000d0;
19549 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
19551 slotbuf[0] = 0xb007;
19555 Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19557 slotbuf[0] = 0x2000b0;
19561 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
19563 slotbuf[0] = 0x3007;
19567 Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19569 slotbuf[0] = 0x2000e0;
19573 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
19575 slotbuf[0] = 0x8007;
19579 Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19581 slotbuf[0] = 0x200060;
19585 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
19591 Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19593 slotbuf[0] = 0x400010;
19597 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
19599 slotbuf[0] = 0x4007;
19603 Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19605 slotbuf[0] = 0x200050;
19609 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19611 slotbuf[0] = 0xc007;
19615 Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19617 slotbuf[0] = 0x2000f0;
19621 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
19623 slotbuf[0] = 0x5007;
19627 Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19629 slotbuf[0] = 0x200070;
19633 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
19635 slotbuf[0] = 0xd007;
19639 Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19641 slotbuf[0] = 0x200090;
19645 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19651 Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19653 slotbuf[0] = 0x180000;
19657 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19663 Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19665 slotbuf[0] = 0x190000;
19669 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19675 Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19677 slotbuf[0] = 0x160000;
19681 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19687 Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19689 slotbuf[0] = 0x170000;
19693 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
19699 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
19705 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19707 slotbuf[0] = 0x40000;
19711 Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19713 slotbuf[0] = 0x140000;
19717 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
19723 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
19729 Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19731 slotbuf[0] = 0x100000;
19735 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
19741 Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19743 slotbuf[0] = 0x1ee031;
19747 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19749 slotbuf[0] = 0x1002;
19753 Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19755 slotbuf[0] = 0x400040;
19759 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
19761 slotbuf[0] = 0x9002;
19765 Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19767 slotbuf[0] = 0x400020;
19771 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19773 slotbuf[0] = 0x2002;
19777 Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19779 slotbuf[0] = 0x400080;
19783 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
19789 Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19791 slotbuf[0] = 0x500000;
19795 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
19801 Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19803 slotbuf[0] = 0x400030;
19807 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
19809 slotbuf[0] = 0x8076;
19813 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19815 slotbuf[0] = 0x9076;
19819 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19821 slotbuf[0] = 0xa076;
19825 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
19827 slotbuf[0] = 0xa002;
19831 Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19833 slotbuf[0] = 0x1a0000;
19837 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19839 slotbuf[0] = 0x830000;
19843 Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19845 slotbuf[0] = 0x1be000;
19849 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19851 slotbuf[0] = 0x930000;
19855 Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19857 slotbuf[0] = 0x1c8000;
19861 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
19863 slotbuf[0] = 0xa30000;
19867 Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19869 slotbuf[0] = 0x1c4000;
19873 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
19875 slotbuf[0] = 0xb30000;
19879 Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19881 slotbuf[0] = 0x1c2000;
19885 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
19887 slotbuf[0] = 0x600000;
19891 Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19893 slotbuf[0] = 0x1f1d00;
19897 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
19899 slotbuf[0] = 0x600100;
19903 Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19905 slotbuf[0] = 0x1f1c00;
19909 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
19911 slotbuf[0] = 0x20f0;
19915 Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
19917 slotbuf[0] = 0x16105;
19921 Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19923 slotbuf[0] = 0x1ee0b1;
19927 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
19933 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19935 slotbuf[0] = 0x5100;
19939 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19941 slotbuf[0] = 0x5002;
19945 Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19947 slotbuf[0] = 0x400050;
19951 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19953 slotbuf[0] = 0x6002;
19957 Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19959 slotbuf[0] = 0x400060;
19963 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
19965 slotbuf[0] = 0x4002;
19969 Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19971 slotbuf[0] = 0x400070;
19975 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
19977 slotbuf[0] = 0x400000;
19981 Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19983 slotbuf[0] = 0x1ee071;
19987 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
19989 slotbuf[0] = 0x401000;
19993 Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
19995 slotbuf[0] = 0x1ee038;
19999 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
20001 slotbuf[0] = 0x402000;
20005 Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20007 slotbuf[0] = 0x1ee034;
20011 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
20013 slotbuf[0] = 0x403000;
20017 Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20019 slotbuf[0] = 0x1ee032;
20023 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
20025 slotbuf[0] = 0x404000;
20029 Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20031 slotbuf[0] = 0x1ef0a0;
20035 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
20037 slotbuf[0] = 0xa10000;
20041 Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20043 slotbuf[0] = 0x1f5003;
20047 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
20049 slotbuf[0] = 0x810000;
20053 Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20055 slotbuf[0] = 0x1c7000;
20059 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
20061 slotbuf[0] = 0x910000;
20065 Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20067 slotbuf[0] = 0x1f1f00;
20071 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
20073 slotbuf[0] = 0xb10000;
20077 Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20079 slotbuf[0] = 0x1f1e00;
20083 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
20085 slotbuf[0] = 0x10000;
20089 Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20091 slotbuf[0] = 0x1c0000;
20095 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
20097 slotbuf[0] = 0x210000;
20101 Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20103 slotbuf[0] = 0x1b0000;
20107 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
20109 slotbuf[0] = 0x410000;
20113 Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20115 slotbuf[0] = 0x1c9000;
20119 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20121 slotbuf[0] = 0x20c0;
20125 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20127 slotbuf[0] = 0x20d0;
20131 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20133 slotbuf[0] = 0x2000;
20137 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20139 slotbuf[0] = 0x2010;
20143 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20145 slotbuf[0] = 0x2020;
20149 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
20151 slotbuf[0] = 0x2030;
20155 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
20157 slotbuf[0] = 0x6000;
20161 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
20163 slotbuf[0] = 0x30100;
20167 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
20169 slotbuf[0] = 0x130100;
20173 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
20175 slotbuf[0] = 0x610100;
20179 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20181 slotbuf[0] = 0x30200;
20185 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20187 slotbuf[0] = 0x130200;
20191 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20193 slotbuf[0] = 0x610200;
20197 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
20199 slotbuf[0] = 0x30000;
20203 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
20205 slotbuf[0] = 0x130000;
20209 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
20211 slotbuf[0] = 0x610000;
20215 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
20217 slotbuf[0] = 0x30300;
20221 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
20223 slotbuf[0] = 0x130300;
20227 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
20229 slotbuf[0] = 0x610300;
20233 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20235 slotbuf[0] = 0x30500;
20239 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20241 slotbuf[0] = 0x130500;
20245 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20247 slotbuf[0] = 0x610500;
20251 Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20253 slotbuf[0] = 0x3b000;
20257 Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20259 slotbuf[0] = 0x13b000;
20263 Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20265 slotbuf[0] = 0x3d000;
20269 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
20271 slotbuf[0] = 0x3e600;
20275 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
20277 slotbuf[0] = 0x13e600;
20281 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
20283 slotbuf[0] = 0x61e600;
20287 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20289 slotbuf[0] = 0x3b100;
20293 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20295 slotbuf[0] = 0x13b100;
20299 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20301 slotbuf[0] = 0x61b100;
20305 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20307 slotbuf[0] = 0x3d100;
20311 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20313 slotbuf[0] = 0x13d100;
20317 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20319 slotbuf[0] = 0x61d100;
20323 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20325 slotbuf[0] = 0x3b200;
20329 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20331 slotbuf[0] = 0x13b200;
20335 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20337 slotbuf[0] = 0x61b200;
20341 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20343 slotbuf[0] = 0x3d200;
20347 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20349 slotbuf[0] = 0x13d200;
20353 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20355 slotbuf[0] = 0x61d200;
20359 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20361 slotbuf[0] = 0x3c200;
20365 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20367 slotbuf[0] = 0x13c200;
20371 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
20373 slotbuf[0] = 0x61c200;
20377 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20379 slotbuf[0] = 0x3ee00;
20383 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20385 slotbuf[0] = 0x13ee00;
20389 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20391 slotbuf[0] = 0x61ee00;
20395 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20397 slotbuf[0] = 0x3c000;
20401 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20403 slotbuf[0] = 0x13c000;
20407 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20409 slotbuf[0] = 0x61c000;
20413 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20415 slotbuf[0] = 0x3e800;
20419 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20421 slotbuf[0] = 0x13e800;
20425 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20427 slotbuf[0] = 0x61e800;
20431 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20433 slotbuf[0] = 0x3f400;
20437 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20439 slotbuf[0] = 0x13f400;
20443 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20445 slotbuf[0] = 0x61f400;
20449 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20451 slotbuf[0] = 0x3f500;
20455 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20457 slotbuf[0] = 0x13f500;
20461 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20463 slotbuf[0] = 0x61f500;
20467 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
20469 slotbuf[0] = 0x3eb00;
20473 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20475 slotbuf[0] = 0x3e700;
20479 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20481 slotbuf[0] = 0x13e700;
20485 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
20487 slotbuf[0] = 0x61e700;
20491 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
20493 slotbuf[0] = 0xc10000;
20497 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
20499 slotbuf[0] = 0xd10000;
20503 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
20505 slotbuf[0] = 0x820000;
20509 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20511 slotbuf[0] = 0x3010;
20515 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
20517 slotbuf[0] = 0x7000;
20521 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
20523 slotbuf[0] = 0x3e200;
20527 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
20529 slotbuf[0] = 0x13e200;
20533 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
20535 slotbuf[0] = 0x13e300;
20539 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
20541 slotbuf[0] = 0x3e400;
20545 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
20547 slotbuf[0] = 0x13e400;
20551 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
20553 slotbuf[0] = 0x61e400;
20557 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
20559 slotbuf[0] = 0x4000;
20563 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
20565 slotbuf[0] = 0xf02d;
20569 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20571 slotbuf[0] = 0x3e900;
20575 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20577 slotbuf[0] = 0x13e900;
20581 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
20583 slotbuf[0] = 0x61e900;
20587 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20589 slotbuf[0] = 0x3ec00;
20593 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20595 slotbuf[0] = 0x13ec00;
20599 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20601 slotbuf[0] = 0x61ec00;
20605 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
20607 slotbuf[0] = 0x3ed00;
20611 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
20613 slotbuf[0] = 0x13ed00;
20617 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
20619 slotbuf[0] = 0x61ed00;
20623 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20625 slotbuf[0] = 0x36800;
20629 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20631 slotbuf[0] = 0x136800;
20635 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20637 slotbuf[0] = 0x616800;
20641 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
20643 slotbuf[0] = 0xf1e000;
20647 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
20649 slotbuf[0] = 0xf1e010;
20653 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20655 slotbuf[0] = 0x20000;
20659 Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20661 slotbuf[0] = 0x1b6000;
20665 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20667 slotbuf[0] = 0x120000;
20671 Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20673 slotbuf[0] = 0x1b7000;
20677 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20679 slotbuf[0] = 0x220000;
20683 Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20685 slotbuf[0] = 0x1c3000;
20689 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
20691 slotbuf[0] = 0x320000;
20695 Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20697 slotbuf[0] = 0x1c5000;
20701 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20703 slotbuf[0] = 0x420000;
20707 Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20709 slotbuf[0] = 0x1cf000;
20713 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
20715 slotbuf[0] = 0x8000;
20719 Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20721 slotbuf[0] = 0x1f2480;
20725 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
20727 slotbuf[0] = 0x9000;
20731 Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20733 slotbuf[0] = 0x1f2800;
20737 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
20739 slotbuf[0] = 0xa000;
20743 Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20745 slotbuf[0] = 0x1ef060;
20749 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
20751 slotbuf[0] = 0xb000;
20755 Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20757 slotbuf[0] = 0x1ef020;
20761 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
20767 Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20769 slotbuf[0] = 0x300005;
20773 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
20775 slotbuf[0] = 0x1076;
20779 Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20781 slotbuf[0] = 0x300006;
20785 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
20787 slotbuf[0] = 0xc30000;
20791 Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20793 slotbuf[0] = 0x1bf000;
20797 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
20799 slotbuf[0] = 0xd30000;
20803 Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
20805 slotbuf[0] = 0x1d0000;
20809 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
20811 slotbuf[0] = 0x30400;
20815 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
20817 slotbuf[0] = 0x130400;
20821 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
20823 slotbuf[0] = 0x610400;
20827 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20829 slotbuf[0] = 0x3ea00;
20833 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20835 slotbuf[0] = 0x13ea00;
20839 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
20841 slotbuf[0] = 0x61ea00;
20845 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20847 slotbuf[0] = 0x3f000;
20851 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20853 slotbuf[0] = 0x13f000;
20857 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20859 slotbuf[0] = 0x61f000;
20863 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20865 slotbuf[0] = 0x3f100;
20869 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20871 slotbuf[0] = 0x13f100;
20875 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20877 slotbuf[0] = 0x61f100;
20881 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
20883 slotbuf[0] = 0x70c2;
20887 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20889 slotbuf[0] = 0x70e2;
20893 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
20895 slotbuf[0] = 0x70f2;
20899 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
20901 slotbuf[0] = 0xf10000;
20905 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20907 slotbuf[0] = 0xf12000;
20911 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
20913 slotbuf[0] = 0xf11000;
20917 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20919 slotbuf[0] = 0xf13000;
20923 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20925 slotbuf[0] = 0x7042;
20929 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20931 slotbuf[0] = 0x7052;
20935 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
20937 slotbuf[0] = 0x47082;
20941 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20943 slotbuf[0] = 0x57082;
20947 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
20949 slotbuf[0] = 0x7062;
20953 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
20955 slotbuf[0] = 0x7072;
20959 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20961 slotbuf[0] = 0x7002;
20965 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
20967 slotbuf[0] = 0x7012;
20971 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
20973 slotbuf[0] = 0x7022;
20977 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
20979 slotbuf[0] = 0x7032;
20983 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
20985 slotbuf[0] = 0xf19000;
20989 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
20991 slotbuf[0] = 0xf18000;
20995 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
20997 slotbuf[0] = 0x135300;
21001 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21003 slotbuf[0] = 0x35300;
21007 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21009 slotbuf[0] = 0x615300;
21013 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
21015 slotbuf[0] = 0x35a00;
21019 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
21021 slotbuf[0] = 0x135a00;
21025 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
21027 slotbuf[0] = 0x615a00;
21031 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21033 slotbuf[0] = 0x35b00;
21037 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21039 slotbuf[0] = 0x135b00;
21043 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21045 slotbuf[0] = 0x615b00;
21049 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21051 slotbuf[0] = 0x35c00;
21055 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21057 slotbuf[0] = 0x135c00;
21061 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
21063 slotbuf[0] = 0x615c00;
21067 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21069 slotbuf[0] = 0x50c000;
21073 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21075 slotbuf[0] = 0x50d000;
21079 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21081 slotbuf[0] = 0x50b000;
21085 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21087 slotbuf[0] = 0x50f000;
21091 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21093 slotbuf[0] = 0x50e000;
21097 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21099 slotbuf[0] = 0x504000;
21103 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21105 slotbuf[0] = 0x505000;
21109 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21111 slotbuf[0] = 0x503000;
21115 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21117 slotbuf[0] = 0x507000;
21121 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
21123 slotbuf[0] = 0x506000;
21127 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
21129 slotbuf[0] = 0xf1f000;
21133 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
21135 slotbuf[0] = 0x501000;
21139 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
21141 slotbuf[0] = 0x509000;
21145 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
21147 slotbuf[0] = 0x3e000;
21151 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
21153 slotbuf[0] = 0x13e000;
21157 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
21159 slotbuf[0] = 0x61e000;
21163 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
21165 slotbuf[0] = 0x330000;
21169 Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21171 slotbuf[0] = 0x1b9000;
21175 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
21177 slotbuf[0] = 0x430000;
21181 Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21183 slotbuf[0] = 0x1bb000;
21187 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
21189 slotbuf[0] = 0x530000;
21193 Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21195 slotbuf[0] = 0x1ba000;
21199 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21201 slotbuf[0] = 0x630000;
21205 Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21207 slotbuf[0] = 0x1bd000;
21211 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21213 slotbuf[0] = 0x730000;
21217 Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21219 slotbuf[0] = 0x1bc000;
21223 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
21225 slotbuf[0] = 0x40e000;
21229 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
21231 slotbuf[0] = 0x40f000;
21235 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
21237 slotbuf[0] = 0x230000;
21241 Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21243 slotbuf[0] = 0x1c6000;
21247 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
21249 slotbuf[0] = 0xb002;
21253 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
21255 slotbuf[0] = 0xf002;
21259 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21261 slotbuf[0] = 0xe002;
21265 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21267 slotbuf[0] = 0x30c00;
21271 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21273 slotbuf[0] = 0x130c00;
21277 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
21279 slotbuf[0] = 0x610c00;
21283 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
21285 slotbuf[0] = 0x36300;
21289 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
21291 slotbuf[0] = 0x136300;
21295 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
21297 slotbuf[0] = 0x616300;
21301 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
21303 slotbuf[0] = 0x406000;
21307 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
21309 slotbuf[0] = 0x407000;
21313 Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21315 slotbuf[0] = 0xe30f00;
21319 Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21321 slotbuf[0] = 0xf3f000;
21325 Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
21327 slotbuf[0] = 0xe30f10;
21331 Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
21333 slotbuf[0] = 0xf3f100;
21337 Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21339 slotbuf[0] = 0xe30f20;
21343 Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21345 slotbuf[0] = 0xf3f200;
21349 Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
21351 slotbuf[0] = 0xe30f30;
21355 Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
21357 slotbuf[0] = 0xf3f300;
21361 Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
21363 slotbuf[0] = 0xc90804;
21367 Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
21369 slotbuf[0] = 0xca0004;
21373 Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21375 slotbuf[0] = 0xc90904;
21379 Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
21381 slotbuf[0] = 0xca1004;
21385 Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21387 slotbuf[0] = 0xc90a04;
21391 Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21393 slotbuf[0] = 0xca2004;
21397 Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
21399 slotbuf[0] = 0xc90b04;
21403 Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
21405 slotbuf[0] = 0xca3004;
21409 Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
21411 slotbuf[0] = 0xc90c04;
21415 Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
21417 slotbuf[0] = 0xca4004;
21421 Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
21423 slotbuf[0] = 0xc90d04;
21427 Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
21429 slotbuf[0] = 0xca5004;
21433 Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
21435 slotbuf[0] = 0xc90e04;
21439 Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
21441 slotbuf[0] = 0xca6004;
21445 Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21447 slotbuf[0] = 0xc90f04;
21451 Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21453 slotbuf[0] = 0xca7004;
21457 Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21459 slotbuf[0] = 0x1d1080;
21463 Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21465 slotbuf[0] = 0xa50004;
21469 Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21471 slotbuf[0] = 0x1d2080;
21475 Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21477 slotbuf[0] = 0xa90004;
21481 Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21483 slotbuf[0] = 0x1d3000;
21487 Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21489 slotbuf[0] = 0xac0004;
21493 Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21495 slotbuf[0] = 0x1d3080;
21499 Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21501 slotbuf[0] = 0xaf0004;
21505 Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21507 slotbuf[0] = 0x1d6080;
21511 Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21513 slotbuf[0] = 0xa58004;
21517 Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21519 slotbuf[0] = 0x1d7000;
21523 Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21525 slotbuf[0] = 0xa98004;
21529 Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21531 slotbuf[0] = 0x1d7080;
21535 Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21537 slotbuf[0] = 0xac8004;
21541 Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21543 slotbuf[0] = 0x1d8080;
21547 Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21549 slotbuf[0] = 0xaf8004;
21553 Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21555 slotbuf[0] = 0x1d9000;
21559 Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21561 slotbuf[0] = 0xa60004;
21565 Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21567 slotbuf[0] = 0x1da000;
21571 Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21573 slotbuf[0] = 0xaa0004;
21577 Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21579 slotbuf[0] = 0x1dc000;
21583 Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21585 slotbuf[0] = 0xad0004;
21589 Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21591 slotbuf[0] = 0x1d9080;
21595 Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21597 slotbuf[0] = 0xb00004;
21601 Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21603 slotbuf[0] = 0x1d4080;
21607 Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21609 slotbuf[0] = 0xa68004;
21613 Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21615 slotbuf[0] = 0x1d5000;
21619 Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21621 slotbuf[0] = 0xaa8004;
21625 Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21627 slotbuf[0] = 0x1d6000;
21631 Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21633 slotbuf[0] = 0xad8004;
21637 Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21639 slotbuf[0] = 0x1d5080;
21643 Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21645 slotbuf[0] = 0xb08004;
21649 Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21651 slotbuf[0] = 0x1dd000;
21655 Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21657 slotbuf[0] = 0xa70004;
21661 Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21663 slotbuf[0] = 0x1de000;
21667 Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21669 slotbuf[0] = 0xab0004;
21673 Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21675 slotbuf[0] = 0x1dd080;
21679 Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21681 slotbuf[0] = 0xae0004;
21685 Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21687 slotbuf[0] = 0x1de080;
21691 Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21693 slotbuf[0] = 0xb10004;
21697 Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21699 slotbuf[0] = 0x1da080;
21703 Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21705 slotbuf[0] = 0xa78004;
21709 Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21711 slotbuf[0] = 0x1db000;
21715 Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21717 slotbuf[0] = 0xab8004;
21721 Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21723 slotbuf[0] = 0x1db080;
21727 Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21729 slotbuf[0] = 0xae8004;
21733 Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21735 slotbuf[0] = 0x1dc080;
21739 Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21741 slotbuf[0] = 0xb18004;
21745 Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21747 slotbuf[0] = 0x1e8000;
21751 Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21753 slotbuf[0] = 0xb20004;
21757 Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21759 slotbuf[0] = 0x1f0000;
21763 Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21765 slotbuf[0] = 0xb50004;
21769 Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21771 slotbuf[0] = 0x1e1080;
21775 Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21777 slotbuf[0] = 0xb80004;
21781 Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21783 slotbuf[0] = 0x1e2080;
21787 Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21789 slotbuf[0] = 0xbb0004;
21793 Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21795 slotbuf[0] = 0x1ec000;
21799 Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21801 slotbuf[0] = 0xb28004;
21805 Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21807 slotbuf[0] = 0x1e9080;
21811 Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21813 slotbuf[0] = 0xb58004;
21817 Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21819 slotbuf[0] = 0x1ea080;
21823 Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21825 slotbuf[0] = 0xb88004;
21829 Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21831 slotbuf[0] = 0x1eb000;
21835 Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21837 slotbuf[0] = 0xbb8004;
21841 Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21843 slotbuf[0] = 0x1e7080;
21847 Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21849 slotbuf[0] = 0xb30004;
21853 Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21855 slotbuf[0] = 0x1e8080;
21859 Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21861 slotbuf[0] = 0xb60004;
21865 Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21867 slotbuf[0] = 0x1e9000;
21871 Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21873 slotbuf[0] = 0xb90004;
21877 Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21879 slotbuf[0] = 0x1ea000;
21883 Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21885 slotbuf[0] = 0xbc0004;
21889 Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21891 slotbuf[0] = 0x1df080;
21895 Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21897 slotbuf[0] = 0xb38004;
21901 Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21903 slotbuf[0] = 0x1e1000;
21907 Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21909 slotbuf[0] = 0xb68004;
21913 Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21915 slotbuf[0] = 0x1e2000;
21919 Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21921 slotbuf[0] = 0xb98004;
21925 Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21927 slotbuf[0] = 0x1e4000;
21931 Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21933 slotbuf[0] = 0xbc8004;
21937 Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21939 slotbuf[0] = 0x1e6000;
21943 Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21945 slotbuf[0] = 0xb40004;
21949 Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21951 slotbuf[0] = 0x1e5080;
21955 Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21957 slotbuf[0] = 0xb70004;
21961 Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21963 slotbuf[0] = 0x1e6080;
21967 Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
21969 slotbuf[0] = 0xba0004;
21973 Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21975 slotbuf[0] = 0x1e7000;
21979 Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21981 slotbuf[0] = 0xbd0004;
21985 Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21987 slotbuf[0] = 0x1e3000;
21991 Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21993 slotbuf[0] = 0xb48004;
21997 Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
21999 slotbuf[0] = 0x1e3080;
22003 Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22005 slotbuf[0] = 0xb78004;
22009 Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22011 slotbuf[0] = 0x1e4080;
22015 Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22017 slotbuf[0] = 0xba8004;
22021 Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22023 slotbuf[0] = 0x1e5000;
22027 Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22029 slotbuf[0] = 0xbd8004;
22033 Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22035 slotbuf[0] = 0x1ed030;
22039 Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22041 slotbuf[0] = 0xc10004;
22045 Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22047 slotbuf[0] = 0x1ee010;
22051 Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22053 slotbuf[0] = 0xc12004;
22057 Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22059 slotbuf[0] = 0x1ee020;
22063 Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22065 slotbuf[0] = 0xc20004;
22069 Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22071 slotbuf[0] = 0x1ef000;
22075 Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22077 slotbuf[0] = 0xc22004;
22081 Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22083 slotbuf[0] = 0x1ed000;
22087 Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22089 slotbuf[0] = 0xc11004;
22093 Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22095 slotbuf[0] = 0x1ee000;
22099 Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22101 slotbuf[0] = 0xc13004;
22105 Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22107 slotbuf[0] = 0x1ed010;
22111 Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22113 slotbuf[0] = 0xc21004;
22117 Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22119 slotbuf[0] = 0x1ed020;
22123 Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22125 slotbuf[0] = 0xc23004;
22129 Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22131 slotbuf[0] = 0x1f0080;
22135 Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22137 slotbuf[0] = 0xc30004;
22141 Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22143 slotbuf[0] = 0x1f00c0;
22147 Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22149 slotbuf[0] = 0xc38004;
22153 Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22155 slotbuf[0] = 0x1f3000;
22159 Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22161 slotbuf[0] = 0xc40004;
22165 Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22167 slotbuf[0] = 0x1f3040;
22171 Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22173 slotbuf[0] = 0xc48004;
22177 Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22179 slotbuf[0] = 0x1ec080;
22183 Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22185 slotbuf[0] = 0xc34004;
22189 Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22191 slotbuf[0] = 0x1ec0c0;
22195 Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22197 slotbuf[0] = 0xc3c004;
22201 Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22203 slotbuf[0] = 0x1f4000;
22207 Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
22209 slotbuf[0] = 0xc44004;
22213 Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22215 slotbuf[0] = 0x1f8000;
22219 Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
22221 slotbuf[0] = 0xc4c004;
22225 Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22227 slotbuf[0] = 0x16b88;
22231 Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22233 slotbuf[0] = 0x16808;
22237 Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22239 slotbuf[0] = 0x1f2400;
22243 Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
22245 slotbuf[0] = 0xc90004;
22249 Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22251 slotbuf[0] = 0x10780;
22255 Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22257 slotbuf[0] = 0x10708;
22261 Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22263 slotbuf[0] = 0x10688;
22267 Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22269 slotbuf[0] = 0x10700;
22273 Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22275 slotbuf[0] = 0x1c200;
22279 Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22281 slotbuf[0] = 0x1c004;
22285 Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22287 slotbuf[0] = 0x10480;
22291 Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22293 slotbuf[0] = 0x10400;
22297 Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22299 slotbuf[0] = 0x1df000;
22303 Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22305 slotbuf[0] = 0xc00004;
22309 Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22311 slotbuf[0] = 0x1eb080;
22315 Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22317 slotbuf[0] = 0xc08004;
22321 Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22323 slotbuf[0] = 0x1f3081;
22327 Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22329 slotbuf[0] = 0xcb0004;
22333 Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22335 slotbuf[0] = 0x1f3080;
22339 Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
22341 slotbuf[0] = 0xcb8004;
22345 Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22347 slotbuf[0] = 0x1d8000;
22351 Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
22353 slotbuf[0] = 0xbe0004;
22357 Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22359 slotbuf[0] = 0x1d4000;
22363 Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
22365 slotbuf[0] = 0xbe8004;
22369 Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22371 slotbuf[0] = 0x1d2000;
22375 Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22377 slotbuf[0] = 0xbf0004;
22381 Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22383 slotbuf[0] = 0x1d1000;
22387 Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
22389 slotbuf[0] = 0xbf8004;
22393 Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22395 slotbuf[0] = 0x51000;
22399 Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22401 slotbuf[0] = 0x16b08;
22405 Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22407 slotbuf[0] = 0x16e48;
22411 Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22413 slotbuf[0] = 0x16e28;
22417 Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22419 slotbuf[0] = 0x16e18;
22423 Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22425 slotbuf[0] = 0x16e08;
22429 Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22431 slotbuf[0] = 0x16908;
22435 Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22437 slotbuf[0] = 0x16888;
22441 Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22443 slotbuf[0] = 0x16085;
22447 Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22449 slotbuf[0] = 0x16007;
22453 Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22455 slotbuf[0] = 0x1f2500;
22459 Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22461 slotbuf[0] = 0xc90414;
22465 Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22467 slotbuf[0] = 0x1f6000;
22471 Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22473 slotbuf[0] = 0xe50014;
22477 Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22479 slotbuf[0] = 0x1f5000;
22483 Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22485 slotbuf[0] = 0xe60014;
22489 Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22491 slotbuf[0] = 0x1ee030;
22495 Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22497 slotbuf[0] = 0xe72034;
22501 Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22503 slotbuf[0] = 0x16006;
22507 Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22509 slotbuf[0] = 0x16005;
22513 Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22515 slotbuf[0] = 0x50139;
22519 Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22521 slotbuf[0] = 0x16047;
22525 Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22527 slotbuf[0] = 0x16027;
22531 Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22533 slotbuf[0] = 0x16017;
22537 Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22539 slotbuf[0] = 0x1f3086;
22543 Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
22545 slotbuf[0] = 0xe70014;
22549 Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22551 slotbuf[0] = 0x1f3084;
22555 Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22557 slotbuf[0] = 0xc70004;
22561 Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22563 slotbuf[0] = 0x1f3082;
22567 Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
22569 slotbuf[0] = 0xc78004;
22573 Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22575 slotbuf[0] = 0x1f3083;
22579 Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22581 slotbuf[0] = 0xc80004;
22585 Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22587 slotbuf[0] = 0x1f3088;
22591 Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
22593 slotbuf[0] = 0xc88004;
22597 Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22599 slotbuf[0] = 0x10500;
22603 Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22605 slotbuf[0] = 0x10788;
22609 Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22611 slotbuf[0] = 0x1c600;
22615 Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22617 slotbuf[0] = 0x1c480;
22621 Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22623 slotbuf[0] = 0x10580;
22627 Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22629 slotbuf[0] = 0x10588;
22633 Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22635 slotbuf[0] = 0x10000;
22639 Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22641 slotbuf[0] = 0x10200;
22645 Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22647 slotbuf[0] = 0x10600;
22651 Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22653 slotbuf[0] = 0x1c400;
22657 Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22659 slotbuf[0] = 0x1c488;
22663 Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22665 slotbuf[0] = 0x1c500;
22669 Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22671 slotbuf[0] = 0x10508;
22675 Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22677 slotbuf[0] = 0x10608;
22681 Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22683 slotbuf[0] = 0x10680;
22687 Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22689 slotbuf[0] = 0x1c408;
22693 Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22695 slotbuf[0] = 0x1c002;
22699 Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22701 slotbuf[0] = 0x1c001;
22705 Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22707 slotbuf[0] = 0x1c000;
22711 Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22713 slotbuf[0] = 0x52000;
22717 Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22719 slotbuf[0] = 0x50035;
22723 Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22725 slotbuf[0] = 0x5003c;
22729 Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22731 slotbuf[0] = 0x50039;
22735 Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22737 slotbuf[0] = 0x50032;
22741 Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22743 slotbuf[0] = 0x50034;
22747 Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22749 slotbuf[0] = 0x50000;
22753 Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22755 slotbuf[0] = 0x50010;
22759 Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22761 slotbuf[0] = 0x50030;
22765 Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22767 slotbuf[0] = 0x50036;
22771 Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22773 slotbuf[0] = 0x500b9;
22777 Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22779 slotbuf[0] = 0x5003a;
22783 Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22785 slotbuf[0] = 0x50031;
22789 Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22791 slotbuf[0] = 0x50038;
22795 Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22797 slotbuf[0] = 0x50033;
22801 Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22803 slotbuf[0] = 0x50037;
22807 Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22809 slotbuf[0] = 0x14000;
22813 Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22815 slotbuf[0] = 0x15000;
22819 Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22821 slotbuf[0] = 0x14800;
22825 Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22827 slotbuf[0] = 0x16a08;
22831 Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22833 slotbuf[0] = 0x16a88;
22837 Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22839 slotbuf[0] = 0x16988;
22843 Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22845 slotbuf[0] = 0x18000;
22849 Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
22851 slotbuf[0] = 0x16c08;
22855 Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22857 slotbuf[0] = 0x1f1000;
22861 Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22863 slotbuf[0] = 0xc50004;
22867 Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22869 slotbuf[0] = 0x1f1800;
22873 Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22875 slotbuf[0] = 0xc50404;
22879 Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22881 slotbuf[0] = 0x1f1400;
22885 Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22887 slotbuf[0] = 0xc50804;
22891 Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22893 slotbuf[0] = 0x1f2600;
22897 Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22899 slotbuf[0] = 0xc90014;
22903 Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22905 slotbuf[0] = 0x1f2504;
22909 Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22911 slotbuf[0] = 0xc90114;
22915 Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22917 slotbuf[0] = 0x1f2502;
22921 Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22923 slotbuf[0] = 0xc90214;
22927 Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22929 slotbuf[0] = 0x1f5001;
22933 Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22935 slotbuf[0] = 0xe10014;
22939 Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22941 slotbuf[0] = 0x1f5008;
22945 Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22947 slotbuf[0] = 0xe20014;
22951 Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22953 slotbuf[0] = 0x1f5004;
22957 Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
22959 slotbuf[0] = 0xe30014;
22963 Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22965 slotbuf[0] = 0x1f2000;
22969 Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22971 slotbuf[0] = 0xc50c04;
22975 Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22977 slotbuf[0] = 0x1f2501;
22981 Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22983 slotbuf[0] = 0xc90314;
22987 Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
22989 slotbuf[0] = 0x1f5002;
22993 Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
22995 slotbuf[0] = 0xe40014;
22999 Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23001 slotbuf[0] = 0x50800;
23005 Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23007 slotbuf[0] = 0x50040;
23011 Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23013 slotbuf[0] = 0x50020;
23017 Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
23019 slotbuf[0] = 0x1f3085;
23023 Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
23025 slotbuf[0] = 0xe74014;
23029 Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23031 slotbuf[0] = 0x60101;
23035 Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23037 slotbuf[0] = 0x6008b;
23041 Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23043 slotbuf[0] = 0x60180;
23047 Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23049 slotbuf[0] = 0x6008f;
23053 Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23055 slotbuf[0] = 0x6008c;
23059 Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23061 slotbuf[0] = 0x60108;
23065 Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23067 slotbuf[0] = 0x6008e;
23071 Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23073 slotbuf[0] = 0x6008a;
23077 Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23079 slotbuf[0] = 0x60104;
23083 Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23085 slotbuf[0] = 0x6008d;
23089 Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23091 slotbuf[0] = 0x60089;
23095 Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23097 slotbuf[0] = 0x60102;
23101 Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23103 slotbuf[0] = 0x60006;
23107 Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23109 slotbuf[0] = 0x64000;
23113 Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23115 slotbuf[0] = 0x6000f;
23119 Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23121 slotbuf[0] = 0x60005;
23125 Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23127 slotbuf[0] = 0x60100;
23131 Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23133 slotbuf[0] = 0x6000e;
23137 Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23139 slotbuf[0] = 0x60003;
23143 Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23145 slotbuf[0] = 0x60080;
23149 Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23151 slotbuf[0] = 0x6000d;
23155 Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23157 slotbuf[0] = 0x68000;
23161 Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23163 slotbuf[0] = 0x60008;
23167 Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23169 slotbuf[0] = 0x6000b;
23173 Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23175 slotbuf[0] = 0x60181;
23179 Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23181 slotbuf[0] = 0x6010b;
23185 Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23187 slotbuf[0] = 0x60189;
23191 Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23193 slotbuf[0] = 0x6010f;
23197 Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23199 slotbuf[0] = 0x6010c;
23203 Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23205 slotbuf[0] = 0x60187;
23209 Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23211 slotbuf[0] = 0x6010e;
23215 Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23217 slotbuf[0] = 0x6010a;
23221 Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23223 slotbuf[0] = 0x60186;
23227 Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23229 slotbuf[0] = 0x6010d;
23233 Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23235 slotbuf[0] = 0x60109;
23239 Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23241 slotbuf[0] = 0x60185;
23245 Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23247 slotbuf[0] = 0x6000c;
23251 Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23253 slotbuf[0] = 0x60088;
23257 Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23259 slotbuf[0] = 0x6000a;
23263 Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23265 slotbuf[0] = 0x60084;
23269 Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23271 slotbuf[0] = 0x60009;
23275 Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23277 slotbuf[0] = 0x60082;
23281 Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23283 slotbuf[0] = 0x60007;
23287 Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23289 slotbuf[0] = 0x60081;
23293 Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23295 slotbuf[0] = 0x60183;
23299 Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23301 slotbuf[0] = 0x6018d;
23305 Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23307 slotbuf[0] = 0x60188;
23311 Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23313 slotbuf[0] = 0x6018b;
23317 Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23319 slotbuf[0] = 0x60184;
23323 Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23325 slotbuf[0] = 0x6018c;
23329 Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23331 slotbuf[0] = 0x60182;
23335 Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23337 slotbuf[0] = 0x6018a;
23341 Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23343 slotbuf[0] = 0x15807;
23347 Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23349 slotbuf[0] = 0x15806;
23353 Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23355 slotbuf[0] = 0x1580a;
23359 Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23361 slotbuf[0] = 0x15809;
23365 Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23367 slotbuf[0] = 0x1580b;
23371 Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23373 slotbuf[0] = 0x1580c;
23377 Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23379 slotbuf[0] = 0x1580e;
23383 Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23385 slotbuf[0] = 0x1580d;
23389 Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23391 slotbuf[0] = 0x15800;
23395 Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23397 slotbuf[0] = 0x16000;
23401 Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23403 slotbuf[0] = 0x15802;
23407 Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23409 slotbuf[0] = 0x15801;
23413 Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23415 slotbuf[0] = 0x15808;
23419 Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23421 slotbuf[0] = 0x15804;
23425 Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23427 slotbuf[0] = 0x15805;
23431 Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23433 slotbuf[0] = 0x15803;
23437 Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23439 slotbuf[0] = 0x16001;
23443 Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23445 slotbuf[0] = 0x1580f;
23449 Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23451 slotbuf[0] = 0x16004;
23455 Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23457 slotbuf[0] = 0x16002;
23461 Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23463 slotbuf[0] = 0x16800;
23467 Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23469 slotbuf[0] = 0x16008;
23473 Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23475 slotbuf[0] = 0x16003;
23479 Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23481 slotbuf[0] = 0x17000;
23485 Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23487 slotbuf[0] = 0x20007;
23491 Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23493 slotbuf[0] = 0x20002;
23497 Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23499 slotbuf[0] = 0x2000c;
23503 Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23505 slotbuf[0] = 0x20003;
23509 Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23511 slotbuf[0] = 0x20005;
23515 Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23517 slotbuf[0] = 0x20000;
23521 Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23523 slotbuf[0] = 0x20009;
23527 Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23529 slotbuf[0] = 0x20004;
23533 Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23535 slotbuf[0] = 0x20006;
23539 Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23541 slotbuf[0] = 0x20001;
23545 Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23547 slotbuf[0] = 0x2000a;
23551 Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23553 slotbuf[0] = 0x20008;
23557 Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23559 slotbuf[0] = 0x30008;
23563 Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23565 slotbuf[0] = 0x2000e;
23569 Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23571 slotbuf[0] = 0x30006;
23575 Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23577 slotbuf[0] = 0x30001;
23581 Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23583 slotbuf[0] = 0x30002;
23587 Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23589 slotbuf[0] = 0x2000b;
23593 Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23595 slotbuf[0] = 0x30003;
23599 Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23601 slotbuf[0] = 0x2000f;
23605 Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23607 slotbuf[0] = 0x30004;
23611 Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23613 slotbuf[0] = 0x2000d;
23617 Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23619 slotbuf[0] = 0x30005;
23623 Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23625 slotbuf[0] = 0x30000;
23629 Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23631 slotbuf[0] = 0x40000;
23635 Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23637 slotbuf[0] = 0x3000a;
23641 Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23643 slotbuf[0] = 0x40004;
23647 Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23649 slotbuf[0] = 0x3000d;
23653 Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23655 slotbuf[0] = 0x3000e;
23659 Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23661 slotbuf[0] = 0x30007;
23665 Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23667 slotbuf[0] = 0x40001;
23671 Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23673 slotbuf[0] = 0x3000c;
23677 Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23679 slotbuf[0] = 0x3000f;
23683 Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23685 slotbuf[0] = 0x30009;
23689 Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23691 slotbuf[0] = 0x40002;
23695 Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23697 slotbuf[0] = 0x3000b;
23701 Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23703 slotbuf[0] = 0x4000b;
23707 Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23709 slotbuf[0] = 0x40005;
23713 Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23715 slotbuf[0] = 0x4000f;
23719 Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23721 slotbuf[0] = 0x40009;
23725 Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23727 slotbuf[0] = 0x4000a;
23731 Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23733 slotbuf[0] = 0x40008;
23737 Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23739 slotbuf[0] = 0x4000d;
23743 Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23745 slotbuf[0] = 0x40006;
23749 Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23751 slotbuf[0] = 0x4000c;
23755 Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23757 slotbuf[0] = 0x40003;
23761 Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23763 slotbuf[0] = 0x4000e;
23767 Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23769 slotbuf[0] = 0x40007;
23773 Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23775 slotbuf[0] = 0x64004;
23779 Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23781 slotbuf[0] = 0x64080;
23785 Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23787 slotbuf[0] = 0x64008;
23791 Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23793 slotbuf[0] = 0x64100;
23797 Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23799 slotbuf[0] = 0x64003;
23803 Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23805 slotbuf[0] = 0x64006;
23809 Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23811 slotbuf[0] = 0x64005;
23815 Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23817 slotbuf[0] = 0x64007;
23821 Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23823 slotbuf[0] = 0x64009;
23827 Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23829 slotbuf[0] = 0x6400c;
23833 Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23835 slotbuf[0] = 0x6400a;
23839 Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23841 slotbuf[0] = 0x6400b;
23845 Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23847 slotbuf[0] = 0x6400d;
23851 Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23853 slotbuf[0] = 0x6400f;
23857 Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23859 slotbuf[0] = 0x6400e;
23863 Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23865 slotbuf[0] = 0x64081;
23869 Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23871 slotbuf[0] = 0x60000;
23875 Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23877 slotbuf[0] = 0x60002;
23881 Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23883 slotbuf[0] = 0x60001;
23887 Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23889 slotbuf[0] = 0x60004;
23893 Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23895 slotbuf[0] = 0x60083;
23899 Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23901 slotbuf[0] = 0x60086;
23905 Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23907 slotbuf[0] = 0x60085;
23911 Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23913 slotbuf[0] = 0x60087;
23917 Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23919 slotbuf[0] = 0x60103;
23923 Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23925 slotbuf[0] = 0x60106;
23929 Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23931 slotbuf[0] = 0x60105;
23935 Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23937 slotbuf[0] = 0x60107;
23941 Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23943 slotbuf[0] = 0x6018e;
23947 Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23949 slotbuf[0] = 0x64001;
23953 Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23955 slotbuf[0] = 0x6018f;
23959 Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
23961 slotbuf[0] = 0x64002;
23965 Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
23967 slotbuf[0] = 0xe00014;
23971 Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
23973 slotbuf[0] = 0xa00004;
23977 Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
23979 slotbuf[0] = 0xa10004;
23983 Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
23985 slotbuf[0] = 0xe7e014;
23989 Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
23991 slotbuf[0] = 0xca8004;
23995 Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23997 slotbuf[0] = 0xc60004;
24001 Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
24003 slotbuf[0] = 0xe00024;
24007 Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
24009 slotbuf[0] = 0xa20004;
24013 Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
24015 slotbuf[0] = 0xe00004;
24019 Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
24021 slotbuf[0] = 0xf01004;
24025 Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
24027 slotbuf[0] = 0xf02004;
24031 Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
24033 slotbuf[0] = 0xa30004;
24037 Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
24039 slotbuf[0] = 0xa40004;
24043 Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
24045 slotbuf[0] = 0xf11004;
24049 Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
24051 slotbuf[0] = 0xf00004;
24055 Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
24057 slotbuf[0] = 0xe7c014;
24061 Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
24063 slotbuf[0] = 0xe7d014;
24066 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
24067 Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
24070 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
24071 Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
24074 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
24075 Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
24078 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
24079 Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
24082 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
24083 Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
24086 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
24087 Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
24090 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
24091 Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
24094 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
24095 Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
24098 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
24099 Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
24102 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
24103 Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
24106 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
24107 Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
24110 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
24111 Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
24114 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
24115 Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
24118 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
24119 Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
24122 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
24123 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
24126 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
24127 Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
24130 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
24131 Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
24134 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
24135 Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
24138 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
24139 Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
24142 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
24143 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
24146 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
24147 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
24150 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
24151 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
24154 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
24155 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
24158 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
24159 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
24162 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
24163 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
24166 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
24167 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
24170 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
24171 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
24174 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
24175 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
24178 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
24179 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
24182 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
24183 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
24186 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
24187 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
24190 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
24191 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
24194 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
24195 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
24198 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
24199 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
24202 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
24203 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
24206 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
24207 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
24210 static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
24211 Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
24214 static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
24215 Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
24218 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
24219 Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
24222 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
24223 Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
24226 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
24227 Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
24230 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
24231 Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
24234 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
24235 Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
24238 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
24239 Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
24242 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
24243 Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
24246 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
24247 Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
24250 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
24251 Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
24254 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
24255 Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
24258 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
24259 Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
24262 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
24263 Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
24266 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
24267 Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
24270 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
24271 Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
24274 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
24275 Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
24278 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
24279 Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
24282 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
24283 Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
24286 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
24287 Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
24290 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
24291 Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
24294 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
24295 Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
24298 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
24299 Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
24302 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
24303 Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
24306 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
24307 Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
24310 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
24311 Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
24314 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
24315 Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
24318 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
24319 Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
24322 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
24323 Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
24326 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
24327 Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
24330 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
24331 Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
24334 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
24335 Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
24338 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
24339 Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
24342 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
24343 Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
24346 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
24347 Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
24350 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
24351 Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
24354 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
24355 Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
24358 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
24359 Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
24362 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
24363 Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
24366 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
24367 Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
24370 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
24371 Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
24374 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
24375 Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
24378 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
24379 Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
24382 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
24383 Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
24386 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
24387 Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
24390 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
24391 Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
24394 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
24395 Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
24398 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
24399 Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
24402 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
24403 Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
24406 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
24407 Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
24410 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
24411 Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
24414 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
24415 Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
24418 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
24419 Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
24422 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
24423 Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
24426 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
24427 Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
24430 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
24431 Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
24434 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
24435 Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
24438 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
24439 Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
24442 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
24443 Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
24446 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
24447 Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
24450 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
24451 Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
24454 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
24455 Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
24458 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
24459 Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
24462 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
24463 Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
24466 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
24467 Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
24470 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
24471 Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
24474 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
24475 Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
24478 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
24479 Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
24482 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
24483 Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
24486 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
24487 Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
24490 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
24491 Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
24494 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
24495 Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
24498 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
24499 Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
24502 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
24503 Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
24506 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
24507 Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
24510 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
24511 Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
24514 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
24515 Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
24518 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
24519 Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
24522 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
24523 Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
24526 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
24527 Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
24530 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
24531 Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
24534 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
24535 Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
24538 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
24539 Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
24542 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
24543 Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
24546 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
24547 Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
24550 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
24551 Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
24554 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
24555 Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
24558 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
24559 Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
24562 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
24563 Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
24566 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
24567 Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
24570 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
24571 Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
24574 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
24575 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
24578 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
24579 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
24582 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
24583 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
24586 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
24587 Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
24590 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
24591 Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
24594 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
24595 Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
24598 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
24599 Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24602 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
24603 Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24606 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
24607 Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24610 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
24611 Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
24614 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
24615 Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
24618 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
24619 Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
24622 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
24623 Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
24626 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
24627 Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
24630 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
24631 Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
24634 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
24635 Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
24638 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
24639 Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
24642 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
24643 Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
24646 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
24647 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
24650 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
24651 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
24654 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
24655 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
24658 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
24659 Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
24662 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
24663 Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
24666 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
24667 Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
24670 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
24671 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
24674 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
24675 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
24678 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
24679 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
24682 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
24683 Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
24686 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
24687 Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
24690 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
24691 Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
24694 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
24695 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
24698 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
24699 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
24702 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
24703 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
24706 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
24707 Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
24710 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
24711 Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
24714 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
24715 Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
24718 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
24719 Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
24722 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
24723 Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
24726 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
24727 Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
24730 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
24731 Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
24734 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
24735 Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
24738 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
24739 Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
24742 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
24743 Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
24746 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
24747 Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
24750 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
24751 Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
24754 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
24755 Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
24758 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
24759 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
24762 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
24763 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
24766 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
24767 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
24770 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
24771 Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
24774 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
24775 Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
24778 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
24779 Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
24782 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
24783 Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
24786 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
24787 Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
24790 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
24791 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
24794 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
24795 Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
24798 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
24799 Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
24802 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
24803 Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
24806 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
24807 Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
24810 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
24811 Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
24814 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
24815 Opcode_break_Slot_inst_encode, 0, 0, 0, 0
24818 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
24819 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
24822 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
24823 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
24826 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
24827 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
24830 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
24831 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
24834 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
24835 Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
24838 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
24839 Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
24842 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
24843 Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
24846 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
24847 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
24850 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
24851 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
24854 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
24855 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
24858 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
24859 Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
24862 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
24863 Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
24866 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
24867 Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
24870 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
24871 Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
24874 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
24875 Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
24878 static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
24879 Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
24882 static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
24883 Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
24886 static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
24887 Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
24890 static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
24891 Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
24894 static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
24895 Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
24898 static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
24899 Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
24902 static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
24903 Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
24906 static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
24907 Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
24910 static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
24911 Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
24914 static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
24915 Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
24918 static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
24919 Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
24922 static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
24923 Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
24926 static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
24927 Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
24930 static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
24931 Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
24934 static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
24935 Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
24938 static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
24939 Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
24942 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
24943 Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
24946 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
24947 Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
24950 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
24951 Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
24954 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
24955 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
24958 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
24959 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
24962 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
24963 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
24966 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
24967 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
24970 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
24971 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
24974 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
24975 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
24978 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
24979 Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
24982 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
24983 Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
24986 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
24987 Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
24990 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
24991 Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
24994 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
24995 Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
24998 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
24999 Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
25002 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
25003 Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
25006 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
25007 Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
25010 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
25011 Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
25014 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
25015 Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
25018 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
25019 Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
25022 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
25023 Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
25026 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
25027 Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
25030 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
25031 Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
25034 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
25035 Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
25038 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
25039 Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
25042 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
25043 Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
25046 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
25047 Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
25050 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
25051 Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
25054 static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
25055 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
25058 static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
25059 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
25062 static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
25063 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
25066 static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
25067 Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
25070 static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
25071 Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
25074 static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
25075 Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
25078 static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
25079 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
25082 static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
25083 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
25086 static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
25087 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
25090 static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
25091 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
25094 static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
25095 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
25098 static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
25099 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
25102 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
25103 Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
25106 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
25107 Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
25110 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
25111 Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
25114 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
25115 Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
25118 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
25119 Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
25122 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
25123 Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
25126 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
25127 Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
25130 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
25131 Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
25134 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
25135 Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
25138 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
25139 Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
25142 static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
25143 Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
25146 static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
25147 Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
25150 static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
25151 Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
25154 static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
25155 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
25158 static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
25159 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
25162 static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
25163 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
25166 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
25167 Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
25170 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
25171 Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
25174 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
25175 Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
25178 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
25179 Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
25182 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
25183 Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
25186 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
25187 Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
25190 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
25191 Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
25194 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
25195 Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
25198 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
25199 Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
25202 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
25203 Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
25206 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
25207 Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
25210 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
25211 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
25214 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
25215 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
25218 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
25219 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
25222 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
25223 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
25226 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
25227 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
25230 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
25231 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
25234 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
25235 Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
25238 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
25239 Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
25242 static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
25243 Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
25246 static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
25247 Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
25250 static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
25251 Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
25254 static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
25255 Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
25258 static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
25259 Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
25262 static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
25263 Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
25266 static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
25267 Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
25270 static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
25271 Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
25274 static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
25275 Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
25278 static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
25279 Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
25282 static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
25283 Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
25286 static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
25287 Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
25290 static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
25291 Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
25294 static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
25295 Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
25298 static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
25299 Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
25302 static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
25303 Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
25306 static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
25307 Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
25310 static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
25311 Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
25314 static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
25315 Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
25318 static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
25319 Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
25322 static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
25323 Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
25326 static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
25327 Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
25330 static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
25331 Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
25334 static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
25335 Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
25338 static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
25339 Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
25342 static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
25343 Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
25346 static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
25347 Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
25350 static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
25351 Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
25354 static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
25355 Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
25358 static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
25359 Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
25362 static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
25363 Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
25366 static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
25367 Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
25370 static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
25371 Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
25374 static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
25375 Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
25378 static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
25379 Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
25382 static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
25383 Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
25386 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
25387 Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
25390 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
25391 Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
25394 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
25395 Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
25398 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
25399 Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
25402 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
25403 Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
25406 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
25407 Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
25410 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
25411 Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
25414 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
25415 Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
25418 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
25419 Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
25422 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
25423 Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
25426 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
25427 Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
25430 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
25431 Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
25434 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
25435 Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
25438 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
25439 Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
25442 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
25443 Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
25446 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
25447 Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
25450 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
25451 Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
25454 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
25455 Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
25458 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
25459 Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
25462 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
25463 Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
25466 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
25467 Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
25470 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
25471 Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
25474 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
25475 Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
25478 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
25479 Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
25482 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
25483 Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
25486 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
25487 Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
25490 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
25491 Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
25494 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
25495 Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
25498 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
25499 Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
25502 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
25503 Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
25506 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
25507 Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
25510 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
25511 Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
25514 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
25515 Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
25518 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
25519 Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
25522 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
25523 Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
25526 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
25527 Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
25530 static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
25531 Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
25534 static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
25535 Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
25538 static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
25539 Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
25542 static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
25543 Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
25546 static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
25547 Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
25550 static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
25551 Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
25554 static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
25555 Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
25558 static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
25559 Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
25562 static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
25563 Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
25566 static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
25567 Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
25570 static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
25571 Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
25574 static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
25575 Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
25578 static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
25579 Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
25582 static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
25583 Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
25586 static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
25587 Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
25590 static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
25591 Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
25594 static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
25595 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
25598 static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
25599 Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
25602 static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
25603 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0
25606 static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
25607 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0
25610 static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
25611 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0
25614 static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
25615 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0
25618 static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
25619 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
25622 static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
25623 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
25626 static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
25627 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
25630 static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
25631 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
25634 static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
25635 Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
25638 static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
25639 Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
25642 static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
25643 Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
25646 static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
25647 Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
25650 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
25651 Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
25654 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
25655 Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
25658 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
25659 Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
25662 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
25663 Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
25666 static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
25667 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
25670 static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
25671 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
25674 static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
25675 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
25678 static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
25679 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
25682 static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
25683 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
25686 static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
25687 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
25690 static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
25691 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
25694 static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
25695 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
25698 static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
25699 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
25702 static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
25703 Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
25706 static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
25707 Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
25710 static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
25711 Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
25714 static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
25715 Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
25718 static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
25719 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
25722 static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
25723 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
25726 static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
25727 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
25730 static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
25731 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
25734 static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
25735 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
25738 static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
25739 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
25742 static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
25743 Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
25746 static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
25747 Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
25750 static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
25751 Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
25754 static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
25755 Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
25758 static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
25759 Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
25762 static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
25763 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
25766 static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
25767 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
25770 static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
25771 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
25774 static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
25775 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
25778 static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
25779 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
25782 static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
25783 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
25786 static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
25787 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
25790 static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
25791 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
25794 static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
25795 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
25798 static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
25799 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
25802 static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
25803 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
25806 static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
25807 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
25810 static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
25811 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
25814 static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
25815 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
25818 static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
25819 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
25822 static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
25823 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
25826 static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
25827 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
25830 static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
25831 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
25834 static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
25835 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
25838 static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
25839 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
25842 static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
25843 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
25846 static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
25847 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
25850 static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
25851 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
25854 static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
25855 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
25858 static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
25859 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
25862 static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
25863 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
25866 static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
25867 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
25870 static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
25871 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
25874 static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
25875 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
25878 static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
25879 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
25882 static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
25883 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
25886 static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
25887 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
25890 static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
25891 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
25894 static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
25895 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
25898 static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
25899 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
25902 static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
25903 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
25906 static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
25907 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
25910 static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
25911 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
25914 static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
25915 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
25918 static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
25919 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
25922 static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
25923 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
25926 static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
25927 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
25930 static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
25931 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
25934 static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
25935 Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
25938 static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
25939 Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
25942 static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
25943 Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
25946 static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
25947 Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
25950 static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
25951 Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
25954 static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
25955 Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
25958 static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
25959 Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
25962 static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
25963 Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
25966 static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
25967 Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
25970 static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
25971 Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
25974 static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
25975 Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
25978 static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
25979 Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
25982 static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
25983 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
25986 static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
25987 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
25990 static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
25991 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
25994 static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
25995 Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
25998 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
25999 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
26002 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
26003 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
26006 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
26007 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
26010 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
26011 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
26014 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
26015 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
26018 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
26019 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
26022 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
26023 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
26026 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
26027 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
26030 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
26031 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
26034 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
26035 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
26038 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
26039 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
26042 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
26043 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
26046 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
26047 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
26050 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
26051 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
26054 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
26055 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
26058 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
26059 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
26062 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
26063 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
26066 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
26067 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
26070 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
26071 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
26074 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
26075 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
26078 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
26079 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
26082 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
26083 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
26086 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
26087 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
26090 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
26091 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
26094 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
26095 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
26098 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
26099 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
26102 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
26103 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
26106 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
26107 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
26110 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
26111 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
26114 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
26115 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
26118 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
26119 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
26122 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
26123 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
26126 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
26127 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
26130 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
26131 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
26134 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
26135 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
26138 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
26139 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
26142 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
26143 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
26146 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
26147 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
26150 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
26151 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
26154 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
26155 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
26158 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
26159 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
26162 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
26163 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
26166 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
26167 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
26170 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
26171 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
26174 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
26175 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
26178 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
26179 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
26182 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
26183 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
26186 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
26187 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
26190 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
26191 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
26194 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
26195 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
26198 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
26199 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
26202 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
26203 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
26206 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
26207 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
26210 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
26211 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
26214 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
26215 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
26218 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
26219 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
26222 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
26223 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
26226 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
26227 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
26230 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
26231 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
26234 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
26235 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
26238 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
26239 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
26242 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
26243 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
26246 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
26247 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
26250 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
26251 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
26254 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
26255 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
26258 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
26259 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
26262 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
26263 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
26266 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
26267 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
26270 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
26271 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
26274 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
26275 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
26278 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
26279 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
26282 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
26283 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
26286 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
26287 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
26290 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
26291 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
26294 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
26295 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
26298 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
26299 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
26302 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
26303 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
26306 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
26307 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
26310 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
26311 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
26314 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
26315 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
26318 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
26319 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
26322 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
26323 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
26326 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
26327 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
26330 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
26331 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
26334 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
26335 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
26338 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
26339 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
26342 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
26343 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
26346 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
26347 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
26350 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
26351 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
26354 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
26355 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
26358 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
26359 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
26362 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
26363 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
26366 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
26367 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
26370 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
26371 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
26374 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
26375 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
26378 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
26379 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
26382 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
26383 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
26386 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
26387 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
26390 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
26391 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
26394 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
26395 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
26398 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
26399 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
26402 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
26403 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
26406 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
26407 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
26410 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
26411 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
26414 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
26415 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
26418 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
26419 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
26422 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
26423 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
26426 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
26427 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
26430 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
26431 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
26434 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
26435 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
26438 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
26439 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
26442 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
26443 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
26446 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
26447 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
26450 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
26451 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
26454 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
26455 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
26458 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
26459 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
26462 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
26463 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
26466 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
26467 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
26470 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
26471 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
26474 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
26475 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
26478 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
26479 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
26482 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
26483 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
26486 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
26487 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
26490 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
26491 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
26494 static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
26495 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
26498 static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
26499 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
26502 static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
26503 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
26506 static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
26507 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
26510 static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
26511 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
26514 static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
26515 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
26518 static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
26519 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
26522 static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
26523 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
26526 static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
26527 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
26530 static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
26531 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
26534 static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
26535 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
26538 static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
26539 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
26542 static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
26543 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
26546 static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
26547 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
26550 static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
26551 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
26554 static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
26555 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
26558 static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
26559 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
26562 static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
26563 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
26566 static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
26567 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
26570 static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
26571 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
26574 static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
26575 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
26578 static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
26579 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
26582 static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
26583 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
26586 static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
26587 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
26590 static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
26591 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
26594 static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
26595 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
26598 static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
26599 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
26602 static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
26603 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
26606 static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
26607 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
26610 static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
26611 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
26614 static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
26615 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
26618 static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
26619 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
26622 static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
26623 Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
26626 static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
26627 Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
26630 static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
26631 Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
26634 static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
26635 Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
26638 static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
26639 Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
26642 static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
26643 Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
26646 static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
26647 Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
26650 static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
26651 Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
26654 static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
26655 Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
26658 static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
26659 Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
26662 static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
26663 Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
26666 static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
26667 Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
26670 static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
26671 Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
26674 static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
26675 Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
26678 static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
26679 Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
26682 static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
26683 Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
26686 static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
26687 Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
26691 /* Opcode table. */
26693 static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
26694 { FUNCUNIT_ae_add32, 3 }
26697 static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
26698 { FUNCUNIT_ae_add32, 3 }
26701 static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
26702 { FUNCUNIT_ae_shift32x4, 2 },
26703 { FUNCUNIT_ae_shift32x5, 3 },
26704 { FUNCUNIT_ae_add32, 3 }
26707 static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
26708 { FUNCUNIT_ae_shift32x4, 2 },
26709 { FUNCUNIT_ae_shift32x5, 3 },
26710 { FUNCUNIT_ae_add32, 3 }
26713 static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
26714 { FUNCUNIT_ae_subshift, 2 }
26717 static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
26718 { FUNCUNIT_ae_subshift, 2 }
26721 static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
26722 { FUNCUNIT_ae_subshift, 2 }
26725 static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
26726 { FUNCUNIT_ae_subshift, 2 }
26729 static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
26730 { FUNCUNIT_ae_shift32x4, 2 },
26731 { FUNCUNIT_ae_subshift, 2 }
26734 static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
26735 { FUNCUNIT_ae_shift32x4, 2 },
26736 { FUNCUNIT_ae_subshift, 2 }
26739 static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
26740 { FUNCUNIT_ae_add32, 3 }
26743 static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
26744 { FUNCUNIT_ae_add32, 3 }
26747 static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
26748 { FUNCUNIT_ae_shift32x4, 2 },
26749 { FUNCUNIT_ae_subshift, 2 }
26752 static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
26753 { FUNCUNIT_ae_shift32x4, 2 },
26754 { FUNCUNIT_ae_subshift, 2 }
26757 static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
26758 { FUNCUNIT_ae_shift32x4, 2 },
26759 { FUNCUNIT_ae_subshift, 2 }
26762 static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
26763 { FUNCUNIT_ae_shift32x4, 2 },
26764 { FUNCUNIT_ae_subshift, 2 }
26767 static xtensa_opcode_internal opcodes[] = {
26768 { "excw", ICLASS_xt_iclass_excw,
26770 Opcode_excw_encode_fns, 0, 0 },
26771 { "rfe", ICLASS_xt_iclass_rfe,
26772 XTENSA_OPCODE_IS_JUMP,
26773 Opcode_rfe_encode_fns, 0, 0 },
26774 { "rfde", ICLASS_xt_iclass_rfde,
26775 XTENSA_OPCODE_IS_JUMP,
26776 Opcode_rfde_encode_fns, 0, 0 },
26777 { "syscall", ICLASS_xt_iclass_syscall,
26779 Opcode_syscall_encode_fns, 0, 0 },
26780 { "call12", ICLASS_xt_iclass_call12,
26781 XTENSA_OPCODE_IS_CALL,
26782 Opcode_call12_encode_fns, 0, 0 },
26783 { "call8", ICLASS_xt_iclass_call8,
26784 XTENSA_OPCODE_IS_CALL,
26785 Opcode_call8_encode_fns, 0, 0 },
26786 { "call4", ICLASS_xt_iclass_call4,
26787 XTENSA_OPCODE_IS_CALL,
26788 Opcode_call4_encode_fns, 0, 0 },
26789 { "callx12", ICLASS_xt_iclass_callx12,
26790 XTENSA_OPCODE_IS_CALL,
26791 Opcode_callx12_encode_fns, 0, 0 },
26792 { "callx8", ICLASS_xt_iclass_callx8,
26793 XTENSA_OPCODE_IS_CALL,
26794 Opcode_callx8_encode_fns, 0, 0 },
26795 { "callx4", ICLASS_xt_iclass_callx4,
26796 XTENSA_OPCODE_IS_CALL,
26797 Opcode_callx4_encode_fns, 0, 0 },
26798 { "entry", ICLASS_xt_iclass_entry,
26800 Opcode_entry_encode_fns, 0, 0 },
26801 { "movsp", ICLASS_xt_iclass_movsp,
26803 Opcode_movsp_encode_fns, 0, 0 },
26804 { "rotw", ICLASS_xt_iclass_rotw,
26806 Opcode_rotw_encode_fns, 0, 0 },
26807 { "retw", ICLASS_xt_iclass_retw,
26808 XTENSA_OPCODE_IS_JUMP,
26809 Opcode_retw_encode_fns, 0, 0 },
26810 { "retw.n", ICLASS_xt_iclass_retw,
26811 XTENSA_OPCODE_IS_JUMP,
26812 Opcode_retw_n_encode_fns, 0, 0 },
26813 { "rfwo", ICLASS_xt_iclass_rfwou,
26814 XTENSA_OPCODE_IS_JUMP,
26815 Opcode_rfwo_encode_fns, 0, 0 },
26816 { "rfwu", ICLASS_xt_iclass_rfwou,
26817 XTENSA_OPCODE_IS_JUMP,
26818 Opcode_rfwu_encode_fns, 0, 0 },
26819 { "l32e", ICLASS_xt_iclass_l32e,
26821 Opcode_l32e_encode_fns, 0, 0 },
26822 { "s32e", ICLASS_xt_iclass_s32e,
26824 Opcode_s32e_encode_fns, 0, 0 },
26825 { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
26827 Opcode_rsr_windowbase_encode_fns, 0, 0 },
26828 { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
26830 Opcode_wsr_windowbase_encode_fns, 0, 0 },
26831 { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
26833 Opcode_xsr_windowbase_encode_fns, 0, 0 },
26834 { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
26836 Opcode_rsr_windowstart_encode_fns, 0, 0 },
26837 { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
26839 Opcode_wsr_windowstart_encode_fns, 0, 0 },
26840 { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
26842 Opcode_xsr_windowstart_encode_fns, 0, 0 },
26843 { "add.n", ICLASS_xt_iclass_add_n,
26845 Opcode_add_n_encode_fns, 0, 0 },
26846 { "addi.n", ICLASS_xt_iclass_addi_n,
26848 Opcode_addi_n_encode_fns, 0, 0 },
26849 { "beqz.n", ICLASS_xt_iclass_bz6,
26850 XTENSA_OPCODE_IS_BRANCH,
26851 Opcode_beqz_n_encode_fns, 0, 0 },
26852 { "bnez.n", ICLASS_xt_iclass_bz6,
26853 XTENSA_OPCODE_IS_BRANCH,
26854 Opcode_bnez_n_encode_fns, 0, 0 },
26855 { "ill.n", ICLASS_xt_iclass_ill_n,
26857 Opcode_ill_n_encode_fns, 0, 0 },
26858 { "l32i.n", ICLASS_xt_iclass_loadi4,
26860 Opcode_l32i_n_encode_fns, 0, 0 },
26861 { "mov.n", ICLASS_xt_iclass_mov_n,
26863 Opcode_mov_n_encode_fns, 0, 0 },
26864 { "movi.n", ICLASS_xt_iclass_movi_n,
26866 Opcode_movi_n_encode_fns, 0, 0 },
26867 { "nop.n", ICLASS_xt_iclass_nopn,
26869 Opcode_nop_n_encode_fns, 0, 0 },
26870 { "ret.n", ICLASS_xt_iclass_retn,
26871 XTENSA_OPCODE_IS_JUMP,
26872 Opcode_ret_n_encode_fns, 0, 0 },
26873 { "s32i.n", ICLASS_xt_iclass_storei4,
26875 Opcode_s32i_n_encode_fns, 0, 0 },
26876 { "rur.threadptr", ICLASS_rur_threadptr,
26878 Opcode_rur_threadptr_encode_fns, 0, 0 },
26879 { "wur.threadptr", ICLASS_wur_threadptr,
26881 Opcode_wur_threadptr_encode_fns, 0, 0 },
26882 { "addi", ICLASS_xt_iclass_addi,
26884 Opcode_addi_encode_fns, 0, 0 },
26885 { "addmi", ICLASS_xt_iclass_addmi,
26887 Opcode_addmi_encode_fns, 0, 0 },
26888 { "add", ICLASS_xt_iclass_addsub,
26890 Opcode_add_encode_fns, 0, 0 },
26891 { "sub", ICLASS_xt_iclass_addsub,
26893 Opcode_sub_encode_fns, 0, 0 },
26894 { "addx2", ICLASS_xt_iclass_addsub,
26896 Opcode_addx2_encode_fns, 0, 0 },
26897 { "addx4", ICLASS_xt_iclass_addsub,
26899 Opcode_addx4_encode_fns, 0, 0 },
26900 { "addx8", ICLASS_xt_iclass_addsub,
26902 Opcode_addx8_encode_fns, 0, 0 },
26903 { "subx2", ICLASS_xt_iclass_addsub,
26905 Opcode_subx2_encode_fns, 0, 0 },
26906 { "subx4", ICLASS_xt_iclass_addsub,
26908 Opcode_subx4_encode_fns, 0, 0 },
26909 { "subx8", ICLASS_xt_iclass_addsub,
26911 Opcode_subx8_encode_fns, 0, 0 },
26912 { "and", ICLASS_xt_iclass_bit,
26914 Opcode_and_encode_fns, 0, 0 },
26915 { "or", ICLASS_xt_iclass_bit,
26917 Opcode_or_encode_fns, 0, 0 },
26918 { "xor", ICLASS_xt_iclass_bit,
26920 Opcode_xor_encode_fns, 0, 0 },
26921 { "beqi", ICLASS_xt_iclass_bsi8,
26922 XTENSA_OPCODE_IS_BRANCH,
26923 Opcode_beqi_encode_fns, 0, 0 },
26924 { "bnei", ICLASS_xt_iclass_bsi8,
26925 XTENSA_OPCODE_IS_BRANCH,
26926 Opcode_bnei_encode_fns, 0, 0 },
26927 { "bgei", ICLASS_xt_iclass_bsi8,
26928 XTENSA_OPCODE_IS_BRANCH,
26929 Opcode_bgei_encode_fns, 0, 0 },
26930 { "blti", ICLASS_xt_iclass_bsi8,
26931 XTENSA_OPCODE_IS_BRANCH,
26932 Opcode_blti_encode_fns, 0, 0 },
26933 { "bbci", ICLASS_xt_iclass_bsi8b,
26934 XTENSA_OPCODE_IS_BRANCH,
26935 Opcode_bbci_encode_fns, 0, 0 },
26936 { "bbsi", ICLASS_xt_iclass_bsi8b,
26937 XTENSA_OPCODE_IS_BRANCH,
26938 Opcode_bbsi_encode_fns, 0, 0 },
26939 { "bgeui", ICLASS_xt_iclass_bsi8u,
26940 XTENSA_OPCODE_IS_BRANCH,
26941 Opcode_bgeui_encode_fns, 0, 0 },
26942 { "bltui", ICLASS_xt_iclass_bsi8u,
26943 XTENSA_OPCODE_IS_BRANCH,
26944 Opcode_bltui_encode_fns, 0, 0 },
26945 { "beq", ICLASS_xt_iclass_bst8,
26946 XTENSA_OPCODE_IS_BRANCH,
26947 Opcode_beq_encode_fns, 0, 0 },
26948 { "bne", ICLASS_xt_iclass_bst8,
26949 XTENSA_OPCODE_IS_BRANCH,
26950 Opcode_bne_encode_fns, 0, 0 },
26951 { "bge", ICLASS_xt_iclass_bst8,
26952 XTENSA_OPCODE_IS_BRANCH,
26953 Opcode_bge_encode_fns, 0, 0 },
26954 { "blt", ICLASS_xt_iclass_bst8,
26955 XTENSA_OPCODE_IS_BRANCH,
26956 Opcode_blt_encode_fns, 0, 0 },
26957 { "bgeu", ICLASS_xt_iclass_bst8,
26958 XTENSA_OPCODE_IS_BRANCH,
26959 Opcode_bgeu_encode_fns, 0, 0 },
26960 { "bltu", ICLASS_xt_iclass_bst8,
26961 XTENSA_OPCODE_IS_BRANCH,
26962 Opcode_bltu_encode_fns, 0, 0 },
26963 { "bany", ICLASS_xt_iclass_bst8,
26964 XTENSA_OPCODE_IS_BRANCH,
26965 Opcode_bany_encode_fns, 0, 0 },
26966 { "bnone", ICLASS_xt_iclass_bst8,
26967 XTENSA_OPCODE_IS_BRANCH,
26968 Opcode_bnone_encode_fns, 0, 0 },
26969 { "ball", ICLASS_xt_iclass_bst8,
26970 XTENSA_OPCODE_IS_BRANCH,
26971 Opcode_ball_encode_fns, 0, 0 },
26972 { "bnall", ICLASS_xt_iclass_bst8,
26973 XTENSA_OPCODE_IS_BRANCH,
26974 Opcode_bnall_encode_fns, 0, 0 },
26975 { "bbc", ICLASS_xt_iclass_bst8,
26976 XTENSA_OPCODE_IS_BRANCH,
26977 Opcode_bbc_encode_fns, 0, 0 },
26978 { "bbs", ICLASS_xt_iclass_bst8,
26979 XTENSA_OPCODE_IS_BRANCH,
26980 Opcode_bbs_encode_fns, 0, 0 },
26981 { "beqz", ICLASS_xt_iclass_bsz12,
26982 XTENSA_OPCODE_IS_BRANCH,
26983 Opcode_beqz_encode_fns, 0, 0 },
26984 { "bnez", ICLASS_xt_iclass_bsz12,
26985 XTENSA_OPCODE_IS_BRANCH,
26986 Opcode_bnez_encode_fns, 0, 0 },
26987 { "bgez", ICLASS_xt_iclass_bsz12,
26988 XTENSA_OPCODE_IS_BRANCH,
26989 Opcode_bgez_encode_fns, 0, 0 },
26990 { "bltz", ICLASS_xt_iclass_bsz12,
26991 XTENSA_OPCODE_IS_BRANCH,
26992 Opcode_bltz_encode_fns, 0, 0 },
26993 { "call0", ICLASS_xt_iclass_call0,
26994 XTENSA_OPCODE_IS_CALL,
26995 Opcode_call0_encode_fns, 0, 0 },
26996 { "callx0", ICLASS_xt_iclass_callx0,
26997 XTENSA_OPCODE_IS_CALL,
26998 Opcode_callx0_encode_fns, 0, 0 },
26999 { "extui", ICLASS_xt_iclass_exti,
27001 Opcode_extui_encode_fns, 0, 0 },
27002 { "ill", ICLASS_xt_iclass_ill,
27004 Opcode_ill_encode_fns, 0, 0 },
27005 { "j", ICLASS_xt_iclass_jump,
27006 XTENSA_OPCODE_IS_JUMP,
27007 Opcode_j_encode_fns, 0, 0 },
27008 { "jx", ICLASS_xt_iclass_jumpx,
27009 XTENSA_OPCODE_IS_JUMP,
27010 Opcode_jx_encode_fns, 0, 0 },
27011 { "l16ui", ICLASS_xt_iclass_l16ui,
27013 Opcode_l16ui_encode_fns, 0, 0 },
27014 { "l16si", ICLASS_xt_iclass_l16si,
27016 Opcode_l16si_encode_fns, 0, 0 },
27017 { "l32i", ICLASS_xt_iclass_l32i,
27019 Opcode_l32i_encode_fns, 0, 0 },
27020 { "l32r", ICLASS_xt_iclass_l32r,
27022 Opcode_l32r_encode_fns, 0, 0 },
27023 { "l8ui", ICLASS_xt_iclass_l8i,
27025 Opcode_l8ui_encode_fns, 0, 0 },
27026 { "loop", ICLASS_xt_iclass_loop,
27027 XTENSA_OPCODE_IS_LOOP,
27028 Opcode_loop_encode_fns, 0, 0 },
27029 { "loopnez", ICLASS_xt_iclass_loopz,
27030 XTENSA_OPCODE_IS_LOOP,
27031 Opcode_loopnez_encode_fns, 0, 0 },
27032 { "loopgtz", ICLASS_xt_iclass_loopz,
27033 XTENSA_OPCODE_IS_LOOP,
27034 Opcode_loopgtz_encode_fns, 0, 0 },
27035 { "movi", ICLASS_xt_iclass_movi,
27037 Opcode_movi_encode_fns, 0, 0 },
27038 { "moveqz", ICLASS_xt_iclass_movz,
27040 Opcode_moveqz_encode_fns, 0, 0 },
27041 { "movnez", ICLASS_xt_iclass_movz,
27043 Opcode_movnez_encode_fns, 0, 0 },
27044 { "movltz", ICLASS_xt_iclass_movz,
27046 Opcode_movltz_encode_fns, 0, 0 },
27047 { "movgez", ICLASS_xt_iclass_movz,
27049 Opcode_movgez_encode_fns, 0, 0 },
27050 { "neg", ICLASS_xt_iclass_neg,
27052 Opcode_neg_encode_fns, 0, 0 },
27053 { "abs", ICLASS_xt_iclass_neg,
27055 Opcode_abs_encode_fns, 0, 0 },
27056 { "nop", ICLASS_xt_iclass_nop,
27058 Opcode_nop_encode_fns, 0, 0 },
27059 { "ret", ICLASS_xt_iclass_return,
27060 XTENSA_OPCODE_IS_JUMP,
27061 Opcode_ret_encode_fns, 0, 0 },
27062 { "simcall", ICLASS_xt_iclass_simcall,
27064 Opcode_simcall_encode_fns, 0, 0 },
27065 { "s16i", ICLASS_xt_iclass_s16i,
27067 Opcode_s16i_encode_fns, 0, 0 },
27068 { "s32i", ICLASS_xt_iclass_s32i,
27070 Opcode_s32i_encode_fns, 0, 0 },
27071 { "s8i", ICLASS_xt_iclass_s8i,
27073 Opcode_s8i_encode_fns, 0, 0 },
27074 { "ssr", ICLASS_xt_iclass_sar,
27076 Opcode_ssr_encode_fns, 0, 0 },
27077 { "ssl", ICLASS_xt_iclass_sar,
27079 Opcode_ssl_encode_fns, 0, 0 },
27080 { "ssa8l", ICLASS_xt_iclass_sar,
27082 Opcode_ssa8l_encode_fns, 0, 0 },
27083 { "ssa8b", ICLASS_xt_iclass_sar,
27085 Opcode_ssa8b_encode_fns, 0, 0 },
27086 { "ssai", ICLASS_xt_iclass_sari,
27088 Opcode_ssai_encode_fns, 0, 0 },
27089 { "sll", ICLASS_xt_iclass_shifts,
27091 Opcode_sll_encode_fns, 0, 0 },
27092 { "src", ICLASS_xt_iclass_shiftst,
27094 Opcode_src_encode_fns, 0, 0 },
27095 { "srl", ICLASS_xt_iclass_shiftt,
27097 Opcode_srl_encode_fns, 0, 0 },
27098 { "sra", ICLASS_xt_iclass_shiftt,
27100 Opcode_sra_encode_fns, 0, 0 },
27101 { "slli", ICLASS_xt_iclass_slli,
27103 Opcode_slli_encode_fns, 0, 0 },
27104 { "srai", ICLASS_xt_iclass_srai,
27106 Opcode_srai_encode_fns, 0, 0 },
27107 { "srli", ICLASS_xt_iclass_srli,
27109 Opcode_srli_encode_fns, 0, 0 },
27110 { "memw", ICLASS_xt_iclass_memw,
27112 Opcode_memw_encode_fns, 0, 0 },
27113 { "extw", ICLASS_xt_iclass_extw,
27115 Opcode_extw_encode_fns, 0, 0 },
27116 { "isync", ICLASS_xt_iclass_isync,
27118 Opcode_isync_encode_fns, 0, 0 },
27119 { "rsync", ICLASS_xt_iclass_sync,
27121 Opcode_rsync_encode_fns, 0, 0 },
27122 { "esync", ICLASS_xt_iclass_sync,
27124 Opcode_esync_encode_fns, 0, 0 },
27125 { "dsync", ICLASS_xt_iclass_sync,
27127 Opcode_dsync_encode_fns, 0, 0 },
27128 { "rsil", ICLASS_xt_iclass_rsil,
27130 Opcode_rsil_encode_fns, 0, 0 },
27131 { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
27133 Opcode_rsr_lend_encode_fns, 0, 0 },
27134 { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
27136 Opcode_wsr_lend_encode_fns, 0, 0 },
27137 { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
27139 Opcode_xsr_lend_encode_fns, 0, 0 },
27140 { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
27142 Opcode_rsr_lcount_encode_fns, 0, 0 },
27143 { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
27145 Opcode_wsr_lcount_encode_fns, 0, 0 },
27146 { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
27148 Opcode_xsr_lcount_encode_fns, 0, 0 },
27149 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
27151 Opcode_rsr_lbeg_encode_fns, 0, 0 },
27152 { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
27154 Opcode_wsr_lbeg_encode_fns, 0, 0 },
27155 { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
27157 Opcode_xsr_lbeg_encode_fns, 0, 0 },
27158 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
27160 Opcode_rsr_sar_encode_fns, 0, 0 },
27161 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
27163 Opcode_wsr_sar_encode_fns, 0, 0 },
27164 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
27166 Opcode_xsr_sar_encode_fns, 0, 0 },
27167 { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
27169 Opcode_rsr_litbase_encode_fns, 0, 0 },
27170 { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
27172 Opcode_wsr_litbase_encode_fns, 0, 0 },
27173 { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
27175 Opcode_xsr_litbase_encode_fns, 0, 0 },
27176 { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
27178 Opcode_rsr_configid0_encode_fns, 0, 0 },
27179 { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
27181 Opcode_wsr_configid0_encode_fns, 0, 0 },
27182 { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
27184 Opcode_rsr_configid1_encode_fns, 0, 0 },
27185 { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
27187 Opcode_rsr_ps_encode_fns, 0, 0 },
27188 { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
27190 Opcode_wsr_ps_encode_fns, 0, 0 },
27191 { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
27193 Opcode_xsr_ps_encode_fns, 0, 0 },
27194 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
27196 Opcode_rsr_epc1_encode_fns, 0, 0 },
27197 { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
27199 Opcode_wsr_epc1_encode_fns, 0, 0 },
27200 { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
27202 Opcode_xsr_epc1_encode_fns, 0, 0 },
27203 { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
27205 Opcode_rsr_excsave1_encode_fns, 0, 0 },
27206 { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
27208 Opcode_wsr_excsave1_encode_fns, 0, 0 },
27209 { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
27211 Opcode_xsr_excsave1_encode_fns, 0, 0 },
27212 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
27214 Opcode_rsr_epc2_encode_fns, 0, 0 },
27215 { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
27217 Opcode_wsr_epc2_encode_fns, 0, 0 },
27218 { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
27220 Opcode_xsr_epc2_encode_fns, 0, 0 },
27221 { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
27223 Opcode_rsr_excsave2_encode_fns, 0, 0 },
27224 { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
27226 Opcode_wsr_excsave2_encode_fns, 0, 0 },
27227 { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
27229 Opcode_xsr_excsave2_encode_fns, 0, 0 },
27230 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
27232 Opcode_rsr_eps2_encode_fns, 0, 0 },
27233 { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
27235 Opcode_wsr_eps2_encode_fns, 0, 0 },
27236 { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
27238 Opcode_xsr_eps2_encode_fns, 0, 0 },
27239 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
27241 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
27242 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
27244 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
27245 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
27247 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
27248 { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
27250 Opcode_rsr_depc_encode_fns, 0, 0 },
27251 { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
27253 Opcode_wsr_depc_encode_fns, 0, 0 },
27254 { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
27256 Opcode_xsr_depc_encode_fns, 0, 0 },
27257 { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
27259 Opcode_rsr_exccause_encode_fns, 0, 0 },
27260 { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
27262 Opcode_wsr_exccause_encode_fns, 0, 0 },
27263 { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
27265 Opcode_xsr_exccause_encode_fns, 0, 0 },
27266 { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
27268 Opcode_rsr_misc0_encode_fns, 0, 0 },
27269 { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
27271 Opcode_wsr_misc0_encode_fns, 0, 0 },
27272 { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
27274 Opcode_xsr_misc0_encode_fns, 0, 0 },
27275 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
27277 Opcode_rsr_misc1_encode_fns, 0, 0 },
27278 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
27280 Opcode_wsr_misc1_encode_fns, 0, 0 },
27281 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
27283 Opcode_xsr_misc1_encode_fns, 0, 0 },
27284 { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
27286 Opcode_rsr_prid_encode_fns, 0, 0 },
27287 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
27289 Opcode_rsr_vecbase_encode_fns, 0, 0 },
27290 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
27292 Opcode_wsr_vecbase_encode_fns, 0, 0 },
27293 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
27295 Opcode_xsr_vecbase_encode_fns, 0, 0 },
27296 { "mul16u", ICLASS_xt_mul16,
27298 Opcode_mul16u_encode_fns, 0, 0 },
27299 { "mul16s", ICLASS_xt_mul16,
27301 Opcode_mul16s_encode_fns, 0, 0 },
27302 { "mull", ICLASS_xt_mul32,
27304 Opcode_mull_encode_fns, 0, 0 },
27305 { "rfi", ICLASS_xt_iclass_rfi,
27306 XTENSA_OPCODE_IS_JUMP,
27307 Opcode_rfi_encode_fns, 0, 0 },
27308 { "waiti", ICLASS_xt_iclass_wait,
27310 Opcode_waiti_encode_fns, 0, 0 },
27311 { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
27313 Opcode_rsr_interrupt_encode_fns, 0, 0 },
27314 { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
27316 Opcode_wsr_intset_encode_fns, 0, 0 },
27317 { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
27319 Opcode_wsr_intclear_encode_fns, 0, 0 },
27320 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
27322 Opcode_rsr_intenable_encode_fns, 0, 0 },
27323 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
27325 Opcode_wsr_intenable_encode_fns, 0, 0 },
27326 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
27328 Opcode_xsr_intenable_encode_fns, 0, 0 },
27329 { "break", ICLASS_xt_iclass_break,
27331 Opcode_break_encode_fns, 0, 0 },
27332 { "break.n", ICLASS_xt_iclass_break_n,
27334 Opcode_break_n_encode_fns, 0, 0 },
27335 { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
27337 Opcode_rsr_debugcause_encode_fns, 0, 0 },
27338 { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
27340 Opcode_wsr_debugcause_encode_fns, 0, 0 },
27341 { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
27343 Opcode_xsr_debugcause_encode_fns, 0, 0 },
27344 { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
27346 Opcode_rsr_icount_encode_fns, 0, 0 },
27347 { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
27349 Opcode_wsr_icount_encode_fns, 0, 0 },
27350 { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
27352 Opcode_xsr_icount_encode_fns, 0, 0 },
27353 { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
27355 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
27356 { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
27358 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
27359 { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
27361 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
27362 { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
27364 Opcode_rsr_ddr_encode_fns, 0, 0 },
27365 { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
27367 Opcode_wsr_ddr_encode_fns, 0, 0 },
27368 { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
27370 Opcode_xsr_ddr_encode_fns, 0, 0 },
27371 { "rfdo", ICLASS_xt_iclass_rfdo,
27372 XTENSA_OPCODE_IS_JUMP,
27373 Opcode_rfdo_encode_fns, 0, 0 },
27374 { "rfdd", ICLASS_xt_iclass_rfdd,
27375 XTENSA_OPCODE_IS_JUMP,
27376 Opcode_rfdd_encode_fns, 0, 0 },
27377 { "andb", ICLASS_xt_iclass_bbool1,
27379 Opcode_andb_encode_fns, 0, 0 },
27380 { "andbc", ICLASS_xt_iclass_bbool1,
27382 Opcode_andbc_encode_fns, 0, 0 },
27383 { "orb", ICLASS_xt_iclass_bbool1,
27385 Opcode_orb_encode_fns, 0, 0 },
27386 { "orbc", ICLASS_xt_iclass_bbool1,
27388 Opcode_orbc_encode_fns, 0, 0 },
27389 { "xorb", ICLASS_xt_iclass_bbool1,
27391 Opcode_xorb_encode_fns, 0, 0 },
27392 { "any4", ICLASS_xt_iclass_bbool4,
27394 Opcode_any4_encode_fns, 0, 0 },
27395 { "all4", ICLASS_xt_iclass_bbool4,
27397 Opcode_all4_encode_fns, 0, 0 },
27398 { "any8", ICLASS_xt_iclass_bbool8,
27400 Opcode_any8_encode_fns, 0, 0 },
27401 { "all8", ICLASS_xt_iclass_bbool8,
27403 Opcode_all8_encode_fns, 0, 0 },
27404 { "bf", ICLASS_xt_iclass_bbranch,
27405 XTENSA_OPCODE_IS_BRANCH,
27406 Opcode_bf_encode_fns, 0, 0 },
27407 { "bt", ICLASS_xt_iclass_bbranch,
27408 XTENSA_OPCODE_IS_BRANCH,
27409 Opcode_bt_encode_fns, 0, 0 },
27410 { "movf", ICLASS_xt_iclass_bmove,
27412 Opcode_movf_encode_fns, 0, 0 },
27413 { "movt", ICLASS_xt_iclass_bmove,
27415 Opcode_movt_encode_fns, 0, 0 },
27416 { "rsr.br", ICLASS_xt_iclass_RSR_BR,
27418 Opcode_rsr_br_encode_fns, 0, 0 },
27419 { "wsr.br", ICLASS_xt_iclass_WSR_BR,
27421 Opcode_wsr_br_encode_fns, 0, 0 },
27422 { "xsr.br", ICLASS_xt_iclass_XSR_BR,
27424 Opcode_xsr_br_encode_fns, 0, 0 },
27425 { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
27427 Opcode_rsr_ccount_encode_fns, 0, 0 },
27428 { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
27430 Opcode_wsr_ccount_encode_fns, 0, 0 },
27431 { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
27433 Opcode_xsr_ccount_encode_fns, 0, 0 },
27434 { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
27436 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
27437 { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
27439 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
27440 { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
27442 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
27443 { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
27445 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
27446 { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
27448 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
27449 { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
27451 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
27452 { "ipf", ICLASS_xt_iclass_icache,
27454 Opcode_ipf_encode_fns, 0, 0 },
27455 { "ihi", ICLASS_xt_iclass_icache,
27457 Opcode_ihi_encode_fns, 0, 0 },
27458 { "iii", ICLASS_xt_iclass_icache_inv,
27460 Opcode_iii_encode_fns, 0, 0 },
27461 { "lict", ICLASS_xt_iclass_licx,
27463 Opcode_lict_encode_fns, 0, 0 },
27464 { "licw", ICLASS_xt_iclass_licx,
27466 Opcode_licw_encode_fns, 0, 0 },
27467 { "sict", ICLASS_xt_iclass_sicx,
27469 Opcode_sict_encode_fns, 0, 0 },
27470 { "sicw", ICLASS_xt_iclass_sicx,
27472 Opcode_sicw_encode_fns, 0, 0 },
27473 { "dhwb", ICLASS_xt_iclass_dcache,
27475 Opcode_dhwb_encode_fns, 0, 0 },
27476 { "dhwbi", ICLASS_xt_iclass_dcache,
27478 Opcode_dhwbi_encode_fns, 0, 0 },
27479 { "diwb", ICLASS_xt_iclass_dcache_ind,
27481 Opcode_diwb_encode_fns, 0, 0 },
27482 { "diwbi", ICLASS_xt_iclass_dcache_ind,
27484 Opcode_diwbi_encode_fns, 0, 0 },
27485 { "dhi", ICLASS_xt_iclass_dcache_inv,
27487 Opcode_dhi_encode_fns, 0, 0 },
27488 { "dii", ICLASS_xt_iclass_dcache_inv,
27490 Opcode_dii_encode_fns, 0, 0 },
27491 { "dpfr", ICLASS_xt_iclass_dpf,
27493 Opcode_dpfr_encode_fns, 0, 0 },
27494 { "dpfw", ICLASS_xt_iclass_dpf,
27496 Opcode_dpfw_encode_fns, 0, 0 },
27497 { "dpfro", ICLASS_xt_iclass_dpf,
27499 Opcode_dpfro_encode_fns, 0, 0 },
27500 { "dpfwo", ICLASS_xt_iclass_dpf,
27502 Opcode_dpfwo_encode_fns, 0, 0 },
27503 { "sdct", ICLASS_xt_iclass_sdct,
27505 Opcode_sdct_encode_fns, 0, 0 },
27506 { "ldct", ICLASS_xt_iclass_ldct,
27508 Opcode_ldct_encode_fns, 0, 0 },
27509 { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
27511 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
27512 { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
27514 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
27515 { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
27517 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
27518 { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
27520 Opcode_rsr_rasid_encode_fns, 0, 0 },
27521 { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
27523 Opcode_wsr_rasid_encode_fns, 0, 0 },
27524 { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
27526 Opcode_xsr_rasid_encode_fns, 0, 0 },
27527 { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
27529 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
27530 { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
27532 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
27533 { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
27535 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
27536 { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
27538 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
27539 { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
27541 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
27542 { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
27544 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
27545 { "idtlb", ICLASS_xt_iclass_idtlb,
27547 Opcode_idtlb_encode_fns, 0, 0 },
27548 { "pdtlb", ICLASS_xt_iclass_rdtlb,
27550 Opcode_pdtlb_encode_fns, 0, 0 },
27551 { "rdtlb0", ICLASS_xt_iclass_rdtlb,
27553 Opcode_rdtlb0_encode_fns, 0, 0 },
27554 { "rdtlb1", ICLASS_xt_iclass_rdtlb,
27556 Opcode_rdtlb1_encode_fns, 0, 0 },
27557 { "wdtlb", ICLASS_xt_iclass_wdtlb,
27559 Opcode_wdtlb_encode_fns, 0, 0 },
27560 { "iitlb", ICLASS_xt_iclass_iitlb,
27562 Opcode_iitlb_encode_fns, 0, 0 },
27563 { "pitlb", ICLASS_xt_iclass_ritlb,
27565 Opcode_pitlb_encode_fns, 0, 0 },
27566 { "ritlb0", ICLASS_xt_iclass_ritlb,
27568 Opcode_ritlb0_encode_fns, 0, 0 },
27569 { "ritlb1", ICLASS_xt_iclass_ritlb,
27571 Opcode_ritlb1_encode_fns, 0, 0 },
27572 { "witlb", ICLASS_xt_iclass_witlb,
27574 Opcode_witlb_encode_fns, 0, 0 },
27575 { "ldpte", ICLASS_xt_iclass_ldpte,
27577 Opcode_ldpte_encode_fns, 0, 0 },
27578 { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
27579 XTENSA_OPCODE_IS_BRANCH,
27580 Opcode_hwwitlba_encode_fns, 0, 0 },
27581 { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
27583 Opcode_hwwdtlba_encode_fns, 0, 0 },
27584 { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
27586 Opcode_rsr_cpenable_encode_fns, 0, 0 },
27587 { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
27589 Opcode_wsr_cpenable_encode_fns, 0, 0 },
27590 { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
27592 Opcode_xsr_cpenable_encode_fns, 0, 0 },
27593 { "clamps", ICLASS_xt_iclass_clamp,
27595 Opcode_clamps_encode_fns, 0, 0 },
27596 { "min", ICLASS_xt_iclass_minmax,
27598 Opcode_min_encode_fns, 0, 0 },
27599 { "max", ICLASS_xt_iclass_minmax,
27601 Opcode_max_encode_fns, 0, 0 },
27602 { "minu", ICLASS_xt_iclass_minmax,
27604 Opcode_minu_encode_fns, 0, 0 },
27605 { "maxu", ICLASS_xt_iclass_minmax,
27607 Opcode_maxu_encode_fns, 0, 0 },
27608 { "nsa", ICLASS_xt_iclass_nsa,
27610 Opcode_nsa_encode_fns, 0, 0 },
27611 { "nsau", ICLASS_xt_iclass_nsa,
27613 Opcode_nsau_encode_fns, 0, 0 },
27614 { "sext", ICLASS_xt_iclass_sx,
27616 Opcode_sext_encode_fns, 0, 0 },
27617 { "l32ai", ICLASS_xt_iclass_l32ai,
27619 Opcode_l32ai_encode_fns, 0, 0 },
27620 { "s32ri", ICLASS_xt_iclass_s32ri,
27622 Opcode_s32ri_encode_fns, 0, 0 },
27623 { "s32c1i", ICLASS_xt_iclass_s32c1i,
27625 Opcode_s32c1i_encode_fns, 0, 0 },
27626 { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
27628 Opcode_rsr_scompare1_encode_fns, 0, 0 },
27629 { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
27631 Opcode_wsr_scompare1_encode_fns, 0, 0 },
27632 { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
27634 Opcode_xsr_scompare1_encode_fns, 0, 0 },
27635 { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
27637 Opcode_rsr_atomctl_encode_fns, 0, 0 },
27638 { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
27640 Opcode_wsr_atomctl_encode_fns, 0, 0 },
27641 { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
27643 Opcode_xsr_atomctl_encode_fns, 0, 0 },
27644 { "rer", ICLASS_xt_iclass_rer,
27646 Opcode_rer_encode_fns, 0, 0 },
27647 { "wer", ICLASS_xt_iclass_wer,
27649 Opcode_wer_encode_fns, 0, 0 },
27650 { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
27652 Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
27653 { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
27655 Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
27656 { "rur.ae_bithead", ICLASS_rur_ae_bithead,
27658 Opcode_rur_ae_bithead_encode_fns, 0, 0 },
27659 { "wur.ae_bithead", ICLASS_wur_ae_bithead,
27661 Opcode_wur_ae_bithead_encode_fns, 0, 0 },
27662 { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
27664 Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
27665 { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
27667 Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
27668 { "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
27670 Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
27671 { "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
27673 Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
27674 { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
27676 Opcode_rur_ae_overflow_encode_fns, 0, 0 },
27677 { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
27679 Opcode_wur_ae_overflow_encode_fns, 0, 0 },
27680 { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
27682 Opcode_rur_ae_sar_encode_fns, 0, 0 },
27683 { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
27685 Opcode_wur_ae_sar_encode_fns, 0, 0 },
27686 { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
27688 Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
27689 { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
27691 Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
27692 { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
27694 Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
27695 { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
27697 Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
27698 { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
27700 Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
27701 { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
27703 Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
27704 { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
27706 Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
27707 { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
27709 Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
27710 { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
27712 Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
27713 { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
27715 Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
27716 { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
27718 Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
27719 { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
27721 Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
27722 { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
27724 Opcode_ae_lp16f_i_encode_fns, 0, 0 },
27725 { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
27727 Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
27728 { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
27730 Opcode_ae_lp16f_x_encode_fns, 0, 0 },
27731 { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
27733 Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
27734 { "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
27736 Opcode_ae_lp24_i_encode_fns, 0, 0 },
27737 { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
27739 Opcode_ae_lp24_iu_encode_fns, 0, 0 },
27740 { "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
27742 Opcode_ae_lp24_x_encode_fns, 0, 0 },
27743 { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
27745 Opcode_ae_lp24_xu_encode_fns, 0, 0 },
27746 { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
27748 Opcode_ae_lp24f_i_encode_fns, 0, 0 },
27749 { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
27751 Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
27752 { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
27754 Opcode_ae_lp24f_x_encode_fns, 0, 0 },
27755 { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
27757 Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
27758 { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
27760 Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
27761 { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
27763 Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
27764 { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
27766 Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
27767 { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
27769 Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
27770 { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
27772 Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
27773 { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
27775 Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
27776 { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
27778 Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
27779 { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
27781 Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
27782 { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
27784 Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
27785 { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
27787 Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
27788 { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
27790 Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
27791 { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
27793 Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
27794 { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
27796 Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
27797 { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
27799 Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
27800 { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
27802 Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
27803 { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
27805 Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
27806 { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
27808 Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
27809 { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
27811 Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
27812 { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
27814 Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
27815 { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
27817 Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
27818 { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
27820 Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
27821 { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
27823 Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
27824 { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
27826 Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
27827 { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
27829 Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
27830 { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
27832 Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
27833 { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
27835 Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
27836 { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
27838 Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
27839 { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
27841 Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
27842 { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
27844 Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
27845 { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
27847 Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
27848 { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
27850 Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
27851 { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
27853 Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
27854 { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
27856 Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
27857 { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
27859 Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
27860 { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
27862 Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
27863 { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
27865 Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
27866 { "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
27868 Opcode_ae_lq56_i_encode_fns, 0, 0 },
27869 { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
27871 Opcode_ae_lq56_iu_encode_fns, 0, 0 },
27872 { "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
27874 Opcode_ae_lq56_x_encode_fns, 0, 0 },
27875 { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
27877 Opcode_ae_lq56_xu_encode_fns, 0, 0 },
27878 { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
27880 Opcode_ae_lq32f_i_encode_fns, 0, 0 },
27881 { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
27883 Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
27884 { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
27886 Opcode_ae_lq32f_x_encode_fns, 0, 0 },
27887 { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
27889 Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
27890 { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
27892 Opcode_ae_sq56s_i_encode_fns, 0, 0 },
27893 { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
27895 Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
27896 { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
27898 Opcode_ae_sq56s_x_encode_fns, 0, 0 },
27899 { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
27901 Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
27902 { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
27904 Opcode_ae_sq32f_i_encode_fns, 0, 0 },
27905 { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
27907 Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
27908 { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
27910 Opcode_ae_sq32f_x_encode_fns, 0, 0 },
27911 { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
27913 Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
27914 { "ae_zerop48", ICLASS_ae_iclass_zerop48,
27916 Opcode_ae_zerop48_encode_fns, 0, 0 },
27917 { "ae_movp48", ICLASS_ae_iclass_movp48,
27919 Opcode_ae_movp48_encode_fns, 0, 0 },
27920 { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
27922 Opcode_ae_selp24_ll_encode_fns, 0, 0 },
27923 { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
27925 Opcode_ae_selp24_lh_encode_fns, 0, 0 },
27926 { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
27928 Opcode_ae_selp24_hl_encode_fns, 0, 0 },
27929 { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
27931 Opcode_ae_selp24_hh_encode_fns, 0, 0 },
27932 { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
27934 Opcode_ae_movtp24x2_encode_fns, 0, 0 },
27935 { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
27937 Opcode_ae_movfp24x2_encode_fns, 0, 0 },
27938 { "ae_movtp48", ICLASS_ae_iclass_movtp48,
27940 Opcode_ae_movtp48_encode_fns, 0, 0 },
27941 { "ae_movfp48", ICLASS_ae_iclass_movfp48,
27943 Opcode_ae_movfp48_encode_fns, 0, 0 },
27944 { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
27946 Opcode_ae_movpa24x2_encode_fns, 0, 0 },
27947 { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
27949 Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
27950 { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
27952 Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
27953 { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
27955 Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
27956 { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
27958 Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
27959 { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
27961 Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
27962 { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
27964 Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
27965 { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
27967 Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
27968 { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
27970 Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
27971 { "ae_truncp16", ICLASS_ae_iclass_truncp16,
27973 Opcode_ae_truncp16_encode_fns, 0, 0 },
27974 { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
27976 Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
27977 { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
27979 Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
27980 { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
27982 Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
27983 { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
27985 Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
27986 { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
27988 Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
27989 { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
27991 Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
27992 { "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
27994 Opcode_ae_zeroq56_encode_fns, 0, 0 },
27995 { "ae_movq56", ICLASS_ae_iclass_movq56,
27997 Opcode_ae_movq56_encode_fns, 0, 0 },
27998 { "ae_movtq56", ICLASS_ae_iclass_movtq56,
28000 Opcode_ae_movtq56_encode_fns, 0, 0 },
28001 { "ae_movfq56", ICLASS_ae_iclass_movfq56,
28003 Opcode_ae_movfq56_encode_fns, 0, 0 },
28004 { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
28006 Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
28007 { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
28009 Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
28010 { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
28012 Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
28013 { "ae_satq48s", ICLASS_ae_iclass_satq48s,
28015 Opcode_ae_satq48s_encode_fns, 0, 0 },
28016 { "ae_truncq32", ICLASS_ae_iclass_truncq32,
28018 Opcode_ae_truncq32_encode_fns, 0, 0 },
28019 { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
28021 Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
28022 { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
28024 Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
28025 { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
28027 Opcode_ae_trunca32q48_encode_fns, 0, 0 },
28028 { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
28030 Opcode_ae_movap24s_l_encode_fns, 0, 0 },
28031 { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
28033 Opcode_ae_movap24s_h_encode_fns, 0, 0 },
28034 { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
28036 Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
28037 { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
28039 Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
28040 { "ae_addp24", ICLASS_ae_iclass_addp24,
28042 Opcode_ae_addp24_encode_fns, 0, 0 },
28043 { "ae_subp24", ICLASS_ae_iclass_subp24,
28045 Opcode_ae_subp24_encode_fns, 0, 0 },
28046 { "ae_negp24", ICLASS_ae_iclass_negp24,
28048 Opcode_ae_negp24_encode_fns, 0, 0 },
28049 { "ae_absp24", ICLASS_ae_iclass_absp24,
28051 Opcode_ae_absp24_encode_fns, 0, 0 },
28052 { "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
28054 Opcode_ae_maxp24s_encode_fns, 0, 0 },
28055 { "ae_minp24s", ICLASS_ae_iclass_minp24s,
28057 Opcode_ae_minp24s_encode_fns, 0, 0 },
28058 { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
28060 Opcode_ae_maxbp24s_encode_fns, 0, 0 },
28061 { "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
28063 Opcode_ae_minbp24s_encode_fns, 0, 0 },
28064 { "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
28066 Opcode_ae_addsp24s_encode_fns, 0, 0 },
28067 { "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
28069 Opcode_ae_subsp24s_encode_fns, 0, 0 },
28070 { "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
28072 Opcode_ae_negsp24s_encode_fns, 0, 0 },
28073 { "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
28075 Opcode_ae_abssp24s_encode_fns, 0, 0 },
28076 { "ae_andp48", ICLASS_ae_iclass_andp48,
28078 Opcode_ae_andp48_encode_fns, 0, 0 },
28079 { "ae_nandp48", ICLASS_ae_iclass_nandp48,
28081 Opcode_ae_nandp48_encode_fns, 0, 0 },
28082 { "ae_orp48", ICLASS_ae_iclass_orp48,
28084 Opcode_ae_orp48_encode_fns, 0, 0 },
28085 { "ae_xorp48", ICLASS_ae_iclass_xorp48,
28087 Opcode_ae_xorp48_encode_fns, 0, 0 },
28088 { "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
28090 Opcode_ae_ltp24s_encode_fns, 0, 0 },
28091 { "ae_lep24s", ICLASS_ae_iclass_lep24s,
28093 Opcode_ae_lep24s_encode_fns, 0, 0 },
28094 { "ae_eqp24", ICLASS_ae_iclass_eqp24,
28096 Opcode_ae_eqp24_encode_fns, 0, 0 },
28097 { "ae_addq56", ICLASS_ae_iclass_addq56,
28099 Opcode_ae_addq56_encode_fns, 0, 0 },
28100 { "ae_subq56", ICLASS_ae_iclass_subq56,
28102 Opcode_ae_subq56_encode_fns, 0, 0 },
28103 { "ae_negq56", ICLASS_ae_iclass_negq56,
28105 Opcode_ae_negq56_encode_fns, 0, 0 },
28106 { "ae_absq56", ICLASS_ae_iclass_absq56,
28108 Opcode_ae_absq56_encode_fns, 0, 0 },
28109 { "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
28111 Opcode_ae_maxq56s_encode_fns, 0, 0 },
28112 { "ae_minq56s", ICLASS_ae_iclass_minq56s,
28114 Opcode_ae_minq56s_encode_fns, 0, 0 },
28115 { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
28117 Opcode_ae_maxbq56s_encode_fns, 0, 0 },
28118 { "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
28120 Opcode_ae_minbq56s_encode_fns, 0, 0 },
28121 { "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
28123 Opcode_ae_addsq56s_encode_fns, 0, 0 },
28124 { "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
28126 Opcode_ae_subsq56s_encode_fns, 0, 0 },
28127 { "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
28129 Opcode_ae_negsq56s_encode_fns, 0, 0 },
28130 { "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
28132 Opcode_ae_abssq56s_encode_fns, 0, 0 },
28133 { "ae_andq56", ICLASS_ae_iclass_andq56,
28135 Opcode_ae_andq56_encode_fns, 0, 0 },
28136 { "ae_nandq56", ICLASS_ae_iclass_nandq56,
28138 Opcode_ae_nandq56_encode_fns, 0, 0 },
28139 { "ae_orq56", ICLASS_ae_iclass_orq56,
28141 Opcode_ae_orq56_encode_fns, 0, 0 },
28142 { "ae_xorq56", ICLASS_ae_iclass_xorq56,
28144 Opcode_ae_xorq56_encode_fns, 0, 0 },
28145 { "ae_sllip24", ICLASS_ae_iclass_sllip24,
28147 Opcode_ae_sllip24_encode_fns, 0, 0 },
28148 { "ae_srlip24", ICLASS_ae_iclass_srlip24,
28150 Opcode_ae_srlip24_encode_fns, 0, 0 },
28151 { "ae_sraip24", ICLASS_ae_iclass_sraip24,
28153 Opcode_ae_sraip24_encode_fns, 0, 0 },
28154 { "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
28156 Opcode_ae_sllsp24_encode_fns, 0, 0 },
28157 { "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
28159 Opcode_ae_srlsp24_encode_fns, 0, 0 },
28160 { "ae_srasp24", ICLASS_ae_iclass_srasp24,
28162 Opcode_ae_srasp24_encode_fns, 0, 0 },
28163 { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
28165 Opcode_ae_sllisp24s_encode_fns, 0, 0 },
28166 { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
28168 Opcode_ae_sllssp24s_encode_fns, 0, 0 },
28169 { "ae_slliq56", ICLASS_ae_iclass_slliq56,
28171 Opcode_ae_slliq56_encode_fns, 0, 0 },
28172 { "ae_srliq56", ICLASS_ae_iclass_srliq56,
28174 Opcode_ae_srliq56_encode_fns, 0, 0 },
28175 { "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
28177 Opcode_ae_sraiq56_encode_fns, 0, 0 },
28178 { "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
28180 Opcode_ae_sllsq56_encode_fns, 0, 0 },
28181 { "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
28183 Opcode_ae_srlsq56_encode_fns, 0, 0 },
28184 { "ae_srasq56", ICLASS_ae_iclass_srasq56,
28186 Opcode_ae_srasq56_encode_fns, 0, 0 },
28187 { "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
28189 Opcode_ae_sllaq56_encode_fns, 0, 0 },
28190 { "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
28192 Opcode_ae_srlaq56_encode_fns, 0, 0 },
28193 { "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
28195 Opcode_ae_sraaq56_encode_fns, 0, 0 },
28196 { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
28198 Opcode_ae_sllisq56s_encode_fns, 0, 0 },
28199 { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
28201 Opcode_ae_sllssq56s_encode_fns, 0, 0 },
28202 { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
28204 Opcode_ae_sllasq56s_encode_fns, 0, 0 },
28205 { "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
28207 Opcode_ae_ltq56s_encode_fns, 0, 0 },
28208 { "ae_leq56s", ICLASS_ae_iclass_leq56s,
28210 Opcode_ae_leq56s_encode_fns, 0, 0 },
28211 { "ae_eqq56", ICLASS_ae_iclass_eqq56,
28213 Opcode_ae_eqq56_encode_fns, 0, 0 },
28214 { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
28216 Opcode_ae_nsaq56s_encode_fns, 0, 0 },
28217 { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
28219 Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
28220 { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
28222 Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
28223 { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
28225 Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
28226 { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
28228 Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
28229 { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
28231 Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
28232 { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
28234 Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
28235 { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
28237 Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
28238 { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
28240 Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
28241 { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
28243 Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
28244 { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
28246 Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
28247 { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
28249 Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
28250 { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
28252 Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
28253 { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
28255 Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
28256 { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
28258 Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
28259 { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
28261 Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
28262 { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
28264 Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
28265 { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
28267 Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
28268 { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
28270 Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
28271 { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
28273 Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
28274 { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
28276 Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
28277 { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
28279 Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
28280 { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
28282 Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
28283 { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
28285 Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
28286 { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
28288 Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
28289 { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
28291 Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
28292 { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
28294 Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
28295 { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
28297 Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
28298 { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
28300 Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
28301 { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
28303 Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
28304 { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
28306 Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
28307 { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
28309 Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
28310 { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
28312 Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
28313 { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
28315 Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
28316 { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
28318 Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
28319 { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
28321 Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
28322 { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
28324 Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
28325 { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
28327 Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
28328 { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
28330 Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
28331 { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
28333 Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
28334 { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
28336 Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
28337 { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
28339 Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
28340 { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
28342 Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
28343 { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
28345 Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
28346 { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
28348 Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
28349 { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
28351 Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
28352 { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
28354 Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
28355 { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
28357 Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
28358 { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
28360 Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
28361 { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
28363 Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
28364 { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
28366 Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
28367 { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
28369 Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
28370 { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
28372 Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
28373 { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
28375 Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
28376 { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
28378 Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
28379 { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
28381 Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
28382 { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
28384 Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
28385 { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
28387 Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
28388 { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
28390 Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
28391 { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
28393 Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
28394 { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
28396 Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
28397 { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
28399 Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
28400 { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
28402 Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
28403 { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
28405 Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
28406 { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
28408 Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
28409 { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
28411 Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
28412 { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
28414 Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
28415 { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
28417 Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
28418 { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
28420 Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
28421 { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
28423 Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
28424 { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
28426 Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
28427 { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
28429 Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
28430 { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
28432 Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
28433 { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
28435 Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
28436 { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
28438 Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
28439 { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
28441 Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
28442 { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
28444 Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
28445 { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
28447 Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
28448 { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
28450 Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
28451 { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
28453 Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
28454 { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
28456 Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
28457 { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
28459 Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
28460 { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
28462 Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
28463 { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
28465 Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
28466 { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
28468 Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
28469 { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
28471 Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
28472 { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
28474 Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
28475 { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
28477 Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
28478 { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
28480 Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
28481 { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
28483 Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
28484 { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
28486 Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
28487 { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
28489 Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
28490 { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
28492 Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
28493 { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
28495 Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
28496 { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
28498 Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
28499 { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
28501 Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
28502 { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
28504 Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
28505 { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
28507 Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
28508 { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
28510 Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
28511 { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
28513 Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
28514 { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
28516 Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
28517 { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
28519 Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
28520 { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
28522 Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
28523 { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
28525 Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
28526 { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
28528 Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
28529 { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
28531 Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
28532 { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
28534 Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
28535 { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
28537 Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
28538 { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
28540 Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
28541 { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
28543 Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
28544 { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
28546 Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
28547 { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
28549 Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
28550 { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
28552 Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
28553 { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
28555 Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
28556 { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
28558 Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
28559 { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
28561 Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
28562 { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
28564 Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
28565 { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
28567 Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
28568 { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
28570 Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
28571 { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
28573 Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
28574 { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
28576 Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
28577 { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
28579 Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
28580 { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
28582 Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
28583 { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
28585 Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
28586 { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
28588 Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
28589 { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
28591 Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
28592 { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
28594 Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
28595 { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
28597 Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
28598 { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
28600 Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
28601 { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
28603 Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
28604 { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
28606 Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
28607 { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
28609 Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
28610 { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
28612 Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
28613 { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
28615 Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
28616 { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
28618 Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
28619 { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
28621 Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
28622 { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
28624 Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
28625 { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
28627 Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
28628 { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
28630 Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
28631 { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
28633 Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
28634 { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
28636 Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
28637 { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
28639 Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
28640 { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
28642 Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
28643 { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
28645 Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
28646 { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
28648 Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
28649 { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
28651 Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
28652 { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
28654 Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
28655 { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
28657 Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
28658 { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
28660 Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
28661 { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
28663 Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
28664 { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
28666 Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
28667 { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
28669 Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
28670 { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
28672 Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
28673 { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
28675 Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
28676 { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
28678 Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
28679 { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
28681 Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
28682 { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
28684 Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
28685 { "ae_sha32", ICLASS_ae_iclass_sha32,
28687 Opcode_ae_sha32_encode_fns, 0, 0 },
28688 { "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
28690 Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
28691 { "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
28693 Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
28694 { "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
28696 Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
28697 { "ae_vldsht", ICLASS_ae_iclass_vldsht,
28699 Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
28700 { "ae_lb", ICLASS_ae_iclass_lb,
28702 Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
28703 { "ae_lbi", ICLASS_ae_iclass_lbi,
28705 Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
28706 { "ae_lbk", ICLASS_ae_iclass_lbk,
28708 Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
28709 { "ae_lbki", ICLASS_ae_iclass_lbki,
28711 Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
28712 { "ae_db", ICLASS_ae_iclass_db,
28714 Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
28715 { "ae_dbi", ICLASS_ae_iclass_dbi,
28717 Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
28718 { "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
28720 Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
28721 { "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
28723 Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
28724 { "ae_sb", ICLASS_ae_iclass_sb,
28726 Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
28727 { "ae_sbi", ICLASS_ae_iclass_sbi,
28729 Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
28730 { "ae_vles16c", ICLASS_ae_iclass_vles16c,
28732 Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
28733 { "ae_sbf", ICLASS_ae_iclass_sbf,
28735 Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }
28738 enum xtensa_opcode_id {
28758 OPCODE_RSR_WINDOWBASE,
28759 OPCODE_WSR_WINDOWBASE,
28760 OPCODE_XSR_WINDOWBASE,
28761 OPCODE_RSR_WINDOWSTART,
28762 OPCODE_WSR_WINDOWSTART,
28763 OPCODE_XSR_WINDOWSTART,
28775 OPCODE_RUR_THREADPTR,
28776 OPCODE_WUR_THREADPTR,
28872 OPCODE_RSR_LITBASE,
28873 OPCODE_WSR_LITBASE,
28874 OPCODE_XSR_LITBASE,
28875 OPCODE_RSR_CONFIGID0,
28876 OPCODE_WSR_CONFIGID0,
28877 OPCODE_RSR_CONFIGID1,
28884 OPCODE_RSR_EXCSAVE1,
28885 OPCODE_WSR_EXCSAVE1,
28886 OPCODE_XSR_EXCSAVE1,
28890 OPCODE_RSR_EXCSAVE2,
28891 OPCODE_WSR_EXCSAVE2,
28892 OPCODE_XSR_EXCSAVE2,
28896 OPCODE_RSR_EXCVADDR,
28897 OPCODE_WSR_EXCVADDR,
28898 OPCODE_XSR_EXCVADDR,
28902 OPCODE_RSR_EXCCAUSE,
28903 OPCODE_WSR_EXCCAUSE,
28904 OPCODE_XSR_EXCCAUSE,
28912 OPCODE_RSR_VECBASE,
28913 OPCODE_WSR_VECBASE,
28914 OPCODE_XSR_VECBASE,
28920 OPCODE_RSR_INTERRUPT,
28922 OPCODE_WSR_INTCLEAR,
28923 OPCODE_RSR_INTENABLE,
28924 OPCODE_WSR_INTENABLE,
28925 OPCODE_XSR_INTENABLE,
28928 OPCODE_RSR_DEBUGCAUSE,
28929 OPCODE_WSR_DEBUGCAUSE,
28930 OPCODE_XSR_DEBUGCAUSE,
28934 OPCODE_RSR_ICOUNTLEVEL,
28935 OPCODE_WSR_ICOUNTLEVEL,
28936 OPCODE_XSR_ICOUNTLEVEL,
28961 OPCODE_RSR_CCOMPARE0,
28962 OPCODE_WSR_CCOMPARE0,
28963 OPCODE_XSR_CCOMPARE0,
28964 OPCODE_RSR_CCOMPARE1,
28965 OPCODE_WSR_CCOMPARE1,
28966 OPCODE_XSR_CCOMPARE1,
28986 OPCODE_WSR_PTEVADDR,
28987 OPCODE_RSR_PTEVADDR,
28988 OPCODE_XSR_PTEVADDR,
28992 OPCODE_RSR_ITLBCFG,
28993 OPCODE_WSR_ITLBCFG,
28994 OPCODE_XSR_ITLBCFG,
28995 OPCODE_RSR_DTLBCFG,
28996 OPCODE_WSR_DTLBCFG,
28997 OPCODE_XSR_DTLBCFG,
29011 OPCODE_RSR_CPENABLE,
29012 OPCODE_WSR_CPENABLE,
29013 OPCODE_XSR_CPENABLE,
29025 OPCODE_RSR_SCOMPARE1,
29026 OPCODE_WSR_SCOMPARE1,
29027 OPCODE_XSR_SCOMPARE1,
29028 OPCODE_RSR_ATOMCTL,
29029 OPCODE_WSR_ATOMCTL,
29030 OPCODE_XSR_ATOMCTL,
29033 OPCODE_RUR_AE_OVF_SAR,
29034 OPCODE_WUR_AE_OVF_SAR,
29035 OPCODE_RUR_AE_BITHEAD,
29036 OPCODE_WUR_AE_BITHEAD,
29037 OPCODE_RUR_AE_TS_FTS_BU_BP,
29038 OPCODE_WUR_AE_TS_FTS_BU_BP,
29039 OPCODE_RUR_AE_SD_NO,
29040 OPCODE_WUR_AE_SD_NO,
29041 OPCODE_RUR_AE_OVERFLOW,
29042 OPCODE_WUR_AE_OVERFLOW,
29045 OPCODE_RUR_AE_BITPTR,
29046 OPCODE_WUR_AE_BITPTR,
29047 OPCODE_RUR_AE_BITSUSED,
29048 OPCODE_WUR_AE_BITSUSED,
29049 OPCODE_RUR_AE_TABLESIZE,
29050 OPCODE_WUR_AE_TABLESIZE,
29051 OPCODE_RUR_AE_FIRST_TS,
29052 OPCODE_WUR_AE_FIRST_TS,
29053 OPCODE_RUR_AE_NEXTOFFSET,
29054 OPCODE_WUR_AE_NEXTOFFSET,
29055 OPCODE_RUR_AE_SEARCHDONE,
29056 OPCODE_WUR_AE_SEARCHDONE,
29058 OPCODE_AE_LP16F_IU,
29060 OPCODE_AE_LP16F_XU,
29066 OPCODE_AE_LP24F_IU,
29068 OPCODE_AE_LP24F_XU,
29069 OPCODE_AE_LP16X2F_I,
29070 OPCODE_AE_LP16X2F_IU,
29071 OPCODE_AE_LP16X2F_X,
29072 OPCODE_AE_LP16X2F_XU,
29073 OPCODE_AE_LP24X2F_I,
29074 OPCODE_AE_LP24X2F_IU,
29075 OPCODE_AE_LP24X2F_X,
29076 OPCODE_AE_LP24X2F_XU,
29077 OPCODE_AE_LP24X2_I,
29078 OPCODE_AE_LP24X2_IU,
29079 OPCODE_AE_LP24X2_X,
29080 OPCODE_AE_LP24X2_XU,
29081 OPCODE_AE_SP16X2F_I,
29082 OPCODE_AE_SP16X2F_IU,
29083 OPCODE_AE_SP16X2F_X,
29084 OPCODE_AE_SP16X2F_XU,
29085 OPCODE_AE_SP24X2S_I,
29086 OPCODE_AE_SP24X2S_IU,
29087 OPCODE_AE_SP24X2S_X,
29088 OPCODE_AE_SP24X2S_XU,
29089 OPCODE_AE_SP24X2F_I,
29090 OPCODE_AE_SP24X2F_IU,
29091 OPCODE_AE_SP24X2F_X,
29092 OPCODE_AE_SP24X2F_XU,
29093 OPCODE_AE_SP16F_L_I,
29094 OPCODE_AE_SP16F_L_IU,
29095 OPCODE_AE_SP16F_L_X,
29096 OPCODE_AE_SP16F_L_XU,
29097 OPCODE_AE_SP24S_L_I,
29098 OPCODE_AE_SP24S_L_IU,
29099 OPCODE_AE_SP24S_L_X,
29100 OPCODE_AE_SP24S_L_XU,
29101 OPCODE_AE_SP24F_L_I,
29102 OPCODE_AE_SP24F_L_IU,
29103 OPCODE_AE_SP24F_L_X,
29104 OPCODE_AE_SP24F_L_XU,
29110 OPCODE_AE_LQ32F_IU,
29112 OPCODE_AE_LQ32F_XU,
29114 OPCODE_AE_SQ56S_IU,
29116 OPCODE_AE_SQ56S_XU,
29118 OPCODE_AE_SQ32F_IU,
29120 OPCODE_AE_SQ32F_XU,
29123 OPCODE_AE_SELP24_LL,
29124 OPCODE_AE_SELP24_LH,
29125 OPCODE_AE_SELP24_HL,
29126 OPCODE_AE_SELP24_HH,
29127 OPCODE_AE_MOVTP24X2,
29128 OPCODE_AE_MOVFP24X2,
29131 OPCODE_AE_MOVPA24X2,
29132 OPCODE_AE_TRUNCP24A32X2,
29133 OPCODE_AE_CVTA32P24_L,
29134 OPCODE_AE_CVTA32P24_H,
29135 OPCODE_AE_CVTP24A16X2_LL,
29136 OPCODE_AE_CVTP24A16X2_LH,
29137 OPCODE_AE_CVTP24A16X2_HL,
29138 OPCODE_AE_CVTP24A16X2_HH,
29139 OPCODE_AE_TRUNCP24Q48X2,
29140 OPCODE_AE_TRUNCP16,
29141 OPCODE_AE_ROUNDSP24Q48SYM,
29142 OPCODE_AE_ROUNDSP24Q48ASYM,
29143 OPCODE_AE_ROUNDSP16Q48SYM,
29144 OPCODE_AE_ROUNDSP16Q48ASYM,
29145 OPCODE_AE_ROUNDSP16SYM,
29146 OPCODE_AE_ROUNDSP16ASYM,
29151 OPCODE_AE_CVTQ48A32S,
29152 OPCODE_AE_CVTQ48P24S_L,
29153 OPCODE_AE_CVTQ48P24S_H,
29155 OPCODE_AE_TRUNCQ32,
29156 OPCODE_AE_ROUNDSQ32SYM,
29157 OPCODE_AE_ROUNDSQ32ASYM,
29158 OPCODE_AE_TRUNCA32Q48,
29159 OPCODE_AE_MOVAP24S_L,
29160 OPCODE_AE_MOVAP24S_H,
29161 OPCODE_AE_TRUNCA16P24S_L,
29162 OPCODE_AE_TRUNCA16P24S_H,
29169 OPCODE_AE_MAXBP24S,
29170 OPCODE_AE_MINBP24S,
29171 OPCODE_AE_ADDSP24S,
29172 OPCODE_AE_SUBSP24S,
29173 OPCODE_AE_NEGSP24S,
29174 OPCODE_AE_ABSSP24S,
29188 OPCODE_AE_MAXBQ56S,
29189 OPCODE_AE_MINBQ56S,
29190 OPCODE_AE_ADDSQ56S,
29191 OPCODE_AE_SUBSQ56S,
29192 OPCODE_AE_NEGSQ56S,
29193 OPCODE_AE_ABSSQ56S,
29204 OPCODE_AE_SLLISP24S,
29205 OPCODE_AE_SLLSSP24S,
29215 OPCODE_AE_SLLISQ56S,
29216 OPCODE_AE_SLLSSQ56S,
29217 OPCODE_AE_SLLASQ56S,
29222 OPCODE_AE_MULFS32P16S_LL,
29223 OPCODE_AE_MULFP24S_LL,
29224 OPCODE_AE_MULP24S_LL,
29225 OPCODE_AE_MULFS32P16S_LH,
29226 OPCODE_AE_MULFP24S_LH,
29227 OPCODE_AE_MULP24S_LH,
29228 OPCODE_AE_MULFS32P16S_HL,
29229 OPCODE_AE_MULFP24S_HL,
29230 OPCODE_AE_MULP24S_HL,
29231 OPCODE_AE_MULFS32P16S_HH,
29232 OPCODE_AE_MULFP24S_HH,
29233 OPCODE_AE_MULP24S_HH,
29234 OPCODE_AE_MULAFS32P16S_LL,
29235 OPCODE_AE_MULAFP24S_LL,
29236 OPCODE_AE_MULAP24S_LL,
29237 OPCODE_AE_MULAFS32P16S_LH,
29238 OPCODE_AE_MULAFP24S_LH,
29239 OPCODE_AE_MULAP24S_LH,
29240 OPCODE_AE_MULAFS32P16S_HL,
29241 OPCODE_AE_MULAFP24S_HL,
29242 OPCODE_AE_MULAP24S_HL,
29243 OPCODE_AE_MULAFS32P16S_HH,
29244 OPCODE_AE_MULAFP24S_HH,
29245 OPCODE_AE_MULAP24S_HH,
29246 OPCODE_AE_MULSFS32P16S_LL,
29247 OPCODE_AE_MULSFP24S_LL,
29248 OPCODE_AE_MULSP24S_LL,
29249 OPCODE_AE_MULSFS32P16S_LH,
29250 OPCODE_AE_MULSFP24S_LH,
29251 OPCODE_AE_MULSP24S_LH,
29252 OPCODE_AE_MULSFS32P16S_HL,
29253 OPCODE_AE_MULSFP24S_HL,
29254 OPCODE_AE_MULSP24S_HL,
29255 OPCODE_AE_MULSFS32P16S_HH,
29256 OPCODE_AE_MULSFP24S_HH,
29257 OPCODE_AE_MULSP24S_HH,
29258 OPCODE_AE_MULAFS56P24S_LL,
29259 OPCODE_AE_MULAS56P24S_LL,
29260 OPCODE_AE_MULAFS56P24S_LH,
29261 OPCODE_AE_MULAS56P24S_LH,
29262 OPCODE_AE_MULAFS56P24S_HL,
29263 OPCODE_AE_MULAS56P24S_HL,
29264 OPCODE_AE_MULAFS56P24S_HH,
29265 OPCODE_AE_MULAS56P24S_HH,
29266 OPCODE_AE_MULSFS56P24S_LL,
29267 OPCODE_AE_MULSS56P24S_LL,
29268 OPCODE_AE_MULSFS56P24S_LH,
29269 OPCODE_AE_MULSS56P24S_LH,
29270 OPCODE_AE_MULSFS56P24S_HL,
29271 OPCODE_AE_MULSS56P24S_HL,
29272 OPCODE_AE_MULSFS56P24S_HH,
29273 OPCODE_AE_MULSS56P24S_HH,
29274 OPCODE_AE_MULFQ32SP16S_L,
29275 OPCODE_AE_MULFQ32SP16S_H,
29276 OPCODE_AE_MULFQ32SP16U_L,
29277 OPCODE_AE_MULFQ32SP16U_H,
29278 OPCODE_AE_MULQ32SP16S_L,
29279 OPCODE_AE_MULQ32SP16S_H,
29280 OPCODE_AE_MULQ32SP16U_L,
29281 OPCODE_AE_MULQ32SP16U_H,
29282 OPCODE_AE_MULAFQ32SP16S_L,
29283 OPCODE_AE_MULAFQ32SP16S_H,
29284 OPCODE_AE_MULAFQ32SP16U_L,
29285 OPCODE_AE_MULAFQ32SP16U_H,
29286 OPCODE_AE_MULAQ32SP16S_L,
29287 OPCODE_AE_MULAQ32SP16S_H,
29288 OPCODE_AE_MULAQ32SP16U_L,
29289 OPCODE_AE_MULAQ32SP16U_H,
29290 OPCODE_AE_MULSFQ32SP16S_L,
29291 OPCODE_AE_MULSFQ32SP16S_H,
29292 OPCODE_AE_MULSFQ32SP16U_L,
29293 OPCODE_AE_MULSFQ32SP16U_H,
29294 OPCODE_AE_MULSQ32SP16S_L,
29295 OPCODE_AE_MULSQ32SP16S_H,
29296 OPCODE_AE_MULSQ32SP16U_L,
29297 OPCODE_AE_MULSQ32SP16U_H,
29298 OPCODE_AE_MULZAAQ32SP16S_LL,
29299 OPCODE_AE_MULZAAFQ32SP16S_LL,
29300 OPCODE_AE_MULZAAQ32SP16U_LL,
29301 OPCODE_AE_MULZAAFQ32SP16U_LL,
29302 OPCODE_AE_MULZAAQ32SP16S_HH,
29303 OPCODE_AE_MULZAAFQ32SP16S_HH,
29304 OPCODE_AE_MULZAAQ32SP16U_HH,
29305 OPCODE_AE_MULZAAFQ32SP16U_HH,
29306 OPCODE_AE_MULZAAQ32SP16S_LH,
29307 OPCODE_AE_MULZAAFQ32SP16S_LH,
29308 OPCODE_AE_MULZAAQ32SP16U_LH,
29309 OPCODE_AE_MULZAAFQ32SP16U_LH,
29310 OPCODE_AE_MULZASQ32SP16S_LL,
29311 OPCODE_AE_MULZASFQ32SP16S_LL,
29312 OPCODE_AE_MULZASQ32SP16U_LL,
29313 OPCODE_AE_MULZASFQ32SP16U_LL,
29314 OPCODE_AE_MULZASQ32SP16S_HH,
29315 OPCODE_AE_MULZASFQ32SP16S_HH,
29316 OPCODE_AE_MULZASQ32SP16U_HH,
29317 OPCODE_AE_MULZASFQ32SP16U_HH,
29318 OPCODE_AE_MULZASQ32SP16S_LH,
29319 OPCODE_AE_MULZASFQ32SP16S_LH,
29320 OPCODE_AE_MULZASQ32SP16U_LH,
29321 OPCODE_AE_MULZASFQ32SP16U_LH,
29322 OPCODE_AE_MULZSAQ32SP16S_LL,
29323 OPCODE_AE_MULZSAFQ32SP16S_LL,
29324 OPCODE_AE_MULZSAQ32SP16U_LL,
29325 OPCODE_AE_MULZSAFQ32SP16U_LL,
29326 OPCODE_AE_MULZSAQ32SP16S_HH,
29327 OPCODE_AE_MULZSAFQ32SP16S_HH,
29328 OPCODE_AE_MULZSAQ32SP16U_HH,
29329 OPCODE_AE_MULZSAFQ32SP16U_HH,
29330 OPCODE_AE_MULZSAQ32SP16S_LH,
29331 OPCODE_AE_MULZSAFQ32SP16S_LH,
29332 OPCODE_AE_MULZSAQ32SP16U_LH,
29333 OPCODE_AE_MULZSAFQ32SP16U_LH,
29334 OPCODE_AE_MULZSSQ32SP16S_LL,
29335 OPCODE_AE_MULZSSFQ32SP16S_LL,
29336 OPCODE_AE_MULZSSQ32SP16U_LL,
29337 OPCODE_AE_MULZSSFQ32SP16U_LL,
29338 OPCODE_AE_MULZSSQ32SP16S_HH,
29339 OPCODE_AE_MULZSSFQ32SP16S_HH,
29340 OPCODE_AE_MULZSSQ32SP16U_HH,
29341 OPCODE_AE_MULZSSFQ32SP16U_HH,
29342 OPCODE_AE_MULZSSQ32SP16S_LH,
29343 OPCODE_AE_MULZSSFQ32SP16S_LH,
29344 OPCODE_AE_MULZSSQ32SP16U_LH,
29345 OPCODE_AE_MULZSSFQ32SP16U_LH,
29346 OPCODE_AE_MULZAAFP24S_HH_LL,
29347 OPCODE_AE_MULZAAP24S_HH_LL,
29348 OPCODE_AE_MULZAAFP24S_HL_LH,
29349 OPCODE_AE_MULZAAP24S_HL_LH,
29350 OPCODE_AE_MULZASFP24S_HH_LL,
29351 OPCODE_AE_MULZASP24S_HH_LL,
29352 OPCODE_AE_MULZASFP24S_HL_LH,
29353 OPCODE_AE_MULZASP24S_HL_LH,
29354 OPCODE_AE_MULZSAFP24S_HH_LL,
29355 OPCODE_AE_MULZSAP24S_HH_LL,
29356 OPCODE_AE_MULZSAFP24S_HL_LH,
29357 OPCODE_AE_MULZSAP24S_HL_LH,
29358 OPCODE_AE_MULZSSFP24S_HH_LL,
29359 OPCODE_AE_MULZSSP24S_HH_LL,
29360 OPCODE_AE_MULZSSFP24S_HL_LH,
29361 OPCODE_AE_MULZSSP24S_HL_LH,
29362 OPCODE_AE_MULAAFP24S_HH_LL,
29363 OPCODE_AE_MULAAP24S_HH_LL,
29364 OPCODE_AE_MULAAFP24S_HL_LH,
29365 OPCODE_AE_MULAAP24S_HL_LH,
29366 OPCODE_AE_MULASFP24S_HH_LL,
29367 OPCODE_AE_MULASP24S_HH_LL,
29368 OPCODE_AE_MULASFP24S_HL_LH,
29369 OPCODE_AE_MULASP24S_HL_LH,
29370 OPCODE_AE_MULSAFP24S_HH_LL,
29371 OPCODE_AE_MULSAP24S_HH_LL,
29372 OPCODE_AE_MULSAFP24S_HL_LH,
29373 OPCODE_AE_MULSAP24S_HL_LH,
29374 OPCODE_AE_MULSSFP24S_HH_LL,
29375 OPCODE_AE_MULSSP24S_HH_LL,
29376 OPCODE_AE_MULSSFP24S_HL_LH,
29377 OPCODE_AE_MULSSP24S_HL_LH,
29398 /* Slot-specific opcode decode functions. */
29401 Slot_inst_decode (const xtensa_insnbuf insn)
29403 if (Field_op0_Slot_inst_get (insn) == 0)
29405 if (Field_op1_Slot_inst_get (insn) == 0)
29407 if (Field_op2_Slot_inst_get (insn) == 0)
29409 if (Field_r_Slot_inst_get (insn) == 0)
29411 if (Field_m_Slot_inst_get (insn) == 0 &&
29412 Field_s_Slot_inst_get (insn) == 0 &&
29413 Field_n_Slot_inst_get (insn) == 0)
29415 if (Field_m_Slot_inst_get (insn) == 2)
29417 if (Field_n_Slot_inst_get (insn) == 0)
29419 if (Field_n_Slot_inst_get (insn) == 1)
29420 return OPCODE_RETW;
29421 if (Field_n_Slot_inst_get (insn) == 2)
29424 if (Field_m_Slot_inst_get (insn) == 3)
29426 if (Field_n_Slot_inst_get (insn) == 0)
29427 return OPCODE_CALLX0;
29428 if (Field_n_Slot_inst_get (insn) == 1)
29429 return OPCODE_CALLX4;
29430 if (Field_n_Slot_inst_get (insn) == 2)
29431 return OPCODE_CALLX8;
29432 if (Field_n_Slot_inst_get (insn) == 3)
29433 return OPCODE_CALLX12;
29436 if (Field_r_Slot_inst_get (insn) == 1)
29437 return OPCODE_MOVSP;
29438 if (Field_r_Slot_inst_get (insn) == 2)
29440 if (Field_s_Slot_inst_get (insn) == 0)
29442 if (Field_t_Slot_inst_get (insn) == 0)
29443 return OPCODE_ISYNC;
29444 if (Field_t_Slot_inst_get (insn) == 1)
29445 return OPCODE_RSYNC;
29446 if (Field_t_Slot_inst_get (insn) == 2)
29447 return OPCODE_ESYNC;
29448 if (Field_t_Slot_inst_get (insn) == 3)
29449 return OPCODE_DSYNC;
29450 if (Field_t_Slot_inst_get (insn) == 8)
29451 return OPCODE_EXCW;
29452 if (Field_t_Slot_inst_get (insn) == 12)
29453 return OPCODE_MEMW;
29454 if (Field_t_Slot_inst_get (insn) == 13)
29455 return OPCODE_EXTW;
29456 if (Field_t_Slot_inst_get (insn) == 15)
29460 if (Field_r_Slot_inst_get (insn) == 3)
29462 if (Field_t_Slot_inst_get (insn) == 0)
29464 if (Field_s_Slot_inst_get (insn) == 0)
29466 if (Field_s_Slot_inst_get (insn) == 2)
29467 return OPCODE_RFDE;
29468 if (Field_s_Slot_inst_get (insn) == 4)
29469 return OPCODE_RFWO;
29470 if (Field_s_Slot_inst_get (insn) == 5)
29471 return OPCODE_RFWU;
29473 if (Field_t_Slot_inst_get (insn) == 1)
29476 if (Field_r_Slot_inst_get (insn) == 4)
29477 return OPCODE_BREAK;
29478 if (Field_r_Slot_inst_get (insn) == 5)
29480 if (Field_s_Slot_inst_get (insn) == 0 &&
29481 Field_t_Slot_inst_get (insn) == 0)
29482 return OPCODE_SYSCALL;
29483 if (Field_s_Slot_inst_get (insn) == 1 &&
29484 Field_t_Slot_inst_get (insn) == 0)
29485 return OPCODE_SIMCALL;
29487 if (Field_r_Slot_inst_get (insn) == 6)
29488 return OPCODE_RSIL;
29489 if (Field_r_Slot_inst_get (insn) == 7 &&
29490 Field_t_Slot_inst_get (insn) == 0)
29491 return OPCODE_WAITI;
29492 if (Field_r_Slot_inst_get (insn) == 8)
29493 return OPCODE_ANY4;
29494 if (Field_r_Slot_inst_get (insn) == 9)
29495 return OPCODE_ALL4;
29496 if (Field_r_Slot_inst_get (insn) == 10)
29497 return OPCODE_ANY8;
29498 if (Field_r_Slot_inst_get (insn) == 11)
29499 return OPCODE_ALL8;
29501 if (Field_op2_Slot_inst_get (insn) == 1)
29503 if (Field_op2_Slot_inst_get (insn) == 2)
29505 if (Field_op2_Slot_inst_get (insn) == 3)
29507 if (Field_op2_Slot_inst_get (insn) == 4)
29509 if (Field_r_Slot_inst_get (insn) == 0 &&
29510 Field_t_Slot_inst_get (insn) == 0)
29512 if (Field_r_Slot_inst_get (insn) == 1 &&
29513 Field_t_Slot_inst_get (insn) == 0)
29515 if (Field_r_Slot_inst_get (insn) == 2 &&
29516 Field_t_Slot_inst_get (insn) == 0)
29517 return OPCODE_SSA8L;
29518 if (Field_r_Slot_inst_get (insn) == 3 &&
29519 Field_t_Slot_inst_get (insn) == 0)
29520 return OPCODE_SSA8B;
29521 if (Field_r_Slot_inst_get (insn) == 4 &&
29522 Field_thi3_Slot_inst_get (insn) == 0)
29523 return OPCODE_SSAI;
29524 if (Field_r_Slot_inst_get (insn) == 6)
29526 if (Field_r_Slot_inst_get (insn) == 7)
29528 if (Field_r_Slot_inst_get (insn) == 8 &&
29529 Field_s_Slot_inst_get (insn) == 0)
29530 return OPCODE_ROTW;
29531 if (Field_r_Slot_inst_get (insn) == 14)
29533 if (Field_r_Slot_inst_get (insn) == 15)
29534 return OPCODE_NSAU;
29536 if (Field_op2_Slot_inst_get (insn) == 5)
29538 if (Field_r_Slot_inst_get (insn) == 1)
29539 return OPCODE_HWWITLBA;
29540 if (Field_r_Slot_inst_get (insn) == 3)
29541 return OPCODE_RITLB0;
29542 if (Field_r_Slot_inst_get (insn) == 4 &&
29543 Field_t_Slot_inst_get (insn) == 0)
29544 return OPCODE_IITLB;
29545 if (Field_r_Slot_inst_get (insn) == 5)
29546 return OPCODE_PITLB;
29547 if (Field_r_Slot_inst_get (insn) == 6)
29548 return OPCODE_WITLB;
29549 if (Field_r_Slot_inst_get (insn) == 7)
29550 return OPCODE_RITLB1;
29551 if (Field_r_Slot_inst_get (insn) == 9)
29552 return OPCODE_HWWDTLBA;
29553 if (Field_r_Slot_inst_get (insn) == 11)
29554 return OPCODE_RDTLB0;
29555 if (Field_r_Slot_inst_get (insn) == 12 &&
29556 Field_t_Slot_inst_get (insn) == 0)
29557 return OPCODE_IDTLB;
29558 if (Field_r_Slot_inst_get (insn) == 13)
29559 return OPCODE_PDTLB;
29560 if (Field_r_Slot_inst_get (insn) == 14)
29561 return OPCODE_WDTLB;
29562 if (Field_r_Slot_inst_get (insn) == 15)
29563 return OPCODE_RDTLB1;
29565 if (Field_op2_Slot_inst_get (insn) == 6)
29567 if (Field_s_Slot_inst_get (insn) == 0)
29569 if (Field_s_Slot_inst_get (insn) == 1)
29572 if (Field_op2_Slot_inst_get (insn) == 8)
29574 if (Field_op2_Slot_inst_get (insn) == 9)
29575 return OPCODE_ADDX2;
29576 if (Field_op2_Slot_inst_get (insn) == 10)
29577 return OPCODE_ADDX4;
29578 if (Field_op2_Slot_inst_get (insn) == 11)
29579 return OPCODE_ADDX8;
29580 if (Field_op2_Slot_inst_get (insn) == 12)
29582 if (Field_op2_Slot_inst_get (insn) == 13)
29583 return OPCODE_SUBX2;
29584 if (Field_op2_Slot_inst_get (insn) == 14)
29585 return OPCODE_SUBX4;
29586 if (Field_op2_Slot_inst_get (insn) == 15)
29587 return OPCODE_SUBX8;
29589 if (Field_op1_Slot_inst_get (insn) == 1)
29591 if ((Field_op2_Slot_inst_get (insn) == 0 ||
29592 Field_op2_Slot_inst_get (insn) == 1))
29593 return OPCODE_SLLI;
29594 if ((Field_op2_Slot_inst_get (insn) == 2 ||
29595 Field_op2_Slot_inst_get (insn) == 3))
29596 return OPCODE_SRAI;
29597 if (Field_op2_Slot_inst_get (insn) == 4)
29598 return OPCODE_SRLI;
29599 if (Field_op2_Slot_inst_get (insn) == 6)
29601 if (Field_sr_Slot_inst_get (insn) == 0)
29602 return OPCODE_XSR_LBEG;
29603 if (Field_sr_Slot_inst_get (insn) == 1)
29604 return OPCODE_XSR_LEND;
29605 if (Field_sr_Slot_inst_get (insn) == 2)
29606 return OPCODE_XSR_LCOUNT;
29607 if (Field_sr_Slot_inst_get (insn) == 3)
29608 return OPCODE_XSR_SAR;
29609 if (Field_sr_Slot_inst_get (insn) == 4)
29610 return OPCODE_XSR_BR;
29611 if (Field_sr_Slot_inst_get (insn) == 5)
29612 return OPCODE_XSR_LITBASE;
29613 if (Field_sr_Slot_inst_get (insn) == 12)
29614 return OPCODE_XSR_SCOMPARE1;
29615 if (Field_sr_Slot_inst_get (insn) == 72)
29616 return OPCODE_XSR_WINDOWBASE;
29617 if (Field_sr_Slot_inst_get (insn) == 73)
29618 return OPCODE_XSR_WINDOWSTART;
29619 if (Field_sr_Slot_inst_get (insn) == 83)
29620 return OPCODE_XSR_PTEVADDR;
29621 if (Field_sr_Slot_inst_get (insn) == 90)
29622 return OPCODE_XSR_RASID;
29623 if (Field_sr_Slot_inst_get (insn) == 91)
29624 return OPCODE_XSR_ITLBCFG;
29625 if (Field_sr_Slot_inst_get (insn) == 92)
29626 return OPCODE_XSR_DTLBCFG;
29627 if (Field_sr_Slot_inst_get (insn) == 99)
29628 return OPCODE_XSR_ATOMCTL;
29629 if (Field_sr_Slot_inst_get (insn) == 104)
29630 return OPCODE_XSR_DDR;
29631 if (Field_sr_Slot_inst_get (insn) == 177)
29632 return OPCODE_XSR_EPC1;
29633 if (Field_sr_Slot_inst_get (insn) == 178)
29634 return OPCODE_XSR_EPC2;
29635 if (Field_sr_Slot_inst_get (insn) == 192)
29636 return OPCODE_XSR_DEPC;
29637 if (Field_sr_Slot_inst_get (insn) == 194)
29638 return OPCODE_XSR_EPS2;
29639 if (Field_sr_Slot_inst_get (insn) == 209)
29640 return OPCODE_XSR_EXCSAVE1;
29641 if (Field_sr_Slot_inst_get (insn) == 210)
29642 return OPCODE_XSR_EXCSAVE2;
29643 if (Field_sr_Slot_inst_get (insn) == 224)
29644 return OPCODE_XSR_CPENABLE;
29645 if (Field_sr_Slot_inst_get (insn) == 228)
29646 return OPCODE_XSR_INTENABLE;
29647 if (Field_sr_Slot_inst_get (insn) == 230)
29648 return OPCODE_XSR_PS;
29649 if (Field_sr_Slot_inst_get (insn) == 231)
29650 return OPCODE_XSR_VECBASE;
29651 if (Field_sr_Slot_inst_get (insn) == 232)
29652 return OPCODE_XSR_EXCCAUSE;
29653 if (Field_sr_Slot_inst_get (insn) == 233)
29654 return OPCODE_XSR_DEBUGCAUSE;
29655 if (Field_sr_Slot_inst_get (insn) == 234)
29656 return OPCODE_XSR_CCOUNT;
29657 if (Field_sr_Slot_inst_get (insn) == 236)
29658 return OPCODE_XSR_ICOUNT;
29659 if (Field_sr_Slot_inst_get (insn) == 237)
29660 return OPCODE_XSR_ICOUNTLEVEL;
29661 if (Field_sr_Slot_inst_get (insn) == 238)
29662 return OPCODE_XSR_EXCVADDR;
29663 if (Field_sr_Slot_inst_get (insn) == 240)
29664 return OPCODE_XSR_CCOMPARE0;
29665 if (Field_sr_Slot_inst_get (insn) == 241)
29666 return OPCODE_XSR_CCOMPARE1;
29667 if (Field_sr_Slot_inst_get (insn) == 244)
29668 return OPCODE_XSR_MISC0;
29669 if (Field_sr_Slot_inst_get (insn) == 245)
29670 return OPCODE_XSR_MISC1;
29672 if (Field_op2_Slot_inst_get (insn) == 8)
29674 if (Field_op2_Slot_inst_get (insn) == 9 &&
29675 Field_s_Slot_inst_get (insn) == 0)
29677 if (Field_op2_Slot_inst_get (insn) == 10 &&
29678 Field_t_Slot_inst_get (insn) == 0)
29680 if (Field_op2_Slot_inst_get (insn) == 11 &&
29681 Field_s_Slot_inst_get (insn) == 0)
29683 if (Field_op2_Slot_inst_get (insn) == 12)
29684 return OPCODE_MUL16U;
29685 if (Field_op2_Slot_inst_get (insn) == 13)
29686 return OPCODE_MUL16S;
29687 if (Field_op2_Slot_inst_get (insn) == 15)
29689 if (Field_r_Slot_inst_get (insn) == 0)
29690 return OPCODE_LICT;
29691 if (Field_r_Slot_inst_get (insn) == 1)
29692 return OPCODE_SICT;
29693 if (Field_r_Slot_inst_get (insn) == 2)
29694 return OPCODE_LICW;
29695 if (Field_r_Slot_inst_get (insn) == 3)
29696 return OPCODE_SICW;
29697 if (Field_r_Slot_inst_get (insn) == 8)
29698 return OPCODE_LDCT;
29699 if (Field_r_Slot_inst_get (insn) == 9)
29700 return OPCODE_SDCT;
29701 if (Field_r_Slot_inst_get (insn) == 14 &&
29702 Field_t_Slot_inst_get (insn) == 0)
29703 return OPCODE_RFDO;
29704 if (Field_r_Slot_inst_get (insn) == 14 &&
29705 Field_t_Slot_inst_get (insn) == 1)
29706 return OPCODE_RFDD;
29707 if (Field_r_Slot_inst_get (insn) == 15)
29708 return OPCODE_LDPTE;
29711 if (Field_op1_Slot_inst_get (insn) == 2)
29713 if (Field_op2_Slot_inst_get (insn) == 0)
29714 return OPCODE_ANDB;
29715 if (Field_op2_Slot_inst_get (insn) == 1)
29716 return OPCODE_ANDBC;
29717 if (Field_op2_Slot_inst_get (insn) == 2)
29719 if (Field_op2_Slot_inst_get (insn) == 3)
29720 return OPCODE_ORBC;
29721 if (Field_op2_Slot_inst_get (insn) == 4)
29722 return OPCODE_XORB;
29723 if (Field_op2_Slot_inst_get (insn) == 8)
29724 return OPCODE_MULL;
29726 if (Field_op1_Slot_inst_get (insn) == 3)
29728 if (Field_op2_Slot_inst_get (insn) == 0)
29730 if (Field_sr_Slot_inst_get (insn) == 0)
29731 return OPCODE_RSR_LBEG;
29732 if (Field_sr_Slot_inst_get (insn) == 1)
29733 return OPCODE_RSR_LEND;
29734 if (Field_sr_Slot_inst_get (insn) == 2)
29735 return OPCODE_RSR_LCOUNT;
29736 if (Field_sr_Slot_inst_get (insn) == 3)
29737 return OPCODE_RSR_SAR;
29738 if (Field_sr_Slot_inst_get (insn) == 4)
29739 return OPCODE_RSR_BR;
29740 if (Field_sr_Slot_inst_get (insn) == 5)
29741 return OPCODE_RSR_LITBASE;
29742 if (Field_sr_Slot_inst_get (insn) == 12)
29743 return OPCODE_RSR_SCOMPARE1;
29744 if (Field_sr_Slot_inst_get (insn) == 72)
29745 return OPCODE_RSR_WINDOWBASE;
29746 if (Field_sr_Slot_inst_get (insn) == 73)
29747 return OPCODE_RSR_WINDOWSTART;
29748 if (Field_sr_Slot_inst_get (insn) == 83)
29749 return OPCODE_RSR_PTEVADDR;
29750 if (Field_sr_Slot_inst_get (insn) == 90)
29751 return OPCODE_RSR_RASID;
29752 if (Field_sr_Slot_inst_get (insn) == 91)
29753 return OPCODE_RSR_ITLBCFG;
29754 if (Field_sr_Slot_inst_get (insn) == 92)
29755 return OPCODE_RSR_DTLBCFG;
29756 if (Field_sr_Slot_inst_get (insn) == 99)
29757 return OPCODE_RSR_ATOMCTL;
29758 if (Field_sr_Slot_inst_get (insn) == 104)
29759 return OPCODE_RSR_DDR;
29760 if (Field_sr_Slot_inst_get (insn) == 176)
29761 return OPCODE_RSR_CONFIGID0;
29762 if (Field_sr_Slot_inst_get (insn) == 177)
29763 return OPCODE_RSR_EPC1;
29764 if (Field_sr_Slot_inst_get (insn) == 178)
29765 return OPCODE_RSR_EPC2;
29766 if (Field_sr_Slot_inst_get (insn) == 192)
29767 return OPCODE_RSR_DEPC;
29768 if (Field_sr_Slot_inst_get (insn) == 194)
29769 return OPCODE_RSR_EPS2;
29770 if (Field_sr_Slot_inst_get (insn) == 208)
29771 return OPCODE_RSR_CONFIGID1;
29772 if (Field_sr_Slot_inst_get (insn) == 209)
29773 return OPCODE_RSR_EXCSAVE1;
29774 if (Field_sr_Slot_inst_get (insn) == 210)
29775 return OPCODE_RSR_EXCSAVE2;
29776 if (Field_sr_Slot_inst_get (insn) == 224)
29777 return OPCODE_RSR_CPENABLE;
29778 if (Field_sr_Slot_inst_get (insn) == 226)
29779 return OPCODE_RSR_INTERRUPT;
29780 if (Field_sr_Slot_inst_get (insn) == 228)
29781 return OPCODE_RSR_INTENABLE;
29782 if (Field_sr_Slot_inst_get (insn) == 230)
29783 return OPCODE_RSR_PS;
29784 if (Field_sr_Slot_inst_get (insn) == 231)
29785 return OPCODE_RSR_VECBASE;
29786 if (Field_sr_Slot_inst_get (insn) == 232)
29787 return OPCODE_RSR_EXCCAUSE;
29788 if (Field_sr_Slot_inst_get (insn) == 233)
29789 return OPCODE_RSR_DEBUGCAUSE;
29790 if (Field_sr_Slot_inst_get (insn) == 234)
29791 return OPCODE_RSR_CCOUNT;
29792 if (Field_sr_Slot_inst_get (insn) == 235)
29793 return OPCODE_RSR_PRID;
29794 if (Field_sr_Slot_inst_get (insn) == 236)
29795 return OPCODE_RSR_ICOUNT;
29796 if (Field_sr_Slot_inst_get (insn) == 237)
29797 return OPCODE_RSR_ICOUNTLEVEL;
29798 if (Field_sr_Slot_inst_get (insn) == 238)
29799 return OPCODE_RSR_EXCVADDR;
29800 if (Field_sr_Slot_inst_get (insn) == 240)
29801 return OPCODE_RSR_CCOMPARE0;
29802 if (Field_sr_Slot_inst_get (insn) == 241)
29803 return OPCODE_RSR_CCOMPARE1;
29804 if (Field_sr_Slot_inst_get (insn) == 244)
29805 return OPCODE_RSR_MISC0;
29806 if (Field_sr_Slot_inst_get (insn) == 245)
29807 return OPCODE_RSR_MISC1;
29809 if (Field_op2_Slot_inst_get (insn) == 1)
29811 if (Field_sr_Slot_inst_get (insn) == 0)
29812 return OPCODE_WSR_LBEG;
29813 if (Field_sr_Slot_inst_get (insn) == 1)
29814 return OPCODE_WSR_LEND;
29815 if (Field_sr_Slot_inst_get (insn) == 2)
29816 return OPCODE_WSR_LCOUNT;
29817 if (Field_sr_Slot_inst_get (insn) == 3)
29818 return OPCODE_WSR_SAR;
29819 if (Field_sr_Slot_inst_get (insn) == 4)
29820 return OPCODE_WSR_BR;
29821 if (Field_sr_Slot_inst_get (insn) == 5)
29822 return OPCODE_WSR_LITBASE;
29823 if (Field_sr_Slot_inst_get (insn) == 12)
29824 return OPCODE_WSR_SCOMPARE1;
29825 if (Field_sr_Slot_inst_get (insn) == 72)
29826 return OPCODE_WSR_WINDOWBASE;
29827 if (Field_sr_Slot_inst_get (insn) == 73)
29828 return OPCODE_WSR_WINDOWSTART;
29829 if (Field_sr_Slot_inst_get (insn) == 83)
29830 return OPCODE_WSR_PTEVADDR;
29831 if (Field_sr_Slot_inst_get (insn) == 90)
29832 return OPCODE_WSR_RASID;
29833 if (Field_sr_Slot_inst_get (insn) == 91)
29834 return OPCODE_WSR_ITLBCFG;
29835 if (Field_sr_Slot_inst_get (insn) == 92)
29836 return OPCODE_WSR_DTLBCFG;
29837 if (Field_sr_Slot_inst_get (insn) == 99)
29838 return OPCODE_WSR_ATOMCTL;
29839 if (Field_sr_Slot_inst_get (insn) == 104)
29840 return OPCODE_WSR_DDR;
29841 if (Field_sr_Slot_inst_get (insn) == 176)
29842 return OPCODE_WSR_CONFIGID0;
29843 if (Field_sr_Slot_inst_get (insn) == 177)
29844 return OPCODE_WSR_EPC1;
29845 if (Field_sr_Slot_inst_get (insn) == 178)
29846 return OPCODE_WSR_EPC2;
29847 if (Field_sr_Slot_inst_get (insn) == 192)
29848 return OPCODE_WSR_DEPC;
29849 if (Field_sr_Slot_inst_get (insn) == 194)
29850 return OPCODE_WSR_EPS2;
29851 if (Field_sr_Slot_inst_get (insn) == 209)
29852 return OPCODE_WSR_EXCSAVE1;
29853 if (Field_sr_Slot_inst_get (insn) == 210)
29854 return OPCODE_WSR_EXCSAVE2;
29855 if (Field_sr_Slot_inst_get (insn) == 224)
29856 return OPCODE_WSR_CPENABLE;
29857 if (Field_sr_Slot_inst_get (insn) == 226)
29858 return OPCODE_WSR_INTSET;
29859 if (Field_sr_Slot_inst_get (insn) == 227)
29860 return OPCODE_WSR_INTCLEAR;
29861 if (Field_sr_Slot_inst_get (insn) == 228)
29862 return OPCODE_WSR_INTENABLE;
29863 if (Field_sr_Slot_inst_get (insn) == 230)
29864 return OPCODE_WSR_PS;
29865 if (Field_sr_Slot_inst_get (insn) == 231)
29866 return OPCODE_WSR_VECBASE;
29867 if (Field_sr_Slot_inst_get (insn) == 232)
29868 return OPCODE_WSR_EXCCAUSE;
29869 if (Field_sr_Slot_inst_get (insn) == 233)
29870 return OPCODE_WSR_DEBUGCAUSE;
29871 if (Field_sr_Slot_inst_get (insn) == 234)
29872 return OPCODE_WSR_CCOUNT;
29873 if (Field_sr_Slot_inst_get (insn) == 236)
29874 return OPCODE_WSR_ICOUNT;
29875 if (Field_sr_Slot_inst_get (insn) == 237)
29876 return OPCODE_WSR_ICOUNTLEVEL;
29877 if (Field_sr_Slot_inst_get (insn) == 238)
29878 return OPCODE_WSR_EXCVADDR;
29879 if (Field_sr_Slot_inst_get (insn) == 240)
29880 return OPCODE_WSR_CCOMPARE0;
29881 if (Field_sr_Slot_inst_get (insn) == 241)
29882 return OPCODE_WSR_CCOMPARE1;
29883 if (Field_sr_Slot_inst_get (insn) == 244)
29884 return OPCODE_WSR_MISC0;
29885 if (Field_sr_Slot_inst_get (insn) == 245)
29886 return OPCODE_WSR_MISC1;
29888 if (Field_op2_Slot_inst_get (insn) == 2)
29889 return OPCODE_SEXT;
29890 if (Field_op2_Slot_inst_get (insn) == 3)
29891 return OPCODE_CLAMPS;
29892 if (Field_op2_Slot_inst_get (insn) == 4)
29894 if (Field_op2_Slot_inst_get (insn) == 5)
29896 if (Field_op2_Slot_inst_get (insn) == 6)
29897 return OPCODE_MINU;
29898 if (Field_op2_Slot_inst_get (insn) == 7)
29899 return OPCODE_MAXU;
29900 if (Field_op2_Slot_inst_get (insn) == 8)
29901 return OPCODE_MOVEQZ;
29902 if (Field_op2_Slot_inst_get (insn) == 9)
29903 return OPCODE_MOVNEZ;
29904 if (Field_op2_Slot_inst_get (insn) == 10)
29905 return OPCODE_MOVLTZ;
29906 if (Field_op2_Slot_inst_get (insn) == 11)
29907 return OPCODE_MOVGEZ;
29908 if (Field_op2_Slot_inst_get (insn) == 12)
29909 return OPCODE_MOVF;
29910 if (Field_op2_Slot_inst_get (insn) == 13)
29911 return OPCODE_MOVT;
29912 if (Field_op2_Slot_inst_get (insn) == 14)
29914 if (Field_st_Slot_inst_get (insn) == 231)
29915 return OPCODE_RUR_THREADPTR;
29916 if (Field_st_Slot_inst_get (insn) == 240)
29917 return OPCODE_RUR_AE_OVF_SAR;
29918 if (Field_st_Slot_inst_get (insn) == 241)
29919 return OPCODE_RUR_AE_BITHEAD;
29920 if (Field_st_Slot_inst_get (insn) == 242)
29921 return OPCODE_RUR_AE_TS_FTS_BU_BP;
29922 if (Field_st_Slot_inst_get (insn) == 243)
29923 return OPCODE_RUR_AE_SD_NO;
29925 if (Field_op2_Slot_inst_get (insn) == 15)
29927 if (Field_sr_Slot_inst_get (insn) == 231)
29928 return OPCODE_WUR_THREADPTR;
29929 if (Field_sr_Slot_inst_get (insn) == 240)
29930 return OPCODE_WUR_AE_OVF_SAR;
29931 if (Field_sr_Slot_inst_get (insn) == 241)
29932 return OPCODE_WUR_AE_BITHEAD;
29933 if (Field_sr_Slot_inst_get (insn) == 242)
29934 return OPCODE_WUR_AE_TS_FTS_BU_BP;
29935 if (Field_sr_Slot_inst_get (insn) == 243)
29936 return OPCODE_WUR_AE_SD_NO;
29939 if ((Field_op1_Slot_inst_get (insn) == 4 ||
29940 Field_op1_Slot_inst_get (insn) == 5))
29941 return OPCODE_EXTUI;
29942 if (Field_op1_Slot_inst_get (insn) == 9)
29944 if (Field_op2_Slot_inst_get (insn) == 0)
29945 return OPCODE_L32E;
29946 if (Field_op2_Slot_inst_get (insn) == 4)
29947 return OPCODE_S32E;
29950 if (Field_op0_Slot_inst_get (insn) == 1)
29951 return OPCODE_L32R;
29952 if (Field_op0_Slot_inst_get (insn) == 2)
29954 if (Field_r_Slot_inst_get (insn) == 0)
29955 return OPCODE_L8UI;
29956 if (Field_r_Slot_inst_get (insn) == 1)
29957 return OPCODE_L16UI;
29958 if (Field_r_Slot_inst_get (insn) == 2)
29959 return OPCODE_L32I;
29960 if (Field_r_Slot_inst_get (insn) == 4)
29962 if (Field_r_Slot_inst_get (insn) == 5)
29963 return OPCODE_S16I;
29964 if (Field_r_Slot_inst_get (insn) == 6)
29965 return OPCODE_S32I;
29966 if (Field_r_Slot_inst_get (insn) == 7)
29968 if (Field_t_Slot_inst_get (insn) == 0)
29969 return OPCODE_DPFR;
29970 if (Field_t_Slot_inst_get (insn) == 1)
29971 return OPCODE_DPFW;
29972 if (Field_t_Slot_inst_get (insn) == 2)
29973 return OPCODE_DPFRO;
29974 if (Field_t_Slot_inst_get (insn) == 3)
29975 return OPCODE_DPFWO;
29976 if (Field_t_Slot_inst_get (insn) == 4)
29977 return OPCODE_DHWB;
29978 if (Field_t_Slot_inst_get (insn) == 5)
29979 return OPCODE_DHWBI;
29980 if (Field_t_Slot_inst_get (insn) == 6)
29982 if (Field_t_Slot_inst_get (insn) == 7)
29984 if (Field_t_Slot_inst_get (insn) == 8)
29986 if (Field_op1_Slot_inst_get (insn) == 4)
29987 return OPCODE_DIWB;
29988 if (Field_op1_Slot_inst_get (insn) == 5)
29989 return OPCODE_DIWBI;
29991 if (Field_t_Slot_inst_get (insn) == 12)
29993 if (Field_t_Slot_inst_get (insn) == 14)
29995 if (Field_t_Slot_inst_get (insn) == 15)
29998 if (Field_r_Slot_inst_get (insn) == 9)
29999 return OPCODE_L16SI;
30000 if (Field_r_Slot_inst_get (insn) == 10)
30001 return OPCODE_MOVI;
30002 if (Field_r_Slot_inst_get (insn) == 11)
30003 return OPCODE_L32AI;
30004 if (Field_r_Slot_inst_get (insn) == 12)
30005 return OPCODE_ADDI;
30006 if (Field_r_Slot_inst_get (insn) == 13)
30007 return OPCODE_ADDMI;
30008 if (Field_r_Slot_inst_get (insn) == 14)
30009 return OPCODE_S32C1I;
30010 if (Field_r_Slot_inst_get (insn) == 15)
30011 return OPCODE_S32RI;
30013 if (Field_op0_Slot_inst_get (insn) == 4)
30015 if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
30016 Field_op1_Slot_inst_get (insn) == 1 &&
30017 Field_op2_Slot_inst_get (insn) == 12)
30018 return OPCODE_AE_LQ56_I;
30019 if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
30020 Field_op1_Slot_inst_get (insn) == 2 &&
30021 Field_op2_Slot_inst_get (insn) == 12)
30022 return OPCODE_AE_LQ56_X;
30023 if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
30024 Field_op1_Slot_inst_get (insn) == 1 &&
30025 Field_op2_Slot_inst_get (insn) == 12)
30026 return OPCODE_AE_LQ32F_I;
30027 if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
30028 Field_op1_Slot_inst_get (insn) == 2 &&
30029 Field_op2_Slot_inst_get (insn) == 12)
30030 return OPCODE_AE_LQ32F_X;
30031 if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30032 Field_op1_Slot_inst_get (insn) == 1 &&
30033 Field_op2_Slot_inst_get (insn) == 12)
30034 return OPCODE_AE_LQ56_IU;
30035 if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30036 Field_op1_Slot_inst_get (insn) == 2 &&
30037 Field_op2_Slot_inst_get (insn) == 12)
30038 return OPCODE_AE_LQ56_XU;
30039 if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30040 Field_op1_Slot_inst_get (insn) == 7 &&
30041 Field_t_Slot_inst_get (insn) == 3 &&
30042 Field_op2_Slot_inst_get (insn) == 14)
30043 return OPCODE_AE_CVTQ48A32S;
30044 if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
30045 Field_op1_Slot_inst_get (insn) == 1 &&
30046 Field_op2_Slot_inst_get (insn) == 12)
30047 return OPCODE_AE_LQ32F_IU;
30048 if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
30049 Field_op1_Slot_inst_get (insn) == 2 &&
30050 Field_op2_Slot_inst_get (insn) == 12)
30051 return OPCODE_AE_LQ32F_XU;
30052 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30053 Field_op1_Slot_inst_get (insn) == 5 &&
30054 Field_op2_Slot_inst_get (insn) == 10)
30055 return OPCODE_AE_LP16F_I;
30056 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30057 Field_op1_Slot_inst_get (insn) == 9 &&
30058 Field_op2_Slot_inst_get (insn) == 10)
30059 return OPCODE_AE_LP16F_IU;
30060 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30061 Field_op1_Slot_inst_get (insn) == 12 &&
30062 Field_op2_Slot_inst_get (insn) == 10)
30063 return OPCODE_AE_LP16F_X;
30064 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30065 Field_op1_Slot_inst_get (insn) == 15 &&
30066 Field_op2_Slot_inst_get (insn) == 10)
30067 return OPCODE_AE_LP16F_XU;
30068 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30069 Field_op1_Slot_inst_get (insn) == 6 &&
30070 Field_op2_Slot_inst_get (insn) == 10)
30071 return OPCODE_AE_LP24F_I;
30072 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30073 Field_op1_Slot_inst_get (insn) == 10 &&
30074 Field_op2_Slot_inst_get (insn) == 10)
30075 return OPCODE_AE_LP24F_IU;
30076 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30077 Field_op1_Slot_inst_get (insn) == 13 &&
30078 Field_op2_Slot_inst_get (insn) == 10)
30079 return OPCODE_AE_LP24F_X;
30080 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30081 Field_op1_Slot_inst_get (insn) == 0 &&
30082 Field_op2_Slot_inst_get (insn) == 11)
30083 return OPCODE_AE_LP24F_XU;
30084 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30085 Field_op1_Slot_inst_get (insn) == 7 &&
30086 Field_op2_Slot_inst_get (insn) == 10)
30087 return OPCODE_AE_LP24X2F_I;
30088 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30089 Field_op1_Slot_inst_get (insn) == 11 &&
30090 Field_op2_Slot_inst_get (insn) == 10)
30091 return OPCODE_AE_LP24X2F_IU;
30092 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30093 Field_op1_Slot_inst_get (insn) == 14 &&
30094 Field_op2_Slot_inst_get (insn) == 10)
30095 return OPCODE_AE_LP24X2F_X;
30096 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30097 Field_op1_Slot_inst_get (insn) == 1 &&
30098 Field_op2_Slot_inst_get (insn) == 11)
30099 return OPCODE_AE_LP24X2F_XU;
30100 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30101 Field_op1_Slot_inst_get (insn) == 2 &&
30102 Field_op2_Slot_inst_get (insn) == 11)
30103 return OPCODE_AE_SP16X2F_I;
30104 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30105 Field_op1_Slot_inst_get (insn) == 5 &&
30106 Field_op2_Slot_inst_get (insn) == 11)
30107 return OPCODE_AE_SP16X2F_IU;
30108 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30109 Field_op1_Slot_inst_get (insn) == 8 &&
30110 Field_op2_Slot_inst_get (insn) == 11)
30111 return OPCODE_AE_SP16X2F_X;
30112 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30113 Field_op1_Slot_inst_get (insn) == 11 &&
30114 Field_op2_Slot_inst_get (insn) == 11)
30115 return OPCODE_AE_SP16X2F_XU;
30116 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30117 Field_op1_Slot_inst_get (insn) == 3 &&
30118 Field_op2_Slot_inst_get (insn) == 11)
30119 return OPCODE_AE_SP24X2F_I;
30120 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30121 Field_op1_Slot_inst_get (insn) == 6 &&
30122 Field_op2_Slot_inst_get (insn) == 11)
30123 return OPCODE_AE_SP24X2F_IU;
30124 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30125 Field_op1_Slot_inst_get (insn) == 9 &&
30126 Field_op2_Slot_inst_get (insn) == 11)
30127 return OPCODE_AE_SP24X2F_X;
30128 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30129 Field_op1_Slot_inst_get (insn) == 12 &&
30130 Field_op2_Slot_inst_get (insn) == 11)
30131 return OPCODE_AE_SP24X2F_XU;
30132 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30133 Field_op1_Slot_inst_get (insn) == 4 &&
30134 Field_op2_Slot_inst_get (insn) == 11)
30135 return OPCODE_AE_SP24S_L_I;
30136 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30137 Field_op1_Slot_inst_get (insn) == 7 &&
30138 Field_op2_Slot_inst_get (insn) == 11)
30139 return OPCODE_AE_SP24S_L_IU;
30140 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30141 Field_op1_Slot_inst_get (insn) == 10 &&
30142 Field_op2_Slot_inst_get (insn) == 11)
30143 return OPCODE_AE_SP24S_L_X;
30144 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30145 Field_op1_Slot_inst_get (insn) == 13 &&
30146 Field_op2_Slot_inst_get (insn) == 11)
30147 return OPCODE_AE_SP24S_L_XU;
30148 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30149 Field_ae_s3_Slot_inst_get (insn) == 0 &&
30150 Field_t_Slot_inst_get (insn) == 0 &&
30151 Field_op1_Slot_inst_get (insn) == 9 &&
30152 Field_op2_Slot_inst_get (insn) == 12)
30153 return OPCODE_AE_MOVP48;
30154 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30155 Field_op1_Slot_inst_get (insn) == 0 &&
30156 Field_op2_Slot_inst_get (insn) == 12)
30157 return OPCODE_AE_MOVPA24X2;
30158 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30159 Field_t_Slot_inst_get (insn) == 0 &&
30160 Field_op1_Slot_inst_get (insn) == 11 &&
30161 Field_op2_Slot_inst_get (insn) == 12)
30162 return OPCODE_AE_CVTA32P24_L;
30163 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30164 Field_op1_Slot_inst_get (insn) == 14 &&
30165 Field_op2_Slot_inst_get (insn) == 11)
30166 return OPCODE_AE_CVTP24A16X2_LL;
30167 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30168 Field_op1_Slot_inst_get (insn) == 15 &&
30169 Field_op2_Slot_inst_get (insn) == 11)
30170 return OPCODE_AE_CVTP24A16X2_HL;
30171 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30172 Field_t_Slot_inst_get (insn) == 0 &&
30173 Field_op1_Slot_inst_get (insn) == 7 &&
30174 Field_op2_Slot_inst_get (insn) == 12)
30175 return OPCODE_AE_MOVAP24S_L;
30176 if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30177 Field_t_Slot_inst_get (insn) == 0 &&
30178 Field_op1_Slot_inst_get (insn) == 8 &&
30179 Field_op2_Slot_inst_get (insn) == 12)
30180 return OPCODE_AE_TRUNCA16P24S_L;
30181 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30182 Field_op1_Slot_inst_get (insn) == 5 &&
30183 Field_op2_Slot_inst_get (insn) == 10)
30184 return OPCODE_AE_LP24_I;
30185 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30186 Field_op1_Slot_inst_get (insn) == 9 &&
30187 Field_op2_Slot_inst_get (insn) == 10)
30188 return OPCODE_AE_LP24_IU;
30189 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30190 Field_op1_Slot_inst_get (insn) == 12 &&
30191 Field_op2_Slot_inst_get (insn) == 10)
30192 return OPCODE_AE_LP24_X;
30193 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30194 Field_op1_Slot_inst_get (insn) == 15 &&
30195 Field_op2_Slot_inst_get (insn) == 10)
30196 return OPCODE_AE_LP24_XU;
30197 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30198 Field_op1_Slot_inst_get (insn) == 6 &&
30199 Field_op2_Slot_inst_get (insn) == 10)
30200 return OPCODE_AE_LP16X2F_I;
30201 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30202 Field_op1_Slot_inst_get (insn) == 10 &&
30203 Field_op2_Slot_inst_get (insn) == 10)
30204 return OPCODE_AE_LP16X2F_IU;
30205 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30206 Field_op1_Slot_inst_get (insn) == 13 &&
30207 Field_op2_Slot_inst_get (insn) == 10)
30208 return OPCODE_AE_LP16X2F_X;
30209 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30210 Field_op1_Slot_inst_get (insn) == 0 &&
30211 Field_op2_Slot_inst_get (insn) == 11)
30212 return OPCODE_AE_LP16X2F_XU;
30213 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30214 Field_op1_Slot_inst_get (insn) == 7 &&
30215 Field_op2_Slot_inst_get (insn) == 10)
30216 return OPCODE_AE_LP24X2_I;
30217 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30218 Field_op1_Slot_inst_get (insn) == 11 &&
30219 Field_op2_Slot_inst_get (insn) == 10)
30220 return OPCODE_AE_LP24X2_IU;
30221 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30222 Field_op1_Slot_inst_get (insn) == 14 &&
30223 Field_op2_Slot_inst_get (insn) == 10)
30224 return OPCODE_AE_LP24X2_X;
30225 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30226 Field_op1_Slot_inst_get (insn) == 1 &&
30227 Field_op2_Slot_inst_get (insn) == 11)
30228 return OPCODE_AE_LP24X2_XU;
30229 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30230 Field_op1_Slot_inst_get (insn) == 2 &&
30231 Field_op2_Slot_inst_get (insn) == 11)
30232 return OPCODE_AE_SP24X2S_I;
30233 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30234 Field_op1_Slot_inst_get (insn) == 5 &&
30235 Field_op2_Slot_inst_get (insn) == 11)
30236 return OPCODE_AE_SP24X2S_IU;
30237 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30238 Field_op1_Slot_inst_get (insn) == 8 &&
30239 Field_op2_Slot_inst_get (insn) == 11)
30240 return OPCODE_AE_SP24X2S_X;
30241 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30242 Field_op1_Slot_inst_get (insn) == 11 &&
30243 Field_op2_Slot_inst_get (insn) == 11)
30244 return OPCODE_AE_SP24X2S_XU;
30245 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30246 Field_op1_Slot_inst_get (insn) == 3 &&
30247 Field_op2_Slot_inst_get (insn) == 11)
30248 return OPCODE_AE_SP16F_L_I;
30249 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30250 Field_op1_Slot_inst_get (insn) == 6 &&
30251 Field_op2_Slot_inst_get (insn) == 11)
30252 return OPCODE_AE_SP16F_L_IU;
30253 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30254 Field_op1_Slot_inst_get (insn) == 9 &&
30255 Field_op2_Slot_inst_get (insn) == 11)
30256 return OPCODE_AE_SP16F_L_X;
30257 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30258 Field_op1_Slot_inst_get (insn) == 12 &&
30259 Field_op2_Slot_inst_get (insn) == 11)
30260 return OPCODE_AE_SP16F_L_XU;
30261 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30262 Field_op1_Slot_inst_get (insn) == 4 &&
30263 Field_op2_Slot_inst_get (insn) == 11)
30264 return OPCODE_AE_SP24F_L_I;
30265 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30266 Field_op1_Slot_inst_get (insn) == 7 &&
30267 Field_op2_Slot_inst_get (insn) == 11)
30268 return OPCODE_AE_SP24F_L_IU;
30269 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30270 Field_op1_Slot_inst_get (insn) == 10 &&
30271 Field_op2_Slot_inst_get (insn) == 11)
30272 return OPCODE_AE_SP24F_L_X;
30273 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30274 Field_op1_Slot_inst_get (insn) == 13 &&
30275 Field_op2_Slot_inst_get (insn) == 11)
30276 return OPCODE_AE_SP24F_L_XU;
30277 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30278 Field_op1_Slot_inst_get (insn) == 0 &&
30279 Field_op2_Slot_inst_get (insn) == 12)
30280 return OPCODE_AE_TRUNCP24A32X2;
30281 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30282 Field_t_Slot_inst_get (insn) == 0 &&
30283 Field_op1_Slot_inst_get (insn) == 11 &&
30284 Field_op2_Slot_inst_get (insn) == 12)
30285 return OPCODE_AE_CVTA32P24_H;
30286 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30287 Field_op1_Slot_inst_get (insn) == 14 &&
30288 Field_op2_Slot_inst_get (insn) == 11)
30289 return OPCODE_AE_CVTP24A16X2_LH;
30290 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30291 Field_op1_Slot_inst_get (insn) == 15 &&
30292 Field_op2_Slot_inst_get (insn) == 11)
30293 return OPCODE_AE_CVTP24A16X2_HH;
30294 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30295 Field_t_Slot_inst_get (insn) == 0 &&
30296 Field_op1_Slot_inst_get (insn) == 7 &&
30297 Field_op2_Slot_inst_get (insn) == 12)
30298 return OPCODE_AE_MOVAP24S_H;
30299 if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30300 Field_t_Slot_inst_get (insn) == 0 &&
30301 Field_op1_Slot_inst_get (insn) == 8 &&
30302 Field_op2_Slot_inst_get (insn) == 12)
30303 return OPCODE_AE_TRUNCA16P24S_H;
30304 if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30305 Field_op1_Slot_inst_get (insn) == 3 &&
30306 Field_op2_Slot_inst_get (insn) == 12)
30307 return OPCODE_AE_SQ56S_I;
30308 if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30309 Field_op1_Slot_inst_get (insn) == 4 &&
30310 Field_op2_Slot_inst_get (insn) == 12)
30311 return OPCODE_AE_SQ56S_X;
30312 if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30313 Field_op1_Slot_inst_get (insn) == 7 &&
30314 Field_t_Slot_inst_get (insn) == 1 &&
30315 Field_op2_Slot_inst_get (insn) == 14)
30316 return OPCODE_AE_TRUNCA32Q48;
30317 if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30318 Field_op1_Slot_inst_get (insn) == 3 &&
30319 Field_op2_Slot_inst_get (insn) == 12)
30320 return OPCODE_AE_SQ32F_I;
30321 if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30322 Field_op1_Slot_inst_get (insn) == 4 &&
30323 Field_op2_Slot_inst_get (insn) == 12)
30324 return OPCODE_AE_SQ32F_X;
30325 if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30326 Field_op1_Slot_inst_get (insn) == 7 &&
30327 Field_t_Slot_inst_get (insn) == 1 &&
30328 Field_op2_Slot_inst_get (insn) == 14)
30329 return OPCODE_AE_NSAQ56S;
30330 if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
30331 Field_op1_Slot_inst_get (insn) == 3 &&
30332 Field_op2_Slot_inst_get (insn) == 12)
30333 return OPCODE_AE_SQ56S_IU;
30334 if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
30335 Field_op1_Slot_inst_get (insn) == 4 &&
30336 Field_op2_Slot_inst_get (insn) == 12)
30337 return OPCODE_AE_SQ56S_XU;
30338 if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
30339 Field_op1_Slot_inst_get (insn) == 3 &&
30340 Field_op2_Slot_inst_get (insn) == 12)
30341 return OPCODE_AE_SQ32F_IU;
30342 if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
30343 Field_op1_Slot_inst_get (insn) == 4 &&
30344 Field_op2_Slot_inst_get (insn) == 12)
30345 return OPCODE_AE_SQ32F_XU;
30346 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
30347 Field_op1_Slot_inst_get (insn) == 5 &&
30348 Field_op2_Slot_inst_get (insn) == 12)
30349 return OPCODE_AE_SLLIQ56;
30350 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
30351 Field_op1_Slot_inst_get (insn) == 5 &&
30352 Field_op2_Slot_inst_get (insn) == 12)
30353 return OPCODE_AE_SRLIQ56;
30354 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
30355 Field_op1_Slot_inst_get (insn) == 5 &&
30356 Field_op2_Slot_inst_get (insn) == 12)
30357 return OPCODE_AE_SRAIQ56;
30358 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
30359 Field_op1_Slot_inst_get (insn) == 5 &&
30360 Field_op2_Slot_inst_get (insn) == 12)
30361 return OPCODE_AE_SLLISQ56S;
30362 if (Field_op1_Slot_inst_get (insn) == 0 &&
30363 Field_t_Slot_inst_get (insn) == 1 &&
30364 Field_op2_Slot_inst_get (insn) == 14)
30365 return OPCODE_AE_SHA32;
30366 if (Field_op1_Slot_inst_get (insn) == 0 &&
30367 Field_op2_Slot_inst_get (insn) == 10)
30368 return OPCODE_AE_VLDL32T;
30369 if (Field_op1_Slot_inst_get (insn) == 1 &&
30370 Field_t_Slot_inst_get (insn) == 1 &&
30371 Field_op2_Slot_inst_get (insn) == 14)
30372 return OPCODE_AE_SLLAQ56;
30373 if (Field_op1_Slot_inst_get (insn) == 1 &&
30374 Field_op2_Slot_inst_get (insn) == 10)
30375 return OPCODE_AE_VLDL16T;
30376 if (Field_op1_Slot_inst_get (insn) == 2 &&
30377 Field_t_Slot_inst_get (insn) == 1 &&
30378 Field_op2_Slot_inst_get (insn) == 14)
30379 return OPCODE_AE_SRLAQ56;
30380 if (Field_op1_Slot_inst_get (insn) == 2 &&
30381 Field_op2_Slot_inst_get (insn) == 10)
30382 return OPCODE_AE_LBK;
30383 if (Field_op1_Slot_inst_get (insn) == 3 &&
30384 Field_t_Slot_inst_get (insn) == 1 &&
30385 Field_op2_Slot_inst_get (insn) == 14)
30386 return OPCODE_AE_SRAAQ56;
30387 if (Field_op1_Slot_inst_get (insn) == 3 &&
30388 Field_op2_Slot_inst_get (insn) == 10)
30389 return OPCODE_AE_VLEL32T;
30390 if (Field_op1_Slot_inst_get (insn) == 4 &&
30391 Field_t_Slot_inst_get (insn) == 1 &&
30392 Field_op2_Slot_inst_get (insn) == 14)
30393 return OPCODE_AE_SLLASQ56S;
30394 if (Field_op1_Slot_inst_get (insn) == 4 &&
30395 Field_op2_Slot_inst_get (insn) == 10)
30396 return OPCODE_AE_VLEL16T;
30397 if (Field_op1_Slot_inst_get (insn) == 5 &&
30398 Field_t_Slot_inst_get (insn) == 1 &&
30399 Field_op2_Slot_inst_get (insn) == 14)
30400 return OPCODE_AE_MOVTQ56;
30401 if (Field_op1_Slot_inst_get (insn) == 6 &&
30402 Field_t_Slot_inst_get (insn) == 1 &&
30403 Field_op2_Slot_inst_get (insn) == 14)
30404 return OPCODE_AE_MOVFQ56;
30405 if (Field_r_Slot_inst_get (insn) == 0 &&
30406 Field_s_Slot_inst_get (insn) == 0 &&
30407 Field_op1_Slot_inst_get (insn) == 10 &&
30408 Field_op2_Slot_inst_get (insn) == 12)
30409 return OPCODE_WUR_AE_OVERFLOW;
30410 if (Field_r_Slot_inst_get (insn) == 0 &&
30411 Field_op2_Slot_inst_get (insn) == 15)
30412 return OPCODE_AE_SBI;
30413 if (Field_r_Slot_inst_get (insn) == 1 &&
30414 Field_s_Slot_inst_get (insn) == 0 &&
30415 Field_op1_Slot_inst_get (insn) == 10 &&
30416 Field_op2_Slot_inst_get (insn) == 12)
30417 return OPCODE_WUR_AE_SAR;
30418 if (Field_r_Slot_inst_get (insn) == 1 &&
30419 Field_op1_Slot_inst_get (insn) == 0 &&
30420 Field_op2_Slot_inst_get (insn) == 15)
30421 return OPCODE_AE_DB;
30422 if (Field_r_Slot_inst_get (insn) == 1 &&
30423 Field_op1_Slot_inst_get (insn) == 1 &&
30424 Field_op2_Slot_inst_get (insn) == 15)
30425 return OPCODE_AE_SB;
30426 if (Field_r_Slot_inst_get (insn) == 2 &&
30427 Field_s_Slot_inst_get (insn) == 0 &&
30428 Field_op1_Slot_inst_get (insn) == 10 &&
30429 Field_op2_Slot_inst_get (insn) == 12)
30430 return OPCODE_WUR_AE_BITPTR;
30431 if (Field_r_Slot_inst_get (insn) == 3 &&
30432 Field_s_Slot_inst_get (insn) == 0 &&
30433 Field_op1_Slot_inst_get (insn) == 10 &&
30434 Field_op2_Slot_inst_get (insn) == 12)
30435 return OPCODE_WUR_AE_BITSUSED;
30436 if (Field_r_Slot_inst_get (insn) == 4 &&
30437 Field_s_Slot_inst_get (insn) == 0 &&
30438 Field_op1_Slot_inst_get (insn) == 10 &&
30439 Field_op2_Slot_inst_get (insn) == 12)
30440 return OPCODE_WUR_AE_TABLESIZE;
30441 if (Field_r_Slot_inst_get (insn) == 5 &&
30442 Field_s_Slot_inst_get (insn) == 0 &&
30443 Field_op1_Slot_inst_get (insn) == 10 &&
30444 Field_op2_Slot_inst_get (insn) == 12)
30445 return OPCODE_WUR_AE_FIRST_TS;
30446 if (Field_r_Slot_inst_get (insn) == 6 &&
30447 Field_s_Slot_inst_get (insn) == 0 &&
30448 Field_op1_Slot_inst_get (insn) == 10 &&
30449 Field_op2_Slot_inst_get (insn) == 12)
30450 return OPCODE_WUR_AE_NEXTOFFSET;
30451 if (Field_r_Slot_inst_get (insn) == 7 &&
30452 Field_s_Slot_inst_get (insn) == 0 &&
30453 Field_op1_Slot_inst_get (insn) == 10 &&
30454 Field_op2_Slot_inst_get (insn) == 12)
30455 return OPCODE_WUR_AE_SEARCHDONE;
30456 if (Field_r_Slot_inst_get (insn) == 8 &&
30457 Field_s_Slot_inst_get (insn) == 0 &&
30458 Field_op1_Slot_inst_get (insn) == 10 &&
30459 Field_op2_Slot_inst_get (insn) == 12)
30460 return OPCODE_AE_VLDSHT;
30461 if (Field_r_Slot_inst_get (insn) == 12 &&
30462 Field_op1_Slot_inst_get (insn) == 7 &&
30463 Field_t_Slot_inst_get (insn) == 1 &&
30464 Field_op2_Slot_inst_get (insn) == 14)
30465 return OPCODE_AE_VLES16C;
30466 if (Field_r_Slot_inst_get (insn) == 13 &&
30467 Field_op1_Slot_inst_get (insn) == 7 &&
30468 Field_t_Slot_inst_get (insn) == 1 &&
30469 Field_op2_Slot_inst_get (insn) == 14)
30470 return OPCODE_AE_SBF;
30471 if (Field_r_Slot_inst_get (insn) == 14 &&
30472 Field_op1_Slot_inst_get (insn) == 7 &&
30473 Field_t_Slot_inst_get (insn) == 1 &&
30474 Field_op2_Slot_inst_get (insn) == 14)
30475 return OPCODE_AE_VLDL16C;
30476 if (Field_s_Slot_inst_get (insn) == 0 &&
30477 Field_t_Slot_inst_get (insn) == 1 &&
30478 Field_op1_Slot_inst_get (insn) == 9 &&
30479 Field_op2_Slot_inst_get (insn) == 12)
30480 return OPCODE_AE_SLLSQ56;
30481 if (Field_s_Slot_inst_get (insn) == 0 &&
30482 Field_op1_Slot_inst_get (insn) == 6 &&
30483 Field_op2_Slot_inst_get (insn) == 12)
30484 return OPCODE_AE_LB;
30485 if (Field_s_Slot_inst_get (insn) == 1 &&
30486 Field_t_Slot_inst_get (insn) == 1 &&
30487 Field_op1_Slot_inst_get (insn) == 9 &&
30488 Field_op2_Slot_inst_get (insn) == 12)
30489 return OPCODE_AE_SRLSQ56;
30490 if (Field_s_Slot_inst_get (insn) == 2 &&
30491 Field_t_Slot_inst_get (insn) == 1 &&
30492 Field_op1_Slot_inst_get (insn) == 9 &&
30493 Field_op2_Slot_inst_get (insn) == 12)
30494 return OPCODE_AE_SRASQ56;
30495 if (Field_s_Slot_inst_get (insn) == 3 &&
30496 Field_t_Slot_inst_get (insn) == 1 &&
30497 Field_op1_Slot_inst_get (insn) == 9 &&
30498 Field_op2_Slot_inst_get (insn) == 12)
30499 return OPCODE_AE_SLLSSQ56S;
30500 if (Field_s_Slot_inst_get (insn) == 4 &&
30501 Field_t_Slot_inst_get (insn) == 1 &&
30502 Field_op1_Slot_inst_get (insn) == 9 &&
30503 Field_op2_Slot_inst_get (insn) == 12)
30504 return OPCODE_AE_MOVQ56;
30505 if (Field_s_Slot_inst_get (insn) == 8 &&
30506 Field_t_Slot_inst_get (insn) == 0 &&
30507 Field_op1_Slot_inst_get (insn) == 9 &&
30508 Field_op2_Slot_inst_get (insn) == 12)
30509 return OPCODE_RUR_AE_OVERFLOW;
30510 if (Field_s_Slot_inst_get (insn) == 9 &&
30511 Field_t_Slot_inst_get (insn) == 0 &&
30512 Field_op1_Slot_inst_get (insn) == 9 &&
30513 Field_op2_Slot_inst_get (insn) == 12)
30514 return OPCODE_RUR_AE_SAR;
30515 if (Field_s_Slot_inst_get (insn) == 10 &&
30516 Field_t_Slot_inst_get (insn) == 0 &&
30517 Field_op1_Slot_inst_get (insn) == 9 &&
30518 Field_op2_Slot_inst_get (insn) == 12)
30519 return OPCODE_RUR_AE_BITPTR;
30520 if (Field_s_Slot_inst_get (insn) == 11 &&
30521 Field_t_Slot_inst_get (insn) == 0 &&
30522 Field_op1_Slot_inst_get (insn) == 9 &&
30523 Field_op2_Slot_inst_get (insn) == 12)
30524 return OPCODE_RUR_AE_BITSUSED;
30525 if (Field_s_Slot_inst_get (insn) == 12 &&
30526 Field_t_Slot_inst_get (insn) == 0 &&
30527 Field_op1_Slot_inst_get (insn) == 9 &&
30528 Field_op2_Slot_inst_get (insn) == 12)
30529 return OPCODE_RUR_AE_TABLESIZE;
30530 if (Field_s_Slot_inst_get (insn) == 13 &&
30531 Field_t_Slot_inst_get (insn) == 0 &&
30532 Field_op1_Slot_inst_get (insn) == 9 &&
30533 Field_op2_Slot_inst_get (insn) == 12)
30534 return OPCODE_RUR_AE_FIRST_TS;
30535 if (Field_s_Slot_inst_get (insn) == 14 &&
30536 Field_t_Slot_inst_get (insn) == 0 &&
30537 Field_op1_Slot_inst_get (insn) == 9 &&
30538 Field_op2_Slot_inst_get (insn) == 12)
30539 return OPCODE_RUR_AE_NEXTOFFSET;
30540 if (Field_s_Slot_inst_get (insn) == 15 &&
30541 Field_t_Slot_inst_get (insn) == 0 &&
30542 Field_op1_Slot_inst_get (insn) == 9 &&
30543 Field_op2_Slot_inst_get (insn) == 12)
30544 return OPCODE_RUR_AE_SEARCHDONE;
30545 if (Field_t_Slot_inst_get (insn) == 0 &&
30546 Field_op2_Slot_inst_get (insn) == 14)
30547 return OPCODE_AE_LBKI;
30548 if (Field_t_Slot_inst_get (insn) == 0 &&
30549 Field_r_Slot_inst_get (insn) == 2 &&
30550 Field_op2_Slot_inst_get (insn) == 15)
30551 return OPCODE_AE_DBI;
30552 if (Field_t_Slot_inst_get (insn) == 2 &&
30553 Field_s_Slot_inst_get (insn) == 0 &&
30554 Field_op2_Slot_inst_get (insn) == 14)
30555 return OPCODE_AE_LBI;
30557 if (Field_op0_Slot_inst_get (insn) == 5)
30559 if (Field_n_Slot_inst_get (insn) == 0)
30560 return OPCODE_CALL0;
30561 if (Field_n_Slot_inst_get (insn) == 1)
30562 return OPCODE_CALL4;
30563 if (Field_n_Slot_inst_get (insn) == 2)
30564 return OPCODE_CALL8;
30565 if (Field_n_Slot_inst_get (insn) == 3)
30566 return OPCODE_CALL12;
30568 if (Field_op0_Slot_inst_get (insn) == 6)
30570 if (Field_n_Slot_inst_get (insn) == 0)
30572 if (Field_n_Slot_inst_get (insn) == 1)
30574 if (Field_m_Slot_inst_get (insn) == 0)
30575 return OPCODE_BEQZ;
30576 if (Field_m_Slot_inst_get (insn) == 1)
30577 return OPCODE_BNEZ;
30578 if (Field_m_Slot_inst_get (insn) == 2)
30579 return OPCODE_BLTZ;
30580 if (Field_m_Slot_inst_get (insn) == 3)
30581 return OPCODE_BGEZ;
30583 if (Field_n_Slot_inst_get (insn) == 2)
30585 if (Field_m_Slot_inst_get (insn) == 0)
30586 return OPCODE_BEQI;
30587 if (Field_m_Slot_inst_get (insn) == 1)
30588 return OPCODE_BNEI;
30589 if (Field_m_Slot_inst_get (insn) == 2)
30590 return OPCODE_BLTI;
30591 if (Field_m_Slot_inst_get (insn) == 3)
30592 return OPCODE_BGEI;
30594 if (Field_n_Slot_inst_get (insn) == 3)
30596 if (Field_m_Slot_inst_get (insn) == 0)
30597 return OPCODE_ENTRY;
30598 if (Field_m_Slot_inst_get (insn) == 1)
30600 if (Field_r_Slot_inst_get (insn) == 0)
30602 if (Field_r_Slot_inst_get (insn) == 1)
30604 if (Field_r_Slot_inst_get (insn) == 8)
30605 return OPCODE_LOOP;
30606 if (Field_r_Slot_inst_get (insn) == 9)
30607 return OPCODE_LOOPNEZ;
30608 if (Field_r_Slot_inst_get (insn) == 10)
30609 return OPCODE_LOOPGTZ;
30611 if (Field_m_Slot_inst_get (insn) == 2)
30612 return OPCODE_BLTUI;
30613 if (Field_m_Slot_inst_get (insn) == 3)
30614 return OPCODE_BGEUI;
30617 if (Field_op0_Slot_inst_get (insn) == 7)
30619 if (Field_r_Slot_inst_get (insn) == 0)
30620 return OPCODE_BNONE;
30621 if (Field_r_Slot_inst_get (insn) == 1)
30623 if (Field_r_Slot_inst_get (insn) == 2)
30625 if (Field_r_Slot_inst_get (insn) == 3)
30626 return OPCODE_BLTU;
30627 if (Field_r_Slot_inst_get (insn) == 4)
30628 return OPCODE_BALL;
30629 if (Field_r_Slot_inst_get (insn) == 5)
30631 if ((Field_r_Slot_inst_get (insn) == 6 ||
30632 Field_r_Slot_inst_get (insn) == 7))
30633 return OPCODE_BBCI;
30634 if (Field_r_Slot_inst_get (insn) == 8)
30635 return OPCODE_BANY;
30636 if (Field_r_Slot_inst_get (insn) == 9)
30638 if (Field_r_Slot_inst_get (insn) == 10)
30640 if (Field_r_Slot_inst_get (insn) == 11)
30641 return OPCODE_BGEU;
30642 if (Field_r_Slot_inst_get (insn) == 12)
30643 return OPCODE_BNALL;
30644 if (Field_r_Slot_inst_get (insn) == 13)
30646 if ((Field_r_Slot_inst_get (insn) == 14 ||
30647 Field_r_Slot_inst_get (insn) == 15))
30648 return OPCODE_BBSI;
30650 return XTENSA_UNDEFINED;
30654 Slot_inst16b_decode (const xtensa_insnbuf insn)
30656 if (Field_op0_Slot_inst16b_get (insn) == 12)
30658 if (Field_i_Slot_inst16b_get (insn) == 0)
30659 return OPCODE_MOVI_N;
30660 if (Field_i_Slot_inst16b_get (insn) == 1)
30662 if (Field_z_Slot_inst16b_get (insn) == 0)
30663 return OPCODE_BEQZ_N;
30664 if (Field_z_Slot_inst16b_get (insn) == 1)
30665 return OPCODE_BNEZ_N;
30668 if (Field_op0_Slot_inst16b_get (insn) == 13)
30670 if (Field_r_Slot_inst16b_get (insn) == 0)
30671 return OPCODE_MOV_N;
30672 if (Field_r_Slot_inst16b_get (insn) == 15)
30674 if (Field_t_Slot_inst16b_get (insn) == 0)
30675 return OPCODE_RET_N;
30676 if (Field_t_Slot_inst16b_get (insn) == 1)
30677 return OPCODE_RETW_N;
30678 if (Field_t_Slot_inst16b_get (insn) == 2)
30679 return OPCODE_BREAK_N;
30680 if (Field_t_Slot_inst16b_get (insn) == 3 &&
30681 Field_s_Slot_inst16b_get (insn) == 0)
30682 return OPCODE_NOP_N;
30683 if (Field_t_Slot_inst16b_get (insn) == 6 &&
30684 Field_s_Slot_inst16b_get (insn) == 0)
30685 return OPCODE_ILL_N;
30688 return XTENSA_UNDEFINED;
30692 Slot_inst16a_decode (const xtensa_insnbuf insn)
30694 if (Field_op0_Slot_inst16a_get (insn) == 8)
30695 return OPCODE_L32I_N;
30696 if (Field_op0_Slot_inst16a_get (insn) == 9)
30697 return OPCODE_S32I_N;
30698 if (Field_op0_Slot_inst16a_get (insn) == 10)
30699 return OPCODE_ADD_N;
30700 if (Field_op0_Slot_inst16a_get (insn) == 11)
30701 return OPCODE_ADDI_N;
30702 return XTENSA_UNDEFINED;
30706 Slot_ae_slot0_decode (const xtensa_insnbuf insn)
30708 if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
30709 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30711 if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
30712 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30713 return OPCODE_EXTUI;
30714 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
30715 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30716 return OPCODE_BGEZ;
30717 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
30718 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30719 return OPCODE_BLTZ;
30720 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 &&
30721 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30722 return OPCODE_BEQZ;
30723 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 &&
30724 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30725 return OPCODE_BNEZ;
30726 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
30727 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30728 return OPCODE_MOVI;
30729 if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 &&
30730 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30731 return OPCODE_SRAI;
30732 if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 &&
30733 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30734 return OPCODE_SLLI;
30735 if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
30736 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30737 Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
30738 return OPCODE_AE_MOVTQ56;
30739 if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
30740 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30741 return OPCODE_AE_CVTP24A16X2_HH;
30742 if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 &&
30743 Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
30744 Field_ae_r20_Slot_ae_slot0_get (insn) == 0)
30745 return OPCODE_L32I;
30746 if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 &&
30747 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30748 return OPCODE_AE_LP16F_I;
30749 if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 &&
30750 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30751 return OPCODE_AE_CVTP24A16X2_HL;
30752 if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 &&
30753 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30754 return OPCODE_AE_LP16F_IU;
30755 if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 &&
30756 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30757 return OPCODE_AE_LP16F_X;
30758 if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 &&
30759 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30760 return OPCODE_AE_LP16F_XU;
30761 if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 &&
30762 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30763 return OPCODE_AE_CVTP24A16X2_LH;
30764 if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 &&
30765 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30766 return OPCODE_AE_LP16X2F_I;
30767 if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
30768 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30769 return OPCODE_AE_LP16X2F_IU;
30770 if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
30771 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30772 return OPCODE_AE_LP16X2F_XU;
30773 if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 &&
30774 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30775 return OPCODE_AE_LP16X2F_X;
30776 if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 &&
30777 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30778 return OPCODE_AE_LP24_I;
30779 if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
30780 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30781 return OPCODE_AE_LP24_IU;
30782 if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
30783 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30784 return OPCODE_AE_LP24_X;
30785 if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 &&
30786 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30787 return OPCODE_AE_CVTP24A16X2_LL;
30788 if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 &&
30789 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30790 return OPCODE_AE_LP24_XU;
30791 if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 &&
30792 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30793 return OPCODE_AE_LP24F_I;
30794 if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 &&
30795 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30796 return OPCODE_AE_LP24F_XU;
30797 if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 &&
30798 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30799 return OPCODE_AE_LP24F_IU;
30800 if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 &&
30801 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30802 return OPCODE_AE_LP24X2_I;
30803 if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 &&
30804 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30805 return OPCODE_AE_LP24X2_IU;
30806 if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 &&
30807 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30808 return OPCODE_AE_LP24X2_X;
30809 if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 &&
30810 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30811 return OPCODE_AE_LP24F_X;
30812 if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 &&
30813 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30814 return OPCODE_AE_LP24X2_XU;
30815 if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
30816 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30817 return OPCODE_AE_LP24X2F_I;
30818 if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
30819 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30820 return OPCODE_AE_LP24X2F_X;
30821 if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 &&
30822 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30823 return OPCODE_AE_LP24X2F_IU;
30824 if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 &&
30825 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30826 return OPCODE_AE_LP24X2F_XU;
30827 if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
30828 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30829 return OPCODE_AE_MOVPA24X2;
30830 if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
30831 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30832 return OPCODE_AE_SP16F_L_I;
30833 if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 &&
30834 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30835 return OPCODE_AE_SP16F_L_IU;
30836 if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 &&
30837 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30838 return OPCODE_AE_SP16X2F_X;
30839 if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 &&
30840 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30841 return OPCODE_AE_SP16F_L_X;
30842 if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 &&
30843 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30844 return OPCODE_AE_SP16X2F_XU;
30845 if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 &&
30846 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30847 return OPCODE_AE_SP24F_L_I;
30848 if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 &&
30849 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30850 return OPCODE_AE_SP24F_L_IU;
30851 if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 &&
30852 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30853 return OPCODE_AE_SP16F_L_XU;
30854 if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 &&
30855 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30856 return OPCODE_AE_SP24F_L_X;
30857 if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 &&
30858 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30859 return OPCODE_AE_SP24F_L_XU;
30860 if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
30861 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30862 return OPCODE_AE_SP24S_L_IU;
30863 if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 &&
30864 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30865 return OPCODE_AE_SP24S_L_I;
30866 if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 &&
30867 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30868 return OPCODE_AE_SP24S_L_X;
30869 if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 &&
30870 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30871 return OPCODE_AE_SP24S_L_XU;
30872 if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 &&
30873 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30874 return OPCODE_AE_SP24X2F_I;
30875 if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 &&
30876 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30877 return OPCODE_AE_SP16X2F_I;
30878 if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 &&
30879 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30880 return OPCODE_AE_SP24X2F_IU;
30881 if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 &&
30882 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30883 return OPCODE_AE_SP24X2F_X;
30884 if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 &&
30885 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30886 return OPCODE_AE_SP24X2S_IU;
30887 if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 &&
30888 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30889 return OPCODE_AE_SP24X2F_XU;
30890 if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 &&
30891 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30892 return OPCODE_AE_SP24X2S_X;
30893 if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 &&
30894 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30895 return OPCODE_AE_SP24X2S_XU;
30896 if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 &&
30897 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30898 return OPCODE_AE_TRUNCP24A32X2;
30899 if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 &&
30900 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30901 return OPCODE_AE_SP24X2S_I;
30902 if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 &&
30903 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30904 return OPCODE_AE_SQ32F_I;
30905 if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 &&
30906 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30907 return OPCODE_AE_SQ32F_IU;
30908 if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 &&
30909 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30910 return OPCODE_AE_LQ32F_I;
30911 if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 &&
30912 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30913 return OPCODE_AE_LQ32F_X;
30914 if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 &&
30915 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30916 return OPCODE_AE_LQ32F_XU;
30917 if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 &&
30918 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30919 return OPCODE_AE_LQ56_I;
30920 if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 &&
30921 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30922 return OPCODE_AE_LQ32F_IU;
30923 if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 &&
30924 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30925 return OPCODE_AE_LQ56_IU;
30926 if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 &&
30927 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30928 return OPCODE_AE_LQ56_X;
30929 if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 &&
30930 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30931 return OPCODE_AE_CVTQ48A32S;
30932 if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 &&
30933 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30935 if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 &&
30936 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30938 if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 &&
30939 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30940 Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0)
30942 if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 &&
30943 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30944 Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0)
30945 return OPCODE_SSA8B;
30946 if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 &&
30947 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30948 Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0)
30949 return OPCODE_SSA8L;
30950 if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 &&
30951 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30952 Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0)
30954 if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
30955 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30956 Field_s8_Slot_ae_slot0_get (insn) == 0)
30957 return OPCODE_AE_LQ56_XU;
30958 if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 &&
30959 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30960 Field_s_Slot_ae_slot0_get (insn) == 0)
30961 return OPCODE_ALL8;
30962 if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 &&
30963 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
30964 return OPCODE_BBCI;
30965 if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 &&
30966 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
30967 return OPCODE_BBSI;
30968 if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
30969 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30970 Field_s_Slot_ae_slot0_get (insn) == 0)
30971 return OPCODE_ANY8;
30972 if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 &&
30973 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30974 Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0)
30975 return OPCODE_SSAI;
30976 if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 &&
30977 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30978 return OPCODE_AE_SP16X2F_IU;
30979 if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 &&
30980 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30981 return OPCODE_AE_SQ56S_I;
30982 if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
30983 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30984 return OPCODE_AE_SQ56S_IU;
30985 if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 &&
30986 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30987 return OPCODE_AE_SLLIQ56;
30988 if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 &&
30989 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30990 return OPCODE_AE_SRAIQ56;
30991 if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 &&
30992 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30993 return OPCODE_AE_SRLIQ56;
30994 if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 &&
30995 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30996 return OPCODE_AE_SLLISQ56S;
30997 if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 &&
30998 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31000 if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 &&
31001 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31003 if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 &&
31004 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31006 if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 &&
31007 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31009 if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 &&
31010 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31011 Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31012 return OPCODE_AE_MOVP48;
31013 if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 &&
31014 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31015 Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
31016 return OPCODE_ANY4;
31017 if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
31018 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31019 Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31020 return OPCODE_AE_MOVQ56;
31021 if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 &&
31022 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31023 Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31024 return OPCODE_AE_SLLSSQ56S;
31025 if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 &&
31026 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31027 Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0)
31028 return OPCODE_AE_SRASQ56;
31029 if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 &&
31030 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31031 Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
31032 return OPCODE_AE_SRLSQ56;
31033 if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 &&
31034 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31035 Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
31036 return OPCODE_AE_SLLSQ56;
31037 if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 &&
31038 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31039 Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
31040 return OPCODE_ALL4;
31041 if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 &&
31042 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31043 return OPCODE_AE_SQ56S_X;
31044 if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 &&
31045 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31046 return OPCODE_AE_SQ56S_XU;
31047 if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 &&
31048 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31049 return OPCODE_AE_CVTA32P24_H;
31050 if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 &&
31051 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31052 return OPCODE_AE_CVTA32P24_L;
31053 if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 &&
31054 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31055 return OPCODE_AE_MOVAP24S_H;
31056 if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 &&
31057 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31058 return OPCODE_AE_TRUNCA16P24S_L;
31059 if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 &&
31060 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31061 return OPCODE_AE_MOVAP24S_L;
31062 if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 &&
31063 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31064 Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
31065 return OPCODE_AE_NSAQ56S;
31066 if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 &&
31067 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31068 Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0)
31069 return OPCODE_AE_TRUNCA32Q48;
31070 if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 &&
31071 Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31072 Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
31074 if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 &&
31075 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31076 Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
31077 return OPCODE_AE_TRUNCA16P24S_H;
31078 if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 &&
31079 Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31080 Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
31081 return OPCODE_BLTUI;
31082 if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 &&
31083 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31084 return OPCODE_AE_MOVFQ56;
31085 if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 &&
31086 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31087 return OPCODE_AE_SLLAQ56;
31088 if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 &&
31089 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31090 return OPCODE_AE_SLLASQ56S;
31091 if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 &&
31092 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31094 if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 &&
31095 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31096 Field_ftsf357_Slot_ae_slot0_get (insn) == 0)
31097 return OPCODE_AE_SRAAQ56;
31098 if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 &&
31099 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31100 Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
31101 return OPCODE_AE_SRLAQ56;
31102 if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
31103 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31104 Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
31105 return OPCODE_AE_SQ32F_XU;
31106 if (Field_imm8_Slot_ae_slot0_get (insn) == 178 &&
31107 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31109 if (Field_imm8_Slot_ae_slot0_get (insn) == 179 &&
31110 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31111 return OPCODE_ADDX8;
31112 if (Field_imm8_Slot_ae_slot0_get (insn) == 180 &&
31113 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31114 return OPCODE_ADDX2;
31115 if (Field_imm8_Slot_ae_slot0_get (insn) == 181 &&
31116 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31118 if (Field_imm8_Slot_ae_slot0_get (insn) == 182 &&
31119 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31120 return OPCODE_ANDB;
31121 if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
31122 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31123 return OPCODE_ANDBC;
31124 if (Field_imm8_Slot_ae_slot0_get (insn) == 184 &&
31125 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31126 return OPCODE_ADDX4;
31127 if (Field_imm8_Slot_ae_slot0_get (insn) == 185 &&
31128 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31129 return OPCODE_CLAMPS;
31130 if (Field_imm8_Slot_ae_slot0_get (insn) == 186 &&
31131 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31133 if (Field_imm8_Slot_ae_slot0_get (insn) == 187 &&
31134 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31136 if (Field_imm8_Slot_ae_slot0_get (insn) == 188 &&
31137 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31138 return OPCODE_MAXU;
31139 if (Field_imm8_Slot_ae_slot0_get (insn) == 189 &&
31140 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31141 return OPCODE_MINU;
31142 if (Field_imm8_Slot_ae_slot0_get (insn) == 190 &&
31143 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31144 return OPCODE_MOVEQZ;
31145 if (Field_imm8_Slot_ae_slot0_get (insn) == 191 &&
31146 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31147 return OPCODE_MOVF;
31148 if (Field_imm8_Slot_ae_slot0_get (insn) == 194 &&
31149 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31150 return OPCODE_MOVGEZ;
31151 if (Field_imm8_Slot_ae_slot0_get (insn) == 195 &&
31152 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31154 if (Field_imm8_Slot_ae_slot0_get (insn) == 196 &&
31155 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31156 return OPCODE_MOVLTZ;
31157 if (Field_imm8_Slot_ae_slot0_get (insn) == 197 &&
31158 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31159 return OPCODE_ORBC;
31160 if (Field_imm8_Slot_ae_slot0_get (insn) == 198 &&
31161 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31162 return OPCODE_SEXT;
31163 if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
31164 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31166 if (Field_imm8_Slot_ae_slot0_get (insn) == 200 &&
31167 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31168 return OPCODE_MOVNEZ;
31169 if (Field_imm8_Slot_ae_slot0_get (insn) == 201 &&
31170 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31171 return OPCODE_SRLI;
31172 if (Field_imm8_Slot_ae_slot0_get (insn) == 202 &&
31173 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31175 if (Field_imm8_Slot_ae_slot0_get (insn) == 203 &&
31176 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31177 return OPCODE_SUBX4;
31178 if (Field_imm8_Slot_ae_slot0_get (insn) == 204 &&
31179 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31180 return OPCODE_SUBX2;
31181 if (Field_imm8_Slot_ae_slot0_get (insn) == 205 &&
31182 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31183 return OPCODE_SUBX8;
31184 if (Field_imm8_Slot_ae_slot0_get (insn) == 206 &&
31185 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31187 if (Field_imm8_Slot_ae_slot0_get (insn) == 207 &&
31188 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31189 return OPCODE_XORB;
31190 if (Field_imm8_Slot_ae_slot0_get (insn) == 208 &&
31191 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31192 return OPCODE_MOVT;
31193 if (Field_imm8_Slot_ae_slot0_get (insn) == 224 &&
31194 Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31196 if (Field_imm8_Slot_ae_slot0_get (insn) == 244 &&
31197 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31198 Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
31199 return OPCODE_AE_SQ32F_X;
31200 if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
31201 return OPCODE_L32R;
31202 if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
31203 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31205 if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
31206 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31207 return OPCODE_BNONE;
31208 if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
31209 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31210 return OPCODE_L16SI;
31211 if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
31212 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31213 return OPCODE_L8UI;
31214 if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
31215 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31216 return OPCODE_ADDI;
31217 if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
31218 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31219 return OPCODE_L16UI;
31220 if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
31221 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31222 return OPCODE_BALL;
31223 if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
31224 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31225 return OPCODE_S16I;
31226 if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
31227 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31228 return OPCODE_BANY;
31229 if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
31230 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31231 return OPCODE_S32I;
31232 if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
31233 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31235 if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
31236 Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31238 if (Field_r_Slot_ae_slot0_get (insn) == 8 &&
31239 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31240 return OPCODE_ADDMI;
31241 if (Field_r_Slot_ae_slot0_get (insn) == 9 &&
31242 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31244 if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
31245 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31247 if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
31248 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31249 return OPCODE_BGEU;
31250 if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
31251 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31253 if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
31254 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31256 if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
31257 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31258 return OPCODE_BLTU;
31259 if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
31260 Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31261 return OPCODE_BNALL;
31262 if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
31263 Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31264 return OPCODE_BEQI;
31265 if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
31266 Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31267 return OPCODE_BGEI;
31268 if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
31269 Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31270 return OPCODE_BGEUI;
31271 if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
31272 Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31273 return OPCODE_BNEI;
31274 if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
31275 Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31276 return OPCODE_BLTI;
31277 if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
31278 Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31279 Field_r_Slot_ae_slot0_get (insn) == 0)
31281 return XTENSA_UNDEFINED;
31285 Slot_ae_slot1_decode (const xtensa_insnbuf insn)
31287 if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 &&
31288 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31289 Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31290 return OPCODE_AE_NEGSP24S;
31291 if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31292 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31293 Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
31294 return OPCODE_AE_ABSSP24S;
31295 if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
31296 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31297 Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
31298 return OPCODE_AE_NEGP24;
31299 if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
31300 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31301 return OPCODE_AE_MAXBQ56S;
31302 if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31303 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31304 return OPCODE_AE_MINBQ56S;
31305 if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
31306 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31307 Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
31308 return OPCODE_AE_EQQ56;
31309 if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
31310 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31311 return OPCODE_AE_ADDSQ56S;
31312 if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
31313 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31314 return OPCODE_AE_ANDQ56;
31315 if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
31316 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31317 return OPCODE_AE_MAXQ56S;
31318 if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
31319 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31320 return OPCODE_AE_ORQ56;
31321 if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
31322 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31323 return OPCODE_AE_MINQ56S;
31324 if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
31325 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31326 return OPCODE_AE_SUBQ56;
31327 if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
31328 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31329 return OPCODE_AE_SUBSQ56S;
31330 if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
31331 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31332 return OPCODE_AE_XORQ56;
31333 if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
31334 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31335 return OPCODE_AE_NANDQ56;
31336 if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
31337 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31338 return OPCODE_AE_ABSQ56;
31339 if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
31340 Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
31341 return OPCODE_AE_NEGSQ56S;
31342 if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
31343 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31344 Field_ftsf338_Slot_ae_slot1_get (insn) == 0)
31345 return OPCODE_AE_SATQ48S;
31346 if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 &&
31347 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31348 Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
31349 return OPCODE_AE_LTQ56S;
31350 if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31351 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31352 Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
31353 return OPCODE_AE_ABSSQ56S;
31354 if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
31355 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31356 Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0)
31357 return OPCODE_AE_NEGQ56;
31358 if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31359 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31360 Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
31361 return OPCODE_AE_LEQ56S;
31362 if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31363 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31364 Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
31365 return OPCODE_AE_TRUNCP24Q48X2;
31366 if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31367 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
31368 Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
31369 return OPCODE_AE_ADDQ56;
31370 if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
31371 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31372 return OPCODE_AE_MULAAFP24S_HH_LL;
31373 if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31374 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31375 return OPCODE_AE_MULAAFP24S_HL_LH;
31376 if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
31377 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31378 return OPCODE_AE_MULAAP24S_HH_LL;
31379 if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 &&
31380 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31381 Field_ftsf12_Slot_ae_slot1_get (insn) == 0)
31382 return OPCODE_AE_SLLISP24S;
31383 if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
31384 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31385 return OPCODE_AE_MULAFS32P16S_HL;
31386 if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
31387 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31388 return OPCODE_AE_MULAAP24S_HL_LH;
31389 if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
31390 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31391 return OPCODE_AE_MULAFS32P16S_LH;
31392 if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
31393 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31394 return OPCODE_AE_MULAFS32P16S_LL;
31395 if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
31396 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31397 return OPCODE_AE_MULAFS56P24S_HH;
31398 if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31399 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31400 return OPCODE_AE_MULAFP24S_HH;
31401 if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31402 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31403 return OPCODE_AE_MULAFS56P24S_HL;
31404 if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31405 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31406 return OPCODE_AE_MULAFS56P24S_LH;
31407 if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
31408 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31409 return OPCODE_AE_MULAP24S_HH;
31410 if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
31411 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31412 return OPCODE_AE_MULAFS56P24S_LL;
31413 if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
31414 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31415 return OPCODE_AE_MULAP24S_HL;
31416 if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
31417 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31418 return OPCODE_AE_MULAP24S_LH;
31419 if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
31420 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31421 return OPCODE_AE_MULAP24S_LL;
31422 if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
31423 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31424 return OPCODE_AE_MULAFP24S_HL;
31425 if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
31426 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31427 return OPCODE_AE_MULAS56P24S_HH;
31428 if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
31429 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31430 return OPCODE_AE_MULAS56P24S_HL;
31431 if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
31432 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31433 return OPCODE_AE_MULASFP24S_HH_LL;
31434 if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
31435 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31436 return OPCODE_AE_MULAS56P24S_LH;
31437 if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
31438 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31439 return OPCODE_AE_MULASFP24S_HL_LH;
31440 if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
31441 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31442 return OPCODE_AE_MULASP24S_HH_LL;
31443 if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
31444 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31445 return OPCODE_AE_MULASP24S_HL_LH;
31446 if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
31447 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31448 return OPCODE_AE_MULAS56P24S_LL;
31449 if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31450 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31451 return OPCODE_AE_MULFP24S_HH;
31452 if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
31453 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31454 return OPCODE_AE_MULFP24S_HL;
31455 if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
31456 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31457 return OPCODE_AE_MULFP24S_LL;
31458 if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
31459 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31460 return OPCODE_AE_MULFP24S_LH;
31461 if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31462 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31463 return OPCODE_AE_MULFS32P16S_HH;
31464 if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
31465 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31466 return OPCODE_AE_MULFS32P16S_HL;
31467 if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
31468 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31469 return OPCODE_AE_MULFS32P16S_LH;
31470 if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
31471 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31472 return OPCODE_AE_MULAFP24S_LH;
31473 if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
31474 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31475 return OPCODE_AE_MULFS32P16S_LL;
31476 if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
31477 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31478 return OPCODE_AE_MULP24S_HH;
31479 if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
31480 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31481 return OPCODE_AE_MULSAFP24S_HH_LL;
31482 if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
31483 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31484 return OPCODE_AE_MULP24S_HL;
31485 if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
31486 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31487 return OPCODE_AE_MULSAFP24S_HL_LH;
31488 if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
31489 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31490 return OPCODE_AE_MULSAP24S_HH_LL;
31491 if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
31492 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31493 return OPCODE_AE_MULSAP24S_HL_LH;
31494 if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
31495 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31496 return OPCODE_AE_MULP24S_LH;
31497 if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
31498 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31499 return OPCODE_AE_MULSFP24S_HH;
31500 if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
31501 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31502 return OPCODE_AE_MULSFP24S_HL;
31503 if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
31504 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31505 return OPCODE_AE_MULSFP24S_LL;
31506 if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
31507 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31508 return OPCODE_AE_MULSFP24S_LH;
31509 if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
31510 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31511 return OPCODE_AE_MULSFS32P16S_HH;
31512 if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
31513 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31514 return OPCODE_AE_MULSFS32P16S_HL;
31515 if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
31516 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31517 return OPCODE_AE_MULSFS32P16S_LH;
31518 if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
31519 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31520 return OPCODE_AE_MULP24S_LL;
31521 if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
31522 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31523 return OPCODE_AE_MULSFS32P16S_LL;
31524 if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
31525 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31526 return OPCODE_AE_MULSFS56P24S_HH;
31527 if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
31528 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31529 return OPCODE_AE_MULSFS56P24S_LL;
31530 if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
31531 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31532 return OPCODE_AE_MULSFS56P24S_HL;
31533 if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
31534 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31535 return OPCODE_AE_MULSP24S_HH;
31536 if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
31537 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31538 return OPCODE_AE_MULSP24S_HL;
31539 if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
31540 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31541 return OPCODE_AE_MULSP24S_LH;
31542 if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
31543 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31544 return OPCODE_AE_MULSFS56P24S_LH;
31545 if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
31546 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31547 return OPCODE_AE_MULSP24S_LL;
31548 if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
31549 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31550 return OPCODE_AE_MULSS56P24S_HH;
31551 if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
31552 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31553 return OPCODE_AE_MULSS56P24S_LH;
31554 if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
31555 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31556 return OPCODE_AE_MULSS56P24S_HL;
31557 if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
31558 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31559 return OPCODE_AE_MULSS56P24S_LL;
31560 if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
31561 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31562 return OPCODE_AE_MULSSFP24S_HH_LL;
31563 if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
31564 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31565 return OPCODE_AE_MULSSFP24S_HL_LH;
31566 if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
31567 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31568 return OPCODE_AE_MULAFP24S_LL;
31569 if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
31570 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31571 return OPCODE_AE_MULSSP24S_HH_LL;
31572 if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
31573 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31574 return OPCODE_AE_MULSSP24S_HL_LH;
31575 if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
31576 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31577 return OPCODE_AE_MULZASFP24S_HH_LL;
31578 if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
31579 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31580 return OPCODE_AE_MULZAAFP24S_HH_LL;
31581 if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
31582 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31583 return OPCODE_AE_MULZASFP24S_HL_LH;
31584 if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
31585 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31586 return OPCODE_AE_MULZASP24S_HH_LL;
31587 if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
31588 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31589 return OPCODE_AE_MULZASP24S_HL_LH;
31590 if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
31591 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31592 return OPCODE_AE_MULZAAFP24S_HL_LH;
31593 if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
31594 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31595 return OPCODE_AE_MULZSAFP24S_HH_LL;
31596 if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
31597 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31598 return OPCODE_AE_MULZSAFP24S_HL_LH;
31599 if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
31600 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31601 return OPCODE_AE_MULZSAP24S_HL_LH;
31602 if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
31603 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31604 return OPCODE_AE_MULZSAP24S_HH_LL;
31605 if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
31606 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31607 return OPCODE_AE_MULZSSFP24S_HH_LL;
31608 if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
31609 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31610 return OPCODE_AE_MULZSSFP24S_HL_LH;
31611 if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
31612 Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
31613 return OPCODE_AE_MULZSSP24S_HH_LL;
31614 if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31615 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31616 Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
31617 return OPCODE_AE_MULZAAP24S_HH_LL;
31618 if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
31619 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31620 Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
31621 return OPCODE_AE_MULZSSP24S_HL_LH;
31622 if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
31623 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31624 Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
31625 return OPCODE_AE_MULZAAP24S_HL_LH;
31626 if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31627 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
31628 Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0)
31629 return OPCODE_AE_MULAFS32P16S_HH;
31630 if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
31631 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31632 return OPCODE_AE_MAXBP24S;
31633 if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
31634 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31635 return OPCODE_AE_MINBP24S;
31636 if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31637 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31638 return OPCODE_AE_MOVFP48;
31639 if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31640 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31641 return OPCODE_AE_MOVTP48;
31642 if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
31643 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31644 return OPCODE_AE_ADDP24;
31645 if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
31646 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31647 return OPCODE_AE_ANDP48;
31648 if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
31649 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31650 return OPCODE_AE_MAXP24S;
31651 if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
31652 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31653 return OPCODE_AE_MINP24S;
31654 if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
31655 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31656 return OPCODE_AE_ADDSP24S;
31657 if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31658 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31659 return OPCODE_AE_NANDP48;
31660 if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
31661 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31662 return OPCODE_AE_ORP48;
31663 if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
31664 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31665 return OPCODE_AE_SELP24_HL;
31666 if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
31667 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31668 return OPCODE_AE_SELP24_HH;
31669 if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
31670 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31671 return OPCODE_AE_SELP24_LH;
31672 if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
31673 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31674 return OPCODE_AE_SELP24_LL;
31675 if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
31676 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31677 return OPCODE_AE_SUBP24;
31678 if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31679 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31680 return OPCODE_AE_SLLIP24;
31681 if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31682 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31683 return OPCODE_AE_SRAIP24;
31684 if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31685 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31686 return OPCODE_AE_SRLIP24;
31687 if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
31688 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31689 return OPCODE_AE_MULAFQ32SP16S_L;
31690 if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 &&
31691 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31692 return OPCODE_AE_MULAFQ32SP16U_H;
31693 if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 &&
31694 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31695 return OPCODE_AE_MULAFQ32SP16U_L;
31696 if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 &&
31697 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31698 return OPCODE_AE_MULAQ32SP16U_H;
31699 if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 &&
31700 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31701 return OPCODE_AE_MULAQ32SP16S_H;
31702 if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 &&
31703 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31704 return OPCODE_AE_MULAQ32SP16U_L;
31705 if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 &&
31706 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31707 return OPCODE_AE_MULFQ32SP16S_H;
31708 if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 &&
31709 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31710 return OPCODE_AE_MULFQ32SP16S_L;
31711 if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 &&
31712 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31713 return OPCODE_AE_MULAQ32SP16S_L;
31714 if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
31715 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31716 return OPCODE_AE_MULFQ32SP16U_H;
31717 if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 &&
31718 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31719 return OPCODE_AE_MULFQ32SP16U_L;
31720 if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 &&
31721 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31722 return OPCODE_AE_MULQ32SP16S_L;
31723 if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 &&
31724 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31725 return OPCODE_AE_MULQ32SP16S_H;
31726 if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 &&
31727 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31728 return OPCODE_AE_MULQ32SP16U_H;
31729 if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 &&
31730 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31731 return OPCODE_AE_MULQ32SP16U_L;
31732 if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 &&
31733 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31734 return OPCODE_AE_MULSFQ32SP16S_H;
31735 if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 &&
31736 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31737 return OPCODE_AE_MULAFQ32SP16S_H;
31738 if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 &&
31739 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31740 return OPCODE_AE_MULSFQ32SP16S_L;
31741 if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 &&
31742 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31743 return OPCODE_AE_MULSFQ32SP16U_H;
31744 if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
31745 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31746 return OPCODE_AE_MULSQ32SP16U_L;
31747 if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 &&
31748 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31749 return OPCODE_AE_MULSFQ32SP16U_L;
31750 if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 &&
31751 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31752 return OPCODE_AE_CVTQ48P24S_H;
31753 if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 &&
31754 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31755 Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31756 return OPCODE_AE_ZEROQ56;
31757 if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 &&
31758 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31759 Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0)
31761 if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 &&
31762 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31763 Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
31764 return OPCODE_AE_CVTQ48P24S_L;
31765 if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 &&
31766 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31767 return OPCODE_AE_MOVQ56;
31768 if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 &&
31769 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31770 return OPCODE_AE_ROUNDSQ32ASYM;
31771 if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 &&
31772 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31773 Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
31774 return OPCODE_AE_ROUNDSQ32SYM;
31775 if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 &&
31776 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31777 Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
31778 return OPCODE_AE_TRUNCQ32;
31779 if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31780 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31781 Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
31782 return OPCODE_AE_MULSQ32SP16S_H;
31783 if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
31784 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31785 Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
31786 return OPCODE_AE_MULSQ32SP16S_L;
31787 if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 &&
31788 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31789 return OPCODE_AE_MOVP48;
31790 if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 &&
31791 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31792 return OPCODE_AE_ROUNDSP16ASYM;
31793 if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 &&
31794 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31795 return OPCODE_AE_ROUNDSP16SYM;
31796 if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
31797 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31798 return OPCODE_AE_SRASP24;
31799 if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 &&
31800 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31801 return OPCODE_AE_SLLSP24;
31802 if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 &&
31803 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31804 return OPCODE_AE_SRLSP24;
31805 if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 &&
31806 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31807 return OPCODE_AE_TRUNCP16;
31808 if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 &&
31809 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31810 Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31811 return OPCODE_AE_ZEROP48;
31812 if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 &&
31813 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31814 Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
31815 return OPCODE_AE_SLLSSP24S;
31816 if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 &&
31817 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31818 return OPCODE_AE_ROUNDSP16Q48ASYM;
31819 if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 &&
31820 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31821 return OPCODE_AE_ROUNDSP16Q48SYM;
31822 if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 &&
31823 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31824 Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
31825 return OPCODE_AE_ROUNDSP24Q48ASYM;
31826 if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 &&
31827 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31828 Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
31829 return OPCODE_AE_ROUNDSP24Q48SYM;
31830 if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
31831 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31832 Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
31833 return OPCODE_AE_MULSQ32SP16U_H;
31834 if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 &&
31835 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31836 return OPCODE_AE_EQP24;
31837 if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
31838 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31839 return OPCODE_AE_LEP24S;
31840 if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
31841 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31842 Field_ftsf208_Slot_ae_slot1_get (insn) == 0)
31843 return OPCODE_AE_LTP24S;
31844 if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
31845 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31846 Field_ftsf347_Slot_ae_slot1_get (insn) == 0)
31847 return OPCODE_AE_MOVFP24X2;
31848 if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
31849 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31850 Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
31851 return OPCODE_AE_MOVTP24X2;
31852 if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 &&
31853 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31854 return OPCODE_AE_SUBSP24S;
31855 if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 &&
31856 Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31857 return OPCODE_AE_XORP48;
31858 if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 &&
31859 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
31860 Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
31861 return OPCODE_AE_ABSP24;
31862 if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31863 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31864 return OPCODE_AE_MULZAAFQ32SP16S_HH;
31865 if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31866 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31867 return OPCODE_AE_MULZASFQ32SP16U_LH;
31868 if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31869 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31870 return OPCODE_AE_MULZSAQ32SP16S_LL;
31871 if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31872 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31873 return OPCODE_AE_MULZAAFQ32SP16S_LH;
31874 if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31875 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31876 return OPCODE_AE_MULZASFQ32SP16U_LL;
31877 if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31878 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31879 return OPCODE_AE_MULZSAQ32SP16U_HH;
31880 if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31881 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31882 return OPCODE_AE_MULZAAFQ32SP16S_LL;
31883 if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31884 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31885 return OPCODE_AE_MULZASQ32SP16S_HH;
31886 if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31887 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31888 return OPCODE_AE_MULZSAQ32SP16U_LH;
31889 if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31890 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31891 return OPCODE_AE_MULZAAFQ32SP16U_LL;
31892 if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31893 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31894 return OPCODE_AE_MULZASQ32SP16U_HH;
31895 if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31896 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31897 return OPCODE_AE_MULZSSFQ32SP16S_LH;
31898 if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31899 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31900 return OPCODE_AE_MULZAAFQ32SP16U_HH;
31901 if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31902 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31903 return OPCODE_AE_MULZASQ32SP16S_LH;
31904 if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31905 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31906 return OPCODE_AE_MULZSAQ32SP16U_LL;
31907 if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31908 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31909 return OPCODE_AE_MULZAAQ32SP16S_HH;
31910 if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31911 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31912 return OPCODE_AE_MULZASQ32SP16U_LH;
31913 if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31914 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31915 return OPCODE_AE_MULZSSFQ32SP16S_LL;
31916 if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31917 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31918 return OPCODE_AE_MULZAAQ32SP16S_LH;
31919 if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31920 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31921 return OPCODE_AE_MULZASQ32SP16U_LL;
31922 if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31923 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31924 return OPCODE_AE_MULZSSFQ32SP16U_HH;
31925 if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31926 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31927 return OPCODE_AE_MULZAAQ32SP16S_LL;
31928 if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31929 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31930 return OPCODE_AE_MULZSAFQ32SP16S_HH;
31931 if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31932 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31933 return OPCODE_AE_MULZSSFQ32SP16U_LH;
31934 if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31935 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31936 return OPCODE_AE_MULZAAFQ32SP16U_LH;
31937 if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31938 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31939 return OPCODE_AE_MULZASQ32SP16S_LL;
31940 if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31941 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31942 return OPCODE_AE_MULZSSFQ32SP16S_HH;
31943 if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31944 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31945 return OPCODE_AE_MULZAAQ32SP16U_HH;
31946 if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31947 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31948 return OPCODE_AE_MULZSAFQ32SP16S_LH;
31949 if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31950 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31951 return OPCODE_AE_MULZSSFQ32SP16U_LL;
31952 if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31953 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31954 return OPCODE_AE_MULZAAQ32SP16U_LH;
31955 if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31956 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31957 return OPCODE_AE_MULZSAFQ32SP16S_LL;
31958 if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31959 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31960 return OPCODE_AE_MULZSSQ32SP16S_HH;
31961 if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31962 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31963 return OPCODE_AE_MULZASFQ32SP16S_HH;
31964 if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31965 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31966 return OPCODE_AE_MULZSAFQ32SP16U_LH;
31967 if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31968 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31969 return OPCODE_AE_MULZSSQ32SP16S_LL;
31970 if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31971 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31972 return OPCODE_AE_MULZAAQ32SP16U_LL;
31973 if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31974 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31975 return OPCODE_AE_MULZSAFQ32SP16U_HH;
31976 if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31977 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31978 return OPCODE_AE_MULZSSQ32SP16S_LH;
31979 if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31980 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31981 return OPCODE_AE_MULZASFQ32SP16S_LH;
31982 if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31983 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31984 return OPCODE_AE_MULZSAFQ32SP16U_LL;
31985 if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31986 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31987 return OPCODE_AE_MULZSSQ32SP16U_HH;
31988 if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31989 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31990 return OPCODE_AE_MULZASFQ32SP16S_LL;
31991 if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31992 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31993 return OPCODE_AE_MULZSAQ32SP16S_HH;
31994 if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31995 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31996 return OPCODE_AE_MULZSSQ32SP16U_LH;
31997 if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
31998 Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31999 return OPCODE_AE_MULZASFQ32SP16U_HH;
32000 if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
32001 Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32002 return OPCODE_AE_MULZSAQ32SP16S_LH;
32003 if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
32004 Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32005 return OPCODE_AE_MULZSSQ32SP16U_LL;
32006 return XTENSA_UNDEFINED;
32010 /* Instruction slots. */
32013 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
32014 xtensa_insnbuf slotbuf)
32017 slotbuf[0] = (insn[0] & 0xffffff);
32021 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
32022 const xtensa_insnbuf slotbuf)
32024 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
32028 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
32029 xtensa_insnbuf slotbuf)
32032 slotbuf[0] = (insn[0] & 0xffff);
32036 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
32037 const xtensa_insnbuf slotbuf)
32039 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
32043 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
32044 xtensa_insnbuf slotbuf)
32047 slotbuf[0] = (insn[0] & 0xffff);
32051 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
32052 const xtensa_insnbuf slotbuf)
32054 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
32058 Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn,
32059 xtensa_insnbuf slotbuf)
32062 slotbuf[0] = ((insn[0] & 0x80000000) >> 31);
32063 slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1);
32067 Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn,
32068 const xtensa_insnbuf slotbuf)
32070 insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31);
32071 insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1);
32075 Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn,
32076 xtensa_insnbuf slotbuf)
32079 slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4);
32083 Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn,
32084 const xtensa_insnbuf slotbuf)
32086 insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4);
32089 static xtensa_get_field_fn
32090 Slot_inst_get_field_fns[] = {
32091 Field_t_Slot_inst_get,
32092 Field_bbi4_Slot_inst_get,
32093 Field_bbi_Slot_inst_get,
32094 Field_imm12_Slot_inst_get,
32095 Field_imm8_Slot_inst_get,
32096 Field_s_Slot_inst_get,
32097 Field_imm12b_Slot_inst_get,
32098 Field_imm16_Slot_inst_get,
32099 Field_m_Slot_inst_get,
32100 Field_n_Slot_inst_get,
32101 Field_offset_Slot_inst_get,
32102 Field_op0_Slot_inst_get,
32103 Field_op1_Slot_inst_get,
32104 Field_op2_Slot_inst_get,
32105 Field_r_Slot_inst_get,
32106 Field_sa4_Slot_inst_get,
32107 Field_sae4_Slot_inst_get,
32108 Field_sae_Slot_inst_get,
32109 Field_sal_Slot_inst_get,
32110 Field_sargt_Slot_inst_get,
32111 Field_sas4_Slot_inst_get,
32112 Field_sas_Slot_inst_get,
32113 Field_sr_Slot_inst_get,
32114 Field_st_Slot_inst_get,
32115 Field_thi3_Slot_inst_get,
32116 Field_imm4_Slot_inst_get,
32117 Field_mn_Slot_inst_get,
32126 Field_t2_Slot_inst_get,
32127 Field_s2_Slot_inst_get,
32128 Field_r2_Slot_inst_get,
32129 Field_t4_Slot_inst_get,
32130 Field_s4_Slot_inst_get,
32131 Field_r4_Slot_inst_get,
32132 Field_t8_Slot_inst_get,
32133 Field_s8_Slot_inst_get,
32134 Field_r8_Slot_inst_get,
32135 Field_xt_wbr15_imm_Slot_inst_get,
32136 Field_xt_wbr18_imm_Slot_inst_get,
32137 Field_ae_r3_Slot_inst_get,
32138 Field_ae_s_non_samt_Slot_inst_get,
32139 Field_ae_s3_Slot_inst_get,
32140 Field_ae_r32_Slot_inst_get,
32141 Field_ae_samt_s_t_Slot_inst_get,
32142 Field_ae_r20_Slot_inst_get,
32143 Field_ae_r10_Slot_inst_get,
32144 Field_ae_s20_Slot_inst_get,
32145 Field_ae_fld_ohba_Slot_inst_get,
32146 Field_ae_fld_ohba2_Slot_inst_get,
32148 Field_ftsf12_Slot_inst_get,
32149 Field_ftsf13_Slot_inst_get,
32472 Implicit_Field_ar0_get,
32473 Implicit_Field_ar4_get,
32474 Implicit_Field_ar8_get,
32475 Implicit_Field_ar12_get,
32476 Implicit_Field_bt16_get,
32477 Implicit_Field_bs16_get,
32478 Implicit_Field_br16_get,
32479 Implicit_Field_brall_get
32482 static xtensa_set_field_fn
32483 Slot_inst_set_field_fns[] = {
32484 Field_t_Slot_inst_set,
32485 Field_bbi4_Slot_inst_set,
32486 Field_bbi_Slot_inst_set,
32487 Field_imm12_Slot_inst_set,
32488 Field_imm8_Slot_inst_set,
32489 Field_s_Slot_inst_set,
32490 Field_imm12b_Slot_inst_set,
32491 Field_imm16_Slot_inst_set,
32492 Field_m_Slot_inst_set,
32493 Field_n_Slot_inst_set,
32494 Field_offset_Slot_inst_set,
32495 Field_op0_Slot_inst_set,
32496 Field_op1_Slot_inst_set,
32497 Field_op2_Slot_inst_set,
32498 Field_r_Slot_inst_set,
32499 Field_sa4_Slot_inst_set,
32500 Field_sae4_Slot_inst_set,
32501 Field_sae_Slot_inst_set,
32502 Field_sal_Slot_inst_set,
32503 Field_sargt_Slot_inst_set,
32504 Field_sas4_Slot_inst_set,
32505 Field_sas_Slot_inst_set,
32506 Field_sr_Slot_inst_set,
32507 Field_st_Slot_inst_set,
32508 Field_thi3_Slot_inst_set,
32509 Field_imm4_Slot_inst_set,
32510 Field_mn_Slot_inst_set,
32519 Field_t2_Slot_inst_set,
32520 Field_s2_Slot_inst_set,
32521 Field_r2_Slot_inst_set,
32522 Field_t4_Slot_inst_set,
32523 Field_s4_Slot_inst_set,
32524 Field_r4_Slot_inst_set,
32525 Field_t8_Slot_inst_set,
32526 Field_s8_Slot_inst_set,
32527 Field_r8_Slot_inst_set,
32528 Field_xt_wbr15_imm_Slot_inst_set,
32529 Field_xt_wbr18_imm_Slot_inst_set,
32530 Field_ae_r3_Slot_inst_set,
32531 Field_ae_s_non_samt_Slot_inst_set,
32532 Field_ae_s3_Slot_inst_set,
32533 Field_ae_r32_Slot_inst_set,
32534 Field_ae_samt_s_t_Slot_inst_set,
32535 Field_ae_r20_Slot_inst_set,
32536 Field_ae_r10_Slot_inst_set,
32537 Field_ae_s20_Slot_inst_set,
32538 Field_ae_fld_ohba_Slot_inst_set,
32539 Field_ae_fld_ohba2_Slot_inst_set,
32541 Field_ftsf12_Slot_inst_set,
32542 Field_ftsf13_Slot_inst_set,
32865 Implicit_Field_set,
32866 Implicit_Field_set,
32867 Implicit_Field_set,
32868 Implicit_Field_set,
32869 Implicit_Field_set,
32870 Implicit_Field_set,
32871 Implicit_Field_set,
32875 static xtensa_get_field_fn
32876 Slot_inst16a_get_field_fns[] = {
32877 Field_t_Slot_inst16a_get,
32882 Field_s_Slot_inst16a_get,
32888 Field_op0_Slot_inst16a_get,
32891 Field_r_Slot_inst16a_get,
32899 Field_sr_Slot_inst16a_get,
32900 Field_st_Slot_inst16a_get,
32902 Field_imm4_Slot_inst16a_get,
32904 Field_i_Slot_inst16a_get,
32905 Field_imm6lo_Slot_inst16a_get,
32906 Field_imm6hi_Slot_inst16a_get,
32907 Field_imm7lo_Slot_inst16a_get,
32908 Field_imm7hi_Slot_inst16a_get,
32909 Field_z_Slot_inst16a_get,
32910 Field_imm6_Slot_inst16a_get,
32911 Field_imm7_Slot_inst16a_get,
32912 Field_t2_Slot_inst16a_get,
32913 Field_s2_Slot_inst16a_get,
32914 Field_r2_Slot_inst16a_get,
32915 Field_t4_Slot_inst16a_get,
32916 Field_s4_Slot_inst16a_get,
32917 Field_r4_Slot_inst16a_get,
32918 Field_t8_Slot_inst16a_get,
32919 Field_s8_Slot_inst16a_get,
32920 Field_r8_Slot_inst16a_get,
33258 Implicit_Field_ar0_get,
33259 Implicit_Field_ar4_get,
33260 Implicit_Field_ar8_get,
33261 Implicit_Field_ar12_get,
33262 Implicit_Field_bt16_get,
33263 Implicit_Field_bs16_get,
33264 Implicit_Field_br16_get,
33265 Implicit_Field_brall_get
33268 static xtensa_set_field_fn
33269 Slot_inst16a_set_field_fns[] = {
33270 Field_t_Slot_inst16a_set,
33275 Field_s_Slot_inst16a_set,
33281 Field_op0_Slot_inst16a_set,
33284 Field_r_Slot_inst16a_set,
33292 Field_sr_Slot_inst16a_set,
33293 Field_st_Slot_inst16a_set,
33295 Field_imm4_Slot_inst16a_set,
33297 Field_i_Slot_inst16a_set,
33298 Field_imm6lo_Slot_inst16a_set,
33299 Field_imm6hi_Slot_inst16a_set,
33300 Field_imm7lo_Slot_inst16a_set,
33301 Field_imm7hi_Slot_inst16a_set,
33302 Field_z_Slot_inst16a_set,
33303 Field_imm6_Slot_inst16a_set,
33304 Field_imm7_Slot_inst16a_set,
33305 Field_t2_Slot_inst16a_set,
33306 Field_s2_Slot_inst16a_set,
33307 Field_r2_Slot_inst16a_set,
33308 Field_t4_Slot_inst16a_set,
33309 Field_s4_Slot_inst16a_set,
33310 Field_r4_Slot_inst16a_set,
33311 Field_t8_Slot_inst16a_set,
33312 Field_s8_Slot_inst16a_set,
33313 Field_r8_Slot_inst16a_set,
33651 Implicit_Field_set,
33652 Implicit_Field_set,
33653 Implicit_Field_set,
33654 Implicit_Field_set,
33655 Implicit_Field_set,
33656 Implicit_Field_set,
33657 Implicit_Field_set,
33661 static xtensa_get_field_fn
33662 Slot_inst16b_get_field_fns[] = {
33663 Field_t_Slot_inst16b_get,
33668 Field_s_Slot_inst16b_get,
33674 Field_op0_Slot_inst16b_get,
33677 Field_r_Slot_inst16b_get,
33685 Field_sr_Slot_inst16b_get,
33686 Field_st_Slot_inst16b_get,
33688 Field_imm4_Slot_inst16b_get,
33690 Field_i_Slot_inst16b_get,
33691 Field_imm6lo_Slot_inst16b_get,
33692 Field_imm6hi_Slot_inst16b_get,
33693 Field_imm7lo_Slot_inst16b_get,
33694 Field_imm7hi_Slot_inst16b_get,
33695 Field_z_Slot_inst16b_get,
33696 Field_imm6_Slot_inst16b_get,
33697 Field_imm7_Slot_inst16b_get,
33698 Field_t2_Slot_inst16b_get,
33699 Field_s2_Slot_inst16b_get,
33700 Field_r2_Slot_inst16b_get,
33701 Field_t4_Slot_inst16b_get,
33702 Field_s4_Slot_inst16b_get,
33703 Field_r4_Slot_inst16b_get,
33704 Field_t8_Slot_inst16b_get,
33705 Field_s8_Slot_inst16b_get,
33706 Field_r8_Slot_inst16b_get,
34044 Implicit_Field_ar0_get,
34045 Implicit_Field_ar4_get,
34046 Implicit_Field_ar8_get,
34047 Implicit_Field_ar12_get,
34048 Implicit_Field_bt16_get,
34049 Implicit_Field_bs16_get,
34050 Implicit_Field_br16_get,
34051 Implicit_Field_brall_get
34054 static xtensa_set_field_fn
34055 Slot_inst16b_set_field_fns[] = {
34056 Field_t_Slot_inst16b_set,
34061 Field_s_Slot_inst16b_set,
34067 Field_op0_Slot_inst16b_set,
34070 Field_r_Slot_inst16b_set,
34078 Field_sr_Slot_inst16b_set,
34079 Field_st_Slot_inst16b_set,
34081 Field_imm4_Slot_inst16b_set,
34083 Field_i_Slot_inst16b_set,
34084 Field_imm6lo_Slot_inst16b_set,
34085 Field_imm6hi_Slot_inst16b_set,
34086 Field_imm7lo_Slot_inst16b_set,
34087 Field_imm7hi_Slot_inst16b_set,
34088 Field_z_Slot_inst16b_set,
34089 Field_imm6_Slot_inst16b_set,
34090 Field_imm7_Slot_inst16b_set,
34091 Field_t2_Slot_inst16b_set,
34092 Field_s2_Slot_inst16b_set,
34093 Field_r2_Slot_inst16b_set,
34094 Field_t4_Slot_inst16b_set,
34095 Field_s4_Slot_inst16b_set,
34096 Field_r4_Slot_inst16b_set,
34097 Field_t8_Slot_inst16b_set,
34098 Field_s8_Slot_inst16b_set,
34099 Field_r8_Slot_inst16b_set,
34437 Implicit_Field_set,
34438 Implicit_Field_set,
34439 Implicit_Field_set,
34440 Implicit_Field_set,
34441 Implicit_Field_set,
34442 Implicit_Field_set,
34443 Implicit_Field_set,
34447 static xtensa_get_field_fn
34448 Slot_ae_slot1_get_field_fns[] = {
34449 Field_t_Slot_ae_slot1_get,
34484 Field_t2_Slot_ae_slot1_get,
34498 Field_ae_r32_Slot_ae_slot1_get,
34500 Field_ae_r20_Slot_ae_slot1_get,
34501 Field_ae_r10_Slot_ae_slot1_get,
34502 Field_ae_s20_Slot_ae_slot1_get,
34505 Field_op0_s3_Slot_ae_slot1_get,
34506 Field_ftsf12_Slot_ae_slot1_get,
34507 Field_ftsf13_Slot_ae_slot1_get,
34508 Field_ftsf14_Slot_ae_slot1_get,
34509 Field_ftsf21ae_slot1_Slot_ae_slot1_get,
34510 Field_ftsf22ae_slot1_Slot_ae_slot1_get,
34511 Field_ftsf23ae_slot1_Slot_ae_slot1_get,
34512 Field_ftsf24ae_slot1_Slot_ae_slot1_get,
34513 Field_ftsf25ae_slot1_Slot_ae_slot1_get,
34514 Field_ftsf26ae_slot1_Slot_ae_slot1_get,
34515 Field_ftsf27ae_slot1_Slot_ae_slot1_get,
34516 Field_ftsf28ae_slot1_Slot_ae_slot1_get,
34517 Field_ftsf29ae_slot1_Slot_ae_slot1_get,
34518 Field_ftsf30ae_slot1_Slot_ae_slot1_get,
34519 Field_ftsf31ae_slot1_Slot_ae_slot1_get,
34520 Field_ftsf32ae_slot1_Slot_ae_slot1_get,
34521 Field_ftsf33ae_slot1_Slot_ae_slot1_get,
34522 Field_ftsf34ae_slot1_Slot_ae_slot1_get,
34523 Field_ftsf35ae_slot1_Slot_ae_slot1_get,
34524 Field_ftsf36ae_slot1_Slot_ae_slot1_get,
34525 Field_ftsf37ae_slot1_Slot_ae_slot1_get,
34526 Field_ftsf38ae_slot1_Slot_ae_slot1_get,
34527 Field_ftsf39ae_slot1_Slot_ae_slot1_get,
34528 Field_ftsf40ae_slot1_Slot_ae_slot1_get,
34529 Field_ftsf41ae_slot1_Slot_ae_slot1_get,
34530 Field_ftsf42ae_slot1_Slot_ae_slot1_get,
34531 Field_ftsf43ae_slot1_Slot_ae_slot1_get,
34532 Field_ftsf44ae_slot1_Slot_ae_slot1_get,
34533 Field_ftsf45ae_slot1_Slot_ae_slot1_get,
34534 Field_ftsf46ae_slot1_Slot_ae_slot1_get,
34535 Field_ftsf47ae_slot1_Slot_ae_slot1_get,
34536 Field_ftsf48ae_slot1_Slot_ae_slot1_get,
34537 Field_ftsf49ae_slot1_Slot_ae_slot1_get,
34538 Field_ftsf50ae_slot1_Slot_ae_slot1_get,
34539 Field_ftsf51ae_slot1_Slot_ae_slot1_get,
34540 Field_ftsf52ae_slot1_Slot_ae_slot1_get,
34541 Field_ftsf53ae_slot1_Slot_ae_slot1_get,
34542 Field_ftsf54ae_slot1_Slot_ae_slot1_get,
34543 Field_ftsf55ae_slot1_Slot_ae_slot1_get,
34544 Field_ftsf56ae_slot1_Slot_ae_slot1_get,
34545 Field_ftsf57ae_slot1_Slot_ae_slot1_get,
34546 Field_ftsf58ae_slot1_Slot_ae_slot1_get,
34547 Field_ftsf59ae_slot1_Slot_ae_slot1_get,
34548 Field_ftsf60ae_slot1_Slot_ae_slot1_get,
34549 Field_ftsf61ae_slot1_Slot_ae_slot1_get,
34550 Field_ftsf63ae_slot1_Slot_ae_slot1_get,
34551 Field_ftsf64ae_slot1_Slot_ae_slot1_get,
34552 Field_ftsf66ae_slot1_Slot_ae_slot1_get,
34553 Field_ftsf67ae_slot1_Slot_ae_slot1_get,
34554 Field_ftsf69ae_slot1_Slot_ae_slot1_get,
34555 Field_ftsf71ae_slot1_Slot_ae_slot1_get,
34556 Field_ftsf72ae_slot1_Slot_ae_slot1_get,
34557 Field_ftsf73ae_slot1_Slot_ae_slot1_get,
34558 Field_ftsf75ae_slot1_Slot_ae_slot1_get,
34559 Field_ftsf76ae_slot1_Slot_ae_slot1_get,
34560 Field_ftsf77ae_slot1_Slot_ae_slot1_get,
34561 Field_ftsf78ae_slot1_Slot_ae_slot1_get,
34562 Field_ftsf79ae_slot1_Slot_ae_slot1_get,
34563 Field_ftsf80ae_slot1_Slot_ae_slot1_get,
34564 Field_ftsf81ae_slot1_Slot_ae_slot1_get,
34565 Field_ftsf82ae_slot1_Slot_ae_slot1_get,
34566 Field_ftsf84ae_slot1_Slot_ae_slot1_get,
34567 Field_ftsf86ae_slot1_Slot_ae_slot1_get,
34568 Field_ftsf87ae_slot1_Slot_ae_slot1_get,
34569 Field_ftsf88ae_slot1_Slot_ae_slot1_get,
34570 Field_ftsf89ae_slot1_Slot_ae_slot1_get,
34571 Field_ftsf90ae_slot1_Slot_ae_slot1_get,
34572 Field_ftsf91ae_slot1_Slot_ae_slot1_get,
34573 Field_ftsf92ae_slot1_Slot_ae_slot1_get,
34574 Field_ftsf94ae_slot1_Slot_ae_slot1_get,
34575 Field_ftsf96ae_slot1_Slot_ae_slot1_get,
34576 Field_ftsf97ae_slot1_Slot_ae_slot1_get,
34577 Field_ftsf98ae_slot1_Slot_ae_slot1_get,
34578 Field_ftsf99ae_slot1_Slot_ae_slot1_get,
34579 Field_ftsf100ae_slot1_Slot_ae_slot1_get,
34580 Field_ftsf101ae_slot1_Slot_ae_slot1_get,
34581 Field_ftsf103ae_slot1_Slot_ae_slot1_get,
34582 Field_ftsf104ae_slot1_Slot_ae_slot1_get,
34583 Field_ftsf105ae_slot1_Slot_ae_slot1_get,
34584 Field_ftsf106ae_slot1_Slot_ae_slot1_get,
34585 Field_ftsf107ae_slot1_Slot_ae_slot1_get,
34586 Field_ftsf108ae_slot1_Slot_ae_slot1_get,
34587 Field_ftsf109ae_slot1_Slot_ae_slot1_get,
34588 Field_ftsf110ae_slot1_Slot_ae_slot1_get,
34589 Field_ftsf111ae_slot1_Slot_ae_slot1_get,
34590 Field_ftsf112ae_slot1_Slot_ae_slot1_get,
34591 Field_ftsf113ae_slot1_Slot_ae_slot1_get,
34592 Field_ftsf114ae_slot1_Slot_ae_slot1_get,
34593 Field_ftsf115ae_slot1_Slot_ae_slot1_get,
34594 Field_ftsf116ae_slot1_Slot_ae_slot1_get,
34595 Field_ftsf118ae_slot1_Slot_ae_slot1_get,
34596 Field_ftsf119ae_slot1_Slot_ae_slot1_get,
34597 Field_ftsf120ae_slot1_Slot_ae_slot1_get,
34598 Field_ftsf122ae_slot1_Slot_ae_slot1_get,
34599 Field_ftsf124ae_slot1_Slot_ae_slot1_get,
34600 Field_ftsf125ae_slot1_Slot_ae_slot1_get,
34601 Field_ftsf126ae_slot1_Slot_ae_slot1_get,
34602 Field_ftsf127ae_slot1_Slot_ae_slot1_get,
34603 Field_ftsf128ae_slot1_Slot_ae_slot1_get,
34604 Field_ftsf129ae_slot1_Slot_ae_slot1_get,
34605 Field_ftsf130ae_slot1_Slot_ae_slot1_get,
34606 Field_ftsf131ae_slot1_Slot_ae_slot1_get,
34607 Field_ftsf132ae_slot1_Slot_ae_slot1_get,
34608 Field_ftsf133ae_slot1_Slot_ae_slot1_get,
34609 Field_ftsf134ae_slot1_Slot_ae_slot1_get,
34610 Field_ftsf135ae_slot1_Slot_ae_slot1_get,
34611 Field_ftsf136ae_slot1_Slot_ae_slot1_get,
34612 Field_ftsf137ae_slot1_Slot_ae_slot1_get,
34613 Field_ftsf138ae_slot1_Slot_ae_slot1_get,
34614 Field_ftsf139ae_slot1_Slot_ae_slot1_get,
34615 Field_ftsf140ae_slot1_Slot_ae_slot1_get,
34616 Field_ftsf141ae_slot1_Slot_ae_slot1_get,
34617 Field_ftsf142ae_slot1_Slot_ae_slot1_get,
34618 Field_ftsf143ae_slot1_Slot_ae_slot1_get,
34619 Field_ftsf144ae_slot1_Slot_ae_slot1_get,
34620 Field_ftsf145ae_slot1_Slot_ae_slot1_get,
34621 Field_ftsf146ae_slot1_Slot_ae_slot1_get,
34622 Field_ftsf147ae_slot1_Slot_ae_slot1_get,
34623 Field_ftsf148ae_slot1_Slot_ae_slot1_get,
34624 Field_ftsf149ae_slot1_Slot_ae_slot1_get,
34625 Field_ftsf150ae_slot1_Slot_ae_slot1_get,
34626 Field_ftsf151ae_slot1_Slot_ae_slot1_get,
34627 Field_ftsf152ae_slot1_Slot_ae_slot1_get,
34628 Field_ftsf153ae_slot1_Slot_ae_slot1_get,
34629 Field_ftsf154ae_slot1_Slot_ae_slot1_get,
34630 Field_ftsf155ae_slot1_Slot_ae_slot1_get,
34631 Field_ftsf156ae_slot1_Slot_ae_slot1_get,
34632 Field_ftsf157ae_slot1_Slot_ae_slot1_get,
34633 Field_ftsf158ae_slot1_Slot_ae_slot1_get,
34634 Field_ftsf159ae_slot1_Slot_ae_slot1_get,
34635 Field_ftsf160ae_slot1_Slot_ae_slot1_get,
34636 Field_ftsf161ae_slot1_Slot_ae_slot1_get,
34637 Field_ftsf162ae_slot1_Slot_ae_slot1_get,
34638 Field_ftsf163ae_slot1_Slot_ae_slot1_get,
34639 Field_ftsf164ae_slot1_Slot_ae_slot1_get,
34640 Field_ftsf165ae_slot1_Slot_ae_slot1_get,
34641 Field_ftsf166ae_slot1_Slot_ae_slot1_get,
34642 Field_ftsf167ae_slot1_Slot_ae_slot1_get,
34643 Field_ftsf168ae_slot1_Slot_ae_slot1_get,
34644 Field_ftsf169ae_slot1_Slot_ae_slot1_get,
34645 Field_ftsf170ae_slot1_Slot_ae_slot1_get,
34646 Field_ftsf171ae_slot1_Slot_ae_slot1_get,
34647 Field_ftsf172ae_slot1_Slot_ae_slot1_get,
34648 Field_ftsf173ae_slot1_Slot_ae_slot1_get,
34649 Field_ftsf174ae_slot1_Slot_ae_slot1_get,
34650 Field_ftsf175ae_slot1_Slot_ae_slot1_get,
34651 Field_ftsf176ae_slot1_Slot_ae_slot1_get,
34652 Field_ftsf177ae_slot1_Slot_ae_slot1_get,
34653 Field_ftsf178ae_slot1_Slot_ae_slot1_get,
34654 Field_ftsf179ae_slot1_Slot_ae_slot1_get,
34655 Field_ftsf180ae_slot1_Slot_ae_slot1_get,
34656 Field_ftsf181ae_slot1_Slot_ae_slot1_get,
34657 Field_ftsf182ae_slot1_Slot_ae_slot1_get,
34658 Field_ftsf183ae_slot1_Slot_ae_slot1_get,
34659 Field_ftsf184ae_slot1_Slot_ae_slot1_get,
34660 Field_ftsf185ae_slot1_Slot_ae_slot1_get,
34661 Field_ftsf186ae_slot1_Slot_ae_slot1_get,
34662 Field_ftsf187ae_slot1_Slot_ae_slot1_get,
34663 Field_ftsf188ae_slot1_Slot_ae_slot1_get,
34664 Field_ftsf189ae_slot1_Slot_ae_slot1_get,
34665 Field_ftsf190ae_slot1_Slot_ae_slot1_get,
34666 Field_ftsf191ae_slot1_Slot_ae_slot1_get,
34667 Field_ftsf192ae_slot1_Slot_ae_slot1_get,
34668 Field_ftsf193ae_slot1_Slot_ae_slot1_get,
34669 Field_ftsf194ae_slot1_Slot_ae_slot1_get,
34670 Field_ftsf195ae_slot1_Slot_ae_slot1_get,
34671 Field_ftsf196ae_slot1_Slot_ae_slot1_get,
34672 Field_ftsf197ae_slot1_Slot_ae_slot1_get,
34673 Field_ftsf198ae_slot1_Slot_ae_slot1_get,
34674 Field_ftsf199ae_slot1_Slot_ae_slot1_get,
34675 Field_ftsf200ae_slot1_Slot_ae_slot1_get,
34676 Field_ftsf201ae_slot1_Slot_ae_slot1_get,
34677 Field_ftsf202ae_slot1_Slot_ae_slot1_get,
34678 Field_ftsf203ae_slot1_Slot_ae_slot1_get,
34679 Field_ftsf204ae_slot1_Slot_ae_slot1_get,
34680 Field_ftsf205ae_slot1_Slot_ae_slot1_get,
34681 Field_ftsf206ae_slot1_Slot_ae_slot1_get,
34682 Field_ftsf207ae_slot1_Slot_ae_slot1_get,
34683 Field_ftsf208_Slot_ae_slot1_get,
34684 Field_ftsf209ae_slot1_Slot_ae_slot1_get,
34685 Field_ftsf210ae_slot1_Slot_ae_slot1_get,
34686 Field_ftsf211ae_slot1_Slot_ae_slot1_get,
34687 Field_ftsf330ae_slot1_Slot_ae_slot1_get,
34688 Field_ftsf332ae_slot1_Slot_ae_slot1_get,
34689 Field_ftsf334ae_slot1_Slot_ae_slot1_get,
34690 Field_ftsf336ae_slot1_Slot_ae_slot1_get,
34691 Field_ftsf337ae_slot1_Slot_ae_slot1_get,
34692 Field_ftsf338_Slot_ae_slot1_get,
34693 Field_ftsf339ae_slot1_Slot_ae_slot1_get,
34694 Field_ftsf340_Slot_ae_slot1_get,
34695 Field_ftsf341ae_slot1_Slot_ae_slot1_get,
34696 Field_ftsf342ae_slot1_Slot_ae_slot1_get,
34697 Field_ftsf343ae_slot1_Slot_ae_slot1_get,
34698 Field_ftsf344ae_slot1_Slot_ae_slot1_get,
34699 Field_ftsf346ae_slot1_Slot_ae_slot1_get,
34700 Field_ftsf347_Slot_ae_slot1_get,
34701 Field_ftsf348ae_slot1_Slot_ae_slot1_get,
34702 Field_ftsf349ae_slot1_Slot_ae_slot1_get,
34703 Field_ftsf350ae_slot1_Slot_ae_slot1_get,
34830 Implicit_Field_ar0_get,
34831 Implicit_Field_ar4_get,
34832 Implicit_Field_ar8_get,
34833 Implicit_Field_ar12_get,
34834 Implicit_Field_bt16_get,
34835 Implicit_Field_bs16_get,
34836 Implicit_Field_br16_get,
34837 Implicit_Field_brall_get
34840 static xtensa_set_field_fn
34841 Slot_ae_slot1_set_field_fns[] = {
34842 Field_t_Slot_ae_slot1_set,
34877 Field_t2_Slot_ae_slot1_set,
34891 Field_ae_r32_Slot_ae_slot1_set,
34893 Field_ae_r20_Slot_ae_slot1_set,
34894 Field_ae_r10_Slot_ae_slot1_set,
34895 Field_ae_s20_Slot_ae_slot1_set,
34898 Field_op0_s3_Slot_ae_slot1_set,
34899 Field_ftsf12_Slot_ae_slot1_set,
34900 Field_ftsf13_Slot_ae_slot1_set,
34901 Field_ftsf14_Slot_ae_slot1_set,
34902 Field_ftsf21ae_slot1_Slot_ae_slot1_set,
34903 Field_ftsf22ae_slot1_Slot_ae_slot1_set,
34904 Field_ftsf23ae_slot1_Slot_ae_slot1_set,
34905 Field_ftsf24ae_slot1_Slot_ae_slot1_set,
34906 Field_ftsf25ae_slot1_Slot_ae_slot1_set,
34907 Field_ftsf26ae_slot1_Slot_ae_slot1_set,
34908 Field_ftsf27ae_slot1_Slot_ae_slot1_set,
34909 Field_ftsf28ae_slot1_Slot_ae_slot1_set,
34910 Field_ftsf29ae_slot1_Slot_ae_slot1_set,
34911 Field_ftsf30ae_slot1_Slot_ae_slot1_set,
34912 Field_ftsf31ae_slot1_Slot_ae_slot1_set,
34913 Field_ftsf32ae_slot1_Slot_ae_slot1_set,
34914 Field_ftsf33ae_slot1_Slot_ae_slot1_set,
34915 Field_ftsf34ae_slot1_Slot_ae_slot1_set,
34916 Field_ftsf35ae_slot1_Slot_ae_slot1_set,
34917 Field_ftsf36ae_slot1_Slot_ae_slot1_set,
34918 Field_ftsf37ae_slot1_Slot_ae_slot1_set,
34919 Field_ftsf38ae_slot1_Slot_ae_slot1_set,
34920 Field_ftsf39ae_slot1_Slot_ae_slot1_set,
34921 Field_ftsf40ae_slot1_Slot_ae_slot1_set,
34922 Field_ftsf41ae_slot1_Slot_ae_slot1_set,
34923 Field_ftsf42ae_slot1_Slot_ae_slot1_set,
34924 Field_ftsf43ae_slot1_Slot_ae_slot1_set,
34925 Field_ftsf44ae_slot1_Slot_ae_slot1_set,
34926 Field_ftsf45ae_slot1_Slot_ae_slot1_set,
34927 Field_ftsf46ae_slot1_Slot_ae_slot1_set,
34928 Field_ftsf47ae_slot1_Slot_ae_slot1_set,
34929 Field_ftsf48ae_slot1_Slot_ae_slot1_set,
34930 Field_ftsf49ae_slot1_Slot_ae_slot1_set,
34931 Field_ftsf50ae_slot1_Slot_ae_slot1_set,
34932 Field_ftsf51ae_slot1_Slot_ae_slot1_set,
34933 Field_ftsf52ae_slot1_Slot_ae_slot1_set,
34934 Field_ftsf53ae_slot1_Slot_ae_slot1_set,
34935 Field_ftsf54ae_slot1_Slot_ae_slot1_set,
34936 Field_ftsf55ae_slot1_Slot_ae_slot1_set,
34937 Field_ftsf56ae_slot1_Slot_ae_slot1_set,
34938 Field_ftsf57ae_slot1_Slot_ae_slot1_set,
34939 Field_ftsf58ae_slot1_Slot_ae_slot1_set,
34940 Field_ftsf59ae_slot1_Slot_ae_slot1_set,
34941 Field_ftsf60ae_slot1_Slot_ae_slot1_set,
34942 Field_ftsf61ae_slot1_Slot_ae_slot1_set,
34943 Field_ftsf63ae_slot1_Slot_ae_slot1_set,
34944 Field_ftsf64ae_slot1_Slot_ae_slot1_set,
34945 Field_ftsf66ae_slot1_Slot_ae_slot1_set,
34946 Field_ftsf67ae_slot1_Slot_ae_slot1_set,
34947 Field_ftsf69ae_slot1_Slot_ae_slot1_set,
34948 Field_ftsf71ae_slot1_Slot_ae_slot1_set,
34949 Field_ftsf72ae_slot1_Slot_ae_slot1_set,
34950 Field_ftsf73ae_slot1_Slot_ae_slot1_set,
34951 Field_ftsf75ae_slot1_Slot_ae_slot1_set,
34952 Field_ftsf76ae_slot1_Slot_ae_slot1_set,
34953 Field_ftsf77ae_slot1_Slot_ae_slot1_set,
34954 Field_ftsf78ae_slot1_Slot_ae_slot1_set,
34955 Field_ftsf79ae_slot1_Slot_ae_slot1_set,
34956 Field_ftsf80ae_slot1_Slot_ae_slot1_set,
34957 Field_ftsf81ae_slot1_Slot_ae_slot1_set,
34958 Field_ftsf82ae_slot1_Slot_ae_slot1_set,
34959 Field_ftsf84ae_slot1_Slot_ae_slot1_set,
34960 Field_ftsf86ae_slot1_Slot_ae_slot1_set,
34961 Field_ftsf87ae_slot1_Slot_ae_slot1_set,
34962 Field_ftsf88ae_slot1_Slot_ae_slot1_set,
34963 Field_ftsf89ae_slot1_Slot_ae_slot1_set,
34964 Field_ftsf90ae_slot1_Slot_ae_slot1_set,
34965 Field_ftsf91ae_slot1_Slot_ae_slot1_set,
34966 Field_ftsf92ae_slot1_Slot_ae_slot1_set,
34967 Field_ftsf94ae_slot1_Slot_ae_slot1_set,
34968 Field_ftsf96ae_slot1_Slot_ae_slot1_set,
34969 Field_ftsf97ae_slot1_Slot_ae_slot1_set,
34970 Field_ftsf98ae_slot1_Slot_ae_slot1_set,
34971 Field_ftsf99ae_slot1_Slot_ae_slot1_set,
34972 Field_ftsf100ae_slot1_Slot_ae_slot1_set,
34973 Field_ftsf101ae_slot1_Slot_ae_slot1_set,
34974 Field_ftsf103ae_slot1_Slot_ae_slot1_set,
34975 Field_ftsf104ae_slot1_Slot_ae_slot1_set,
34976 Field_ftsf105ae_slot1_Slot_ae_slot1_set,
34977 Field_ftsf106ae_slot1_Slot_ae_slot1_set,
34978 Field_ftsf107ae_slot1_Slot_ae_slot1_set,
34979 Field_ftsf108ae_slot1_Slot_ae_slot1_set,
34980 Field_ftsf109ae_slot1_Slot_ae_slot1_set,
34981 Field_ftsf110ae_slot1_Slot_ae_slot1_set,
34982 Field_ftsf111ae_slot1_Slot_ae_slot1_set,
34983 Field_ftsf112ae_slot1_Slot_ae_slot1_set,
34984 Field_ftsf113ae_slot1_Slot_ae_slot1_set,
34985 Field_ftsf114ae_slot1_Slot_ae_slot1_set,
34986 Field_ftsf115ae_slot1_Slot_ae_slot1_set,
34987 Field_ftsf116ae_slot1_Slot_ae_slot1_set,
34988 Field_ftsf118ae_slot1_Slot_ae_slot1_set,
34989 Field_ftsf119ae_slot1_Slot_ae_slot1_set,
34990 Field_ftsf120ae_slot1_Slot_ae_slot1_set,
34991 Field_ftsf122ae_slot1_Slot_ae_slot1_set,
34992 Field_ftsf124ae_slot1_Slot_ae_slot1_set,
34993 Field_ftsf125ae_slot1_Slot_ae_slot1_set,
34994 Field_ftsf126ae_slot1_Slot_ae_slot1_set,
34995 Field_ftsf127ae_slot1_Slot_ae_slot1_set,
34996 Field_ftsf128ae_slot1_Slot_ae_slot1_set,
34997 Field_ftsf129ae_slot1_Slot_ae_slot1_set,
34998 Field_ftsf130ae_slot1_Slot_ae_slot1_set,
34999 Field_ftsf131ae_slot1_Slot_ae_slot1_set,
35000 Field_ftsf132ae_slot1_Slot_ae_slot1_set,
35001 Field_ftsf133ae_slot1_Slot_ae_slot1_set,
35002 Field_ftsf134ae_slot1_Slot_ae_slot1_set,
35003 Field_ftsf135ae_slot1_Slot_ae_slot1_set,
35004 Field_ftsf136ae_slot1_Slot_ae_slot1_set,
35005 Field_ftsf137ae_slot1_Slot_ae_slot1_set,
35006 Field_ftsf138ae_slot1_Slot_ae_slot1_set,
35007 Field_ftsf139ae_slot1_Slot_ae_slot1_set,
35008 Field_ftsf140ae_slot1_Slot_ae_slot1_set,
35009 Field_ftsf141ae_slot1_Slot_ae_slot1_set,
35010 Field_ftsf142ae_slot1_Slot_ae_slot1_set,
35011 Field_ftsf143ae_slot1_Slot_ae_slot1_set,
35012 Field_ftsf144ae_slot1_Slot_ae_slot1_set,
35013 Field_ftsf145ae_slot1_Slot_ae_slot1_set,
35014 Field_ftsf146ae_slot1_Slot_ae_slot1_set,
35015 Field_ftsf147ae_slot1_Slot_ae_slot1_set,
35016 Field_ftsf148ae_slot1_Slot_ae_slot1_set,
35017 Field_ftsf149ae_slot1_Slot_ae_slot1_set,
35018 Field_ftsf150ae_slot1_Slot_ae_slot1_set,
35019 Field_ftsf151ae_slot1_Slot_ae_slot1_set,
35020 Field_ftsf152ae_slot1_Slot_ae_slot1_set,
35021 Field_ftsf153ae_slot1_Slot_ae_slot1_set,
35022 Field_ftsf154ae_slot1_Slot_ae_slot1_set,
35023 Field_ftsf155ae_slot1_Slot_ae_slot1_set,
35024 Field_ftsf156ae_slot1_Slot_ae_slot1_set,
35025 Field_ftsf157ae_slot1_Slot_ae_slot1_set,
35026 Field_ftsf158ae_slot1_Slot_ae_slot1_set,
35027 Field_ftsf159ae_slot1_Slot_ae_slot1_set,
35028 Field_ftsf160ae_slot1_Slot_ae_slot1_set,
35029 Field_ftsf161ae_slot1_Slot_ae_slot1_set,
35030 Field_ftsf162ae_slot1_Slot_ae_slot1_set,
35031 Field_ftsf163ae_slot1_Slot_ae_slot1_set,
35032 Field_ftsf164ae_slot1_Slot_ae_slot1_set,
35033 Field_ftsf165ae_slot1_Slot_ae_slot1_set,
35034 Field_ftsf166ae_slot1_Slot_ae_slot1_set,
35035 Field_ftsf167ae_slot1_Slot_ae_slot1_set,
35036 Field_ftsf168ae_slot1_Slot_ae_slot1_set,
35037 Field_ftsf169ae_slot1_Slot_ae_slot1_set,
35038 Field_ftsf170ae_slot1_Slot_ae_slot1_set,
35039 Field_ftsf171ae_slot1_Slot_ae_slot1_set,
35040 Field_ftsf172ae_slot1_Slot_ae_slot1_set,
35041 Field_ftsf173ae_slot1_Slot_ae_slot1_set,
35042 Field_ftsf174ae_slot1_Slot_ae_slot1_set,
35043 Field_ftsf175ae_slot1_Slot_ae_slot1_set,
35044 Field_ftsf176ae_slot1_Slot_ae_slot1_set,
35045 Field_ftsf177ae_slot1_Slot_ae_slot1_set,
35046 Field_ftsf178ae_slot1_Slot_ae_slot1_set,
35047 Field_ftsf179ae_slot1_Slot_ae_slot1_set,
35048 Field_ftsf180ae_slot1_Slot_ae_slot1_set,
35049 Field_ftsf181ae_slot1_Slot_ae_slot1_set,
35050 Field_ftsf182ae_slot1_Slot_ae_slot1_set,
35051 Field_ftsf183ae_slot1_Slot_ae_slot1_set,
35052 Field_ftsf184ae_slot1_Slot_ae_slot1_set,
35053 Field_ftsf185ae_slot1_Slot_ae_slot1_set,
35054 Field_ftsf186ae_slot1_Slot_ae_slot1_set,
35055 Field_ftsf187ae_slot1_Slot_ae_slot1_set,
35056 Field_ftsf188ae_slot1_Slot_ae_slot1_set,
35057 Field_ftsf189ae_slot1_Slot_ae_slot1_set,
35058 Field_ftsf190ae_slot1_Slot_ae_slot1_set,
35059 Field_ftsf191ae_slot1_Slot_ae_slot1_set,
35060 Field_ftsf192ae_slot1_Slot_ae_slot1_set,
35061 Field_ftsf193ae_slot1_Slot_ae_slot1_set,
35062 Field_ftsf194ae_slot1_Slot_ae_slot1_set,
35063 Field_ftsf195ae_slot1_Slot_ae_slot1_set,
35064 Field_ftsf196ae_slot1_Slot_ae_slot1_set,
35065 Field_ftsf197ae_slot1_Slot_ae_slot1_set,
35066 Field_ftsf198ae_slot1_Slot_ae_slot1_set,
35067 Field_ftsf199ae_slot1_Slot_ae_slot1_set,
35068 Field_ftsf200ae_slot1_Slot_ae_slot1_set,
35069 Field_ftsf201ae_slot1_Slot_ae_slot1_set,
35070 Field_ftsf202ae_slot1_Slot_ae_slot1_set,
35071 Field_ftsf203ae_slot1_Slot_ae_slot1_set,
35072 Field_ftsf204ae_slot1_Slot_ae_slot1_set,
35073 Field_ftsf205ae_slot1_Slot_ae_slot1_set,
35074 Field_ftsf206ae_slot1_Slot_ae_slot1_set,
35075 Field_ftsf207ae_slot1_Slot_ae_slot1_set,
35076 Field_ftsf208_Slot_ae_slot1_set,
35077 Field_ftsf209ae_slot1_Slot_ae_slot1_set,
35078 Field_ftsf210ae_slot1_Slot_ae_slot1_set,
35079 Field_ftsf211ae_slot1_Slot_ae_slot1_set,
35080 Field_ftsf330ae_slot1_Slot_ae_slot1_set,
35081 Field_ftsf332ae_slot1_Slot_ae_slot1_set,
35082 Field_ftsf334ae_slot1_Slot_ae_slot1_set,
35083 Field_ftsf336ae_slot1_Slot_ae_slot1_set,
35084 Field_ftsf337ae_slot1_Slot_ae_slot1_set,
35085 Field_ftsf338_Slot_ae_slot1_set,
35086 Field_ftsf339ae_slot1_Slot_ae_slot1_set,
35087 Field_ftsf340_Slot_ae_slot1_set,
35088 Field_ftsf341ae_slot1_Slot_ae_slot1_set,
35089 Field_ftsf342ae_slot1_Slot_ae_slot1_set,
35090 Field_ftsf343ae_slot1_Slot_ae_slot1_set,
35091 Field_ftsf344ae_slot1_Slot_ae_slot1_set,
35092 Field_ftsf346ae_slot1_Slot_ae_slot1_set,
35093 Field_ftsf347_Slot_ae_slot1_set,
35094 Field_ftsf348ae_slot1_Slot_ae_slot1_set,
35095 Field_ftsf349ae_slot1_Slot_ae_slot1_set,
35096 Field_ftsf350ae_slot1_Slot_ae_slot1_set,
35223 Implicit_Field_set,
35224 Implicit_Field_set,
35225 Implicit_Field_set,
35226 Implicit_Field_set,
35227 Implicit_Field_set,
35228 Implicit_Field_set,
35229 Implicit_Field_set,
35233 static xtensa_get_field_fn
35234 Slot_ae_slot0_get_field_fns[] = {
35235 Field_t_Slot_ae_slot0_get,
35237 Field_bbi_Slot_ae_slot0_get,
35238 Field_imm12_Slot_ae_slot0_get,
35239 Field_imm8_Slot_ae_slot0_get,
35240 Field_s_Slot_ae_slot0_get,
35241 Field_imm12b_Slot_ae_slot0_get,
35242 Field_imm16_Slot_ae_slot0_get,
35245 Field_offset_Slot_ae_slot0_get,
35248 Field_op2_Slot_ae_slot0_get,
35249 Field_r_Slot_ae_slot0_get,
35252 Field_sae_Slot_ae_slot0_get,
35253 Field_sal_Slot_ae_slot0_get,
35254 Field_sargt_Slot_ae_slot0_get,
35256 Field_sas_Slot_ae_slot0_get,
35274 Field_s4_Slot_ae_slot0_get,
35277 Field_s8_Slot_ae_slot0_get,
35284 Field_ae_r32_Slot_ae_slot0_get,
35285 Field_ae_samt_s_t_Slot_ae_slot0_get,
35286 Field_ae_r20_Slot_ae_slot0_get,
35287 Field_ae_r10_Slot_ae_slot0_get,
35288 Field_ae_s20_Slot_ae_slot0_get,
35490 Field_op0_s4_Slot_ae_slot0_get,
35491 Field_ftsf212ae_slot0_Slot_ae_slot0_get,
35492 Field_ftsf213ae_slot0_Slot_ae_slot0_get,
35493 Field_ftsf214ae_slot0_Slot_ae_slot0_get,
35494 Field_ftsf215ae_slot0_Slot_ae_slot0_get,
35495 Field_ftsf216ae_slot0_Slot_ae_slot0_get,
35496 Field_ftsf217_Slot_ae_slot0_get,
35497 Field_ftsf218ae_slot0_Slot_ae_slot0_get,
35498 Field_ftsf219ae_slot0_Slot_ae_slot0_get,
35499 Field_ftsf220ae_slot0_Slot_ae_slot0_get,
35500 Field_ftsf221ae_slot0_Slot_ae_slot0_get,
35501 Field_ftsf222ae_slot0_Slot_ae_slot0_get,
35502 Field_ftsf223ae_slot0_Slot_ae_slot0_get,
35503 Field_ftsf224ae_slot0_Slot_ae_slot0_get,
35504 Field_ftsf225ae_slot0_Slot_ae_slot0_get,
35505 Field_ftsf226ae_slot0_Slot_ae_slot0_get,
35506 Field_ftsf227ae_slot0_Slot_ae_slot0_get,
35507 Field_ftsf228ae_slot0_Slot_ae_slot0_get,
35508 Field_ftsf229ae_slot0_Slot_ae_slot0_get,
35509 Field_ftsf230ae_slot0_Slot_ae_slot0_get,
35510 Field_ftsf231ae_slot0_Slot_ae_slot0_get,
35511 Field_ftsf232ae_slot0_Slot_ae_slot0_get,
35512 Field_ftsf233ae_slot0_Slot_ae_slot0_get,
35513 Field_ftsf234ae_slot0_Slot_ae_slot0_get,
35514 Field_ftsf235ae_slot0_Slot_ae_slot0_get,
35515 Field_ftsf236ae_slot0_Slot_ae_slot0_get,
35516 Field_ftsf237ae_slot0_Slot_ae_slot0_get,
35517 Field_ftsf238ae_slot0_Slot_ae_slot0_get,
35518 Field_ftsf239ae_slot0_Slot_ae_slot0_get,
35519 Field_ftsf240ae_slot0_Slot_ae_slot0_get,
35520 Field_ftsf241ae_slot0_Slot_ae_slot0_get,
35521 Field_ftsf242ae_slot0_Slot_ae_slot0_get,
35522 Field_ftsf243ae_slot0_Slot_ae_slot0_get,
35523 Field_ftsf244ae_slot0_Slot_ae_slot0_get,
35524 Field_ftsf245ae_slot0_Slot_ae_slot0_get,
35525 Field_ftsf246ae_slot0_Slot_ae_slot0_get,
35526 Field_ftsf247ae_slot0_Slot_ae_slot0_get,
35527 Field_ftsf248ae_slot0_Slot_ae_slot0_get,
35528 Field_ftsf249ae_slot0_Slot_ae_slot0_get,
35529 Field_ftsf250ae_slot0_Slot_ae_slot0_get,
35530 Field_ftsf251ae_slot0_Slot_ae_slot0_get,
35531 Field_ftsf252ae_slot0_Slot_ae_slot0_get,
35532 Field_ftsf253ae_slot0_Slot_ae_slot0_get,
35533 Field_ftsf254ae_slot0_Slot_ae_slot0_get,
35534 Field_ftsf255ae_slot0_Slot_ae_slot0_get,
35535 Field_ftsf256ae_slot0_Slot_ae_slot0_get,
35536 Field_ftsf257ae_slot0_Slot_ae_slot0_get,
35537 Field_ftsf258ae_slot0_Slot_ae_slot0_get,
35538 Field_ftsf259ae_slot0_Slot_ae_slot0_get,
35539 Field_ftsf260ae_slot0_Slot_ae_slot0_get,
35540 Field_ftsf261ae_slot0_Slot_ae_slot0_get,
35541 Field_ftsf262ae_slot0_Slot_ae_slot0_get,
35542 Field_ftsf263ae_slot0_Slot_ae_slot0_get,
35543 Field_ftsf264ae_slot0_Slot_ae_slot0_get,
35544 Field_ftsf265ae_slot0_Slot_ae_slot0_get,
35545 Field_ftsf266ae_slot0_Slot_ae_slot0_get,
35546 Field_ftsf267ae_slot0_Slot_ae_slot0_get,
35547 Field_ftsf268ae_slot0_Slot_ae_slot0_get,
35548 Field_ftsf269ae_slot0_Slot_ae_slot0_get,
35549 Field_ftsf270ae_slot0_Slot_ae_slot0_get,
35550 Field_ftsf271ae_slot0_Slot_ae_slot0_get,
35551 Field_ftsf272ae_slot0_Slot_ae_slot0_get,
35552 Field_ftsf273ae_slot0_Slot_ae_slot0_get,
35553 Field_ftsf274ae_slot0_Slot_ae_slot0_get,
35554 Field_ftsf275ae_slot0_Slot_ae_slot0_get,
35555 Field_ftsf276ae_slot0_Slot_ae_slot0_get,
35556 Field_ftsf277ae_slot0_Slot_ae_slot0_get,
35557 Field_ftsf278ae_slot0_Slot_ae_slot0_get,
35558 Field_ftsf279ae_slot0_Slot_ae_slot0_get,
35559 Field_ftsf281ae_slot0_Slot_ae_slot0_get,
35560 Field_ftsf282ae_slot0_Slot_ae_slot0_get,
35561 Field_ftsf283ae_slot0_Slot_ae_slot0_get,
35562 Field_ftsf284ae_slot0_Slot_ae_slot0_get,
35563 Field_ftsf286ae_slot0_Slot_ae_slot0_get,
35564 Field_ftsf288ae_slot0_Slot_ae_slot0_get,
35565 Field_ftsf290ae_slot0_Slot_ae_slot0_get,
35566 Field_ftsf292ae_slot0_Slot_ae_slot0_get,
35567 Field_ftsf293_Slot_ae_slot0_get,
35568 Field_ftsf294ae_slot0_Slot_ae_slot0_get,
35569 Field_ftsf295ae_slot0_Slot_ae_slot0_get,
35570 Field_ftsf296ae_slot0_Slot_ae_slot0_get,
35571 Field_ftsf297ae_slot0_Slot_ae_slot0_get,
35572 Field_ftsf298ae_slot0_Slot_ae_slot0_get,
35573 Field_ftsf299ae_slot0_Slot_ae_slot0_get,
35574 Field_ftsf300ae_slot0_Slot_ae_slot0_get,
35575 Field_ftsf301ae_slot0_Slot_ae_slot0_get,
35576 Field_ftsf302ae_slot0_Slot_ae_slot0_get,
35577 Field_ftsf303ae_slot0_Slot_ae_slot0_get,
35578 Field_ftsf304ae_slot0_Slot_ae_slot0_get,
35579 Field_ftsf306ae_slot0_Slot_ae_slot0_get,
35580 Field_ftsf308ae_slot0_Slot_ae_slot0_get,
35581 Field_ftsf309ae_slot0_Slot_ae_slot0_get,
35582 Field_ftsf310ae_slot0_Slot_ae_slot0_get,
35583 Field_ftsf311ae_slot0_Slot_ae_slot0_get,
35584 Field_ftsf312ae_slot0_Slot_ae_slot0_get,
35585 Field_ftsf313ae_slot0_Slot_ae_slot0_get,
35586 Field_ftsf314ae_slot0_Slot_ae_slot0_get,
35587 Field_ftsf315ae_slot0_Slot_ae_slot0_get,
35588 Field_ftsf316ae_slot0_Slot_ae_slot0_get,
35589 Field_ftsf317ae_slot0_Slot_ae_slot0_get,
35590 Field_ftsf318ae_slot0_Slot_ae_slot0_get,
35591 Field_ftsf319_Slot_ae_slot0_get,
35592 Field_ftsf320ae_slot0_Slot_ae_slot0_get,
35593 Field_ftsf321_Slot_ae_slot0_get,
35594 Field_ftsf322ae_slot0_Slot_ae_slot0_get,
35595 Field_ftsf323ae_slot0_Slot_ae_slot0_get,
35596 Field_ftsf324ae_slot0_Slot_ae_slot0_get,
35597 Field_ftsf325ae_slot0_Slot_ae_slot0_get,
35598 Field_ftsf326ae_slot0_Slot_ae_slot0_get,
35599 Field_ftsf328ae_slot0_Slot_ae_slot0_get,
35600 Field_ftsf329ae_slot0_Slot_ae_slot0_get,
35601 Field_ftsf352ae_slot0_Slot_ae_slot0_get,
35602 Field_ftsf353_Slot_ae_slot0_get,
35603 Field_ftsf354ae_slot0_Slot_ae_slot0_get,
35604 Field_ftsf356ae_slot0_Slot_ae_slot0_get,
35605 Field_ftsf357_Slot_ae_slot0_get,
35606 Field_ftsf358ae_slot0_Slot_ae_slot0_get,
35607 Field_ftsf359ae_slot0_Slot_ae_slot0_get,
35608 Field_ftsf360ae_slot0_Slot_ae_slot0_get,
35609 Field_ftsf361ae_slot0_Slot_ae_slot0_get,
35610 Field_ftsf362ae_slot0_Slot_ae_slot0_get,
35611 Field_ftsf364ae_slot0_Slot_ae_slot0_get,
35612 Field_ftsf365ae_slot0_Slot_ae_slot0_get,
35613 Field_ftsf366ae_slot0_Slot_ae_slot0_get,
35614 Field_ftsf368ae_slot0_Slot_ae_slot0_get,
35615 Field_ftsf369ae_slot0_Slot_ae_slot0_get,
35616 Implicit_Field_ar0_get,
35617 Implicit_Field_ar4_get,
35618 Implicit_Field_ar8_get,
35619 Implicit_Field_ar12_get,
35620 Implicit_Field_bt16_get,
35621 Implicit_Field_bs16_get,
35622 Implicit_Field_br16_get,
35623 Implicit_Field_brall_get
35626 static xtensa_set_field_fn
35627 Slot_ae_slot0_set_field_fns[] = {
35628 Field_t_Slot_ae_slot0_set,
35630 Field_bbi_Slot_ae_slot0_set,
35631 Field_imm12_Slot_ae_slot0_set,
35632 Field_imm8_Slot_ae_slot0_set,
35633 Field_s_Slot_ae_slot0_set,
35634 Field_imm12b_Slot_ae_slot0_set,
35635 Field_imm16_Slot_ae_slot0_set,
35638 Field_offset_Slot_ae_slot0_set,
35641 Field_op2_Slot_ae_slot0_set,
35642 Field_r_Slot_ae_slot0_set,
35645 Field_sae_Slot_ae_slot0_set,
35646 Field_sal_Slot_ae_slot0_set,
35647 Field_sargt_Slot_ae_slot0_set,
35649 Field_sas_Slot_ae_slot0_set,
35667 Field_s4_Slot_ae_slot0_set,
35670 Field_s8_Slot_ae_slot0_set,
35677 Field_ae_r32_Slot_ae_slot0_set,
35678 Field_ae_samt_s_t_Slot_ae_slot0_set,
35679 Field_ae_r20_Slot_ae_slot0_set,
35680 Field_ae_r10_Slot_ae_slot0_set,
35681 Field_ae_s20_Slot_ae_slot0_set,
35883 Field_op0_s4_Slot_ae_slot0_set,
35884 Field_ftsf212ae_slot0_Slot_ae_slot0_set,
35885 Field_ftsf213ae_slot0_Slot_ae_slot0_set,
35886 Field_ftsf214ae_slot0_Slot_ae_slot0_set,
35887 Field_ftsf215ae_slot0_Slot_ae_slot0_set,
35888 Field_ftsf216ae_slot0_Slot_ae_slot0_set,
35889 Field_ftsf217_Slot_ae_slot0_set,
35890 Field_ftsf218ae_slot0_Slot_ae_slot0_set,
35891 Field_ftsf219ae_slot0_Slot_ae_slot0_set,
35892 Field_ftsf220ae_slot0_Slot_ae_slot0_set,
35893 Field_ftsf221ae_slot0_Slot_ae_slot0_set,
35894 Field_ftsf222ae_slot0_Slot_ae_slot0_set,
35895 Field_ftsf223ae_slot0_Slot_ae_slot0_set,
35896 Field_ftsf224ae_slot0_Slot_ae_slot0_set,
35897 Field_ftsf225ae_slot0_Slot_ae_slot0_set,
35898 Field_ftsf226ae_slot0_Slot_ae_slot0_set,
35899 Field_ftsf227ae_slot0_Slot_ae_slot0_set,
35900 Field_ftsf228ae_slot0_Slot_ae_slot0_set,
35901 Field_ftsf229ae_slot0_Slot_ae_slot0_set,
35902 Field_ftsf230ae_slot0_Slot_ae_slot0_set,
35903 Field_ftsf231ae_slot0_Slot_ae_slot0_set,
35904 Field_ftsf232ae_slot0_Slot_ae_slot0_set,
35905 Field_ftsf233ae_slot0_Slot_ae_slot0_set,
35906 Field_ftsf234ae_slot0_Slot_ae_slot0_set,
35907 Field_ftsf235ae_slot0_Slot_ae_slot0_set,
35908 Field_ftsf236ae_slot0_Slot_ae_slot0_set,
35909 Field_ftsf237ae_slot0_Slot_ae_slot0_set,
35910 Field_ftsf238ae_slot0_Slot_ae_slot0_set,
35911 Field_ftsf239ae_slot0_Slot_ae_slot0_set,
35912 Field_ftsf240ae_slot0_Slot_ae_slot0_set,
35913 Field_ftsf241ae_slot0_Slot_ae_slot0_set,
35914 Field_ftsf242ae_slot0_Slot_ae_slot0_set,
35915 Field_ftsf243ae_slot0_Slot_ae_slot0_set,
35916 Field_ftsf244ae_slot0_Slot_ae_slot0_set,
35917 Field_ftsf245ae_slot0_Slot_ae_slot0_set,
35918 Field_ftsf246ae_slot0_Slot_ae_slot0_set,
35919 Field_ftsf247ae_slot0_Slot_ae_slot0_set,
35920 Field_ftsf248ae_slot0_Slot_ae_slot0_set,
35921 Field_ftsf249ae_slot0_Slot_ae_slot0_set,
35922 Field_ftsf250ae_slot0_Slot_ae_slot0_set,
35923 Field_ftsf251ae_slot0_Slot_ae_slot0_set,
35924 Field_ftsf252ae_slot0_Slot_ae_slot0_set,
35925 Field_ftsf253ae_slot0_Slot_ae_slot0_set,
35926 Field_ftsf254ae_slot0_Slot_ae_slot0_set,
35927 Field_ftsf255ae_slot0_Slot_ae_slot0_set,
35928 Field_ftsf256ae_slot0_Slot_ae_slot0_set,
35929 Field_ftsf257ae_slot0_Slot_ae_slot0_set,
35930 Field_ftsf258ae_slot0_Slot_ae_slot0_set,
35931 Field_ftsf259ae_slot0_Slot_ae_slot0_set,
35932 Field_ftsf260ae_slot0_Slot_ae_slot0_set,
35933 Field_ftsf261ae_slot0_Slot_ae_slot0_set,
35934 Field_ftsf262ae_slot0_Slot_ae_slot0_set,
35935 Field_ftsf263ae_slot0_Slot_ae_slot0_set,
35936 Field_ftsf264ae_slot0_Slot_ae_slot0_set,
35937 Field_ftsf265ae_slot0_Slot_ae_slot0_set,
35938 Field_ftsf266ae_slot0_Slot_ae_slot0_set,
35939 Field_ftsf267ae_slot0_Slot_ae_slot0_set,
35940 Field_ftsf268ae_slot0_Slot_ae_slot0_set,
35941 Field_ftsf269ae_slot0_Slot_ae_slot0_set,
35942 Field_ftsf270ae_slot0_Slot_ae_slot0_set,
35943 Field_ftsf271ae_slot0_Slot_ae_slot0_set,
35944 Field_ftsf272ae_slot0_Slot_ae_slot0_set,
35945 Field_ftsf273ae_slot0_Slot_ae_slot0_set,
35946 Field_ftsf274ae_slot0_Slot_ae_slot0_set,
35947 Field_ftsf275ae_slot0_Slot_ae_slot0_set,
35948 Field_ftsf276ae_slot0_Slot_ae_slot0_set,
35949 Field_ftsf277ae_slot0_Slot_ae_slot0_set,
35950 Field_ftsf278ae_slot0_Slot_ae_slot0_set,
35951 Field_ftsf279ae_slot0_Slot_ae_slot0_set,
35952 Field_ftsf281ae_slot0_Slot_ae_slot0_set,
35953 Field_ftsf282ae_slot0_Slot_ae_slot0_set,
35954 Field_ftsf283ae_slot0_Slot_ae_slot0_set,
35955 Field_ftsf284ae_slot0_Slot_ae_slot0_set,
35956 Field_ftsf286ae_slot0_Slot_ae_slot0_set,
35957 Field_ftsf288ae_slot0_Slot_ae_slot0_set,
35958 Field_ftsf290ae_slot0_Slot_ae_slot0_set,
35959 Field_ftsf292ae_slot0_Slot_ae_slot0_set,
35960 Field_ftsf293_Slot_ae_slot0_set,
35961 Field_ftsf294ae_slot0_Slot_ae_slot0_set,
35962 Field_ftsf295ae_slot0_Slot_ae_slot0_set,
35963 Field_ftsf296ae_slot0_Slot_ae_slot0_set,
35964 Field_ftsf297ae_slot0_Slot_ae_slot0_set,
35965 Field_ftsf298ae_slot0_Slot_ae_slot0_set,
35966 Field_ftsf299ae_slot0_Slot_ae_slot0_set,
35967 Field_ftsf300ae_slot0_Slot_ae_slot0_set,
35968 Field_ftsf301ae_slot0_Slot_ae_slot0_set,
35969 Field_ftsf302ae_slot0_Slot_ae_slot0_set,
35970 Field_ftsf303ae_slot0_Slot_ae_slot0_set,
35971 Field_ftsf304ae_slot0_Slot_ae_slot0_set,
35972 Field_ftsf306ae_slot0_Slot_ae_slot0_set,
35973 Field_ftsf308ae_slot0_Slot_ae_slot0_set,
35974 Field_ftsf309ae_slot0_Slot_ae_slot0_set,
35975 Field_ftsf310ae_slot0_Slot_ae_slot0_set,
35976 Field_ftsf311ae_slot0_Slot_ae_slot0_set,
35977 Field_ftsf312ae_slot0_Slot_ae_slot0_set,
35978 Field_ftsf313ae_slot0_Slot_ae_slot0_set,
35979 Field_ftsf314ae_slot0_Slot_ae_slot0_set,
35980 Field_ftsf315ae_slot0_Slot_ae_slot0_set,
35981 Field_ftsf316ae_slot0_Slot_ae_slot0_set,
35982 Field_ftsf317ae_slot0_Slot_ae_slot0_set,
35983 Field_ftsf318ae_slot0_Slot_ae_slot0_set,
35984 Field_ftsf319_Slot_ae_slot0_set,
35985 Field_ftsf320ae_slot0_Slot_ae_slot0_set,
35986 Field_ftsf321_Slot_ae_slot0_set,
35987 Field_ftsf322ae_slot0_Slot_ae_slot0_set,
35988 Field_ftsf323ae_slot0_Slot_ae_slot0_set,
35989 Field_ftsf324ae_slot0_Slot_ae_slot0_set,
35990 Field_ftsf325ae_slot0_Slot_ae_slot0_set,
35991 Field_ftsf326ae_slot0_Slot_ae_slot0_set,
35992 Field_ftsf328ae_slot0_Slot_ae_slot0_set,
35993 Field_ftsf329ae_slot0_Slot_ae_slot0_set,
35994 Field_ftsf352ae_slot0_Slot_ae_slot0_set,
35995 Field_ftsf353_Slot_ae_slot0_set,
35996 Field_ftsf354ae_slot0_Slot_ae_slot0_set,
35997 Field_ftsf356ae_slot0_Slot_ae_slot0_set,
35998 Field_ftsf357_Slot_ae_slot0_set,
35999 Field_ftsf358ae_slot0_Slot_ae_slot0_set,
36000 Field_ftsf359ae_slot0_Slot_ae_slot0_set,
36001 Field_ftsf360ae_slot0_Slot_ae_slot0_set,
36002 Field_ftsf361ae_slot0_Slot_ae_slot0_set,
36003 Field_ftsf362ae_slot0_Slot_ae_slot0_set,
36004 Field_ftsf364ae_slot0_Slot_ae_slot0_set,
36005 Field_ftsf365ae_slot0_Slot_ae_slot0_set,
36006 Field_ftsf366ae_slot0_Slot_ae_slot0_set,
36007 Field_ftsf368ae_slot0_Slot_ae_slot0_set,
36008 Field_ftsf369ae_slot0_Slot_ae_slot0_set,
36009 Implicit_Field_set,
36010 Implicit_Field_set,
36011 Implicit_Field_set,
36012 Implicit_Field_set,
36013 Implicit_Field_set,
36014 Implicit_Field_set,
36015 Implicit_Field_set,
36019 static xtensa_slot_internal slots[] = {
36020 { "Inst", "x24", 0,
36021 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
36022 Slot_inst_get_field_fns, Slot_inst_set_field_fns,
36023 Slot_inst_decode, "nop" },
36024 { "Inst16a", "x16a", 0,
36025 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
36026 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
36027 Slot_inst16a_decode, "" },
36028 { "Inst16b", "x16b", 0,
36029 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
36030 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
36031 Slot_inst16b_decode, "nop.n" },
36032 { "ae_slot1", "ae_format", 1,
36033 Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set,
36034 Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
36035 Slot_ae_slot1_decode, "nop" },
36036 { "ae_slot0", "ae_format", 0,
36037 Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set,
36038 Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
36039 Slot_ae_slot0_decode, "nop" }
36043 /* Instruction formats. */
36046 Format_x24_encode (xtensa_insnbuf insn)
36053 Format_x16a_encode (xtensa_insnbuf insn)
36060 Format_x16b_encode (xtensa_insnbuf insn)
36067 Format_ae_format_encode (xtensa_insnbuf insn)
36073 static int Format_x24_slots[] = { 0 };
36075 static int Format_x16a_slots[] = { 1 };
36077 static int Format_x16b_slots[] = { 2 };
36079 static int Format_ae_format_slots[] = { 4, 3 };
36081 static xtensa_format_internal formats[] = {
36082 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
36083 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
36084 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
36085 { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
36090 format_decoder (const xtensa_insnbuf insn)
36092 if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
36093 return 0; /* x24 */
36094 if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
36095 return 1; /* x16a */
36096 if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
36097 return 2; /* x16b */
36098 if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0)
36099 return 3; /* ae_format */
36103 static int length_table[256] = {
36363 length_decoder (const unsigned char *insn)
36366 return length_table[l];
36370 /* Top-level ISA structure. */
36372 xtensa_isa_internal xtensa_modules = {
36373 0 /* little-endian */,
36374 8 /* insn_size */, 0,
36375 4, formats, format_decoder, length_decoder,
36377 389 /* num_fields */,
36382 NUM_STATES, states, 0,
36383 NUM_SYSREGS, sysregs, 0,
36384 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },