hw/char/milkymist-uart.c

   1 /*
   2  *  QEMU model of the Milkymist UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/uart.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/qdev-properties.h"
  27 #include "hw/qdev-properties-system.h"
  28 #include "hw/sysbus.h"
  29 #include "migration/vmstate.h"
  30 #include "trace.h"
  31 #include "chardev/char-fe.h"
  32 #include "qemu/error-report.h"
  33 #include "qemu/module.h"
  34 #include "qom/object.h"
  35
  36 enum {
  37     R_RXTX = 0,
  38     R_DIV,
  39     R_STAT,
  40     R_CTRL,
  41     R_DBG,
  42     R_MAX
  43 };
  44
  45 enum {
  46     STAT_THRE   = (1<<0),
  47     STAT_RX_EVT = (1<<1),
  48     STAT_TX_EVT = (1<<2),
  49 };
  50
  51 enum {
  52     CTRL_RX_IRQ_EN = (1<<0),
  53     CTRL_TX_IRQ_EN = (1<<1),
  54     CTRL_THRU_EN   = (1<<2),
  55 };
  56
  57 enum {
  58     DBG_BREAK_EN = (1<<0),
  59 };
  60
  61 #define TYPE_MILKYMIST_UART "milkymist-uart"
  62 OBJECT_DECLARE_SIMPLE_TYPE(MilkymistUartState, MILKYMIST_UART)
  63
  64 struct MilkymistUartState {
  65     SysBusDevice parent_obj;
  66
  67     MemoryRegion regs_region;
  68     CharBackend chr;
  69     qemu_irq irq;
  70
  71     uint32_t regs[R_MAX];
  72 };
  73
  74 static void uart_update_irq(MilkymistUartState *s)
  75 {
  76     int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
  77     int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
  78     int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
  79     int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
  80
  81     if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
  82         trace_milkymist_uart_raise_irq();
  83         qemu_irq_raise(s->irq);
  84     } else {
  85         trace_milkymist_uart_lower_irq();
  86         qemu_irq_lower(s->irq);
  87     }
  88 }
  89
  90 static uint64_t uart_read(void *opaque, hwaddr addr,
  91                           unsigned size)
  92 {
  93     MilkymistUartState *s = opaque;
  94     uint32_t r = 0;
  95
  96     addr >>= 2;
  97     switch (addr) {
  98     case R_RXTX:
  99         r = s->regs[addr];
 100         break;
 101     case R_DIV:
 102     case R_STAT:
 103     case R_CTRL:
 104     case R_DBG:
 105         r = s->regs[addr];
 106         break;
 107
 108     default:
 109         error_report("milkymist_uart: read access to unknown register 0x"
 110                 TARGET_FMT_plx, addr << 2);
 111         break;
 112     }
 113
 114     trace_milkymist_uart_memory_read(addr << 2, r);
 115
 116     return r;
 117 }
 118
 119 static void uart_write(void *opaque, hwaddr addr, uint64_t value,
 120                        unsigned size)
 121 {
 122     MilkymistUartState *s = opaque;
 123     unsigned char ch = value;
 124
 125     trace_milkymist_uart_memory_write(addr, value);
 126
 127     addr >>= 2;
 128     switch (addr) {
 129     case R_RXTX:
 130         qemu_chr_fe_write_all(&s->chr, &ch, 1);
 131         s->regs[R_STAT] |= STAT_TX_EVT;
 132         break;
 133     case R_DIV:
 134     case R_CTRL:
 135     case R_DBG:
 136         s->regs[addr] = value;
 137         break;
 138
 139     case R_STAT:
 140         /* write one to clear bits */
 141         s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
 142         qemu_chr_fe_accept_input(&s->chr);
 143         break;
 144
 145     default:
 146         error_report("milkymist_uart: write access to unknown register 0x"
 147                 TARGET_FMT_plx, addr << 2);
 148         break;
 149     }
 150
 151     uart_update_irq(s);
 152 }
 153
 154 static const MemoryRegionOps uart_mmio_ops = {
 155     .read = uart_read,
 156     .write = uart_write,
 157     .valid = {
 158         .min_access_size = 4,
 159         .max_access_size = 4,
 160     },
 161     .endianness = DEVICE_NATIVE_ENDIAN,
 162 };
 163
 164 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 165 {
 166     MilkymistUartState *s = opaque;
 167
 168     assert(!(s->regs[R_STAT] & STAT_RX_EVT));
 169
 170     s->regs[R_STAT] |= STAT_RX_EVT;
 171     s->regs[R_RXTX] = *buf;
 172
 173     uart_update_irq(s);
 174 }
 175
 176 static int uart_can_rx(void *opaque)
 177 {
 178     MilkymistUartState *s = opaque;
 179
 180     return !(s->regs[R_STAT] & STAT_RX_EVT);
 181 }
 182
 183 static void uart_event(void *opaque, QEMUChrEvent event)
 184 {
 185 }
 186
 187 static void milkymist_uart_reset(DeviceState *d)
 188 {
 189     MilkymistUartState *s = MILKYMIST_UART(d);
 190     int i;
 191
 192     for (i = 0; i < R_MAX; i++) {
 193         s->regs[i] = 0;
 194     }
 195
 196     /* THRE is always set */
 197     s->regs[R_STAT] = STAT_THRE;
 198 }
 199
 200 static void milkymist_uart_realize(DeviceState *dev, Error **errp)
 201 {
 202     MilkymistUartState *s = MILKYMIST_UART(dev);
 203
 204     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 205                              uart_event, NULL, s, NULL, true);
 206 }
 207
 208 static void milkymist_uart_init(Object *obj)
 209 {
 210     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 211     MilkymistUartState *s = MILKYMIST_UART(obj);
 212
 213     sysbus_init_irq(sbd, &s->irq);
 214
 215     memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
 216                           "milkymist-uart", R_MAX * 4);
 217     sysbus_init_mmio(sbd, &s->regs_region);
 218 }
 219
 220 static const VMStateDescription vmstate_milkymist_uart = {
 221     .name = "milkymist-uart",
 222     .version_id = 1,
 223     .minimum_version_id = 1,
 224     .fields = (VMStateField[]) {
 225         VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
 226         VMSTATE_END_OF_LIST()
 227     }
 228 };
 229
 230 static Property milkymist_uart_properties[] = {
 231     DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
 232     DEFINE_PROP_END_OF_LIST(),
 233 };
 234
 235 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
 236 {
 237     DeviceClass *dc = DEVICE_CLASS(klass);
 238
 239     dc->realize = milkymist_uart_realize;
 240     dc->reset = milkymist_uart_reset;
 241     dc->vmsd = &vmstate_milkymist_uart;
 242     device_class_set_props(dc, milkymist_uart_properties);
 243 }
 244
 245 static const TypeInfo milkymist_uart_info = {
 246     .name          = TYPE_MILKYMIST_UART,
 247     .parent        = TYPE_SYS_BUS_DEVICE,
 248     .instance_size = sizeof(MilkymistUartState),
 249     .instance_init = milkymist_uart_init,
 250     .class_init    = milkymist_uart_class_init,
 251 };
 252
 253 static void milkymist_uart_register_types(void)
 254 {
 255     type_register_static(&milkymist_uart_info);
 256 }
 257
 258 type_init(milkymist_uart_register_types)