2 * Microblaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
30 #if !defined(CONFIG_USER_ONLY)
32 /* Try to fill the TLB and return an exception if error. If retaddr is
33 * NULL, it means that the function was called in C code (i.e. not
34 * from generated code or from helper.c)
36 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
37 int mmu_idx
, uintptr_t retaddr
)
41 ret
= mb_cpu_handle_mmu_fault(cs
, addr
, access_type
, mmu_idx
);
44 /* now we have a real cpu fault */
45 cpu_restore_state(cs
, retaddr
);
52 void helper_put(uint32_t id
, uint32_t ctrl
, uint32_t data
)
54 int test
= ctrl
& STREAM_TEST
;
55 int atomic
= ctrl
& STREAM_ATOMIC
;
56 int control
= ctrl
& STREAM_CONTROL
;
57 int nonblock
= ctrl
& STREAM_NONBLOCK
;
58 int exception
= ctrl
& STREAM_EXCEPTION
;
60 qemu_log_mask(LOG_UNIMP
, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
69 uint32_t helper_get(uint32_t id
, uint32_t ctrl
)
71 int test
= ctrl
& STREAM_TEST
;
72 int atomic
= ctrl
& STREAM_ATOMIC
;
73 int control
= ctrl
& STREAM_CONTROL
;
74 int nonblock
= ctrl
& STREAM_NONBLOCK
;
75 int exception
= ctrl
& STREAM_EXCEPTION
;
77 qemu_log_mask(LOG_UNIMP
, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
84 return 0xdead0000 | id
;
87 void helper_raise_exception(CPUMBState
*env
, uint32_t index
)
89 CPUState
*cs
= CPU(mb_env_get_cpu(env
));
91 cs
->exception_index
= index
;
95 void helper_debug(CPUMBState
*env
)
99 qemu_log("PC=%8.8x\n", env
->sregs
[SR_PC
]);
100 qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
101 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
], env
->sregs
[SR_EAR
],
102 env
->debug
, env
->imm
, env
->iflags
);
103 qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
104 env
->btaken
, env
->btarget
,
105 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
106 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel",
107 (env
->sregs
[SR_MSR
] & MSR_EIP
),
108 (env
->sregs
[SR_MSR
] & MSR_IE
));
109 for (i
= 0; i
< 32; i
++) {
110 qemu_log("r%2.2d=%8.8x ", i
, env
->regs
[i
]);
111 if ((i
+ 1) % 4 == 0)
117 static inline uint32_t compute_carry(uint32_t a
, uint32_t b
, uint32_t cin
)
121 if ((b
== ~0) && cin
)
123 else if ((~0 - a
) < (b
+ cin
))
128 uint32_t helper_cmp(uint32_t a
, uint32_t b
)
133 if ((b
& 0x80000000) ^ (a
& 0x80000000))
134 t
= (t
& 0x7fffffff) | (b
& 0x80000000);
138 uint32_t helper_cmpu(uint32_t a
, uint32_t b
)
143 if ((b
& 0x80000000) ^ (a
& 0x80000000))
144 t
= (t
& 0x7fffffff) | (a
& 0x80000000);
148 uint32_t helper_carry(uint32_t a
, uint32_t b
, uint32_t cf
)
150 return compute_carry(a
, b
, cf
);
153 static inline int div_prepare(CPUMBState
*env
, uint32_t a
, uint32_t b
)
156 env
->sregs
[SR_MSR
] |= MSR_DZ
;
158 if ((env
->sregs
[SR_MSR
] & MSR_EE
)
159 && !(env
->pvr
.regs
[2] & PVR2_DIV_ZERO_EXC_MASK
)) {
160 env
->sregs
[SR_ESR
] = ESR_EC_DIVZERO
;
161 helper_raise_exception(env
, EXCP_HW_EXCP
);
165 env
->sregs
[SR_MSR
] &= ~MSR_DZ
;
169 uint32_t helper_divs(CPUMBState
*env
, uint32_t a
, uint32_t b
)
171 if (!div_prepare(env
, a
, b
)) {
174 return (int32_t)a
/ (int32_t)b
;
177 uint32_t helper_divu(CPUMBState
*env
, uint32_t a
, uint32_t b
)
179 if (!div_prepare(env
, a
, b
)) {
185 /* raise FPU exception. */
186 static void raise_fpu_exception(CPUMBState
*env
)
188 env
->sregs
[SR_ESR
] = ESR_EC_FPU
;
189 helper_raise_exception(env
, EXCP_HW_EXCP
);
192 static void update_fpu_flags(CPUMBState
*env
, int flags
)
196 if (flags
& float_flag_invalid
) {
197 env
->sregs
[SR_FSR
] |= FSR_IO
;
200 if (flags
& float_flag_divbyzero
) {
201 env
->sregs
[SR_FSR
] |= FSR_DZ
;
204 if (flags
& float_flag_overflow
) {
205 env
->sregs
[SR_FSR
] |= FSR_OF
;
208 if (flags
& float_flag_underflow
) {
209 env
->sregs
[SR_FSR
] |= FSR_UF
;
213 && (env
->pvr
.regs
[2] & PVR2_FPU_EXC_MASK
)
214 && (env
->sregs
[SR_MSR
] & MSR_EE
)) {
215 raise_fpu_exception(env
);
219 uint32_t helper_fadd(CPUMBState
*env
, uint32_t a
, uint32_t b
)
221 CPU_FloatU fd
, fa
, fb
;
224 set_float_exception_flags(0, &env
->fp_status
);
227 fd
.f
= float32_add(fa
.f
, fb
.f
, &env
->fp_status
);
229 flags
= get_float_exception_flags(&env
->fp_status
);
230 update_fpu_flags(env
, flags
);
234 uint32_t helper_frsub(CPUMBState
*env
, uint32_t a
, uint32_t b
)
236 CPU_FloatU fd
, fa
, fb
;
239 set_float_exception_flags(0, &env
->fp_status
);
242 fd
.f
= float32_sub(fb
.f
, fa
.f
, &env
->fp_status
);
243 flags
= get_float_exception_flags(&env
->fp_status
);
244 update_fpu_flags(env
, flags
);
248 uint32_t helper_fmul(CPUMBState
*env
, uint32_t a
, uint32_t b
)
250 CPU_FloatU fd
, fa
, fb
;
253 set_float_exception_flags(0, &env
->fp_status
);
256 fd
.f
= float32_mul(fa
.f
, fb
.f
, &env
->fp_status
);
257 flags
= get_float_exception_flags(&env
->fp_status
);
258 update_fpu_flags(env
, flags
);
263 uint32_t helper_fdiv(CPUMBState
*env
, uint32_t a
, uint32_t b
)
265 CPU_FloatU fd
, fa
, fb
;
268 set_float_exception_flags(0, &env
->fp_status
);
271 fd
.f
= float32_div(fb
.f
, fa
.f
, &env
->fp_status
);
272 flags
= get_float_exception_flags(&env
->fp_status
);
273 update_fpu_flags(env
, flags
);
278 uint32_t helper_fcmp_un(CPUMBState
*env
, uint32_t a
, uint32_t b
)
286 if (float32_is_signaling_nan(fa
.f
, &env
->fp_status
) ||
287 float32_is_signaling_nan(fb
.f
, &env
->fp_status
)) {
288 update_fpu_flags(env
, float_flag_invalid
);
292 if (float32_is_quiet_nan(fa
.f
, &env
->fp_status
) ||
293 float32_is_quiet_nan(fb
.f
, &env
->fp_status
)) {
300 uint32_t helper_fcmp_lt(CPUMBState
*env
, uint32_t a
, uint32_t b
)
306 set_float_exception_flags(0, &env
->fp_status
);
309 r
= float32_lt(fb
.f
, fa
.f
, &env
->fp_status
);
310 flags
= get_float_exception_flags(&env
->fp_status
);
311 update_fpu_flags(env
, flags
& float_flag_invalid
);
316 uint32_t helper_fcmp_eq(CPUMBState
*env
, uint32_t a
, uint32_t b
)
322 set_float_exception_flags(0, &env
->fp_status
);
325 r
= float32_eq_quiet(fa
.f
, fb
.f
, &env
->fp_status
);
326 flags
= get_float_exception_flags(&env
->fp_status
);
327 update_fpu_flags(env
, flags
& float_flag_invalid
);
332 uint32_t helper_fcmp_le(CPUMBState
*env
, uint32_t a
, uint32_t b
)
340 set_float_exception_flags(0, &env
->fp_status
);
341 r
= float32_le(fa
.f
, fb
.f
, &env
->fp_status
);
342 flags
= get_float_exception_flags(&env
->fp_status
);
343 update_fpu_flags(env
, flags
& float_flag_invalid
);
349 uint32_t helper_fcmp_gt(CPUMBState
*env
, uint32_t a
, uint32_t b
)
356 set_float_exception_flags(0, &env
->fp_status
);
357 r
= float32_lt(fa
.f
, fb
.f
, &env
->fp_status
);
358 flags
= get_float_exception_flags(&env
->fp_status
);
359 update_fpu_flags(env
, flags
& float_flag_invalid
);
363 uint32_t helper_fcmp_ne(CPUMBState
*env
, uint32_t a
, uint32_t b
)
370 set_float_exception_flags(0, &env
->fp_status
);
371 r
= !float32_eq_quiet(fa
.f
, fb
.f
, &env
->fp_status
);
372 flags
= get_float_exception_flags(&env
->fp_status
);
373 update_fpu_flags(env
, flags
& float_flag_invalid
);
378 uint32_t helper_fcmp_ge(CPUMBState
*env
, uint32_t a
, uint32_t b
)
385 set_float_exception_flags(0, &env
->fp_status
);
386 r
= !float32_lt(fa
.f
, fb
.f
, &env
->fp_status
);
387 flags
= get_float_exception_flags(&env
->fp_status
);
388 update_fpu_flags(env
, flags
& float_flag_invalid
);
393 uint32_t helper_flt(CPUMBState
*env
, uint32_t a
)
398 fd
.f
= int32_to_float32(fa
.l
, &env
->fp_status
);
402 uint32_t helper_fint(CPUMBState
*env
, uint32_t a
)
408 set_float_exception_flags(0, &env
->fp_status
);
410 r
= float32_to_int32(fa
.f
, &env
->fp_status
);
411 flags
= get_float_exception_flags(&env
->fp_status
);
412 update_fpu_flags(env
, flags
);
417 uint32_t helper_fsqrt(CPUMBState
*env
, uint32_t a
)
422 set_float_exception_flags(0, &env
->fp_status
);
424 fd
.l
= float32_sqrt(fa
.f
, &env
->fp_status
);
425 flags
= get_float_exception_flags(&env
->fp_status
);
426 update_fpu_flags(env
, flags
);
431 uint32_t helper_pcmpbf(uint32_t a
, uint32_t b
)
434 uint32_t mask
= 0xff000000;
436 for (i
= 0; i
< 4; i
++) {
437 if ((a
& mask
) == (b
& mask
))
444 void helper_memalign(CPUMBState
*env
, uint32_t addr
, uint32_t dr
, uint32_t wr
,
448 qemu_log_mask(CPU_LOG_INT
,
449 "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
451 env
->sregs
[SR_EAR
] = addr
;
452 env
->sregs
[SR_ESR
] = ESR_EC_UNALIGNED_DATA
| (wr
<< 10) \
455 env
->sregs
[SR_ESR
] |= 1 << 11;
457 if (!(env
->sregs
[SR_MSR
] & MSR_EE
)) {
460 helper_raise_exception(env
, EXCP_HW_EXCP
);
464 void helper_stackprot(CPUMBState
*env
, uint32_t addr
)
466 if (addr
< env
->slr
|| addr
> env
->shr
) {
467 qemu_log_mask(CPU_LOG_INT
, "Stack protector violation at %x %x %x\n",
468 addr
, env
->slr
, env
->shr
);
469 env
->sregs
[SR_EAR
] = addr
;
470 env
->sregs
[SR_ESR
] = ESR_EC_STACKPROT
;
471 helper_raise_exception(env
, EXCP_HW_EXCP
);
475 #if !defined(CONFIG_USER_ONLY)
476 /* Writes/reads to the MMU's special regs end up here. */
477 uint32_t helper_mmu_read(CPUMBState
*env
, uint32_t rn
)
479 return mmu_read(env
, rn
);
482 void helper_mmu_write(CPUMBState
*env
, uint32_t rn
, uint32_t v
)
484 mmu_write(env
, rn
, v
);
487 void mb_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
488 bool is_write
, bool is_exec
, int is_asi
,
494 qemu_log_mask(CPU_LOG_INT
, "Unassigned " TARGET_FMT_plx
" wr=%d exe=%d\n",
495 addr
, is_write
? 1 : 0, is_exec
? 1 : 0);
499 cpu
= MICROBLAZE_CPU(cs
);
501 if (!(env
->sregs
[SR_MSR
] & MSR_EE
)) {
505 env
->sregs
[SR_EAR
] = addr
;
507 if ((env
->pvr
.regs
[2] & PVR2_IOPB_BUS_EXC_MASK
)) {
508 env
->sregs
[SR_ESR
] = ESR_EC_INSN_BUS
;
509 helper_raise_exception(env
, EXCP_HW_EXCP
);
512 if ((env
->pvr
.regs
[2] & PVR2_DOPB_BUS_EXC_MASK
)) {
513 env
->sregs
[SR_ESR
] = ESR_EC_DATA_BUS
;
514 helper_raise_exception(env
, EXCP_HW_EXCP
);