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target-ppc: Introduce TM Noops
[qemu/ar7.git] / target-ppc / translate.c
blob9c820d1e883b8d5542c8c27b30181d968dd324f0
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define PPC_DEBUG_DISAS
39 //#define DO_PPC_STATISTICS
40
41 #ifdef PPC_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DISAS(...) do { } while (0)
45 #endif
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 + 10*4 + 22*5 /* SPE GPRh */
53 + 10*4 + 22*5 /* FPR */
54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 10*5 + 22*6 /* VSR */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 static TCGv cpu_gprh[32];
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i64 cpu_vsr[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
71 static TCGv cpu_reserve;
72 static TCGv cpu_fpscr;
73 static TCGv_i32 cpu_access_type;
74
75 #include "exec/gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 size_t cpu_reg_names_size;
82 static int done_init = 0;
83
84 if (done_init)
85 return;
86
87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
171
172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, reserve_addr),
174 "reserve_addr");
175
176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
178
179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
180 offsetof(CPUPPCState, access_type), "access_type");
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 bool pr, hv;
193 int mem_idx;
194 int access_type;
195 /* Translation flags */
196 int le_mode;
197 TCGMemOp default_tcg_memop_mask;
198 #if defined(TARGET_PPC64)
199 int sf_mode;
200 int has_cfar;
201 #endif
202 int fpu_enabled;
203 int altivec_enabled;
204 int vsx_enabled;
205 int spe_enabled;
206 int tm_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* Return true iff byteswap is needed in a scalar memop */
214 static inline bool need_byteswap(const DisasContext *ctx)
215 {
216 #if defined(TARGET_WORDS_BIGENDIAN)
217 return ctx->le_mode;
218 #else
219 return !ctx->le_mode;
220 #endif
221 }
222
223 /* True when active word size < size of target_long. */
224 #ifdef TARGET_PPC64
225 # define NARROW_MODE(C) (!(C)->sf_mode)
226 #else
227 # define NARROW_MODE(C) 0
228 #endif
229
230 struct opc_handler_t {
231 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
232 uint32_t inval1;
233 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
234 uint32_t inval2;
235 /* instruction type */
236 uint64_t type;
237 /* extended instruction type */
238 uint64_t type2;
239 /* handler */
240 void (*handler)(DisasContext *ctx);
241 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
242 const char *oname;
243 #endif
244 #if defined(DO_PPC_STATISTICS)
245 uint64_t count;
246 #endif
247 };
248
249 static inline void gen_reset_fpstatus(void)
250 {
251 gen_helper_reset_fpstatus(cpu_env);
252 }
253
254 static inline void gen_compute_fprf(TCGv_i64 arg)
255 {
256 gen_helper_compute_fprf(cpu_env, arg);
257 gen_helper_float_check_status(cpu_env);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 void gen_update_current_nip(void *opaque)
277 {
278 DisasContext *ctx = opaque;
279
280 tcg_gen_movi_tl(cpu_nip, ctx->nip);
281 }
282
283 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
284 {
285 TCGv_i32 t0, t1;
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip);
288 }
289 t0 = tcg_const_i32(excp);
290 t1 = tcg_const_i32(error);
291 gen_helper_raise_exception_err(cpu_env, t0, t1);
292 tcg_temp_free_i32(t0);
293 tcg_temp_free_i32(t1);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
298 {
299 TCGv_i32 t0;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
304 gen_helper_raise_exception(cpu_env, t0);
305 tcg_temp_free_i32(t0);
306 ctx->exception = (excp);
307 }
308
309 static inline void gen_debug_exception(DisasContext *ctx)
310 {
311 TCGv_i32 t0;
312
313 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
314 (ctx->exception != POWERPC_EXCP_SYNC)) {
315 gen_update_nip(ctx, ctx->nip);
316 }
317 t0 = tcg_const_i32(EXCP_DEBUG);
318 gen_helper_raise_exception(cpu_env, t0);
319 tcg_temp_free_i32(t0);
320 }
321
322 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
323 {
324 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
325 }
326
327 /* Stop translation */
328 static inline void gen_stop_exception(DisasContext *ctx)
329 {
330 gen_update_nip(ctx, ctx->nip);
331 ctx->exception = POWERPC_EXCP_STOP;
332 }
333
334 /* No need to update nip here, as execution flow will change */
335 static inline void gen_sync_exception(DisasContext *ctx)
336 {
337 ctx->exception = POWERPC_EXCP_SYNC;
338 }
339
340 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
341 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
342
343 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
344 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
345
346 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
347 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
348
349 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
350 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
351
352 typedef struct opcode_t {
353 unsigned char opc1, opc2, opc3;
354 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
355 unsigned char pad[5];
356 #else
357 unsigned char pad[1];
358 #endif
359 opc_handler_t handler;
360 const char *oname;
361 } opcode_t;
362
363 /*****************************************************************************/
364 /*** Instruction decoding ***/
365 #define EXTRACT_HELPER(name, shift, nb) \
366 static inline uint32_t name(uint32_t opcode) \
367 { \
368 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
369 }
370
371 #define EXTRACT_SHELPER(name, shift, nb) \
372 static inline int32_t name(uint32_t opcode) \
373 { \
374 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
375 }
376
377 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
378 static inline uint32_t name(uint32_t opcode) \
379 { \
380 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
381 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
382 }
383 /* Opcode part 1 */
384 EXTRACT_HELPER(opc1, 26, 6);
385 /* Opcode part 2 */
386 EXTRACT_HELPER(opc2, 1, 5);
387 /* Opcode part 3 */
388 EXTRACT_HELPER(opc3, 6, 5);
389 /* Update Cr0 flags */
390 EXTRACT_HELPER(Rc, 0, 1);
391 /* Update Cr6 flags (Altivec) */
392 EXTRACT_HELPER(Rc21, 10, 1);
393 /* Destination */
394 EXTRACT_HELPER(rD, 21, 5);
395 /* Source */
396 EXTRACT_HELPER(rS, 21, 5);
397 /* First operand */
398 EXTRACT_HELPER(rA, 16, 5);
399 /* Second operand */
400 EXTRACT_HELPER(rB, 11, 5);
401 /* Third operand */
402 EXTRACT_HELPER(rC, 6, 5);
403 /*** Get CRn ***/
404 EXTRACT_HELPER(crfD, 23, 3);
405 EXTRACT_HELPER(crfS, 18, 3);
406 EXTRACT_HELPER(crbD, 21, 5);
407 EXTRACT_HELPER(crbA, 16, 5);
408 EXTRACT_HELPER(crbB, 11, 5);
409 /* SPR / TBL */
410 EXTRACT_HELPER(_SPR, 11, 10);
411 static inline uint32_t SPR(uint32_t opcode)
412 {
413 uint32_t sprn = _SPR(opcode);
414
415 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
416 }
417 /*** Get constants ***/
418 /* 16 bits signed immediate value */
419 EXTRACT_SHELPER(SIMM, 0, 16);
420 /* 16 bits unsigned immediate value */
421 EXTRACT_HELPER(UIMM, 0, 16);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(SIMM5, 16, 5);
424 /* 5 bits signed immediate value */
425 EXTRACT_HELPER(UIMM5, 16, 5);
426 /* Bit count */
427 EXTRACT_HELPER(NB, 11, 5);
428 /* Shift count */
429 EXTRACT_HELPER(SH, 11, 5);
430 /* Vector shift count */
431 EXTRACT_HELPER(VSH, 6, 4);
432 /* Mask start */
433 EXTRACT_HELPER(MB, 6, 5);
434 /* Mask end */
435 EXTRACT_HELPER(ME, 1, 5);
436 /* Trap operand */
437 EXTRACT_HELPER(TO, 21, 5);
438
439 EXTRACT_HELPER(CRM, 12, 8);
440 EXTRACT_HELPER(SR, 16, 4);
441
442 /* mtfsf/mtfsfi */
443 EXTRACT_HELPER(FPBF, 23, 3);
444 EXTRACT_HELPER(FPIMM, 12, 4);
445 EXTRACT_HELPER(FPL, 25, 1);
446 EXTRACT_HELPER(FPFLM, 17, 8);
447 EXTRACT_HELPER(FPW, 16, 1);
448
449 /*** Jump target decoding ***/
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* DFP Z22-form */
469 EXTRACT_HELPER(DCM, 10, 6)
470
471 /* DFP Z23-form */
472 EXTRACT_HELPER(RMC, 9, 2)
473
474 /* Create a mask between <start> and <end> bits */
475 static inline target_ulong MASK(uint32_t start, uint32_t end)
476 {
477 target_ulong ret;
478
479 #if defined(TARGET_PPC64)
480 if (likely(start == 0)) {
481 ret = UINT64_MAX << (63 - end);
482 } else if (likely(end == 63)) {
483 ret = UINT64_MAX >> start;
484 }
485 #else
486 if (likely(start == 0)) {
487 ret = UINT32_MAX << (31 - end);
488 } else if (likely(end == 31)) {
489 ret = UINT32_MAX >> start;
490 }
491 #endif
492 else {
493 ret = (((target_ulong)(-1ULL)) >> (start)) ^
494 (((target_ulong)(-1ULL) >> (end)) >> 1);
495 if (unlikely(start > end))
496 return ~ret;
497 }
498
499 return ret;
500 }
501
502 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
503 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
504 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
505 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
506 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
507 EXTRACT_HELPER(DM, 8, 2);
508 EXTRACT_HELPER(UIM, 16, 2);
509 EXTRACT_HELPER(SHW, 8, 2);
510 EXTRACT_HELPER(SP, 19, 2);
511 /*****************************************************************************/
512 /* PowerPC instructions table */
513
514 #if defined(DO_PPC_STATISTICS)
515 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
516 { \
517 .opc1 = op1, \
518 .opc2 = op2, \
519 .opc3 = op3, \
520 .pad = { 0, }, \
521 .handler = { \
522 .inval1 = invl, \
523 .type = _typ, \
524 .type2 = _typ2, \
525 .handler = &gen_##name, \
526 .oname = stringify(name), \
527 }, \
528 .oname = stringify(name), \
529 }
530 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl1, \
538 .inval2 = invl2, \
539 .type = _typ, \
540 .type2 = _typ2, \
541 .handler = &gen_##name, \
542 .oname = stringify(name), \
543 }, \
544 .oname = stringify(name), \
545 }
546 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
547 { \
548 .opc1 = op1, \
549 .opc2 = op2, \
550 .opc3 = op3, \
551 .pad = { 0, }, \
552 .handler = { \
553 .inval1 = invl, \
554 .type = _typ, \
555 .type2 = _typ2, \
556 .handler = &gen_##name, \
557 .oname = onam, \
558 }, \
559 .oname = onam, \
560 }
561 #else
562 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
563 { \
564 .opc1 = op1, \
565 .opc2 = op2, \
566 .opc3 = op3, \
567 .pad = { 0, }, \
568 .handler = { \
569 .inval1 = invl, \
570 .type = _typ, \
571 .type2 = _typ2, \
572 .handler = &gen_##name, \
573 }, \
574 .oname = stringify(name), \
575 }
576 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
577 { \
578 .opc1 = op1, \
579 .opc2 = op2, \
580 .opc3 = op3, \
581 .pad = { 0, }, \
582 .handler = { \
583 .inval1 = invl1, \
584 .inval2 = invl2, \
585 .type = _typ, \
586 .type2 = _typ2, \
587 .handler = &gen_##name, \
588 }, \
589 .oname = stringify(name), \
590 }
591 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
592 { \
593 .opc1 = op1, \
594 .opc2 = op2, \
595 .opc3 = op3, \
596 .pad = { 0, }, \
597 .handler = { \
598 .inval1 = invl, \
599 .type = _typ, \
600 .type2 = _typ2, \
601 .handler = &gen_##name, \
602 }, \
603 .oname = onam, \
604 }
605 #endif
606
607 /* SPR load/store helpers */
608 static inline void gen_load_spr(TCGv t, int reg)
609 {
610 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
611 }
612
613 static inline void gen_store_spr(int reg, TCGv t)
614 {
615 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
616 }
617
618 /* Invalid instruction */
619 static void gen_invalid(DisasContext *ctx)
620 {
621 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
622 }
623
624 static opc_handler_t invalid_handler = {
625 .inval1 = 0xFFFFFFFF,
626 .inval2 = 0xFFFFFFFF,
627 .type = PPC_NONE,
628 .type2 = PPC_NONE,
629 .handler = gen_invalid,
630 };
631
632 /*** Integer comparison ***/
633
634 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
635 {
636 TCGv t0 = tcg_temp_new();
637 TCGv_i32 t1 = tcg_temp_new_i32();
638
639 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
640
641 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
642 tcg_gen_trunc_tl_i32(t1, t0);
643 tcg_gen_shli_i32(t1, t1, CRF_LT);
644 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
645
646 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
647 tcg_gen_trunc_tl_i32(t1, t0);
648 tcg_gen_shli_i32(t1, t1, CRF_GT);
649 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
650
651 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
652 tcg_gen_trunc_tl_i32(t1, t0);
653 tcg_gen_shli_i32(t1, t1, CRF_EQ);
654 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
655
656 tcg_temp_free(t0);
657 tcg_temp_free_i32(t1);
658 }
659
660 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
661 {
662 TCGv t0 = tcg_const_tl(arg1);
663 gen_op_cmp(arg0, t0, s, crf);
664 tcg_temp_free(t0);
665 }
666
667 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
668 {
669 TCGv t0, t1;
670 t0 = tcg_temp_new();
671 t1 = tcg_temp_new();
672 if (s) {
673 tcg_gen_ext32s_tl(t0, arg0);
674 tcg_gen_ext32s_tl(t1, arg1);
675 } else {
676 tcg_gen_ext32u_tl(t0, arg0);
677 tcg_gen_ext32u_tl(t1, arg1);
678 }
679 gen_op_cmp(t0, t1, s, crf);
680 tcg_temp_free(t1);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
685 {
686 TCGv t0 = tcg_const_tl(arg1);
687 gen_op_cmp32(arg0, t0, s, crf);
688 tcg_temp_free(t0);
689 }
690
691 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
692 {
693 if (NARROW_MODE(ctx)) {
694 gen_op_cmpi32(reg, 0, 1, 0);
695 } else {
696 gen_op_cmpi(reg, 0, 1, 0);
697 }
698 }
699
700 /* cmp */
701 static void gen_cmp(DisasContext *ctx)
702 {
703 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
704 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
705 1, crfD(ctx->opcode));
706 } else {
707 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
708 1, crfD(ctx->opcode));
709 }
710 }
711
712 /* cmpi */
713 static void gen_cmpi(DisasContext *ctx)
714 {
715 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
716 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
717 1, crfD(ctx->opcode));
718 } else {
719 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
720 1, crfD(ctx->opcode));
721 }
722 }
723
724 /* cmpl */
725 static void gen_cmpl(DisasContext *ctx)
726 {
727 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
728 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
729 0, crfD(ctx->opcode));
730 } else {
731 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
732 0, crfD(ctx->opcode));
733 }
734 }
735
736 /* cmpli */
737 static void gen_cmpli(DisasContext *ctx)
738 {
739 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
740 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
741 0, crfD(ctx->opcode));
742 } else {
743 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
744 0, crfD(ctx->opcode));
745 }
746 }
747
748 /* isel (PowerPC 2.03 specification) */
749 static void gen_isel(DisasContext *ctx)
750 {
751 int l1, l2;
752 uint32_t bi = rC(ctx->opcode);
753 uint32_t mask;
754 TCGv_i32 t0;
755
756 l1 = gen_new_label();
757 l2 = gen_new_label();
758
759 mask = 0x08 >> (bi & 0x03);
760 t0 = tcg_temp_new_i32();
761 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
762 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
763 if (rA(ctx->opcode) == 0)
764 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
765 else
766 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
767 tcg_gen_br(l2);
768 gen_set_label(l1);
769 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
770 gen_set_label(l2);
771 tcg_temp_free_i32(t0);
772 }
773
774 /* cmpb: PowerPC 2.05 specification */
775 static void gen_cmpb(DisasContext *ctx)
776 {
777 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
778 cpu_gpr[rB(ctx->opcode)]);
779 }
780
781 /*** Integer arithmetic ***/
782
783 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
784 TCGv arg1, TCGv arg2, int sub)
785 {
786 TCGv t0 = tcg_temp_new();
787
788 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
789 tcg_gen_xor_tl(t0, arg1, arg2);
790 if (sub) {
791 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
792 } else {
793 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
794 }
795 tcg_temp_free(t0);
796 if (NARROW_MODE(ctx)) {
797 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
798 }
799 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
800 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
801 }
802
803 /* Common add function */
804 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
805 TCGv arg2, bool add_ca, bool compute_ca,
806 bool compute_ov, bool compute_rc0)
807 {
808 TCGv t0 = ret;
809
810 if (compute_ca || compute_ov) {
811 t0 = tcg_temp_new();
812 }
813
814 if (compute_ca) {
815 if (NARROW_MODE(ctx)) {
816 /* Caution: a non-obvious corner case of the spec is that we
817 must produce the *entire* 64-bit addition, but produce the
818 carry into bit 32. */
819 TCGv t1 = tcg_temp_new();
820 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
821 tcg_gen_add_tl(t0, arg1, arg2);
822 if (add_ca) {
823 tcg_gen_add_tl(t0, t0, cpu_ca);
824 }
825 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
826 tcg_temp_free(t1);
827 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
828 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
829 } else {
830 TCGv zero = tcg_const_tl(0);
831 if (add_ca) {
832 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
833 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
834 } else {
835 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
836 }
837 tcg_temp_free(zero);
838 }
839 } else {
840 tcg_gen_add_tl(t0, arg1, arg2);
841 if (add_ca) {
842 tcg_gen_add_tl(t0, t0, cpu_ca);
843 }
844 }
845
846 if (compute_ov) {
847 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
848 }
849 if (unlikely(compute_rc0)) {
850 gen_set_Rc0(ctx, t0);
851 }
852
853 if (!TCGV_EQUAL(t0, ret)) {
854 tcg_gen_mov_tl(ret, t0);
855 tcg_temp_free(t0);
856 }
857 }
858 /* Add functions with two operands */
859 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
860 static void glue(gen_, name)(DisasContext *ctx) \
861 { \
862 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
863 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
864 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
865 }
866 /* Add functions with one operand and one immediate */
867 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
868 add_ca, compute_ca, compute_ov) \
869 static void glue(gen_, name)(DisasContext *ctx) \
870 { \
871 TCGv t0 = tcg_const_tl(const_val); \
872 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
873 cpu_gpr[rA(ctx->opcode)], t0, \
874 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
875 tcg_temp_free(t0); \
876 }
877
878 /* add add. addo addo. */
879 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
880 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
881 /* addc addc. addco addco. */
882 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
883 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
884 /* adde adde. addeo addeo. */
885 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
886 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
887 /* addme addme. addmeo addmeo. */
888 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
889 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
890 /* addze addze. addzeo addzeo.*/
891 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
892 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
893 /* addi */
894 static void gen_addi(DisasContext *ctx)
895 {
896 target_long simm = SIMM(ctx->opcode);
897
898 if (rA(ctx->opcode) == 0) {
899 /* li case */
900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
901 } else {
902 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
903 cpu_gpr[rA(ctx->opcode)], simm);
904 }
905 }
906 /* addic addic.*/
907 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
908 {
909 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
910 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
911 c, 0, 1, 0, compute_rc0);
912 tcg_temp_free(c);
913 }
914
915 static void gen_addic(DisasContext *ctx)
916 {
917 gen_op_addic(ctx, 0);
918 }
919
920 static void gen_addic_(DisasContext *ctx)
921 {
922 gen_op_addic(ctx, 1);
923 }
924
925 /* addis */
926 static void gen_addis(DisasContext *ctx)
927 {
928 target_long simm = SIMM(ctx->opcode);
929
930 if (rA(ctx->opcode) == 0) {
931 /* lis case */
932 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
933 } else {
934 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
935 cpu_gpr[rA(ctx->opcode)], simm << 16);
936 }
937 }
938
939 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
940 TCGv arg2, int sign, int compute_ov)
941 {
942 int l1 = gen_new_label();
943 int l2 = gen_new_label();
944 TCGv_i32 t0 = tcg_temp_local_new_i32();
945 TCGv_i32 t1 = tcg_temp_local_new_i32();
946
947 tcg_gen_trunc_tl_i32(t0, arg1);
948 tcg_gen_trunc_tl_i32(t1, arg2);
949 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
950 if (sign) {
951 int l3 = gen_new_label();
952 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
953 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
954 gen_set_label(l3);
955 tcg_gen_div_i32(t0, t0, t1);
956 } else {
957 tcg_gen_divu_i32(t0, t0, t1);
958 }
959 if (compute_ov) {
960 tcg_gen_movi_tl(cpu_ov, 0);
961 }
962 tcg_gen_br(l2);
963 gen_set_label(l1);
964 if (sign) {
965 tcg_gen_sari_i32(t0, t0, 31);
966 } else {
967 tcg_gen_movi_i32(t0, 0);
968 }
969 if (compute_ov) {
970 tcg_gen_movi_tl(cpu_ov, 1);
971 tcg_gen_movi_tl(cpu_so, 1);
972 }
973 gen_set_label(l2);
974 tcg_gen_extu_i32_tl(ret, t0);
975 tcg_temp_free_i32(t0);
976 tcg_temp_free_i32(t1);
977 if (unlikely(Rc(ctx->opcode) != 0))
978 gen_set_Rc0(ctx, ret);
979 }
980 /* Div functions */
981 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
982 static void glue(gen_, name)(DisasContext *ctx) \
983 { \
984 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
985 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
986 sign, compute_ov); \
987 }
988 /* divwu divwu. divwuo divwuo. */
989 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
990 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
991 /* divw divw. divwo divwo. */
992 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
993 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
994
995 /* div[wd]eu[o][.] */
996 #define GEN_DIVE(name, hlpr, compute_ov) \
997 static void gen_##name(DisasContext *ctx) \
998 { \
999 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1000 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1002 tcg_temp_free_i32(t0); \
1003 if (unlikely(Rc(ctx->opcode) != 0)) { \
1004 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1005 } \
1006 }
1007
1008 GEN_DIVE(divweu, divweu, 0);
1009 GEN_DIVE(divweuo, divweu, 1);
1010 GEN_DIVE(divwe, divwe, 0);
1011 GEN_DIVE(divweo, divwe, 1);
1012
1013 #if defined(TARGET_PPC64)
1014 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1015 TCGv arg2, int sign, int compute_ov)
1016 {
1017 int l1 = gen_new_label();
1018 int l2 = gen_new_label();
1019
1020 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1021 if (sign) {
1022 int l3 = gen_new_label();
1023 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1024 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1025 gen_set_label(l3);
1026 tcg_gen_div_i64(ret, arg1, arg2);
1027 } else {
1028 tcg_gen_divu_i64(ret, arg1, arg2);
1029 }
1030 if (compute_ov) {
1031 tcg_gen_movi_tl(cpu_ov, 0);
1032 }
1033 tcg_gen_br(l2);
1034 gen_set_label(l1);
1035 if (sign) {
1036 tcg_gen_sari_i64(ret, arg1, 63);
1037 } else {
1038 tcg_gen_movi_i64(ret, 0);
1039 }
1040 if (compute_ov) {
1041 tcg_gen_movi_tl(cpu_ov, 1);
1042 tcg_gen_movi_tl(cpu_so, 1);
1043 }
1044 gen_set_label(l2);
1045 if (unlikely(Rc(ctx->opcode) != 0))
1046 gen_set_Rc0(ctx, ret);
1047 }
1048 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1049 static void glue(gen_, name)(DisasContext *ctx) \
1050 { \
1051 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1052 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1053 sign, compute_ov); \
1054 }
1055 /* divwu divwu. divwuo divwuo. */
1056 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1057 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1058 /* divw divw. divwo divwo. */
1059 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1060 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1061
1062 GEN_DIVE(divdeu, divdeu, 0);
1063 GEN_DIVE(divdeuo, divdeu, 1);
1064 GEN_DIVE(divde, divde, 0);
1065 GEN_DIVE(divdeo, divde, 1);
1066 #endif
1067
1068 /* mulhw mulhw. */
1069 static void gen_mulhw(DisasContext *ctx)
1070 {
1071 TCGv_i32 t0 = tcg_temp_new_i32();
1072 TCGv_i32 t1 = tcg_temp_new_i32();
1073
1074 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1075 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1076 tcg_gen_muls2_i32(t0, t1, t0, t1);
1077 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1078 tcg_temp_free_i32(t0);
1079 tcg_temp_free_i32(t1);
1080 if (unlikely(Rc(ctx->opcode) != 0))
1081 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1082 }
1083
1084 /* mulhwu mulhwu. */
1085 static void gen_mulhwu(DisasContext *ctx)
1086 {
1087 TCGv_i32 t0 = tcg_temp_new_i32();
1088 TCGv_i32 t1 = tcg_temp_new_i32();
1089
1090 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1091 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1092 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1093 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1094 tcg_temp_free_i32(t0);
1095 tcg_temp_free_i32(t1);
1096 if (unlikely(Rc(ctx->opcode) != 0))
1097 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1098 }
1099
1100 /* mullw mullw. */
1101 static void gen_mullw(DisasContext *ctx)
1102 {
1103 #if defined(TARGET_PPC64)
1104 TCGv_i64 t0, t1;
1105 t0 = tcg_temp_new_i64();
1106 t1 = tcg_temp_new_i64();
1107 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1108 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1109 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1110 tcg_temp_free(t0);
1111 tcg_temp_free(t1);
1112 #else
1113 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1114 cpu_gpr[rB(ctx->opcode)]);
1115 #endif
1116 if (unlikely(Rc(ctx->opcode) != 0))
1117 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1118 }
1119
1120 /* mullwo mullwo. */
1121 static void gen_mullwo(DisasContext *ctx)
1122 {
1123 TCGv_i32 t0 = tcg_temp_new_i32();
1124 TCGv_i32 t1 = tcg_temp_new_i32();
1125
1126 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1127 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1128 tcg_gen_muls2_i32(t0, t1, t0, t1);
1129 #if defined(TARGET_PPC64)
1130 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1131 #else
1132 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1133 #endif
1134
1135 tcg_gen_sari_i32(t0, t0, 31);
1136 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1137 tcg_gen_extu_i32_tl(cpu_ov, t0);
1138 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1139
1140 tcg_temp_free_i32(t0);
1141 tcg_temp_free_i32(t1);
1142 if (unlikely(Rc(ctx->opcode) != 0))
1143 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1144 }
1145
1146 /* mulli */
1147 static void gen_mulli(DisasContext *ctx)
1148 {
1149 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1150 SIMM(ctx->opcode));
1151 }
1152
1153 #if defined(TARGET_PPC64)
1154 /* mulhd mulhd. */
1155 static void gen_mulhd(DisasContext *ctx)
1156 {
1157 TCGv lo = tcg_temp_new();
1158 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1160 tcg_temp_free(lo);
1161 if (unlikely(Rc(ctx->opcode) != 0)) {
1162 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1163 }
1164 }
1165
1166 /* mulhdu mulhdu. */
1167 static void gen_mulhdu(DisasContext *ctx)
1168 {
1169 TCGv lo = tcg_temp_new();
1170 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1171 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1172 tcg_temp_free(lo);
1173 if (unlikely(Rc(ctx->opcode) != 0)) {
1174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1175 }
1176 }
1177
1178 /* mulld mulld. */
1179 static void gen_mulld(DisasContext *ctx)
1180 {
1181 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1182 cpu_gpr[rB(ctx->opcode)]);
1183 if (unlikely(Rc(ctx->opcode) != 0))
1184 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1185 }
1186
1187 /* mulldo mulldo. */
1188 static void gen_mulldo(DisasContext *ctx)
1189 {
1190 TCGv_i64 t0 = tcg_temp_new_i64();
1191 TCGv_i64 t1 = tcg_temp_new_i64();
1192
1193 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1194 cpu_gpr[rB(ctx->opcode)]);
1195 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1196
1197 tcg_gen_sari_i64(t0, t0, 63);
1198 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1199 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1200
1201 tcg_temp_free_i64(t0);
1202 tcg_temp_free_i64(t1);
1203
1204 if (unlikely(Rc(ctx->opcode) != 0)) {
1205 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1206 }
1207 }
1208 #endif
1209
1210 /* Common subf function */
1211 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1212 TCGv arg2, bool add_ca, bool compute_ca,
1213 bool compute_ov, bool compute_rc0)
1214 {
1215 TCGv t0 = ret;
1216
1217 if (compute_ca || compute_ov) {
1218 t0 = tcg_temp_new();
1219 }
1220
1221 if (compute_ca) {
1222 /* dest = ~arg1 + arg2 [+ ca]. */
1223 if (NARROW_MODE(ctx)) {
1224 /* Caution: a non-obvious corner case of the spec is that we
1225 must produce the *entire* 64-bit addition, but produce the
1226 carry into bit 32. */
1227 TCGv inv1 = tcg_temp_new();
1228 TCGv t1 = tcg_temp_new();
1229 tcg_gen_not_tl(inv1, arg1);
1230 if (add_ca) {
1231 tcg_gen_add_tl(t0, arg2, cpu_ca);
1232 } else {
1233 tcg_gen_addi_tl(t0, arg2, 1);
1234 }
1235 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1236 tcg_gen_add_tl(t0, t0, inv1);
1237 tcg_temp_free(inv1);
1238 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1239 tcg_temp_free(t1);
1240 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1241 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1242 } else if (add_ca) {
1243 TCGv zero, inv1 = tcg_temp_new();
1244 tcg_gen_not_tl(inv1, arg1);
1245 zero = tcg_const_tl(0);
1246 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1247 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1248 tcg_temp_free(zero);
1249 tcg_temp_free(inv1);
1250 } else {
1251 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1252 tcg_gen_sub_tl(t0, arg2, arg1);
1253 }
1254 } else if (add_ca) {
1255 /* Since we're ignoring carry-out, we can simplify the
1256 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1257 tcg_gen_sub_tl(t0, arg2, arg1);
1258 tcg_gen_add_tl(t0, t0, cpu_ca);
1259 tcg_gen_subi_tl(t0, t0, 1);
1260 } else {
1261 tcg_gen_sub_tl(t0, arg2, arg1);
1262 }
1263
1264 if (compute_ov) {
1265 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1266 }
1267 if (unlikely(compute_rc0)) {
1268 gen_set_Rc0(ctx, t0);
1269 }
1270
1271 if (!TCGV_EQUAL(t0, ret)) {
1272 tcg_gen_mov_tl(ret, t0);
1273 tcg_temp_free(t0);
1274 }
1275 }
1276 /* Sub functions with Two operands functions */
1277 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1278 static void glue(gen_, name)(DisasContext *ctx) \
1279 { \
1280 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1281 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1282 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1283 }
1284 /* Sub functions with one operand and one immediate */
1285 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1286 add_ca, compute_ca, compute_ov) \
1287 static void glue(gen_, name)(DisasContext *ctx) \
1288 { \
1289 TCGv t0 = tcg_const_tl(const_val); \
1290 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1291 cpu_gpr[rA(ctx->opcode)], t0, \
1292 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1293 tcg_temp_free(t0); \
1294 }
1295 /* subf subf. subfo subfo. */
1296 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1297 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1298 /* subfc subfc. subfco subfco. */
1299 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1300 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1301 /* subfe subfe. subfeo subfo. */
1302 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1303 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1304 /* subfme subfme. subfmeo subfmeo. */
1305 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1306 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1307 /* subfze subfze. subfzeo subfzeo.*/
1308 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1309 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1310
1311 /* subfic */
1312 static void gen_subfic(DisasContext *ctx)
1313 {
1314 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1315 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1316 c, 0, 1, 0, 0);
1317 tcg_temp_free(c);
1318 }
1319
1320 /* neg neg. nego nego. */
1321 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1322 {
1323 TCGv zero = tcg_const_tl(0);
1324 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1325 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1326 tcg_temp_free(zero);
1327 }
1328
1329 static void gen_neg(DisasContext *ctx)
1330 {
1331 gen_op_arith_neg(ctx, 0);
1332 }
1333
1334 static void gen_nego(DisasContext *ctx)
1335 {
1336 gen_op_arith_neg(ctx, 1);
1337 }
1338
1339 /*** Integer logical ***/
1340 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1341 static void glue(gen_, name)(DisasContext *ctx) \
1342 { \
1343 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1344 cpu_gpr[rB(ctx->opcode)]); \
1345 if (unlikely(Rc(ctx->opcode) != 0)) \
1346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1347 }
1348
1349 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1350 static void glue(gen_, name)(DisasContext *ctx) \
1351 { \
1352 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1353 if (unlikely(Rc(ctx->opcode) != 0)) \
1354 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1355 }
1356
1357 /* and & and. */
1358 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1359 /* andc & andc. */
1360 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1361
1362 /* andi. */
1363 static void gen_andi_(DisasContext *ctx)
1364 {
1365 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1367 }
1368
1369 /* andis. */
1370 static void gen_andis_(DisasContext *ctx)
1371 {
1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1374 }
1375
1376 /* cntlzw */
1377 static void gen_cntlzw(DisasContext *ctx)
1378 {
1379 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1382 }
1383 /* eqv & eqv. */
1384 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1385 /* extsb & extsb. */
1386 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1387 /* extsh & extsh. */
1388 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1389 /* nand & nand. */
1390 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1391 /* nor & nor. */
1392 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1393
1394 /* or & or. */
1395 static void gen_or(DisasContext *ctx)
1396 {
1397 int rs, ra, rb;
1398
1399 rs = rS(ctx->opcode);
1400 ra = rA(ctx->opcode);
1401 rb = rB(ctx->opcode);
1402 /* Optimisation for mr. ri case */
1403 if (rs != ra || rs != rb) {
1404 if (rs != rb)
1405 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1406 else
1407 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1408 if (unlikely(Rc(ctx->opcode) != 0))
1409 gen_set_Rc0(ctx, cpu_gpr[ra]);
1410 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1411 gen_set_Rc0(ctx, cpu_gpr[rs]);
1412 #if defined(TARGET_PPC64)
1413 } else {
1414 int prio = 0;
1415
1416 switch (rs) {
1417 case 1:
1418 /* Set process priority to low */
1419 prio = 2;
1420 break;
1421 case 6:
1422 /* Set process priority to medium-low */
1423 prio = 3;
1424 break;
1425 case 2:
1426 /* Set process priority to normal */
1427 prio = 4;
1428 break;
1429 #if !defined(CONFIG_USER_ONLY)
1430 case 31:
1431 if (!ctx->pr) {
1432 /* Set process priority to very low */
1433 prio = 1;
1434 }
1435 break;
1436 case 5:
1437 if (!ctx->pr) {
1438 /* Set process priority to medium-hight */
1439 prio = 5;
1440 }
1441 break;
1442 case 3:
1443 if (!ctx->pr) {
1444 /* Set process priority to high */
1445 prio = 6;
1446 }
1447 break;
1448 case 7:
1449 if (ctx->hv) {
1450 /* Set process priority to very high */
1451 prio = 7;
1452 }
1453 break;
1454 #endif
1455 default:
1456 /* nop */
1457 break;
1458 }
1459 if (prio) {
1460 TCGv t0 = tcg_temp_new();
1461 gen_load_spr(t0, SPR_PPR);
1462 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1463 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1464 gen_store_spr(SPR_PPR, t0);
1465 tcg_temp_free(t0);
1466 }
1467 #endif
1468 }
1469 }
1470 /* orc & orc. */
1471 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1472
1473 /* xor & xor. */
1474 static void gen_xor(DisasContext *ctx)
1475 {
1476 /* Optimisation for "set to zero" case */
1477 if (rS(ctx->opcode) != rB(ctx->opcode))
1478 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1479 else
1480 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1481 if (unlikely(Rc(ctx->opcode) != 0))
1482 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1483 }
1484
1485 /* ori */
1486 static void gen_ori(DisasContext *ctx)
1487 {
1488 target_ulong uimm = UIMM(ctx->opcode);
1489
1490 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1491 /* NOP */
1492 /* XXX: should handle special NOPs for POWER series */
1493 return;
1494 }
1495 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1496 }
1497
1498 /* oris */
1499 static void gen_oris(DisasContext *ctx)
1500 {
1501 target_ulong uimm = UIMM(ctx->opcode);
1502
1503 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1504 /* NOP */
1505 return;
1506 }
1507 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1508 }
1509
1510 /* xori */
1511 static void gen_xori(DisasContext *ctx)
1512 {
1513 target_ulong uimm = UIMM(ctx->opcode);
1514
1515 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1516 /* NOP */
1517 return;
1518 }
1519 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1520 }
1521
1522 /* xoris */
1523 static void gen_xoris(DisasContext *ctx)
1524 {
1525 target_ulong uimm = UIMM(ctx->opcode);
1526
1527 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1528 /* NOP */
1529 return;
1530 }
1531 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1532 }
1533
1534 /* popcntb : PowerPC 2.03 specification */
1535 static void gen_popcntb(DisasContext *ctx)
1536 {
1537 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1538 }
1539
1540 static void gen_popcntw(DisasContext *ctx)
1541 {
1542 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1543 }
1544
1545 #if defined(TARGET_PPC64)
1546 /* popcntd: PowerPC 2.06 specification */
1547 static void gen_popcntd(DisasContext *ctx)
1548 {
1549 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550 }
1551 #endif
1552
1553 /* prtyw: PowerPC 2.05 specification */
1554 static void gen_prtyw(DisasContext *ctx)
1555 {
1556 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1557 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1558 TCGv t0 = tcg_temp_new();
1559 tcg_gen_shri_tl(t0, rs, 16);
1560 tcg_gen_xor_tl(ra, rs, t0);
1561 tcg_gen_shri_tl(t0, ra, 8);
1562 tcg_gen_xor_tl(ra, ra, t0);
1563 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1564 tcg_temp_free(t0);
1565 }
1566
1567 #if defined(TARGET_PPC64)
1568 /* prtyd: PowerPC 2.05 specification */
1569 static void gen_prtyd(DisasContext *ctx)
1570 {
1571 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1572 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1573 TCGv t0 = tcg_temp_new();
1574 tcg_gen_shri_tl(t0, rs, 32);
1575 tcg_gen_xor_tl(ra, rs, t0);
1576 tcg_gen_shri_tl(t0, ra, 16);
1577 tcg_gen_xor_tl(ra, ra, t0);
1578 tcg_gen_shri_tl(t0, ra, 8);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_andi_tl(ra, ra, 1);
1581 tcg_temp_free(t0);
1582 }
1583 #endif
1584
1585 #if defined(TARGET_PPC64)
1586 /* bpermd */
1587 static void gen_bpermd(DisasContext *ctx)
1588 {
1589 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1590 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1591 }
1592 #endif
1593
1594 #if defined(TARGET_PPC64)
1595 /* extsw & extsw. */
1596 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1597
1598 /* cntlzd */
1599 static void gen_cntlzd(DisasContext *ctx)
1600 {
1601 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1602 if (unlikely(Rc(ctx->opcode) != 0))
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1604 }
1605 #endif
1606
1607 /*** Integer rotate ***/
1608
1609 /* rlwimi & rlwimi. */
1610 static void gen_rlwimi(DisasContext *ctx)
1611 {
1612 uint32_t mb, me, sh;
1613
1614 mb = MB(ctx->opcode);
1615 me = ME(ctx->opcode);
1616 sh = SH(ctx->opcode);
1617 if (likely(sh == (31-me) && mb <= me)) {
1618 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1619 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1620 } else {
1621 target_ulong mask;
1622 TCGv t1;
1623 TCGv t0 = tcg_temp_new();
1624 #if defined(TARGET_PPC64)
1625 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1626 cpu_gpr[rS(ctx->opcode)], 32, 32);
1627 tcg_gen_rotli_i64(t0, t0, sh);
1628 #else
1629 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1630 #endif
1631 #if defined(TARGET_PPC64)
1632 mb += 32;
1633 me += 32;
1634 #endif
1635 mask = MASK(mb, me);
1636 t1 = tcg_temp_new();
1637 tcg_gen_andi_tl(t0, t0, mask);
1638 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1639 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1640 tcg_temp_free(t0);
1641 tcg_temp_free(t1);
1642 }
1643 if (unlikely(Rc(ctx->opcode) != 0))
1644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1645 }
1646
1647 /* rlwinm & rlwinm. */
1648 static void gen_rlwinm(DisasContext *ctx)
1649 {
1650 uint32_t mb, me, sh;
1651
1652 sh = SH(ctx->opcode);
1653 mb = MB(ctx->opcode);
1654 me = ME(ctx->opcode);
1655
1656 if (likely(mb == 0 && me == (31 - sh))) {
1657 if (likely(sh == 0)) {
1658 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1659 } else {
1660 TCGv t0 = tcg_temp_new();
1661 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_shli_tl(t0, t0, sh);
1663 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1664 tcg_temp_free(t0);
1665 }
1666 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1667 TCGv t0 = tcg_temp_new();
1668 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669 tcg_gen_shri_tl(t0, t0, mb);
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 tcg_temp_free(t0);
1672 } else if (likely(mb == 0 && me == 31)) {
1673 TCGv_i32 t0 = tcg_temp_new_i32();
1674 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1675 tcg_gen_rotli_i32(t0, t0, sh);
1676 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1677 tcg_temp_free_i32(t0);
1678 } else {
1679 TCGv t0 = tcg_temp_new();
1680 #if defined(TARGET_PPC64)
1681 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1682 cpu_gpr[rS(ctx->opcode)], 32, 32);
1683 tcg_gen_rotli_i64(t0, t0, sh);
1684 #else
1685 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1686 #endif
1687 #if defined(TARGET_PPC64)
1688 mb += 32;
1689 me += 32;
1690 #endif
1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 tcg_temp_free(t0);
1693 }
1694 if (unlikely(Rc(ctx->opcode) != 0))
1695 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1696 }
1697
1698 /* rlwnm & rlwnm. */
1699 static void gen_rlwnm(DisasContext *ctx)
1700 {
1701 uint32_t mb, me;
1702 mb = MB(ctx->opcode);
1703 me = ME(ctx->opcode);
1704
1705 if (likely(mb == 0 && me == 31)) {
1706 TCGv_i32 t0, t1;
1707 t0 = tcg_temp_new_i32();
1708 t1 = tcg_temp_new_i32();
1709 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1710 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1711 tcg_gen_andi_i32(t0, t0, 0x1f);
1712 tcg_gen_rotl_i32(t1, t1, t0);
1713 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1714 tcg_temp_free_i32(t0);
1715 tcg_temp_free_i32(t1);
1716 } else {
1717 TCGv t0;
1718 #if defined(TARGET_PPC64)
1719 TCGv t1;
1720 #endif
1721
1722 t0 = tcg_temp_new();
1723 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1724 #if defined(TARGET_PPC64)
1725 t1 = tcg_temp_new_i64();
1726 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1727 cpu_gpr[rS(ctx->opcode)], 32, 32);
1728 tcg_gen_rotl_i64(t0, t1, t0);
1729 tcg_temp_free_i64(t1);
1730 #else
1731 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1732 #endif
1733 if (unlikely(mb != 0 || me != 31)) {
1734 #if defined(TARGET_PPC64)
1735 mb += 32;
1736 me += 32;
1737 #endif
1738 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1739 } else {
1740 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1742 }
1743 tcg_temp_free(t0);
1744 }
1745 if (unlikely(Rc(ctx->opcode) != 0))
1746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1747 }
1748
1749 #if defined(TARGET_PPC64)
1750 #define GEN_PPC64_R2(name, opc1, opc2) \
1751 static void glue(gen_, name##0)(DisasContext *ctx) \
1752 { \
1753 gen_##name(ctx, 0); \
1754 } \
1755 \
1756 static void glue(gen_, name##1)(DisasContext *ctx) \
1757 { \
1758 gen_##name(ctx, 1); \
1759 }
1760 #define GEN_PPC64_R4(name, opc1, opc2) \
1761 static void glue(gen_, name##0)(DisasContext *ctx) \
1762 { \
1763 gen_##name(ctx, 0, 0); \
1764 } \
1765 \
1766 static void glue(gen_, name##1)(DisasContext *ctx) \
1767 { \
1768 gen_##name(ctx, 0, 1); \
1769 } \
1770 \
1771 static void glue(gen_, name##2)(DisasContext *ctx) \
1772 { \
1773 gen_##name(ctx, 1, 0); \
1774 } \
1775 \
1776 static void glue(gen_, name##3)(DisasContext *ctx) \
1777 { \
1778 gen_##name(ctx, 1, 1); \
1779 }
1780
1781 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1782 uint32_t sh)
1783 {
1784 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1785 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1786 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1787 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1788 } else {
1789 TCGv t0 = tcg_temp_new();
1790 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1791 if (likely(mb == 0 && me == 63)) {
1792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1793 } else {
1794 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1795 }
1796 tcg_temp_free(t0);
1797 }
1798 if (unlikely(Rc(ctx->opcode) != 0))
1799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1800 }
1801 /* rldicl - rldicl. */
1802 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1803 {
1804 uint32_t sh, mb;
1805
1806 sh = SH(ctx->opcode) | (shn << 5);
1807 mb = MB(ctx->opcode) | (mbn << 5);
1808 gen_rldinm(ctx, mb, 63, sh);
1809 }
1810 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1811 /* rldicr - rldicr. */
1812 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1813 {
1814 uint32_t sh, me;
1815
1816 sh = SH(ctx->opcode) | (shn << 5);
1817 me = MB(ctx->opcode) | (men << 5);
1818 gen_rldinm(ctx, 0, me, sh);
1819 }
1820 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1821 /* rldic - rldic. */
1822 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1823 {
1824 uint32_t sh, mb;
1825
1826 sh = SH(ctx->opcode) | (shn << 5);
1827 mb = MB(ctx->opcode) | (mbn << 5);
1828 gen_rldinm(ctx, mb, 63 - sh, sh);
1829 }
1830 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1831
1832 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1833 {
1834 TCGv t0;
1835
1836 t0 = tcg_temp_new();
1837 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1838 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1839 if (unlikely(mb != 0 || me != 63)) {
1840 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1841 } else {
1842 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1843 }
1844 tcg_temp_free(t0);
1845 if (unlikely(Rc(ctx->opcode) != 0))
1846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1847 }
1848
1849 /* rldcl - rldcl. */
1850 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1851 {
1852 uint32_t mb;
1853
1854 mb = MB(ctx->opcode) | (mbn << 5);
1855 gen_rldnm(ctx, mb, 63);
1856 }
1857 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1858 /* rldcr - rldcr. */
1859 static inline void gen_rldcr(DisasContext *ctx, int men)
1860 {
1861 uint32_t me;
1862
1863 me = MB(ctx->opcode) | (men << 5);
1864 gen_rldnm(ctx, 0, me);
1865 }
1866 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1867 /* rldimi - rldimi. */
1868 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1869 {
1870 uint32_t sh, mb, me;
1871
1872 sh = SH(ctx->opcode) | (shn << 5);
1873 mb = MB(ctx->opcode) | (mbn << 5);
1874 me = 63 - sh;
1875 if (unlikely(sh == 0 && mb == 0)) {
1876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1877 } else {
1878 TCGv t0, t1;
1879 target_ulong mask;
1880
1881 t0 = tcg_temp_new();
1882 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1883 t1 = tcg_temp_new();
1884 mask = MASK(mb, me);
1885 tcg_gen_andi_tl(t0, t0, mask);
1886 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1887 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1888 tcg_temp_free(t0);
1889 tcg_temp_free(t1);
1890 }
1891 if (unlikely(Rc(ctx->opcode) != 0))
1892 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1893 }
1894 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1895 #endif
1896
1897 /*** Integer shift ***/
1898
1899 /* slw & slw. */
1900 static void gen_slw(DisasContext *ctx)
1901 {
1902 TCGv t0, t1;
1903
1904 t0 = tcg_temp_new();
1905 /* AND rS with a mask that is 0 when rB >= 0x20 */
1906 #if defined(TARGET_PPC64)
1907 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1908 tcg_gen_sari_tl(t0, t0, 0x3f);
1909 #else
1910 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1911 tcg_gen_sari_tl(t0, t0, 0x1f);
1912 #endif
1913 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1914 t1 = tcg_temp_new();
1915 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1916 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1917 tcg_temp_free(t1);
1918 tcg_temp_free(t0);
1919 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1920 if (unlikely(Rc(ctx->opcode) != 0))
1921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1922 }
1923
1924 /* sraw & sraw. */
1925 static void gen_sraw(DisasContext *ctx)
1926 {
1927 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1928 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1929 if (unlikely(Rc(ctx->opcode) != 0))
1930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1931 }
1932
1933 /* srawi & srawi. */
1934 static void gen_srawi(DisasContext *ctx)
1935 {
1936 int sh = SH(ctx->opcode);
1937 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1938 TCGv src = cpu_gpr[rS(ctx->opcode)];
1939 if (sh == 0) {
1940 tcg_gen_ext32s_tl(dst, src);
1941 tcg_gen_movi_tl(cpu_ca, 0);
1942 } else {
1943 TCGv t0;
1944 tcg_gen_ext32s_tl(dst, src);
1945 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1946 t0 = tcg_temp_new();
1947 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1948 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1949 tcg_temp_free(t0);
1950 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1951 tcg_gen_sari_tl(dst, dst, sh);
1952 }
1953 if (unlikely(Rc(ctx->opcode) != 0)) {
1954 gen_set_Rc0(ctx, dst);
1955 }
1956 }
1957
1958 /* srw & srw. */
1959 static void gen_srw(DisasContext *ctx)
1960 {
1961 TCGv t0, t1;
1962
1963 t0 = tcg_temp_new();
1964 /* AND rS with a mask that is 0 when rB >= 0x20 */
1965 #if defined(TARGET_PPC64)
1966 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1967 tcg_gen_sari_tl(t0, t0, 0x3f);
1968 #else
1969 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1970 tcg_gen_sari_tl(t0, t0, 0x1f);
1971 #endif
1972 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1973 tcg_gen_ext32u_tl(t0, t0);
1974 t1 = tcg_temp_new();
1975 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1976 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1977 tcg_temp_free(t1);
1978 tcg_temp_free(t0);
1979 if (unlikely(Rc(ctx->opcode) != 0))
1980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1981 }
1982
1983 #if defined(TARGET_PPC64)
1984 /* sld & sld. */
1985 static void gen_sld(DisasContext *ctx)
1986 {
1987 TCGv t0, t1;
1988
1989 t0 = tcg_temp_new();
1990 /* AND rS with a mask that is 0 when rB >= 0x40 */
1991 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1992 tcg_gen_sari_tl(t0, t0, 0x3f);
1993 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1994 t1 = tcg_temp_new();
1995 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1996 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1997 tcg_temp_free(t1);
1998 tcg_temp_free(t0);
1999 if (unlikely(Rc(ctx->opcode) != 0))
2000 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2001 }
2002
2003 /* srad & srad. */
2004 static void gen_srad(DisasContext *ctx)
2005 {
2006 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2007 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2008 if (unlikely(Rc(ctx->opcode) != 0))
2009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2010 }
2011 /* sradi & sradi. */
2012 static inline void gen_sradi(DisasContext *ctx, int n)
2013 {
2014 int sh = SH(ctx->opcode) + (n << 5);
2015 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2016 TCGv src = cpu_gpr[rS(ctx->opcode)];
2017 if (sh == 0) {
2018 tcg_gen_mov_tl(dst, src);
2019 tcg_gen_movi_tl(cpu_ca, 0);
2020 } else {
2021 TCGv t0;
2022 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2023 t0 = tcg_temp_new();
2024 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2025 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2026 tcg_temp_free(t0);
2027 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2028 tcg_gen_sari_tl(dst, src, sh);
2029 }
2030 if (unlikely(Rc(ctx->opcode) != 0)) {
2031 gen_set_Rc0(ctx, dst);
2032 }
2033 }
2034
2035 static void gen_sradi0(DisasContext *ctx)
2036 {
2037 gen_sradi(ctx, 0);
2038 }
2039
2040 static void gen_sradi1(DisasContext *ctx)
2041 {
2042 gen_sradi(ctx, 1);
2043 }
2044
2045 /* srd & srd. */
2046 static void gen_srd(DisasContext *ctx)
2047 {
2048 TCGv t0, t1;
2049
2050 t0 = tcg_temp_new();
2051 /* AND rS with a mask that is 0 when rB >= 0x40 */
2052 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2053 tcg_gen_sari_tl(t0, t0, 0x3f);
2054 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2055 t1 = tcg_temp_new();
2056 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2057 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2058 tcg_temp_free(t1);
2059 tcg_temp_free(t0);
2060 if (unlikely(Rc(ctx->opcode) != 0))
2061 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2062 }
2063 #endif
2064
2065 #if defined(TARGET_PPC64)
2066 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2067 {
2068 TCGv_i32 tmp = tcg_temp_new_i32();
2069 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2070 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2071 tcg_temp_free_i32(tmp);
2072 }
2073 #else
2074 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2075 {
2076 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2077 }
2078 #endif
2079
2080 /*** Floating-Point arithmetic ***/
2081 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2082 static void gen_f##name(DisasContext *ctx) \
2083 { \
2084 if (unlikely(!ctx->fpu_enabled)) { \
2085 gen_exception(ctx, POWERPC_EXCP_FPU); \
2086 return; \
2087 } \
2088 /* NIP cannot be restored if the memory exception comes from an helper */ \
2089 gen_update_nip(ctx, ctx->nip - 4); \
2090 gen_reset_fpstatus(); \
2091 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rA(ctx->opcode)], \
2093 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2094 if (isfloat) { \
2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2096 cpu_fpr[rD(ctx->opcode)]); \
2097 } \
2098 if (set_fprf) { \
2099 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2100 } \
2101 if (unlikely(Rc(ctx->opcode) != 0)) { \
2102 gen_set_cr1_from_fpscr(ctx); \
2103 } \
2104 }
2105
2106 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2107 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2108 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2109
2110 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2111 static void gen_f##name(DisasContext *ctx) \
2112 { \
2113 if (unlikely(!ctx->fpu_enabled)) { \
2114 gen_exception(ctx, POWERPC_EXCP_FPU); \
2115 return; \
2116 } \
2117 /* NIP cannot be restored if the memory exception comes from an helper */ \
2118 gen_update_nip(ctx, ctx->nip - 4); \
2119 gen_reset_fpstatus(); \
2120 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2121 cpu_fpr[rA(ctx->opcode)], \
2122 cpu_fpr[rB(ctx->opcode)]); \
2123 if (isfloat) { \
2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2125 cpu_fpr[rD(ctx->opcode)]); \
2126 } \
2127 if (set_fprf) { \
2128 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2129 } \
2130 if (unlikely(Rc(ctx->opcode) != 0)) { \
2131 gen_set_cr1_from_fpscr(ctx); \
2132 } \
2133 }
2134 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2135 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2136 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2137
2138 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2139 static void gen_f##name(DisasContext *ctx) \
2140 { \
2141 if (unlikely(!ctx->fpu_enabled)) { \
2142 gen_exception(ctx, POWERPC_EXCP_FPU); \
2143 return; \
2144 } \
2145 /* NIP cannot be restored if the memory exception comes from an helper */ \
2146 gen_update_nip(ctx, ctx->nip - 4); \
2147 gen_reset_fpstatus(); \
2148 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2149 cpu_fpr[rA(ctx->opcode)], \
2150 cpu_fpr[rC(ctx->opcode)]); \
2151 if (isfloat) { \
2152 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2153 cpu_fpr[rD(ctx->opcode)]); \
2154 } \
2155 if (set_fprf) { \
2156 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2157 } \
2158 if (unlikely(Rc(ctx->opcode) != 0)) { \
2159 gen_set_cr1_from_fpscr(ctx); \
2160 } \
2161 }
2162 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2163 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2164 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2165
2166 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2167 static void gen_f##name(DisasContext *ctx) \
2168 { \
2169 if (unlikely(!ctx->fpu_enabled)) { \
2170 gen_exception(ctx, POWERPC_EXCP_FPU); \
2171 return; \
2172 } \
2173 /* NIP cannot be restored if the memory exception comes from an helper */ \
2174 gen_update_nip(ctx, ctx->nip - 4); \
2175 gen_reset_fpstatus(); \
2176 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2177 cpu_fpr[rB(ctx->opcode)]); \
2178 if (set_fprf) { \
2179 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2180 } \
2181 if (unlikely(Rc(ctx->opcode) != 0)) { \
2182 gen_set_cr1_from_fpscr(ctx); \
2183 } \
2184 }
2185
2186 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2187 static void gen_f##name(DisasContext *ctx) \
2188 { \
2189 if (unlikely(!ctx->fpu_enabled)) { \
2190 gen_exception(ctx, POWERPC_EXCP_FPU); \
2191 return; \
2192 } \
2193 /* NIP cannot be restored if the memory exception comes from an helper */ \
2194 gen_update_nip(ctx, ctx->nip - 4); \
2195 gen_reset_fpstatus(); \
2196 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2197 cpu_fpr[rB(ctx->opcode)]); \
2198 if (set_fprf) { \
2199 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2200 } \
2201 if (unlikely(Rc(ctx->opcode) != 0)) { \
2202 gen_set_cr1_from_fpscr(ctx); \
2203 } \
2204 }
2205
2206 /* fadd - fadds */
2207 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2208 /* fdiv - fdivs */
2209 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2210 /* fmul - fmuls */
2211 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2212
2213 /* fre */
2214 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2215
2216 /* fres */
2217 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2218
2219 /* frsqrte */
2220 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2221
2222 /* frsqrtes */
2223 static void gen_frsqrtes(DisasContext *ctx)
2224 {
2225 if (unlikely(!ctx->fpu_enabled)) {
2226 gen_exception(ctx, POWERPC_EXCP_FPU);
2227 return;
2228 }
2229 /* NIP cannot be restored if the memory exception comes from an helper */
2230 gen_update_nip(ctx, ctx->nip - 4);
2231 gen_reset_fpstatus();
2232 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2233 cpu_fpr[rB(ctx->opcode)]);
2234 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2235 cpu_fpr[rD(ctx->opcode)]);
2236 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2237 if (unlikely(Rc(ctx->opcode) != 0)) {
2238 gen_set_cr1_from_fpscr(ctx);
2239 }
2240 }
2241
2242 /* fsel */
2243 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2244 /* fsub - fsubs */
2245 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2246 /* Optional: */
2247
2248 /* fsqrt */
2249 static void gen_fsqrt(DisasContext *ctx)
2250 {
2251 if (unlikely(!ctx->fpu_enabled)) {
2252 gen_exception(ctx, POWERPC_EXCP_FPU);
2253 return;
2254 }
2255 /* NIP cannot be restored if the memory exception comes from an helper */
2256 gen_update_nip(ctx, ctx->nip - 4);
2257 gen_reset_fpstatus();
2258 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2259 cpu_fpr[rB(ctx->opcode)]);
2260 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2261 if (unlikely(Rc(ctx->opcode) != 0)) {
2262 gen_set_cr1_from_fpscr(ctx);
2263 }
2264 }
2265
2266 static void gen_fsqrts(DisasContext *ctx)
2267 {
2268 if (unlikely(!ctx->fpu_enabled)) {
2269 gen_exception(ctx, POWERPC_EXCP_FPU);
2270 return;
2271 }
2272 /* NIP cannot be restored if the memory exception comes from an helper */
2273 gen_update_nip(ctx, ctx->nip - 4);
2274 gen_reset_fpstatus();
2275 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2276 cpu_fpr[rB(ctx->opcode)]);
2277 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2278 cpu_fpr[rD(ctx->opcode)]);
2279 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2280 if (unlikely(Rc(ctx->opcode) != 0)) {
2281 gen_set_cr1_from_fpscr(ctx);
2282 }
2283 }
2284
2285 /*** Floating-Point multiply-and-add ***/
2286 /* fmadd - fmadds */
2287 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2288 /* fmsub - fmsubs */
2289 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2290 /* fnmadd - fnmadds */
2291 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2292 /* fnmsub - fnmsubs */
2293 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2294
2295 /*** Floating-Point round & convert ***/
2296 /* fctiw */
2297 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2298 /* fctiwu */
2299 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2300 /* fctiwz */
2301 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2302 /* fctiwuz */
2303 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2304 /* frsp */
2305 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2306 /* fcfid */
2307 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2308 /* fcfids */
2309 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2310 /* fcfidu */
2311 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2312 /* fcfidus */
2313 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2314 /* fctid */
2315 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2316 /* fctidu */
2317 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2318 /* fctidz */
2319 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2320 /* fctidu */
2321 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2322
2323 /* frin */
2324 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2325 /* friz */
2326 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2327 /* frip */
2328 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2329 /* frim */
2330 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2331
2332 static void gen_ftdiv(DisasContext *ctx)
2333 {
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2339 cpu_fpr[rB(ctx->opcode)]);
2340 }
2341
2342 static void gen_ftsqrt(DisasContext *ctx)
2343 {
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2349 }
2350
2351
2352
2353 /*** Floating-Point compare ***/
2354
2355 /* fcmpo */
2356 static void gen_fcmpo(DisasContext *ctx)
2357 {
2358 TCGv_i32 crf;
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 /* NIP cannot be restored if the memory exception comes from an helper */
2364 gen_update_nip(ctx, ctx->nip - 4);
2365 gen_reset_fpstatus();
2366 crf = tcg_const_i32(crfD(ctx->opcode));
2367 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2368 cpu_fpr[rB(ctx->opcode)], crf);
2369 tcg_temp_free_i32(crf);
2370 gen_helper_float_check_status(cpu_env);
2371 }
2372
2373 /* fcmpu */
2374 static void gen_fcmpu(DisasContext *ctx)
2375 {
2376 TCGv_i32 crf;
2377 if (unlikely(!ctx->fpu_enabled)) {
2378 gen_exception(ctx, POWERPC_EXCP_FPU);
2379 return;
2380 }
2381 /* NIP cannot be restored if the memory exception comes from an helper */
2382 gen_update_nip(ctx, ctx->nip - 4);
2383 gen_reset_fpstatus();
2384 crf = tcg_const_i32(crfD(ctx->opcode));
2385 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2386 cpu_fpr[rB(ctx->opcode)], crf);
2387 tcg_temp_free_i32(crf);
2388 gen_helper_float_check_status(cpu_env);
2389 }
2390
2391 /*** Floating-point move ***/
2392 /* fabs */
2393 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2394 static void gen_fabs(DisasContext *ctx)
2395 {
2396 if (unlikely(!ctx->fpu_enabled)) {
2397 gen_exception(ctx, POWERPC_EXCP_FPU);
2398 return;
2399 }
2400 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2401 ~(1ULL << 63));
2402 if (unlikely(Rc(ctx->opcode))) {
2403 gen_set_cr1_from_fpscr(ctx);
2404 }
2405 }
2406
2407 /* fmr - fmr. */
2408 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2409 static void gen_fmr(DisasContext *ctx)
2410 {
2411 if (unlikely(!ctx->fpu_enabled)) {
2412 gen_exception(ctx, POWERPC_EXCP_FPU);
2413 return;
2414 }
2415 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2416 if (unlikely(Rc(ctx->opcode))) {
2417 gen_set_cr1_from_fpscr(ctx);
2418 }
2419 }
2420
2421 /* fnabs */
2422 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2423 static void gen_fnabs(DisasContext *ctx)
2424 {
2425 if (unlikely(!ctx->fpu_enabled)) {
2426 gen_exception(ctx, POWERPC_EXCP_FPU);
2427 return;
2428 }
2429 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2430 1ULL << 63);
2431 if (unlikely(Rc(ctx->opcode))) {
2432 gen_set_cr1_from_fpscr(ctx);
2433 }
2434 }
2435
2436 /* fneg */
2437 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2438 static void gen_fneg(DisasContext *ctx)
2439 {
2440 if (unlikely(!ctx->fpu_enabled)) {
2441 gen_exception(ctx, POWERPC_EXCP_FPU);
2442 return;
2443 }
2444 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2445 1ULL << 63);
2446 if (unlikely(Rc(ctx->opcode))) {
2447 gen_set_cr1_from_fpscr(ctx);
2448 }
2449 }
2450
2451 /* fcpsgn: PowerPC 2.05 specification */
2452 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2453 static void gen_fcpsgn(DisasContext *ctx)
2454 {
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2460 cpu_fpr[rB(ctx->opcode)], 0, 63);
2461 if (unlikely(Rc(ctx->opcode))) {
2462 gen_set_cr1_from_fpscr(ctx);
2463 }
2464 }
2465
2466 static void gen_fmrgew(DisasContext *ctx)
2467 {
2468 TCGv_i64 b0;
2469 if (unlikely(!ctx->fpu_enabled)) {
2470 gen_exception(ctx, POWERPC_EXCP_FPU);
2471 return;
2472 }
2473 b0 = tcg_temp_new_i64();
2474 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2475 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2476 b0, 0, 32);
2477 tcg_temp_free_i64(b0);
2478 }
2479
2480 static void gen_fmrgow(DisasContext *ctx)
2481 {
2482 if (unlikely(!ctx->fpu_enabled)) {
2483 gen_exception(ctx, POWERPC_EXCP_FPU);
2484 return;
2485 }
2486 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2487 cpu_fpr[rB(ctx->opcode)],
2488 cpu_fpr[rA(ctx->opcode)],
2489 32, 32);
2490 }
2491
2492 /*** Floating-Point status & ctrl register ***/
2493
2494 /* mcrfs */
2495 static void gen_mcrfs(DisasContext *ctx)
2496 {
2497 TCGv tmp = tcg_temp_new();
2498 int bfa;
2499
2500 if (unlikely(!ctx->fpu_enabled)) {
2501 gen_exception(ctx, POWERPC_EXCP_FPU);
2502 return;
2503 }
2504 bfa = 4 * (7 - crfS(ctx->opcode));
2505 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2506 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2507 tcg_temp_free(tmp);
2508 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2509 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2510 }
2511
2512 /* mffs */
2513 static void gen_mffs(DisasContext *ctx)
2514 {
2515 if (unlikely(!ctx->fpu_enabled)) {
2516 gen_exception(ctx, POWERPC_EXCP_FPU);
2517 return;
2518 }
2519 gen_reset_fpstatus();
2520 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2521 if (unlikely(Rc(ctx->opcode))) {
2522 gen_set_cr1_from_fpscr(ctx);
2523 }
2524 }
2525
2526 /* mtfsb0 */
2527 static void gen_mtfsb0(DisasContext *ctx)
2528 {
2529 uint8_t crb;
2530
2531 if (unlikely(!ctx->fpu_enabled)) {
2532 gen_exception(ctx, POWERPC_EXCP_FPU);
2533 return;
2534 }
2535 crb = 31 - crbD(ctx->opcode);
2536 gen_reset_fpstatus();
2537 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2538 TCGv_i32 t0;
2539 /* NIP cannot be restored if the memory exception comes from an helper */
2540 gen_update_nip(ctx, ctx->nip - 4);
2541 t0 = tcg_const_i32(crb);
2542 gen_helper_fpscr_clrbit(cpu_env, t0);
2543 tcg_temp_free_i32(t0);
2544 }
2545 if (unlikely(Rc(ctx->opcode) != 0)) {
2546 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2547 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2548 }
2549 }
2550
2551 /* mtfsb1 */
2552 static void gen_mtfsb1(DisasContext *ctx)
2553 {
2554 uint8_t crb;
2555
2556 if (unlikely(!ctx->fpu_enabled)) {
2557 gen_exception(ctx, POWERPC_EXCP_FPU);
2558 return;
2559 }
2560 crb = 31 - crbD(ctx->opcode);
2561 gen_reset_fpstatus();
2562 /* XXX: we pretend we can only do IEEE floating-point computations */
2563 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2564 TCGv_i32 t0;
2565 /* NIP cannot be restored if the memory exception comes from an helper */
2566 gen_update_nip(ctx, ctx->nip - 4);
2567 t0 = tcg_const_i32(crb);
2568 gen_helper_fpscr_setbit(cpu_env, t0);
2569 tcg_temp_free_i32(t0);
2570 }
2571 if (unlikely(Rc(ctx->opcode) != 0)) {
2572 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2573 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2574 }
2575 /* We can raise a differed exception */
2576 gen_helper_float_check_status(cpu_env);
2577 }
2578
2579 /* mtfsf */
2580 static void gen_mtfsf(DisasContext *ctx)
2581 {
2582 TCGv_i32 t0;
2583 int flm, l, w;
2584
2585 if (unlikely(!ctx->fpu_enabled)) {
2586 gen_exception(ctx, POWERPC_EXCP_FPU);
2587 return;
2588 }
2589 flm = FPFLM(ctx->opcode);
2590 l = FPL(ctx->opcode);
2591 w = FPW(ctx->opcode);
2592 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2593 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2594 return;
2595 }
2596 /* NIP cannot be restored if the memory exception comes from an helper */
2597 gen_update_nip(ctx, ctx->nip - 4);
2598 gen_reset_fpstatus();
2599 if (l) {
2600 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2601 } else {
2602 t0 = tcg_const_i32(flm << (w * 8));
2603 }
2604 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2605 tcg_temp_free_i32(t0);
2606 if (unlikely(Rc(ctx->opcode) != 0)) {
2607 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2608 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2609 }
2610 /* We can raise a differed exception */
2611 gen_helper_float_check_status(cpu_env);
2612 }
2613
2614 /* mtfsfi */
2615 static void gen_mtfsfi(DisasContext *ctx)
2616 {
2617 int bf, sh, w;
2618 TCGv_i64 t0;
2619 TCGv_i32 t1;
2620
2621 if (unlikely(!ctx->fpu_enabled)) {
2622 gen_exception(ctx, POWERPC_EXCP_FPU);
2623 return;
2624 }
2625 w = FPW(ctx->opcode);
2626 bf = FPBF(ctx->opcode);
2627 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2629 return;
2630 }
2631 sh = (8 * w) + 7 - bf;
2632 /* NIP cannot be restored if the memory exception comes from an helper */
2633 gen_update_nip(ctx, ctx->nip - 4);
2634 gen_reset_fpstatus();
2635 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2636 t1 = tcg_const_i32(1 << sh);
2637 gen_helper_store_fpscr(cpu_env, t0, t1);
2638 tcg_temp_free_i64(t0);
2639 tcg_temp_free_i32(t1);
2640 if (unlikely(Rc(ctx->opcode) != 0)) {
2641 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2642 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2643 }
2644 /* We can raise a differed exception */
2645 gen_helper_float_check_status(cpu_env);
2646 }
2647
2648 /*** Addressing modes ***/
2649 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2650 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2651 target_long maskl)
2652 {
2653 target_long simm = SIMM(ctx->opcode);
2654
2655 simm &= ~maskl;
2656 if (rA(ctx->opcode) == 0) {
2657 if (NARROW_MODE(ctx)) {
2658 simm = (uint32_t)simm;
2659 }
2660 tcg_gen_movi_tl(EA, simm);
2661 } else if (likely(simm != 0)) {
2662 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2663 if (NARROW_MODE(ctx)) {
2664 tcg_gen_ext32u_tl(EA, EA);
2665 }
2666 } else {
2667 if (NARROW_MODE(ctx)) {
2668 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2669 } else {
2670 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2671 }
2672 }
2673 }
2674
2675 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2676 {
2677 if (rA(ctx->opcode) == 0) {
2678 if (NARROW_MODE(ctx)) {
2679 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2680 } else {
2681 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2682 }
2683 } else {
2684 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2685 if (NARROW_MODE(ctx)) {
2686 tcg_gen_ext32u_tl(EA, EA);
2687 }
2688 }
2689 }
2690
2691 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2692 {
2693 if (rA(ctx->opcode) == 0) {
2694 tcg_gen_movi_tl(EA, 0);
2695 } else if (NARROW_MODE(ctx)) {
2696 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2697 } else {
2698 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2699 }
2700 }
2701
2702 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2703 target_long val)
2704 {
2705 tcg_gen_addi_tl(ret, arg1, val);
2706 if (NARROW_MODE(ctx)) {
2707 tcg_gen_ext32u_tl(ret, ret);
2708 }
2709 }
2710
2711 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2712 {
2713 int l1 = gen_new_label();
2714 TCGv t0 = tcg_temp_new();
2715 TCGv_i32 t1, t2;
2716 /* NIP cannot be restored if the memory exception comes from an helper */
2717 gen_update_nip(ctx, ctx->nip - 4);
2718 tcg_gen_andi_tl(t0, EA, mask);
2719 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2720 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2721 t2 = tcg_const_i32(0);
2722 gen_helper_raise_exception_err(cpu_env, t1, t2);
2723 tcg_temp_free_i32(t1);
2724 tcg_temp_free_i32(t2);
2725 gen_set_label(l1);
2726 tcg_temp_free(t0);
2727 }
2728
2729 /*** Integer load ***/
2730 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2731 {
2732 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2733 }
2734
2735 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2736 {
2737 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2738 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2739 }
2740
2741 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2742 {
2743 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2744 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2745 }
2746
2747 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2748 {
2749 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2750 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2751 }
2752
2753 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2754 {
2755 TCGv tmp = tcg_temp_new();
2756 gen_qemu_ld32u(ctx, tmp, addr);
2757 tcg_gen_extu_tl_i64(val, tmp);
2758 tcg_temp_free(tmp);
2759 }
2760
2761 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2762 {
2763 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2764 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2765 }
2766
2767 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2768 {
2769 TCGv tmp = tcg_temp_new();
2770 gen_qemu_ld32s(ctx, tmp, addr);
2771 tcg_gen_ext_tl_i64(val, tmp);
2772 tcg_temp_free(tmp);
2773 }
2774
2775 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2776 {
2777 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2778 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2779 }
2780
2781 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2782 {
2783 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2784 }
2785
2786 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2787 {
2788 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2789 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2790 }
2791
2792 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2793 {
2794 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2795 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2796 }
2797
2798 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2799 {
2800 TCGv tmp = tcg_temp_new();
2801 tcg_gen_trunc_i64_tl(tmp, val);
2802 gen_qemu_st32(ctx, tmp, addr);
2803 tcg_temp_free(tmp);
2804 }
2805
2806 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2807 {
2808 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2809 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2810 }
2811
2812 #define GEN_LD(name, ldop, opc, type) \
2813 static void glue(gen_, name)(DisasContext *ctx) \
2814 { \
2815 TCGv EA; \
2816 gen_set_access_type(ctx, ACCESS_INT); \
2817 EA = tcg_temp_new(); \
2818 gen_addr_imm_index(ctx, EA, 0); \
2819 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \
2821 }
2822
2823 #define GEN_LDU(name, ldop, opc, type) \
2824 static void glue(gen_, name##u)(DisasContext *ctx) \
2825 { \
2826 TCGv EA; \
2827 if (unlikely(rA(ctx->opcode) == 0 || \
2828 rA(ctx->opcode) == rD(ctx->opcode))) { \
2829 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2830 return; \
2831 } \
2832 gen_set_access_type(ctx, ACCESS_INT); \
2833 EA = tcg_temp_new(); \
2834 if (type == PPC_64B) \
2835 gen_addr_imm_index(ctx, EA, 0x03); \
2836 else \
2837 gen_addr_imm_index(ctx, EA, 0); \
2838 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2839 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2840 tcg_temp_free(EA); \
2841 }
2842
2843 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2844 static void glue(gen_, name##ux)(DisasContext *ctx) \
2845 { \
2846 TCGv EA; \
2847 if (unlikely(rA(ctx->opcode) == 0 || \
2848 rA(ctx->opcode) == rD(ctx->opcode))) { \
2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2850 return; \
2851 } \
2852 gen_set_access_type(ctx, ACCESS_INT); \
2853 EA = tcg_temp_new(); \
2854 gen_addr_reg_index(ctx, EA); \
2855 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2856 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2857 tcg_temp_free(EA); \
2858 }
2859
2860 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2861 static void glue(gen_, name##x)(DisasContext *ctx) \
2862 { \
2863 TCGv EA; \
2864 gen_set_access_type(ctx, ACCESS_INT); \
2865 EA = tcg_temp_new(); \
2866 gen_addr_reg_index(ctx, EA); \
2867 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2868 tcg_temp_free(EA); \
2869 }
2870 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2871 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2872
2873 #define GEN_LDS(name, ldop, op, type) \
2874 GEN_LD(name, ldop, op | 0x20, type); \
2875 GEN_LDU(name, ldop, op | 0x21, type); \
2876 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2877 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2878
2879 /* lbz lbzu lbzux lbzx */
2880 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2881 /* lha lhau lhaux lhax */
2882 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2883 /* lhz lhzu lhzux lhzx */
2884 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2885 /* lwz lwzu lwzux lwzx */
2886 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2887 #if defined(TARGET_PPC64)
2888 /* lwaux */
2889 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2890 /* lwax */
2891 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2892 /* ldux */
2893 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2894 /* ldx */
2895 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2896
2897 static void gen_ld(DisasContext *ctx)
2898 {
2899 TCGv EA;
2900 if (Rc(ctx->opcode)) {
2901 if (unlikely(rA(ctx->opcode) == 0 ||
2902 rA(ctx->opcode) == rD(ctx->opcode))) {
2903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2904 return;
2905 }
2906 }
2907 gen_set_access_type(ctx, ACCESS_INT);
2908 EA = tcg_temp_new();
2909 gen_addr_imm_index(ctx, EA, 0x03);
2910 if (ctx->opcode & 0x02) {
2911 /* lwa (lwau is undefined) */
2912 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2913 } else {
2914 /* ld - ldu */
2915 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2916 }
2917 if (Rc(ctx->opcode))
2918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2919 tcg_temp_free(EA);
2920 }
2921
2922 /* lq */
2923 static void gen_lq(DisasContext *ctx)
2924 {
2925 int ra, rd;
2926 TCGv EA;
2927
2928 /* lq is a legal user mode instruction starting in ISA 2.07 */
2929 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2930 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2931
2932 if (!legal_in_user_mode && ctx->pr) {
2933 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2934 return;
2935 }
2936
2937 if (!le_is_supported && ctx->le_mode) {
2938 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2939 return;
2940 }
2941
2942 ra = rA(ctx->opcode);
2943 rd = rD(ctx->opcode);
2944 if (unlikely((rd & 1) || rd == ra)) {
2945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2946 return;
2947 }
2948
2949 gen_set_access_type(ctx, ACCESS_INT);
2950 EA = tcg_temp_new();
2951 gen_addr_imm_index(ctx, EA, 0x0F);
2952
2953 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2954 64-bit byteswap already. */
2955 if (unlikely(ctx->le_mode)) {
2956 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2957 gen_addr_add(ctx, EA, EA, 8);
2958 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2959 } else {
2960 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2961 gen_addr_add(ctx, EA, EA, 8);
2962 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2963 }
2964 tcg_temp_free(EA);
2965 }
2966 #endif
2967
2968 /*** Integer store ***/
2969 #define GEN_ST(name, stop, opc, type) \
2970 static void glue(gen_, name)(DisasContext *ctx) \
2971 { \
2972 TCGv EA; \
2973 gen_set_access_type(ctx, ACCESS_INT); \
2974 EA = tcg_temp_new(); \
2975 gen_addr_imm_index(ctx, EA, 0); \
2976 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2977 tcg_temp_free(EA); \
2978 }
2979
2980 #define GEN_STU(name, stop, opc, type) \
2981 static void glue(gen_, stop##u)(DisasContext *ctx) \
2982 { \
2983 TCGv EA; \
2984 if (unlikely(rA(ctx->opcode) == 0)) { \
2985 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2986 return; \
2987 } \
2988 gen_set_access_type(ctx, ACCESS_INT); \
2989 EA = tcg_temp_new(); \
2990 if (type == PPC_64B) \
2991 gen_addr_imm_index(ctx, EA, 0x03); \
2992 else \
2993 gen_addr_imm_index(ctx, EA, 0); \
2994 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2995 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2996 tcg_temp_free(EA); \
2997 }
2998
2999 #define GEN_STUX(name, stop, opc2, opc3, type) \
3000 static void glue(gen_, name##ux)(DisasContext *ctx) \
3001 { \
3002 TCGv EA; \
3003 if (unlikely(rA(ctx->opcode) == 0)) { \
3004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3005 return; \
3006 } \
3007 gen_set_access_type(ctx, ACCESS_INT); \
3008 EA = tcg_temp_new(); \
3009 gen_addr_reg_index(ctx, EA); \
3010 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3011 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3012 tcg_temp_free(EA); \
3013 }
3014
3015 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3016 static void glue(gen_, name##x)(DisasContext *ctx) \
3017 { \
3018 TCGv EA; \
3019 gen_set_access_type(ctx, ACCESS_INT); \
3020 EA = tcg_temp_new(); \
3021 gen_addr_reg_index(ctx, EA); \
3022 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3023 tcg_temp_free(EA); \
3024 }
3025 #define GEN_STX(name, stop, opc2, opc3, type) \
3026 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3027
3028 #define GEN_STS(name, stop, op, type) \
3029 GEN_ST(name, stop, op | 0x20, type); \
3030 GEN_STU(name, stop, op | 0x21, type); \
3031 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3032 GEN_STX(name, stop, 0x17, op | 0x00, type)
3033
3034 /* stb stbu stbux stbx */
3035 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3036 /* sth sthu sthux sthx */
3037 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3038 /* stw stwu stwux stwx */
3039 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3040 #if defined(TARGET_PPC64)
3041 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3042 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3043
3044 static void gen_std(DisasContext *ctx)
3045 {
3046 int rs;
3047 TCGv EA;
3048
3049 rs = rS(ctx->opcode);
3050 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3051
3052 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3053 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3054
3055 if (!legal_in_user_mode && ctx->pr) {
3056 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3057 return;
3058 }
3059
3060 if (!le_is_supported && ctx->le_mode) {
3061 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3062 return;
3063 }
3064
3065 if (unlikely(rs & 1)) {
3066 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3067 return;
3068 }
3069 gen_set_access_type(ctx, ACCESS_INT);
3070 EA = tcg_temp_new();
3071 gen_addr_imm_index(ctx, EA, 0x03);
3072
3073 /* We only need to swap high and low halves. gen_qemu_st64 does
3074 necessary 64-bit byteswap already. */
3075 if (unlikely(ctx->le_mode)) {
3076 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3077 gen_addr_add(ctx, EA, EA, 8);
3078 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3079 } else {
3080 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3081 gen_addr_add(ctx, EA, EA, 8);
3082 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3083 }
3084 tcg_temp_free(EA);
3085 } else {
3086 /* std / stdu*/
3087 if (Rc(ctx->opcode)) {
3088 if (unlikely(rA(ctx->opcode) == 0)) {
3089 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3090 return;
3091 }
3092 }
3093 gen_set_access_type(ctx, ACCESS_INT);
3094 EA = tcg_temp_new();
3095 gen_addr_imm_index(ctx, EA, 0x03);
3096 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3097 if (Rc(ctx->opcode))
3098 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3099 tcg_temp_free(EA);
3100 }
3101 }
3102 #endif
3103 /*** Integer load and store with byte reverse ***/
3104
3105 /* lhbrx */
3106 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3107 {
3108 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3109 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3110 }
3111 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3112
3113 /* lwbrx */
3114 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3115 {
3116 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3117 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3118 }
3119 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3120
3121 #if defined(TARGET_PPC64)
3122 /* ldbrx */
3123 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3124 {
3125 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3126 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3127 }
3128 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3129 #endif /* TARGET_PPC64 */
3130
3131 /* sthbrx */
3132 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3133 {
3134 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3135 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3136 }
3137 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3138
3139 /* stwbrx */
3140 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3141 {
3142 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3143 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3144 }
3145 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3146
3147 #if defined(TARGET_PPC64)
3148 /* stdbrx */
3149 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3150 {
3151 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3152 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3153 }
3154 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3155 #endif /* TARGET_PPC64 */
3156
3157 /*** Integer load and store multiple ***/
3158
3159 /* lmw */
3160 static void gen_lmw(DisasContext *ctx)
3161 {
3162 TCGv t0;
3163 TCGv_i32 t1;
3164 gen_set_access_type(ctx, ACCESS_INT);
3165 /* NIP cannot be restored if the memory exception comes from an helper */
3166 gen_update_nip(ctx, ctx->nip - 4);
3167 t0 = tcg_temp_new();
3168 t1 = tcg_const_i32(rD(ctx->opcode));
3169 gen_addr_imm_index(ctx, t0, 0);
3170 gen_helper_lmw(cpu_env, t0, t1);
3171 tcg_temp_free(t0);
3172 tcg_temp_free_i32(t1);
3173 }
3174
3175 /* stmw */
3176 static void gen_stmw(DisasContext *ctx)
3177 {
3178 TCGv t0;
3179 TCGv_i32 t1;
3180 gen_set_access_type(ctx, ACCESS_INT);
3181 /* NIP cannot be restored if the memory exception comes from an helper */
3182 gen_update_nip(ctx, ctx->nip - 4);
3183 t0 = tcg_temp_new();
3184 t1 = tcg_const_i32(rS(ctx->opcode));
3185 gen_addr_imm_index(ctx, t0, 0);
3186 gen_helper_stmw(cpu_env, t0, t1);
3187 tcg_temp_free(t0);
3188 tcg_temp_free_i32(t1);
3189 }
3190
3191 /*** Integer load and store strings ***/
3192
3193 /* lswi */
3194 /* PowerPC32 specification says we must generate an exception if
3195 * rA is in the range of registers to be loaded.
3196 * In an other hand, IBM says this is valid, but rA won't be loaded.
3197 * For now, I'll follow the spec...
3198 */
3199 static void gen_lswi(DisasContext *ctx)
3200 {
3201 TCGv t0;
3202 TCGv_i32 t1, t2;
3203 int nb = NB(ctx->opcode);
3204 int start = rD(ctx->opcode);
3205 int ra = rA(ctx->opcode);
3206 int nr;
3207
3208 if (nb == 0)
3209 nb = 32;
3210 nr = nb / 4;
3211 if (unlikely(((start + nr) > 32 &&
3212 start <= ra && (start + nr - 32) > ra) ||
3213 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3215 return;
3216 }
3217 gen_set_access_type(ctx, ACCESS_INT);
3218 /* NIP cannot be restored if the memory exception comes from an helper */
3219 gen_update_nip(ctx, ctx->nip - 4);
3220 t0 = tcg_temp_new();
3221 gen_addr_register(ctx, t0);
3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(start);
3224 gen_helper_lsw(cpu_env, t0, t1, t2);
3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
3228 }
3229
3230 /* lswx */
3231 static void gen_lswx(DisasContext *ctx)
3232 {
3233 TCGv t0;
3234 TCGv_i32 t1, t2, t3;
3235 gen_set_access_type(ctx, ACCESS_INT);
3236 /* NIP cannot be restored if the memory exception comes from an helper */
3237 gen_update_nip(ctx, ctx->nip - 4);
3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_const_i32(rD(ctx->opcode));
3241 t2 = tcg_const_i32(rA(ctx->opcode));
3242 t3 = tcg_const_i32(rB(ctx->opcode));
3243 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 tcg_temp_free_i32(t3);
3248 }
3249
3250 /* stswi */
3251 static void gen_stswi(DisasContext *ctx)
3252 {
3253 TCGv t0;
3254 TCGv_i32 t1, t2;
3255 int nb = NB(ctx->opcode);
3256 gen_set_access_type(ctx, ACCESS_INT);
3257 /* NIP cannot be restored if the memory exception comes from an helper */
3258 gen_update_nip(ctx, ctx->nip - 4);
3259 t0 = tcg_temp_new();
3260 gen_addr_register(ctx, t0);
3261 if (nb == 0)
3262 nb = 32;
3263 t1 = tcg_const_i32(nb);
3264 t2 = tcg_const_i32(rS(ctx->opcode));
3265 gen_helper_stsw(cpu_env, t0, t1, t2);
3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
3269 }
3270
3271 /* stswx */
3272 static void gen_stswx(DisasContext *ctx)
3273 {
3274 TCGv t0;
3275 TCGv_i32 t1, t2;
3276 gen_set_access_type(ctx, ACCESS_INT);
3277 /* NIP cannot be restored if the memory exception comes from an helper */
3278 gen_update_nip(ctx, ctx->nip - 4);
3279 t0 = tcg_temp_new();
3280 gen_addr_reg_index(ctx, t0);
3281 t1 = tcg_temp_new_i32();
3282 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3283 tcg_gen_andi_i32(t1, t1, 0x7F);
3284 t2 = tcg_const_i32(rS(ctx->opcode));
3285 gen_helper_stsw(cpu_env, t0, t1, t2);
3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
3289 }
3290
3291 /*** Memory synchronisation ***/
3292 /* eieio */
3293 static void gen_eieio(DisasContext *ctx)
3294 {
3295 }
3296
3297 /* isync */
3298 static void gen_isync(DisasContext *ctx)
3299 {
3300 gen_stop_exception(ctx);
3301 }
3302
3303 #define LARX(name, len, loadop) \
3304 static void gen_##name(DisasContext *ctx) \
3305 { \
3306 TCGv t0; \
3307 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3308 gen_set_access_type(ctx, ACCESS_RES); \
3309 t0 = tcg_temp_local_new(); \
3310 gen_addr_reg_index(ctx, t0); \
3311 if ((len) > 1) { \
3312 gen_check_align(ctx, t0, (len)-1); \
3313 } \
3314 gen_qemu_##loadop(ctx, gpr, t0); \
3315 tcg_gen_mov_tl(cpu_reserve, t0); \
3316 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3317 tcg_temp_free(t0); \
3318 }
3319
3320 /* lwarx */
3321 LARX(lbarx, 1, ld8u);
3322 LARX(lharx, 2, ld16u);
3323 LARX(lwarx, 4, ld32u);
3324
3325
3326 #if defined(CONFIG_USER_ONLY)
3327 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3328 int reg, int size)
3329 {
3330 TCGv t0 = tcg_temp_new();
3331 uint32_t save_exception = ctx->exception;
3332
3333 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3334 tcg_gen_movi_tl(t0, (size << 5) | reg);
3335 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3336 tcg_temp_free(t0);
3337 gen_update_nip(ctx, ctx->nip-4);
3338 ctx->exception = POWERPC_EXCP_BRANCH;
3339 gen_exception(ctx, POWERPC_EXCP_STCX);
3340 ctx->exception = save_exception;
3341 }
3342 #else
3343 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3344 int reg, int size)
3345 {
3346 int l1;
3347
3348 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3349 l1 = gen_new_label();
3350 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3351 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3352 #if defined(TARGET_PPC64)
3353 if (size == 8) {
3354 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3355 } else
3356 #endif
3357 if (size == 4) {
3358 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3359 } else if (size == 2) {
3360 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3361 #if defined(TARGET_PPC64)
3362 } else if (size == 16) {
3363 TCGv gpr1, gpr2 , EA8;
3364 if (unlikely(ctx->le_mode)) {
3365 gpr1 = cpu_gpr[reg+1];
3366 gpr2 = cpu_gpr[reg];
3367 } else {
3368 gpr1 = cpu_gpr[reg];
3369 gpr2 = cpu_gpr[reg+1];
3370 }
3371 gen_qemu_st64(ctx, gpr1, EA);
3372 EA8 = tcg_temp_local_new();
3373 gen_addr_add(ctx, EA8, EA, 8);
3374 gen_qemu_st64(ctx, gpr2, EA8);
3375 tcg_temp_free(EA8);
3376 #endif
3377 } else {
3378 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3379 }
3380 gen_set_label(l1);
3381 tcg_gen_movi_tl(cpu_reserve, -1);
3382 }
3383 #endif
3384
3385 #define STCX(name, len) \
3386 static void gen_##name(DisasContext *ctx) \
3387 { \
3388 TCGv t0; \
3389 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3390 gen_inval_exception(ctx, \
3391 POWERPC_EXCP_INVAL_INVAL); \
3392 return; \
3393 } \
3394 gen_set_access_type(ctx, ACCESS_RES); \
3395 t0 = tcg_temp_local_new(); \
3396 gen_addr_reg_index(ctx, t0); \
3397 if (len > 1) { \
3398 gen_check_align(ctx, t0, (len)-1); \
3399 } \
3400 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3401 tcg_temp_free(t0); \
3402 }
3403
3404 STCX(stbcx_, 1);
3405 STCX(sthcx_, 2);
3406 STCX(stwcx_, 4);
3407
3408 #if defined(TARGET_PPC64)
3409 /* ldarx */
3410 LARX(ldarx, 8, ld64);
3411
3412 /* lqarx */
3413 static void gen_lqarx(DisasContext *ctx)
3414 {
3415 TCGv EA;
3416 int rd = rD(ctx->opcode);
3417 TCGv gpr1, gpr2;
3418
3419 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3420 (rd == rB(ctx->opcode)))) {
3421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3422 return;
3423 }
3424
3425 gen_set_access_type(ctx, ACCESS_RES);
3426 EA = tcg_temp_local_new();
3427 gen_addr_reg_index(ctx, EA);
3428 gen_check_align(ctx, EA, 15);
3429 if (unlikely(ctx->le_mode)) {
3430 gpr1 = cpu_gpr[rd+1];
3431 gpr2 = cpu_gpr[rd];
3432 } else {
3433 gpr1 = cpu_gpr[rd];
3434 gpr2 = cpu_gpr[rd+1];
3435 }
3436 gen_qemu_ld64(ctx, gpr1, EA);
3437 tcg_gen_mov_tl(cpu_reserve, EA);
3438
3439 gen_addr_add(ctx, EA, EA, 8);
3440 gen_qemu_ld64(ctx, gpr2, EA);
3441
3442 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3443 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3444
3445 tcg_temp_free(EA);
3446 }
3447
3448 /* stdcx. */
3449 STCX(stdcx_, 8);
3450 STCX(stqcx_, 16);
3451 #endif /* defined(TARGET_PPC64) */
3452
3453 /* sync */
3454 static void gen_sync(DisasContext *ctx)
3455 {
3456 }
3457
3458 /* wait */
3459 static void gen_wait(DisasContext *ctx)
3460 {
3461 TCGv_i32 t0 = tcg_temp_new_i32();
3462 tcg_gen_st_i32(t0, cpu_env,
3463 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3464 tcg_temp_free_i32(t0);
3465 /* Stop translation, as the CPU is supposed to sleep from now */
3466 gen_exception_err(ctx, EXCP_HLT, 1);
3467 }
3468
3469 /*** Floating-point load ***/
3470 #define GEN_LDF(name, ldop, opc, type) \
3471 static void glue(gen_, name)(DisasContext *ctx) \
3472 { \
3473 TCGv EA; \
3474 if (unlikely(!ctx->fpu_enabled)) { \
3475 gen_exception(ctx, POWERPC_EXCP_FPU); \
3476 return; \
3477 } \
3478 gen_set_access_type(ctx, ACCESS_FLOAT); \
3479 EA = tcg_temp_new(); \
3480 gen_addr_imm_index(ctx, EA, 0); \
3481 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3482 tcg_temp_free(EA); \
3483 }
3484
3485 #define GEN_LDUF(name, ldop, opc, type) \
3486 static void glue(gen_, name##u)(DisasContext *ctx) \
3487 { \
3488 TCGv EA; \
3489 if (unlikely(!ctx->fpu_enabled)) { \
3490 gen_exception(ctx, POWERPC_EXCP_FPU); \
3491 return; \
3492 } \
3493 if (unlikely(rA(ctx->opcode) == 0)) { \
3494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3495 return; \
3496 } \
3497 gen_set_access_type(ctx, ACCESS_FLOAT); \
3498 EA = tcg_temp_new(); \
3499 gen_addr_imm_index(ctx, EA, 0); \
3500 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3501 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3502 tcg_temp_free(EA); \
3503 }
3504
3505 #define GEN_LDUXF(name, ldop, opc, type) \
3506 static void glue(gen_, name##ux)(DisasContext *ctx) \
3507 { \
3508 TCGv EA; \
3509 if (unlikely(!ctx->fpu_enabled)) { \
3510 gen_exception(ctx, POWERPC_EXCP_FPU); \
3511 return; \
3512 } \
3513 if (unlikely(rA(ctx->opcode) == 0)) { \
3514 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3515 return; \
3516 } \
3517 gen_set_access_type(ctx, ACCESS_FLOAT); \
3518 EA = tcg_temp_new(); \
3519 gen_addr_reg_index(ctx, EA); \
3520 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3521 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3522 tcg_temp_free(EA); \
3523 }
3524
3525 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3526 static void glue(gen_, name##x)(DisasContext *ctx) \
3527 { \
3528 TCGv EA; \
3529 if (unlikely(!ctx->fpu_enabled)) { \
3530 gen_exception(ctx, POWERPC_EXCP_FPU); \
3531 return; \
3532 } \
3533 gen_set_access_type(ctx, ACCESS_FLOAT); \
3534 EA = tcg_temp_new(); \
3535 gen_addr_reg_index(ctx, EA); \
3536 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3537 tcg_temp_free(EA); \
3538 }
3539
3540 #define GEN_LDFS(name, ldop, op, type) \
3541 GEN_LDF(name, ldop, op | 0x20, type); \
3542 GEN_LDUF(name, ldop, op | 0x21, type); \
3543 GEN_LDUXF(name, ldop, op | 0x01, type); \
3544 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3545
3546 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3547 {
3548 TCGv t0 = tcg_temp_new();
3549 TCGv_i32 t1 = tcg_temp_new_i32();
3550 gen_qemu_ld32u(ctx, t0, arg2);
3551 tcg_gen_trunc_tl_i32(t1, t0);
3552 tcg_temp_free(t0);
3553 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3554 tcg_temp_free_i32(t1);
3555 }
3556
3557 /* lfd lfdu lfdux lfdx */
3558 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3559 /* lfs lfsu lfsux lfsx */
3560 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3561
3562 /* lfdp */
3563 static void gen_lfdp(DisasContext *ctx)
3564 {
3565 TCGv EA;
3566 if (unlikely(!ctx->fpu_enabled)) {
3567 gen_exception(ctx, POWERPC_EXCP_FPU);
3568 return;
3569 }
3570 gen_set_access_type(ctx, ACCESS_FLOAT);
3571 EA = tcg_temp_new();
3572 gen_addr_imm_index(ctx, EA, 0);
3573 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3574 64-bit byteswap already. */
3575 if (unlikely(ctx->le_mode)) {
3576 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3577 tcg_gen_addi_tl(EA, EA, 8);
3578 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3579 } else {
3580 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3581 tcg_gen_addi_tl(EA, EA, 8);
3582 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3583 }
3584 tcg_temp_free(EA);
3585 }
3586
3587 /* lfdpx */
3588 static void gen_lfdpx(DisasContext *ctx)
3589 {
3590 TCGv EA;
3591 if (unlikely(!ctx->fpu_enabled)) {
3592 gen_exception(ctx, POWERPC_EXCP_FPU);
3593 return;
3594 }
3595 gen_set_access_type(ctx, ACCESS_FLOAT);
3596 EA = tcg_temp_new();
3597 gen_addr_reg_index(ctx, EA);
3598 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3599 64-bit byteswap already. */
3600 if (unlikely(ctx->le_mode)) {
3601 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3602 tcg_gen_addi_tl(EA, EA, 8);
3603 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3604 } else {
3605 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3606 tcg_gen_addi_tl(EA, EA, 8);
3607 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3608 }
3609 tcg_temp_free(EA);
3610 }
3611
3612 /* lfiwax */
3613 static void gen_lfiwax(DisasContext *ctx)
3614 {
3615 TCGv EA;
3616 TCGv t0;
3617 if (unlikely(!ctx->fpu_enabled)) {
3618 gen_exception(ctx, POWERPC_EXCP_FPU);
3619 return;
3620 }
3621 gen_set_access_type(ctx, ACCESS_FLOAT);
3622 EA = tcg_temp_new();
3623 t0 = tcg_temp_new();
3624 gen_addr_reg_index(ctx, EA);
3625 gen_qemu_ld32s(ctx, t0, EA);
3626 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3627 tcg_temp_free(EA);
3628 tcg_temp_free(t0);
3629 }
3630
3631 /* lfiwzx */
3632 static void gen_lfiwzx(DisasContext *ctx)
3633 {
3634 TCGv EA;
3635 if (unlikely(!ctx->fpu_enabled)) {
3636 gen_exception(ctx, POWERPC_EXCP_FPU);
3637 return;
3638 }
3639 gen_set_access_type(ctx, ACCESS_FLOAT);
3640 EA = tcg_temp_new();
3641 gen_addr_reg_index(ctx, EA);
3642 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3643 tcg_temp_free(EA);
3644 }
3645 /*** Floating-point store ***/
3646 #define GEN_STF(name, stop, opc, type) \
3647 static void glue(gen_, name)(DisasContext *ctx) \
3648 { \
3649 TCGv EA; \
3650 if (unlikely(!ctx->fpu_enabled)) { \
3651 gen_exception(ctx, POWERPC_EXCP_FPU); \
3652 return; \
3653 } \
3654 gen_set_access_type(ctx, ACCESS_FLOAT); \
3655 EA = tcg_temp_new(); \
3656 gen_addr_imm_index(ctx, EA, 0); \
3657 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3658 tcg_temp_free(EA); \
3659 }
3660
3661 #define GEN_STUF(name, stop, opc, type) \
3662 static void glue(gen_, name##u)(DisasContext *ctx) \
3663 { \
3664 TCGv EA; \
3665 if (unlikely(!ctx->fpu_enabled)) { \
3666 gen_exception(ctx, POWERPC_EXCP_FPU); \
3667 return; \
3668 } \
3669 if (unlikely(rA(ctx->opcode) == 0)) { \
3670 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3671 return; \
3672 } \
3673 gen_set_access_type(ctx, ACCESS_FLOAT); \
3674 EA = tcg_temp_new(); \
3675 gen_addr_imm_index(ctx, EA, 0); \
3676 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3677 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3678 tcg_temp_free(EA); \
3679 }
3680
3681 #define GEN_STUXF(name, stop, opc, type) \
3682 static void glue(gen_, name##ux)(DisasContext *ctx) \
3683 { \
3684 TCGv EA; \
3685 if (unlikely(!ctx->fpu_enabled)) { \
3686 gen_exception(ctx, POWERPC_EXCP_FPU); \
3687 return; \
3688 } \
3689 if (unlikely(rA(ctx->opcode) == 0)) { \
3690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3691 return; \
3692 } \
3693 gen_set_access_type(ctx, ACCESS_FLOAT); \
3694 EA = tcg_temp_new(); \
3695 gen_addr_reg_index(ctx, EA); \
3696 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3698 tcg_temp_free(EA); \
3699 }
3700
3701 #define GEN_STXF(name, stop, opc2, opc3, type) \
3702 static void glue(gen_, name##x)(DisasContext *ctx) \
3703 { \
3704 TCGv EA; \
3705 if (unlikely(!ctx->fpu_enabled)) { \
3706 gen_exception(ctx, POWERPC_EXCP_FPU); \
3707 return; \
3708 } \
3709 gen_set_access_type(ctx, ACCESS_FLOAT); \
3710 EA = tcg_temp_new(); \
3711 gen_addr_reg_index(ctx, EA); \
3712 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3713 tcg_temp_free(EA); \
3714 }
3715
3716 #define GEN_STFS(name, stop, op, type) \
3717 GEN_STF(name, stop, op | 0x20, type); \
3718 GEN_STUF(name, stop, op | 0x21, type); \
3719 GEN_STUXF(name, stop, op | 0x01, type); \
3720 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3721
3722 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3723 {
3724 TCGv_i32 t0 = tcg_temp_new_i32();
3725 TCGv t1 = tcg_temp_new();
3726 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3727 tcg_gen_extu_i32_tl(t1, t0);
3728 tcg_temp_free_i32(t0);
3729 gen_qemu_st32(ctx, t1, arg2);
3730 tcg_temp_free(t1);
3731 }
3732
3733 /* stfd stfdu stfdux stfdx */
3734 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3735 /* stfs stfsu stfsux stfsx */
3736 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3737
3738 /* stfdp */
3739 static void gen_stfdp(DisasContext *ctx)
3740 {
3741 TCGv EA;
3742 if (unlikely(!ctx->fpu_enabled)) {
3743 gen_exception(ctx, POWERPC_EXCP_FPU);
3744 return;
3745 }
3746 gen_set_access_type(ctx, ACCESS_FLOAT);
3747 EA = tcg_temp_new();
3748 gen_addr_imm_index(ctx, EA, 0);
3749 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3750 64-bit byteswap already. */
3751 if (unlikely(ctx->le_mode)) {
3752 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3753 tcg_gen_addi_tl(EA, EA, 8);
3754 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3755 } else {
3756 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3757 tcg_gen_addi_tl(EA, EA, 8);
3758 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3759 }
3760 tcg_temp_free(EA);
3761 }
3762
3763 /* stfdpx */
3764 static void gen_stfdpx(DisasContext *ctx)
3765 {
3766 TCGv EA;
3767 if (unlikely(!ctx->fpu_enabled)) {
3768 gen_exception(ctx, POWERPC_EXCP_FPU);
3769 return;
3770 }
3771 gen_set_access_type(ctx, ACCESS_FLOAT);
3772 EA = tcg_temp_new();
3773 gen_addr_reg_index(ctx, EA);
3774 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3775 64-bit byteswap already. */
3776 if (unlikely(ctx->le_mode)) {
3777 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3778 tcg_gen_addi_tl(EA, EA, 8);
3779 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3780 } else {
3781 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3782 tcg_gen_addi_tl(EA, EA, 8);
3783 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3784 }
3785 tcg_temp_free(EA);
3786 }
3787
3788 /* Optional: */
3789 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3790 {
3791 TCGv t0 = tcg_temp_new();
3792 tcg_gen_trunc_i64_tl(t0, arg1),
3793 gen_qemu_st32(ctx, t0, arg2);
3794 tcg_temp_free(t0);
3795 }
3796 /* stfiwx */
3797 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3798
3799 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3800 {
3801 #if defined(TARGET_PPC64)
3802 if (ctx->has_cfar)
3803 tcg_gen_movi_tl(cpu_cfar, nip);
3804 #endif
3805 }
3806
3807 /*** Branch ***/
3808 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3809 {
3810 TranslationBlock *tb;
3811 tb = ctx->tb;
3812 if (NARROW_MODE(ctx)) {
3813 dest = (uint32_t) dest;
3814 }
3815 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3816 likely(!ctx->singlestep_enabled)) {
3817 tcg_gen_goto_tb(n);
3818 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3819 tcg_gen_exit_tb((uintptr_t)tb + n);
3820 } else {
3821 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3822 if (unlikely(ctx->singlestep_enabled)) {
3823 if ((ctx->singlestep_enabled &
3824 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3825 (ctx->exception == POWERPC_EXCP_BRANCH ||
3826 ctx->exception == POWERPC_EXCP_TRACE)) {
3827 target_ulong tmp = ctx->nip;
3828 ctx->nip = dest;
3829 gen_exception(ctx, POWERPC_EXCP_TRACE);
3830 ctx->nip = tmp;
3831 }
3832 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3833 gen_debug_exception(ctx);
3834 }
3835 }
3836 tcg_gen_exit_tb(0);
3837 }
3838 }
3839
3840 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3841 {
3842 if (NARROW_MODE(ctx)) {
3843 nip = (uint32_t)nip;
3844 }
3845 tcg_gen_movi_tl(cpu_lr, nip);
3846 }
3847
3848 /* b ba bl bla */
3849 static void gen_b(DisasContext *ctx)
3850 {
3851 target_ulong li, target;
3852
3853 ctx->exception = POWERPC_EXCP_BRANCH;
3854 /* sign extend LI */
3855 li = LI(ctx->opcode);
3856 li = (li ^ 0x02000000) - 0x02000000;
3857 if (likely(AA(ctx->opcode) == 0)) {
3858 target = ctx->nip + li - 4;
3859 } else {
3860 target = li;
3861 }
3862 if (LK(ctx->opcode)) {
3863 gen_setlr(ctx, ctx->nip);
3864 }
3865 gen_update_cfar(ctx, ctx->nip);
3866 gen_goto_tb(ctx, 0, target);
3867 }
3868
3869 #define BCOND_IM 0
3870 #define BCOND_LR 1
3871 #define BCOND_CTR 2
3872 #define BCOND_TAR 3
3873
3874 static inline void gen_bcond(DisasContext *ctx, int type)
3875 {
3876 uint32_t bo = BO(ctx->opcode);
3877 int l1;
3878 TCGv target;
3879
3880 ctx->exception = POWERPC_EXCP_BRANCH;
3881 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3882 target = tcg_temp_local_new();
3883 if (type == BCOND_CTR)
3884 tcg_gen_mov_tl(target, cpu_ctr);
3885 else if (type == BCOND_TAR)
3886 gen_load_spr(target, SPR_TAR);
3887 else
3888 tcg_gen_mov_tl(target, cpu_lr);
3889 } else {
3890 TCGV_UNUSED(target);
3891 }
3892 if (LK(ctx->opcode))
3893 gen_setlr(ctx, ctx->nip);
3894 l1 = gen_new_label();
3895 if ((bo & 0x4) == 0) {
3896 /* Decrement and test CTR */
3897 TCGv temp = tcg_temp_new();
3898 if (unlikely(type == BCOND_CTR)) {
3899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3900 return;
3901 }
3902 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3903 if (NARROW_MODE(ctx)) {
3904 tcg_gen_ext32u_tl(temp, cpu_ctr);
3905 } else {
3906 tcg_gen_mov_tl(temp, cpu_ctr);
3907 }
3908 if (bo & 0x2) {
3909 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3910 } else {
3911 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3912 }
3913 tcg_temp_free(temp);
3914 }
3915 if ((bo & 0x10) == 0) {
3916 /* Test CR */
3917 uint32_t bi = BI(ctx->opcode);
3918 uint32_t mask = 0x08 >> (bi & 0x03);
3919 TCGv_i32 temp = tcg_temp_new_i32();
3920
3921 if (bo & 0x8) {
3922 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3923 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3924 } else {
3925 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3926 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3927 }
3928 tcg_temp_free_i32(temp);
3929 }
3930 gen_update_cfar(ctx, ctx->nip);
3931 if (type == BCOND_IM) {
3932 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3933 if (likely(AA(ctx->opcode) == 0)) {
3934 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3935 } else {
3936 gen_goto_tb(ctx, 0, li);
3937 }
3938 gen_set_label(l1);
3939 gen_goto_tb(ctx, 1, ctx->nip);
3940 } else {
3941 if (NARROW_MODE(ctx)) {
3942 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3943 } else {
3944 tcg_gen_andi_tl(cpu_nip, target, ~3);
3945 }
3946 tcg_gen_exit_tb(0);
3947 gen_set_label(l1);
3948 gen_update_nip(ctx, ctx->nip);
3949 tcg_gen_exit_tb(0);
3950 }
3951 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3952 tcg_temp_free(target);
3953 }
3954 }
3955
3956 static void gen_bc(DisasContext *ctx)
3957 {
3958 gen_bcond(ctx, BCOND_IM);
3959 }
3960
3961 static void gen_bcctr(DisasContext *ctx)
3962 {
3963 gen_bcond(ctx, BCOND_CTR);
3964 }
3965
3966 static void gen_bclr(DisasContext *ctx)
3967 {
3968 gen_bcond(ctx, BCOND_LR);
3969 }
3970
3971 static void gen_bctar(DisasContext *ctx)
3972 {
3973 gen_bcond(ctx, BCOND_TAR);
3974 }
3975
3976 /*** Condition register logical ***/
3977 #define GEN_CRLOGIC(name, tcg_op, opc) \
3978 static void glue(gen_, name)(DisasContext *ctx) \
3979 { \
3980 uint8_t bitmask; \
3981 int sh; \
3982 TCGv_i32 t0, t1; \
3983 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3984 t0 = tcg_temp_new_i32(); \
3985 if (sh > 0) \
3986 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3987 else if (sh < 0) \
3988 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3989 else \
3990 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3991 t1 = tcg_temp_new_i32(); \
3992 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3993 if (sh > 0) \
3994 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3995 else if (sh < 0) \
3996 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3997 else \
3998 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3999 tcg_op(t0, t0, t1); \
4000 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4001 tcg_gen_andi_i32(t0, t0, bitmask); \
4002 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4003 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4004 tcg_temp_free_i32(t0); \
4005 tcg_temp_free_i32(t1); \
4006 }
4007
4008 /* crand */
4009 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4010 /* crandc */
4011 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4012 /* creqv */
4013 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4014 /* crnand */
4015 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4016 /* crnor */
4017 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4018 /* cror */
4019 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4020 /* crorc */
4021 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4022 /* crxor */
4023 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4024
4025 /* mcrf */
4026 static void gen_mcrf(DisasContext *ctx)
4027 {
4028 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4029 }
4030
4031 /*** System linkage ***/
4032
4033 /* rfi (supervisor only) */
4034 static void gen_rfi(DisasContext *ctx)
4035 {
4036 #if defined(CONFIG_USER_ONLY)
4037 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4038 #else
4039 /* Restore CPU state */
4040 if (unlikely(ctx->pr)) {
4041 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4042 return;
4043 }
4044 gen_update_cfar(ctx, ctx->nip);
4045 gen_helper_rfi(cpu_env);
4046 gen_sync_exception(ctx);
4047 #endif
4048 }
4049
4050 #if defined(TARGET_PPC64)
4051 static void gen_rfid(DisasContext *ctx)
4052 {
4053 #if defined(CONFIG_USER_ONLY)
4054 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4055 #else
4056 /* Restore CPU state */
4057 if (unlikely(ctx->pr)) {
4058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4059 return;
4060 }
4061 gen_update_cfar(ctx, ctx->nip);
4062 gen_helper_rfid(cpu_env);
4063 gen_sync_exception(ctx);
4064 #endif
4065 }
4066
4067 static void gen_hrfid(DisasContext *ctx)
4068 {
4069 #if defined(CONFIG_USER_ONLY)
4070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4071 #else
4072 /* Restore CPU state */
4073 if (unlikely(!ctx->hv)) {
4074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4075 return;
4076 }
4077 gen_helper_hrfid(cpu_env);
4078 gen_sync_exception(ctx);
4079 #endif
4080 }
4081 #endif
4082
4083 /* sc */
4084 #if defined(CONFIG_USER_ONLY)
4085 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4086 #else
4087 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4088 #endif
4089 static void gen_sc(DisasContext *ctx)
4090 {
4091 uint32_t lev;
4092
4093 lev = (ctx->opcode >> 5) & 0x7F;
4094 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4095 }
4096
4097 /*** Trap ***/
4098
4099 /* tw */
4100 static void gen_tw(DisasContext *ctx)
4101 {
4102 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4103 /* Update the nip since this might generate a trap exception */
4104 gen_update_nip(ctx, ctx->nip);
4105 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4106 t0);
4107 tcg_temp_free_i32(t0);
4108 }
4109
4110 /* twi */
4111 static void gen_twi(DisasContext *ctx)
4112 {
4113 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4114 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4115 /* Update the nip since this might generate a trap exception */
4116 gen_update_nip(ctx, ctx->nip);
4117 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4118 tcg_temp_free(t0);
4119 tcg_temp_free_i32(t1);
4120 }
4121
4122 #if defined(TARGET_PPC64)
4123 /* td */
4124 static void gen_td(DisasContext *ctx)
4125 {
4126 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4127 /* Update the nip since this might generate a trap exception */
4128 gen_update_nip(ctx, ctx->nip);
4129 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4130 t0);
4131 tcg_temp_free_i32(t0);
4132 }
4133
4134 /* tdi */
4135 static void gen_tdi(DisasContext *ctx)
4136 {
4137 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4138 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4139 /* Update the nip since this might generate a trap exception */
4140 gen_update_nip(ctx, ctx->nip);
4141 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4142 tcg_temp_free(t0);
4143 tcg_temp_free_i32(t1);
4144 }
4145 #endif
4146
4147 /*** Processor control ***/
4148
4149 static void gen_read_xer(TCGv dst)
4150 {
4151 TCGv t0 = tcg_temp_new();
4152 TCGv t1 = tcg_temp_new();
4153 TCGv t2 = tcg_temp_new();
4154 tcg_gen_mov_tl(dst, cpu_xer);
4155 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4156 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4157 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4158 tcg_gen_or_tl(t0, t0, t1);
4159 tcg_gen_or_tl(dst, dst, t2);
4160 tcg_gen_or_tl(dst, dst, t0);
4161 tcg_temp_free(t0);
4162 tcg_temp_free(t1);
4163 tcg_temp_free(t2);
4164 }
4165
4166 static void gen_write_xer(TCGv src)
4167 {
4168 tcg_gen_andi_tl(cpu_xer, src,
4169 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4170 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4171 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4172 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4173 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4174 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4175 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4176 }
4177
4178 /* mcrxr */
4179 static void gen_mcrxr(DisasContext *ctx)
4180 {
4181 TCGv_i32 t0 = tcg_temp_new_i32();
4182 TCGv_i32 t1 = tcg_temp_new_i32();
4183 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4184
4185 tcg_gen_trunc_tl_i32(t0, cpu_so);
4186 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4187 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4188 tcg_gen_shli_i32(t0, t0, 3);
4189 tcg_gen_shli_i32(t1, t1, 2);
4190 tcg_gen_shli_i32(dst, dst, 1);
4191 tcg_gen_or_i32(dst, dst, t0);
4192 tcg_gen_or_i32(dst, dst, t1);
4193 tcg_temp_free_i32(t0);
4194 tcg_temp_free_i32(t1);
4195
4196 tcg_gen_movi_tl(cpu_so, 0);
4197 tcg_gen_movi_tl(cpu_ov, 0);
4198 tcg_gen_movi_tl(cpu_ca, 0);
4199 }
4200
4201 /* mfcr mfocrf */
4202 static void gen_mfcr(DisasContext *ctx)
4203 {
4204 uint32_t crm, crn;
4205
4206 if (likely(ctx->opcode & 0x00100000)) {
4207 crm = CRM(ctx->opcode);
4208 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4209 crn = ctz32 (crm);
4210 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4211 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4212 cpu_gpr[rD(ctx->opcode)], crn * 4);
4213 }
4214 } else {
4215 TCGv_i32 t0 = tcg_temp_new_i32();
4216 tcg_gen_mov_i32(t0, cpu_crf[0]);
4217 tcg_gen_shli_i32(t0, t0, 4);
4218 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4219 tcg_gen_shli_i32(t0, t0, 4);
4220 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4221 tcg_gen_shli_i32(t0, t0, 4);
4222 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4223 tcg_gen_shli_i32(t0, t0, 4);
4224 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4225 tcg_gen_shli_i32(t0, t0, 4);
4226 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4227 tcg_gen_shli_i32(t0, t0, 4);
4228 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4229 tcg_gen_shli_i32(t0, t0, 4);
4230 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4231 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4232 tcg_temp_free_i32(t0);
4233 }
4234 }
4235
4236 /* mfmsr */
4237 static void gen_mfmsr(DisasContext *ctx)
4238 {
4239 #if defined(CONFIG_USER_ONLY)
4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4241 #else
4242 if (unlikely(ctx->pr)) {
4243 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4244 return;
4245 }
4246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4247 #endif
4248 }
4249
4250 static void spr_noaccess(void *opaque, int gprn, int sprn)
4251 {
4252 #if 0
4253 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4254 printf("ERROR: try to access SPR %d !\n", sprn);
4255 #endif
4256 }
4257 #define SPR_NOACCESS (&spr_noaccess)
4258
4259 /* mfspr */
4260 static inline void gen_op_mfspr(DisasContext *ctx)
4261 {
4262 void (*read_cb)(void *opaque, int gprn, int sprn);
4263 uint32_t sprn = SPR(ctx->opcode);
4264
4265 #if !defined(CONFIG_USER_ONLY)
4266 if (ctx->hv)
4267 read_cb = ctx->spr_cb[sprn].hea_read;
4268 else if (!ctx->pr)
4269 read_cb = ctx->spr_cb[sprn].oea_read;
4270 else
4271 #endif
4272 read_cb = ctx->spr_cb[sprn].uea_read;
4273 if (likely(read_cb != NULL)) {
4274 if (likely(read_cb != SPR_NOACCESS)) {
4275 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4276 } else {
4277 /* Privilege exception */
4278 /* This is a hack to avoid warnings when running Linux:
4279 * this OS breaks the PowerPC virtualisation model,
4280 * allowing userland application to read the PVR
4281 */
4282 if (sprn != SPR_PVR) {
4283 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4284 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4285 printf("Trying to read privileged spr %d (0x%03x) at "
4286 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4287 }
4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4289 }
4290 } else {
4291 /* Not defined */
4292 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4293 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4294 printf("Trying to read invalid spr %d (0x%03x) at "
4295 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4296 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4297 }
4298 }
4299
4300 static void gen_mfspr(DisasContext *ctx)
4301 {
4302 gen_op_mfspr(ctx);
4303 }
4304
4305 /* mftb */
4306 static void gen_mftb(DisasContext *ctx)
4307 {
4308 gen_op_mfspr(ctx);
4309 }
4310
4311 /* mtcrf mtocrf*/
4312 static void gen_mtcrf(DisasContext *ctx)
4313 {
4314 uint32_t crm, crn;
4315
4316 crm = CRM(ctx->opcode);
4317 if (likely((ctx->opcode & 0x00100000))) {
4318 if (crm && ((crm & (crm - 1)) == 0)) {
4319 TCGv_i32 temp = tcg_temp_new_i32();
4320 crn = ctz32 (crm);
4321 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4322 tcg_gen_shri_i32(temp, temp, crn * 4);
4323 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4324 tcg_temp_free_i32(temp);
4325 }
4326 } else {
4327 TCGv_i32 temp = tcg_temp_new_i32();
4328 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4329 for (crn = 0 ; crn < 8 ; crn++) {
4330 if (crm & (1 << crn)) {
4331 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4332 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4333 }
4334 }
4335 tcg_temp_free_i32(temp);
4336 }
4337 }
4338
4339 /* mtmsr */
4340 #if defined(TARGET_PPC64)
4341 static void gen_mtmsrd(DisasContext *ctx)
4342 {
4343 #if defined(CONFIG_USER_ONLY)
4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4345 #else
4346 if (unlikely(ctx->pr)) {
4347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4348 return;
4349 }
4350 if (ctx->opcode & 0x00010000) {
4351 /* Special form that does not need any synchronisation */
4352 TCGv t0 = tcg_temp_new();
4353 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4354 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4355 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4356 tcg_temp_free(t0);
4357 } else {
4358 /* XXX: we need to update nip before the store
4359 * if we enter power saving mode, we will exit the loop
4360 * directly from ppc_store_msr
4361 */
4362 gen_update_nip(ctx, ctx->nip);
4363 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4364 /* Must stop the translation as machine state (may have) changed */
4365 /* Note that mtmsr is not always defined as context-synchronizing */
4366 gen_stop_exception(ctx);
4367 }
4368 #endif
4369 }
4370 #endif
4371
4372 static void gen_mtmsr(DisasContext *ctx)
4373 {
4374 #if defined(CONFIG_USER_ONLY)
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4376 #else
4377 if (unlikely(ctx->pr)) {
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4379 return;
4380 }
4381 if (ctx->opcode & 0x00010000) {
4382 /* Special form that does not need any synchronisation */
4383 TCGv t0 = tcg_temp_new();
4384 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4385 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4386 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4387 tcg_temp_free(t0);
4388 } else {
4389 TCGv msr = tcg_temp_new();
4390
4391 /* XXX: we need to update nip before the store
4392 * if we enter power saving mode, we will exit the loop
4393 * directly from ppc_store_msr
4394 */
4395 gen_update_nip(ctx, ctx->nip);
4396 #if defined(TARGET_PPC64)
4397 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4398 #else
4399 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4400 #endif
4401 gen_helper_store_msr(cpu_env, msr);
4402 tcg_temp_free(msr);
4403 /* Must stop the translation as machine state (may have) changed */
4404 /* Note that mtmsr is not always defined as context-synchronizing */
4405 gen_stop_exception(ctx);
4406 }
4407 #endif
4408 }
4409
4410 /* mtspr */
4411 static void gen_mtspr(DisasContext *ctx)
4412 {
4413 void (*write_cb)(void *opaque, int sprn, int gprn);
4414 uint32_t sprn = SPR(ctx->opcode);
4415
4416 #if !defined(CONFIG_USER_ONLY)
4417 if (ctx->hv)
4418 write_cb = ctx->spr_cb[sprn].hea_write;
4419 else if (!ctx->pr)
4420 write_cb = ctx->spr_cb[sprn].oea_write;
4421 else
4422 #endif
4423 write_cb = ctx->spr_cb[sprn].uea_write;
4424 if (likely(write_cb != NULL)) {
4425 if (likely(write_cb != SPR_NOACCESS)) {
4426 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4427 } else {
4428 /* Privilege exception */
4429 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4430 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4431 printf("Trying to write privileged spr %d (0x%03x) at "
4432 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4434 }
4435 } else {
4436 /* Not defined */
4437 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4438 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4439 printf("Trying to write invalid spr %d (0x%03x) at "
4440 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4442 }
4443 }
4444
4445 /*** Cache management ***/
4446
4447 /* dcbf */
4448 static void gen_dcbf(DisasContext *ctx)
4449 {
4450 /* XXX: specification says this is treated as a load by the MMU */
4451 TCGv t0;
4452 gen_set_access_type(ctx, ACCESS_CACHE);
4453 t0 = tcg_temp_new();
4454 gen_addr_reg_index(ctx, t0);
4455 gen_qemu_ld8u(ctx, t0, t0);
4456 tcg_temp_free(t0);
4457 }
4458
4459 /* dcbi (Supervisor only) */
4460 static void gen_dcbi(DisasContext *ctx)
4461 {
4462 #if defined(CONFIG_USER_ONLY)
4463 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4464 #else
4465 TCGv EA, val;
4466 if (unlikely(ctx->pr)) {
4467 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4468 return;
4469 }
4470 EA = tcg_temp_new();
4471 gen_set_access_type(ctx, ACCESS_CACHE);
4472 gen_addr_reg_index(ctx, EA);
4473 val = tcg_temp_new();
4474 /* XXX: specification says this should be treated as a store by the MMU */
4475 gen_qemu_ld8u(ctx, val, EA);
4476 gen_qemu_st8(ctx, val, EA);
4477 tcg_temp_free(val);
4478 tcg_temp_free(EA);
4479 #endif
4480 }
4481
4482 /* dcdst */
4483 static void gen_dcbst(DisasContext *ctx)
4484 {
4485 /* XXX: specification say this is treated as a load by the MMU */
4486 TCGv t0;
4487 gen_set_access_type(ctx, ACCESS_CACHE);
4488 t0 = tcg_temp_new();
4489 gen_addr_reg_index(ctx, t0);
4490 gen_qemu_ld8u(ctx, t0, t0);
4491 tcg_temp_free(t0);
4492 }
4493
4494 /* dcbt */
4495 static void gen_dcbt(DisasContext *ctx)
4496 {
4497 /* interpreted as no-op */
4498 /* XXX: specification say this is treated as a load by the MMU
4499 * but does not generate any exception
4500 */
4501 }
4502
4503 /* dcbtst */
4504 static void gen_dcbtst(DisasContext *ctx)
4505 {
4506 /* interpreted as no-op */
4507 /* XXX: specification say this is treated as a load by the MMU
4508 * but does not generate any exception
4509 */
4510 }
4511
4512 /* dcbtls */
4513 static void gen_dcbtls(DisasContext *ctx)
4514 {
4515 /* Always fails locking the cache */
4516 TCGv t0 = tcg_temp_new();
4517 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4518 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4519 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4520 tcg_temp_free(t0);
4521 }
4522
4523 /* dcbz */
4524 static void gen_dcbz(DisasContext *ctx)
4525 {
4526 TCGv tcgv_addr;
4527 TCGv_i32 tcgv_is_dcbzl;
4528 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4529
4530 gen_set_access_type(ctx, ACCESS_CACHE);
4531 /* NIP cannot be restored if the memory exception comes from an helper */
4532 gen_update_nip(ctx, ctx->nip - 4);
4533 tcgv_addr = tcg_temp_new();
4534 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4535
4536 gen_addr_reg_index(ctx, tcgv_addr);
4537 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4538
4539 tcg_temp_free(tcgv_addr);
4540 tcg_temp_free_i32(tcgv_is_dcbzl);
4541 }
4542
4543 /* dst / dstt */
4544 static void gen_dst(DisasContext *ctx)
4545 {
4546 if (rA(ctx->opcode) == 0) {
4547 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4548 } else {
4549 /* interpreted as no-op */
4550 }
4551 }
4552
4553 /* dstst /dststt */
4554 static void gen_dstst(DisasContext *ctx)
4555 {
4556 if (rA(ctx->opcode) == 0) {
4557 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4558 } else {
4559 /* interpreted as no-op */
4560 }
4561
4562 }
4563
4564 /* dss / dssall */
4565 static void gen_dss(DisasContext *ctx)
4566 {
4567 /* interpreted as no-op */
4568 }
4569
4570 /* icbi */
4571 static void gen_icbi(DisasContext *ctx)
4572 {
4573 TCGv t0;
4574 gen_set_access_type(ctx, ACCESS_CACHE);
4575 /* NIP cannot be restored if the memory exception comes from an helper */
4576 gen_update_nip(ctx, ctx->nip - 4);
4577 t0 = tcg_temp_new();
4578 gen_addr_reg_index(ctx, t0);
4579 gen_helper_icbi(cpu_env, t0);
4580 tcg_temp_free(t0);
4581 }
4582
4583 /* Optional: */
4584 /* dcba */
4585 static void gen_dcba(DisasContext *ctx)
4586 {
4587 /* interpreted as no-op */
4588 /* XXX: specification say this is treated as a store by the MMU
4589 * but does not generate any exception
4590 */
4591 }
4592
4593 /*** Segment register manipulation ***/
4594 /* Supervisor only: */
4595
4596 /* mfsr */
4597 static void gen_mfsr(DisasContext *ctx)
4598 {
4599 #if defined(CONFIG_USER_ONLY)
4600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4601 #else
4602 TCGv t0;
4603 if (unlikely(ctx->pr)) {
4604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4605 return;
4606 }
4607 t0 = tcg_const_tl(SR(ctx->opcode));
4608 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4609 tcg_temp_free(t0);
4610 #endif
4611 }
4612
4613 /* mfsrin */
4614 static void gen_mfsrin(DisasContext *ctx)
4615 {
4616 #if defined(CONFIG_USER_ONLY)
4617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4618 #else
4619 TCGv t0;
4620 if (unlikely(ctx->pr)) {
4621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4622 return;
4623 }
4624 t0 = tcg_temp_new();
4625 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4626 tcg_gen_andi_tl(t0, t0, 0xF);
4627 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4628 tcg_temp_free(t0);
4629 #endif
4630 }
4631
4632 /* mtsr */
4633 static void gen_mtsr(DisasContext *ctx)
4634 {
4635 #if defined(CONFIG_USER_ONLY)
4636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4637 #else
4638 TCGv t0;
4639 if (unlikely(ctx->pr)) {
4640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4641 return;
4642 }
4643 t0 = tcg_const_tl(SR(ctx->opcode));
4644 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4645 tcg_temp_free(t0);
4646 #endif
4647 }
4648
4649 /* mtsrin */
4650 static void gen_mtsrin(DisasContext *ctx)
4651 {
4652 #if defined(CONFIG_USER_ONLY)
4653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4654 #else
4655 TCGv t0;
4656 if (unlikely(ctx->pr)) {
4657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4658 return;
4659 }
4660 t0 = tcg_temp_new();
4661 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4662 tcg_gen_andi_tl(t0, t0, 0xF);
4663 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4664 tcg_temp_free(t0);
4665 #endif
4666 }
4667
4668 #if defined(TARGET_PPC64)
4669 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4670
4671 /* mfsr */
4672 static void gen_mfsr_64b(DisasContext *ctx)
4673 {
4674 #if defined(CONFIG_USER_ONLY)
4675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4676 #else
4677 TCGv t0;
4678 if (unlikely(ctx->pr)) {
4679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4680 return;
4681 }
4682 t0 = tcg_const_tl(SR(ctx->opcode));
4683 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4684 tcg_temp_free(t0);
4685 #endif
4686 }
4687
4688 /* mfsrin */
4689 static void gen_mfsrin_64b(DisasContext *ctx)
4690 {
4691 #if defined(CONFIG_USER_ONLY)
4692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4693 #else
4694 TCGv t0;
4695 if (unlikely(ctx->pr)) {
4696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4697 return;
4698 }
4699 t0 = tcg_temp_new();
4700 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4701 tcg_gen_andi_tl(t0, t0, 0xF);
4702 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4703 tcg_temp_free(t0);
4704 #endif
4705 }
4706
4707 /* mtsr */
4708 static void gen_mtsr_64b(DisasContext *ctx)
4709 {
4710 #if defined(CONFIG_USER_ONLY)
4711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4712 #else
4713 TCGv t0;
4714 if (unlikely(ctx->pr)) {
4715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4716 return;
4717 }
4718 t0 = tcg_const_tl(SR(ctx->opcode));
4719 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4720 tcg_temp_free(t0);
4721 #endif
4722 }
4723
4724 /* mtsrin */
4725 static void gen_mtsrin_64b(DisasContext *ctx)
4726 {
4727 #if defined(CONFIG_USER_ONLY)
4728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4729 #else
4730 TCGv t0;
4731 if (unlikely(ctx->pr)) {
4732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4733 return;
4734 }
4735 t0 = tcg_temp_new();
4736 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4737 tcg_gen_andi_tl(t0, t0, 0xF);
4738 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4739 tcg_temp_free(t0);
4740 #endif
4741 }
4742
4743 /* slbmte */
4744 static void gen_slbmte(DisasContext *ctx)
4745 {
4746 #if defined(CONFIG_USER_ONLY)
4747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4748 #else
4749 if (unlikely(ctx->pr)) {
4750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4751 return;
4752 }
4753 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4754 cpu_gpr[rS(ctx->opcode)]);
4755 #endif
4756 }
4757
4758 static void gen_slbmfee(DisasContext *ctx)
4759 {
4760 #if defined(CONFIG_USER_ONLY)
4761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4762 #else
4763 if (unlikely(ctx->pr)) {
4764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4765 return;
4766 }
4767 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4768 cpu_gpr[rB(ctx->opcode)]);
4769 #endif
4770 }
4771
4772 static void gen_slbmfev(DisasContext *ctx)
4773 {
4774 #if defined(CONFIG_USER_ONLY)
4775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4776 #else
4777 if (unlikely(ctx->pr)) {
4778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4779 return;
4780 }
4781 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4782 cpu_gpr[rB(ctx->opcode)]);
4783 #endif
4784 }
4785 #endif /* defined(TARGET_PPC64) */
4786
4787 /*** Lookaside buffer management ***/
4788 /* Optional & supervisor only: */
4789
4790 /* tlbia */
4791 static void gen_tlbia(DisasContext *ctx)
4792 {
4793 #if defined(CONFIG_USER_ONLY)
4794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4795 #else
4796 if (unlikely(ctx->pr)) {
4797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4798 return;
4799 }
4800 gen_helper_tlbia(cpu_env);
4801 #endif
4802 }
4803
4804 /* tlbiel */
4805 static void gen_tlbiel(DisasContext *ctx)
4806 {
4807 #if defined(CONFIG_USER_ONLY)
4808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4809 #else
4810 if (unlikely(ctx->pr)) {
4811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4812 return;
4813 }
4814 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4815 #endif
4816 }
4817
4818 /* tlbie */
4819 static void gen_tlbie(DisasContext *ctx)
4820 {
4821 #if defined(CONFIG_USER_ONLY)
4822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4823 #else
4824 if (unlikely(ctx->pr)) {
4825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4826 return;
4827 }
4828 if (NARROW_MODE(ctx)) {
4829 TCGv t0 = tcg_temp_new();
4830 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4831 gen_helper_tlbie(cpu_env, t0);
4832 tcg_temp_free(t0);
4833 } else {
4834 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4835 }
4836 #endif
4837 }
4838
4839 /* tlbsync */
4840 static void gen_tlbsync(DisasContext *ctx)
4841 {
4842 #if defined(CONFIG_USER_ONLY)
4843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4844 #else
4845 if (unlikely(ctx->pr)) {
4846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4847 return;
4848 }
4849 /* This has no effect: it should ensure that all previous
4850 * tlbie have completed
4851 */
4852 gen_stop_exception(ctx);
4853 #endif
4854 }
4855
4856 #if defined(TARGET_PPC64)
4857 /* slbia */
4858 static void gen_slbia(DisasContext *ctx)
4859 {
4860 #if defined(CONFIG_USER_ONLY)
4861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4862 #else
4863 if (unlikely(ctx->pr)) {
4864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4865 return;
4866 }
4867 gen_helper_slbia(cpu_env);
4868 #endif
4869 }
4870
4871 /* slbie */
4872 static void gen_slbie(DisasContext *ctx)
4873 {
4874 #if defined(CONFIG_USER_ONLY)
4875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4876 #else
4877 if (unlikely(ctx->pr)) {
4878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4879 return;
4880 }
4881 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4882 #endif
4883 }
4884 #endif
4885
4886 /*** External control ***/
4887 /* Optional: */
4888
4889 /* eciwx */
4890 static void gen_eciwx(DisasContext *ctx)
4891 {
4892 TCGv t0;
4893 /* Should check EAR[E] ! */
4894 gen_set_access_type(ctx, ACCESS_EXT);
4895 t0 = tcg_temp_new();
4896 gen_addr_reg_index(ctx, t0);
4897 gen_check_align(ctx, t0, 0x03);
4898 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4899 tcg_temp_free(t0);
4900 }
4901
4902 /* ecowx */
4903 static void gen_ecowx(DisasContext *ctx)
4904 {
4905 TCGv t0;
4906 /* Should check EAR[E] ! */
4907 gen_set_access_type(ctx, ACCESS_EXT);
4908 t0 = tcg_temp_new();
4909 gen_addr_reg_index(ctx, t0);
4910 gen_check_align(ctx, t0, 0x03);
4911 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4912 tcg_temp_free(t0);
4913 }
4914
4915 /* PowerPC 601 specific instructions */
4916
4917 /* abs - abs. */
4918 static void gen_abs(DisasContext *ctx)
4919 {
4920 int l1 = gen_new_label();
4921 int l2 = gen_new_label();
4922 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4923 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4924 tcg_gen_br(l2);
4925 gen_set_label(l1);
4926 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4927 gen_set_label(l2);
4928 if (unlikely(Rc(ctx->opcode) != 0))
4929 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4930 }
4931
4932 /* abso - abso. */
4933 static void gen_abso(DisasContext *ctx)
4934 {
4935 int l1 = gen_new_label();
4936 int l2 = gen_new_label();
4937 int l3 = gen_new_label();
4938 /* Start with XER OV disabled, the most likely case */
4939 tcg_gen_movi_tl(cpu_ov, 0);
4940 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4941 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4942 tcg_gen_movi_tl(cpu_ov, 1);
4943 tcg_gen_movi_tl(cpu_so, 1);
4944 tcg_gen_br(l2);
4945 gen_set_label(l1);
4946 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4947 tcg_gen_br(l3);
4948 gen_set_label(l2);
4949 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4950 gen_set_label(l3);
4951 if (unlikely(Rc(ctx->opcode) != 0))
4952 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4953 }
4954
4955 /* clcs */
4956 static void gen_clcs(DisasContext *ctx)
4957 {
4958 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4959 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4960 tcg_temp_free_i32(t0);
4961 /* Rc=1 sets CR0 to an undefined state */
4962 }
4963
4964 /* div - div. */
4965 static void gen_div(DisasContext *ctx)
4966 {
4967 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4968 cpu_gpr[rB(ctx->opcode)]);
4969 if (unlikely(Rc(ctx->opcode) != 0))
4970 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4971 }
4972
4973 /* divo - divo. */
4974 static void gen_divo(DisasContext *ctx)
4975 {
4976 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4977 cpu_gpr[rB(ctx->opcode)]);
4978 if (unlikely(Rc(ctx->opcode) != 0))
4979 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4980 }
4981
4982 /* divs - divs. */
4983 static void gen_divs(DisasContext *ctx)
4984 {
4985 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4986 cpu_gpr[rB(ctx->opcode)]);
4987 if (unlikely(Rc(ctx->opcode) != 0))
4988 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4989 }
4990
4991 /* divso - divso. */
4992 static void gen_divso(DisasContext *ctx)
4993 {
4994 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4995 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4996 if (unlikely(Rc(ctx->opcode) != 0))
4997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4998 }
4999
5000 /* doz - doz. */
5001 static void gen_doz(DisasContext *ctx)
5002 {
5003 int l1 = gen_new_label();
5004 int l2 = gen_new_label();
5005 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5006 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5007 tcg_gen_br(l2);
5008 gen_set_label(l1);
5009 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5010 gen_set_label(l2);
5011 if (unlikely(Rc(ctx->opcode) != 0))
5012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5013 }
5014
5015 /* dozo - dozo. */
5016 static void gen_dozo(DisasContext *ctx)
5017 {
5018 int l1 = gen_new_label();
5019 int l2 = gen_new_label();
5020 TCGv t0 = tcg_temp_new();
5021 TCGv t1 = tcg_temp_new();
5022 TCGv t2 = tcg_temp_new();
5023 /* Start with XER OV disabled, the most likely case */
5024 tcg_gen_movi_tl(cpu_ov, 0);
5025 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5026 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5027 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5028 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5029 tcg_gen_andc_tl(t1, t1, t2);
5030 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5031 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5032 tcg_gen_movi_tl(cpu_ov, 1);
5033 tcg_gen_movi_tl(cpu_so, 1);
5034 tcg_gen_br(l2);
5035 gen_set_label(l1);
5036 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5037 gen_set_label(l2);
5038 tcg_temp_free(t0);
5039 tcg_temp_free(t1);
5040 tcg_temp_free(t2);
5041 if (unlikely(Rc(ctx->opcode) != 0))
5042 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5043 }
5044
5045 /* dozi */
5046 static void gen_dozi(DisasContext *ctx)
5047 {
5048 target_long simm = SIMM(ctx->opcode);
5049 int l1 = gen_new_label();
5050 int l2 = gen_new_label();
5051 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5052 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5053 tcg_gen_br(l2);
5054 gen_set_label(l1);
5055 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5056 gen_set_label(l2);
5057 if (unlikely(Rc(ctx->opcode) != 0))
5058 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5059 }
5060
5061 /* lscbx - lscbx. */
5062 static void gen_lscbx(DisasContext *ctx)
5063 {
5064 TCGv t0 = tcg_temp_new();
5065 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5066 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5067 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5068
5069 gen_addr_reg_index(ctx, t0);
5070 /* NIP cannot be restored if the memory exception comes from an helper */
5071 gen_update_nip(ctx, ctx->nip - 4);
5072 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5073 tcg_temp_free_i32(t1);
5074 tcg_temp_free_i32(t2);
5075 tcg_temp_free_i32(t3);
5076 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5077 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5078 if (unlikely(Rc(ctx->opcode) != 0))
5079 gen_set_Rc0(ctx, t0);
5080 tcg_temp_free(t0);
5081 }
5082
5083 /* maskg - maskg. */
5084 static void gen_maskg(DisasContext *ctx)
5085 {
5086 int l1 = gen_new_label();
5087 TCGv t0 = tcg_temp_new();
5088 TCGv t1 = tcg_temp_new();
5089 TCGv t2 = tcg_temp_new();
5090 TCGv t3 = tcg_temp_new();
5091 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5092 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5093 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5094 tcg_gen_addi_tl(t2, t0, 1);
5095 tcg_gen_shr_tl(t2, t3, t2);
5096 tcg_gen_shr_tl(t3, t3, t1);
5097 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5098 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5099 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5100 gen_set_label(l1);
5101 tcg_temp_free(t0);
5102 tcg_temp_free(t1);
5103 tcg_temp_free(t2);
5104 tcg_temp_free(t3);
5105 if (unlikely(Rc(ctx->opcode) != 0))
5106 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5107 }
5108
5109 /* maskir - maskir. */
5110 static void gen_maskir(DisasContext *ctx)
5111 {
5112 TCGv t0 = tcg_temp_new();
5113 TCGv t1 = tcg_temp_new();
5114 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5115 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5116 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5121 }
5122
5123 /* mul - mul. */
5124 static void gen_mul(DisasContext *ctx)
5125 {
5126 TCGv_i64 t0 = tcg_temp_new_i64();
5127 TCGv_i64 t1 = tcg_temp_new_i64();
5128 TCGv t2 = tcg_temp_new();
5129 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5130 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5131 tcg_gen_mul_i64(t0, t0, t1);
5132 tcg_gen_trunc_i64_tl(t2, t0);
5133 gen_store_spr(SPR_MQ, t2);
5134 tcg_gen_shri_i64(t1, t0, 32);
5135 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5136 tcg_temp_free_i64(t0);
5137 tcg_temp_free_i64(t1);
5138 tcg_temp_free(t2);
5139 if (unlikely(Rc(ctx->opcode) != 0))
5140 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5141 }
5142
5143 /* mulo - mulo. */
5144 static void gen_mulo(DisasContext *ctx)
5145 {
5146 int l1 = gen_new_label();
5147 TCGv_i64 t0 = tcg_temp_new_i64();
5148 TCGv_i64 t1 = tcg_temp_new_i64();
5149 TCGv t2 = tcg_temp_new();
5150 /* Start with XER OV disabled, the most likely case */
5151 tcg_gen_movi_tl(cpu_ov, 0);
5152 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5153 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5154 tcg_gen_mul_i64(t0, t0, t1);
5155 tcg_gen_trunc_i64_tl(t2, t0);
5156 gen_store_spr(SPR_MQ, t2);
5157 tcg_gen_shri_i64(t1, t0, 32);
5158 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5159 tcg_gen_ext32s_i64(t1, t0);
5160 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5161 tcg_gen_movi_tl(cpu_ov, 1);
5162 tcg_gen_movi_tl(cpu_so, 1);
5163 gen_set_label(l1);
5164 tcg_temp_free_i64(t0);
5165 tcg_temp_free_i64(t1);
5166 tcg_temp_free(t2);
5167 if (unlikely(Rc(ctx->opcode) != 0))
5168 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5169 }
5170
5171 /* nabs - nabs. */
5172 static void gen_nabs(DisasContext *ctx)
5173 {
5174 int l1 = gen_new_label();
5175 int l2 = gen_new_label();
5176 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5177 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5178 tcg_gen_br(l2);
5179 gen_set_label(l1);
5180 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5181 gen_set_label(l2);
5182 if (unlikely(Rc(ctx->opcode) != 0))
5183 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5184 }
5185
5186 /* nabso - nabso. */
5187 static void gen_nabso(DisasContext *ctx)
5188 {
5189 int l1 = gen_new_label();
5190 int l2 = gen_new_label();
5191 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5192 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5193 tcg_gen_br(l2);
5194 gen_set_label(l1);
5195 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5196 gen_set_label(l2);
5197 /* nabs never overflows */
5198 tcg_gen_movi_tl(cpu_ov, 0);
5199 if (unlikely(Rc(ctx->opcode) != 0))
5200 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5201 }
5202
5203 /* rlmi - rlmi. */
5204 static void gen_rlmi(DisasContext *ctx)
5205 {
5206 uint32_t mb = MB(ctx->opcode);
5207 uint32_t me = ME(ctx->opcode);
5208 TCGv t0 = tcg_temp_new();
5209 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5210 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5211 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5212 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5213 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5214 tcg_temp_free(t0);
5215 if (unlikely(Rc(ctx->opcode) != 0))
5216 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5217 }
5218
5219 /* rrib - rrib. */
5220 static void gen_rrib(DisasContext *ctx)
5221 {
5222 TCGv t0 = tcg_temp_new();
5223 TCGv t1 = tcg_temp_new();
5224 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5225 tcg_gen_movi_tl(t1, 0x80000000);
5226 tcg_gen_shr_tl(t1, t1, t0);
5227 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5228 tcg_gen_and_tl(t0, t0, t1);
5229 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5230 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5231 tcg_temp_free(t0);
5232 tcg_temp_free(t1);
5233 if (unlikely(Rc(ctx->opcode) != 0))
5234 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5235 }
5236
5237 /* sle - sle. */
5238 static void gen_sle(DisasContext *ctx)
5239 {
5240 TCGv t0 = tcg_temp_new();
5241 TCGv t1 = tcg_temp_new();
5242 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5243 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5244 tcg_gen_subfi_tl(t1, 32, t1);
5245 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5246 tcg_gen_or_tl(t1, t0, t1);
5247 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5248 gen_store_spr(SPR_MQ, t1);
5249 tcg_temp_free(t0);
5250 tcg_temp_free(t1);
5251 if (unlikely(Rc(ctx->opcode) != 0))
5252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5253 }
5254
5255 /* sleq - sleq. */
5256 static void gen_sleq(DisasContext *ctx)
5257 {
5258 TCGv t0 = tcg_temp_new();
5259 TCGv t1 = tcg_temp_new();
5260 TCGv t2 = tcg_temp_new();
5261 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5262 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5263 tcg_gen_shl_tl(t2, t2, t0);
5264 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5265 gen_load_spr(t1, SPR_MQ);
5266 gen_store_spr(SPR_MQ, t0);
5267 tcg_gen_and_tl(t0, t0, t2);
5268 tcg_gen_andc_tl(t1, t1, t2);
5269 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5270 tcg_temp_free(t0);
5271 tcg_temp_free(t1);
5272 tcg_temp_free(t2);
5273 if (unlikely(Rc(ctx->opcode) != 0))
5274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5275 }
5276
5277 /* sliq - sliq. */
5278 static void gen_sliq(DisasContext *ctx)
5279 {
5280 int sh = SH(ctx->opcode);
5281 TCGv t0 = tcg_temp_new();
5282 TCGv t1 = tcg_temp_new();
5283 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5284 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5285 tcg_gen_or_tl(t1, t0, t1);
5286 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5287 gen_store_spr(SPR_MQ, t1);
5288 tcg_temp_free(t0);
5289 tcg_temp_free(t1);
5290 if (unlikely(Rc(ctx->opcode) != 0))
5291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5292 }
5293
5294 /* slliq - slliq. */
5295 static void gen_slliq(DisasContext *ctx)
5296 {
5297 int sh = SH(ctx->opcode);
5298 TCGv t0 = tcg_temp_new();
5299 TCGv t1 = tcg_temp_new();
5300 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5301 gen_load_spr(t1, SPR_MQ);
5302 gen_store_spr(SPR_MQ, t0);
5303 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5304 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5305 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5306 tcg_temp_free(t0);
5307 tcg_temp_free(t1);
5308 if (unlikely(Rc(ctx->opcode) != 0))
5309 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5310 }
5311
5312 /* sllq - sllq. */
5313 static void gen_sllq(DisasContext *ctx)
5314 {
5315 int l1 = gen_new_label();
5316 int l2 = gen_new_label();
5317 TCGv t0 = tcg_temp_local_new();
5318 TCGv t1 = tcg_temp_local_new();
5319 TCGv t2 = tcg_temp_local_new();
5320 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5321 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5322 tcg_gen_shl_tl(t1, t1, t2);
5323 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5324 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5325 gen_load_spr(t0, SPR_MQ);
5326 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5327 tcg_gen_br(l2);
5328 gen_set_label(l1);
5329 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5330 gen_load_spr(t2, SPR_MQ);
5331 tcg_gen_andc_tl(t1, t2, t1);
5332 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5333 gen_set_label(l2);
5334 tcg_temp_free(t0);
5335 tcg_temp_free(t1);
5336 tcg_temp_free(t2);
5337 if (unlikely(Rc(ctx->opcode) != 0))
5338 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5339 }
5340
5341 /* slq - slq. */
5342 static void gen_slq(DisasContext *ctx)
5343 {
5344 int l1 = gen_new_label();
5345 TCGv t0 = tcg_temp_new();
5346 TCGv t1 = tcg_temp_new();
5347 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5348 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5349 tcg_gen_subfi_tl(t1, 32, t1);
5350 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5351 tcg_gen_or_tl(t1, t0, t1);
5352 gen_store_spr(SPR_MQ, t1);
5353 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5354 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5355 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5356 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5357 gen_set_label(l1);
5358 tcg_temp_free(t0);
5359 tcg_temp_free(t1);
5360 if (unlikely(Rc(ctx->opcode) != 0))
5361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5362 }
5363
5364 /* sraiq - sraiq. */
5365 static void gen_sraiq(DisasContext *ctx)
5366 {
5367 int sh = SH(ctx->opcode);
5368 int l1 = gen_new_label();
5369 TCGv t0 = tcg_temp_new();
5370 TCGv t1 = tcg_temp_new();
5371 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5372 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5373 tcg_gen_or_tl(t0, t0, t1);
5374 gen_store_spr(SPR_MQ, t0);
5375 tcg_gen_movi_tl(cpu_ca, 0);
5376 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5377 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5378 tcg_gen_movi_tl(cpu_ca, 1);
5379 gen_set_label(l1);
5380 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5381 tcg_temp_free(t0);
5382 tcg_temp_free(t1);
5383 if (unlikely(Rc(ctx->opcode) != 0))
5384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5385 }
5386
5387 /* sraq - sraq. */
5388 static void gen_sraq(DisasContext *ctx)
5389 {
5390 int l1 = gen_new_label();
5391 int l2 = gen_new_label();
5392 TCGv t0 = tcg_temp_new();
5393 TCGv t1 = tcg_temp_local_new();
5394 TCGv t2 = tcg_temp_local_new();
5395 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5396 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5397 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5398 tcg_gen_subfi_tl(t2, 32, t2);
5399 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5400 tcg_gen_or_tl(t0, t0, t2);
5401 gen_store_spr(SPR_MQ, t0);
5402 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5403 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5404 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5405 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5406 gen_set_label(l1);
5407 tcg_temp_free(t0);
5408 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5409 tcg_gen_movi_tl(cpu_ca, 0);
5410 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5411 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5412 tcg_gen_movi_tl(cpu_ca, 1);
5413 gen_set_label(l2);
5414 tcg_temp_free(t1);
5415 tcg_temp_free(t2);
5416 if (unlikely(Rc(ctx->opcode) != 0))
5417 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5418 }
5419
5420 /* sre - sre. */
5421 static void gen_sre(DisasContext *ctx)
5422 {
5423 TCGv t0 = tcg_temp_new();
5424 TCGv t1 = tcg_temp_new();
5425 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5426 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5427 tcg_gen_subfi_tl(t1, 32, t1);
5428 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5429 tcg_gen_or_tl(t1, t0, t1);
5430 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5431 gen_store_spr(SPR_MQ, t1);
5432 tcg_temp_free(t0);
5433 tcg_temp_free(t1);
5434 if (unlikely(Rc(ctx->opcode) != 0))
5435 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5436 }
5437
5438 /* srea - srea. */
5439 static void gen_srea(DisasContext *ctx)
5440 {
5441 TCGv t0 = tcg_temp_new();
5442 TCGv t1 = tcg_temp_new();
5443 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5444 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5445 gen_store_spr(SPR_MQ, t0);
5446 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5447 tcg_temp_free(t0);
5448 tcg_temp_free(t1);
5449 if (unlikely(Rc(ctx->opcode) != 0))
5450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5451 }
5452
5453 /* sreq */
5454 static void gen_sreq(DisasContext *ctx)
5455 {
5456 TCGv t0 = tcg_temp_new();
5457 TCGv t1 = tcg_temp_new();
5458 TCGv t2 = tcg_temp_new();
5459 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5460 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5461 tcg_gen_shr_tl(t1, t1, t0);
5462 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5463 gen_load_spr(t2, SPR_MQ);
5464 gen_store_spr(SPR_MQ, t0);
5465 tcg_gen_and_tl(t0, t0, t1);
5466 tcg_gen_andc_tl(t2, t2, t1);
5467 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5468 tcg_temp_free(t0);
5469 tcg_temp_free(t1);
5470 tcg_temp_free(t2);
5471 if (unlikely(Rc(ctx->opcode) != 0))
5472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5473 }
5474
5475 /* sriq */
5476 static void gen_sriq(DisasContext *ctx)
5477 {
5478 int sh = SH(ctx->opcode);
5479 TCGv t0 = tcg_temp_new();
5480 TCGv t1 = tcg_temp_new();
5481 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5482 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5483 tcg_gen_or_tl(t1, t0, t1);
5484 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5485 gen_store_spr(SPR_MQ, t1);
5486 tcg_temp_free(t0);
5487 tcg_temp_free(t1);
5488 if (unlikely(Rc(ctx->opcode) != 0))
5489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5490 }
5491
5492 /* srliq */
5493 static void gen_srliq(DisasContext *ctx)
5494 {
5495 int sh = SH(ctx->opcode);
5496 TCGv t0 = tcg_temp_new();
5497 TCGv t1 = tcg_temp_new();
5498 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5499 gen_load_spr(t1, SPR_MQ);
5500 gen_store_spr(SPR_MQ, t0);
5501 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5502 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5503 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5504 tcg_temp_free(t0);
5505 tcg_temp_free(t1);
5506 if (unlikely(Rc(ctx->opcode) != 0))
5507 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5508 }
5509
5510 /* srlq */
5511 static void gen_srlq(DisasContext *ctx)
5512 {
5513 int l1 = gen_new_label();
5514 int l2 = gen_new_label();
5515 TCGv t0 = tcg_temp_local_new();
5516 TCGv t1 = tcg_temp_local_new();
5517 TCGv t2 = tcg_temp_local_new();
5518 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5519 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5520 tcg_gen_shr_tl(t2, t1, t2);
5521 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5522 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5523 gen_load_spr(t0, SPR_MQ);
5524 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5525 tcg_gen_br(l2);
5526 gen_set_label(l1);
5527 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5528 tcg_gen_and_tl(t0, t0, t2);
5529 gen_load_spr(t1, SPR_MQ);
5530 tcg_gen_andc_tl(t1, t1, t2);
5531 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5532 gen_set_label(l2);
5533 tcg_temp_free(t0);
5534 tcg_temp_free(t1);
5535 tcg_temp_free(t2);
5536 if (unlikely(Rc(ctx->opcode) != 0))
5537 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5538 }
5539
5540 /* srq */
5541 static void gen_srq(DisasContext *ctx)
5542 {
5543 int l1 = gen_new_label();
5544 TCGv t0 = tcg_temp_new();
5545 TCGv t1 = tcg_temp_new();
5546 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5547 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5548 tcg_gen_subfi_tl(t1, 32, t1);
5549 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5550 tcg_gen_or_tl(t1, t0, t1);
5551 gen_store_spr(SPR_MQ, t1);
5552 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5553 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5554 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5555 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5556 gen_set_label(l1);
5557 tcg_temp_free(t0);
5558 tcg_temp_free(t1);
5559 if (unlikely(Rc(ctx->opcode) != 0))
5560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5561 }
5562
5563 /* PowerPC 602 specific instructions */
5564
5565 /* dsa */
5566 static void gen_dsa(DisasContext *ctx)
5567 {
5568 /* XXX: TODO */
5569 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5570 }
5571
5572 /* esa */
5573 static void gen_esa(DisasContext *ctx)
5574 {
5575 /* XXX: TODO */
5576 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5577 }
5578
5579 /* mfrom */
5580 static void gen_mfrom(DisasContext *ctx)
5581 {
5582 #if defined(CONFIG_USER_ONLY)
5583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5584 #else
5585 if (unlikely(ctx->pr)) {
5586 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5587 return;
5588 }
5589 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5590 #endif
5591 }
5592
5593 /* 602 - 603 - G2 TLB management */
5594
5595 /* tlbld */
5596 static void gen_tlbld_6xx(DisasContext *ctx)
5597 {
5598 #if defined(CONFIG_USER_ONLY)
5599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5600 #else
5601 if (unlikely(ctx->pr)) {
5602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5603 return;
5604 }
5605 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5606 #endif
5607 }
5608
5609 /* tlbli */
5610 static void gen_tlbli_6xx(DisasContext *ctx)
5611 {
5612 #if defined(CONFIG_USER_ONLY)
5613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5614 #else
5615 if (unlikely(ctx->pr)) {
5616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5617 return;
5618 }
5619 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5620 #endif
5621 }
5622
5623 /* 74xx TLB management */
5624
5625 /* tlbld */
5626 static void gen_tlbld_74xx(DisasContext *ctx)
5627 {
5628 #if defined(CONFIG_USER_ONLY)
5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5630 #else
5631 if (unlikely(ctx->pr)) {
5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5633 return;
5634 }
5635 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5636 #endif
5637 }
5638
5639 /* tlbli */
5640 static void gen_tlbli_74xx(DisasContext *ctx)
5641 {
5642 #if defined(CONFIG_USER_ONLY)
5643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5644 #else
5645 if (unlikely(ctx->pr)) {
5646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5647 return;
5648 }
5649 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5650 #endif
5651 }
5652
5653 /* POWER instructions not in PowerPC 601 */
5654
5655 /* clf */
5656 static void gen_clf(DisasContext *ctx)
5657 {
5658 /* Cache line flush: implemented as no-op */
5659 }
5660
5661 /* cli */
5662 static void gen_cli(DisasContext *ctx)
5663 {
5664 /* Cache line invalidate: privileged and treated as no-op */
5665 #if defined(CONFIG_USER_ONLY)
5666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5667 #else
5668 if (unlikely(ctx->pr)) {
5669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5670 return;
5671 }
5672 #endif
5673 }
5674
5675 /* dclst */
5676 static void gen_dclst(DisasContext *ctx)
5677 {
5678 /* Data cache line store: treated as no-op */
5679 }
5680
5681 static void gen_mfsri(DisasContext *ctx)
5682 {
5683 #if defined(CONFIG_USER_ONLY)
5684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5685 #else
5686 int ra = rA(ctx->opcode);
5687 int rd = rD(ctx->opcode);
5688 TCGv t0;
5689 if (unlikely(ctx->pr)) {
5690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5691 return;
5692 }
5693 t0 = tcg_temp_new();
5694 gen_addr_reg_index(ctx, t0);
5695 tcg_gen_shri_tl(t0, t0, 28);
5696 tcg_gen_andi_tl(t0, t0, 0xF);
5697 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5698 tcg_temp_free(t0);
5699 if (ra != 0 && ra != rd)
5700 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5701 #endif
5702 }
5703
5704 static void gen_rac(DisasContext *ctx)
5705 {
5706 #if defined(CONFIG_USER_ONLY)
5707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5708 #else
5709 TCGv t0;
5710 if (unlikely(ctx->pr)) {
5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5712 return;
5713 }
5714 t0 = tcg_temp_new();
5715 gen_addr_reg_index(ctx, t0);
5716 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5717 tcg_temp_free(t0);
5718 #endif
5719 }
5720
5721 static void gen_rfsvc(DisasContext *ctx)
5722 {
5723 #if defined(CONFIG_USER_ONLY)
5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5725 #else
5726 if (unlikely(ctx->pr)) {
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5728 return;
5729 }
5730 gen_helper_rfsvc(cpu_env);
5731 gen_sync_exception(ctx);
5732 #endif
5733 }
5734
5735 /* svc is not implemented for now */
5736
5737 /* POWER2 specific instructions */
5738 /* Quad manipulation (load/store two floats at a time) */
5739
5740 /* lfq */
5741 static void gen_lfq(DisasContext *ctx)
5742 {
5743 int rd = rD(ctx->opcode);
5744 TCGv t0;
5745 gen_set_access_type(ctx, ACCESS_FLOAT);
5746 t0 = tcg_temp_new();
5747 gen_addr_imm_index(ctx, t0, 0);
5748 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5749 gen_addr_add(ctx, t0, t0, 8);
5750 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5751 tcg_temp_free(t0);
5752 }
5753
5754 /* lfqu */
5755 static void gen_lfqu(DisasContext *ctx)
5756 {
5757 int ra = rA(ctx->opcode);
5758 int rd = rD(ctx->opcode);
5759 TCGv t0, t1;
5760 gen_set_access_type(ctx, ACCESS_FLOAT);
5761 t0 = tcg_temp_new();
5762 t1 = tcg_temp_new();
5763 gen_addr_imm_index(ctx, t0, 0);
5764 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5765 gen_addr_add(ctx, t1, t0, 8);
5766 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5767 if (ra != 0)
5768 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5769 tcg_temp_free(t0);
5770 tcg_temp_free(t1);
5771 }
5772
5773 /* lfqux */
5774 static void gen_lfqux(DisasContext *ctx)
5775 {
5776 int ra = rA(ctx->opcode);
5777 int rd = rD(ctx->opcode);
5778 gen_set_access_type(ctx, ACCESS_FLOAT);
5779 TCGv t0, t1;
5780 t0 = tcg_temp_new();
5781 gen_addr_reg_index(ctx, t0);
5782 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5783 t1 = tcg_temp_new();
5784 gen_addr_add(ctx, t1, t0, 8);
5785 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5786 tcg_temp_free(t1);
5787 if (ra != 0)
5788 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5789 tcg_temp_free(t0);
5790 }
5791
5792 /* lfqx */
5793 static void gen_lfqx(DisasContext *ctx)
5794 {
5795 int rd = rD(ctx->opcode);
5796 TCGv t0;
5797 gen_set_access_type(ctx, ACCESS_FLOAT);
5798 t0 = tcg_temp_new();
5799 gen_addr_reg_index(ctx, t0);
5800 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5801 gen_addr_add(ctx, t0, t0, 8);
5802 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5803 tcg_temp_free(t0);
5804 }
5805
5806 /* stfq */
5807 static void gen_stfq(DisasContext *ctx)
5808 {
5809 int rd = rD(ctx->opcode);
5810 TCGv t0;
5811 gen_set_access_type(ctx, ACCESS_FLOAT);
5812 t0 = tcg_temp_new();
5813 gen_addr_imm_index(ctx, t0, 0);
5814 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5815 gen_addr_add(ctx, t0, t0, 8);
5816 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5817 tcg_temp_free(t0);
5818 }
5819
5820 /* stfqu */
5821 static void gen_stfqu(DisasContext *ctx)
5822 {
5823 int ra = rA(ctx->opcode);
5824 int rd = rD(ctx->opcode);
5825 TCGv t0, t1;
5826 gen_set_access_type(ctx, ACCESS_FLOAT);
5827 t0 = tcg_temp_new();
5828 gen_addr_imm_index(ctx, t0, 0);
5829 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5830 t1 = tcg_temp_new();
5831 gen_addr_add(ctx, t1, t0, 8);
5832 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5833 tcg_temp_free(t1);
5834 if (ra != 0)
5835 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5836 tcg_temp_free(t0);
5837 }
5838
5839 /* stfqux */
5840 static void gen_stfqux(DisasContext *ctx)
5841 {
5842 int ra = rA(ctx->opcode);
5843 int rd = rD(ctx->opcode);
5844 TCGv t0, t1;
5845 gen_set_access_type(ctx, ACCESS_FLOAT);
5846 t0 = tcg_temp_new();
5847 gen_addr_reg_index(ctx, t0);
5848 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5849 t1 = tcg_temp_new();
5850 gen_addr_add(ctx, t1, t0, 8);
5851 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5852 tcg_temp_free(t1);
5853 if (ra != 0)
5854 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5855 tcg_temp_free(t0);
5856 }
5857
5858 /* stfqx */
5859 static void gen_stfqx(DisasContext *ctx)
5860 {
5861 int rd = rD(ctx->opcode);
5862 TCGv t0;
5863 gen_set_access_type(ctx, ACCESS_FLOAT);
5864 t0 = tcg_temp_new();
5865 gen_addr_reg_index(ctx, t0);
5866 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5867 gen_addr_add(ctx, t0, t0, 8);
5868 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5869 tcg_temp_free(t0);
5870 }
5871
5872 /* BookE specific instructions */
5873
5874 /* XXX: not implemented on 440 ? */
5875 static void gen_mfapidi(DisasContext *ctx)
5876 {
5877 /* XXX: TODO */
5878 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5879 }
5880
5881 /* XXX: not implemented on 440 ? */
5882 static void gen_tlbiva(DisasContext *ctx)
5883 {
5884 #if defined(CONFIG_USER_ONLY)
5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5886 #else
5887 TCGv t0;
5888 if (unlikely(ctx->pr)) {
5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5890 return;
5891 }
5892 t0 = tcg_temp_new();
5893 gen_addr_reg_index(ctx, t0);
5894 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5895 tcg_temp_free(t0);
5896 #endif
5897 }
5898
5899 /* All 405 MAC instructions are translated here */
5900 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5901 int ra, int rb, int rt, int Rc)
5902 {
5903 TCGv t0, t1;
5904
5905 t0 = tcg_temp_local_new();
5906 t1 = tcg_temp_local_new();
5907
5908 switch (opc3 & 0x0D) {
5909 case 0x05:
5910 /* macchw - macchw. - macchwo - macchwo. */
5911 /* macchws - macchws. - macchwso - macchwso. */
5912 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5913 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5914 /* mulchw - mulchw. */
5915 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5916 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5917 tcg_gen_ext16s_tl(t1, t1);
5918 break;
5919 case 0x04:
5920 /* macchwu - macchwu. - macchwuo - macchwuo. */
5921 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5922 /* mulchwu - mulchwu. */
5923 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5924 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5925 tcg_gen_ext16u_tl(t1, t1);
5926 break;
5927 case 0x01:
5928 /* machhw - machhw. - machhwo - machhwo. */
5929 /* machhws - machhws. - machhwso - machhwso. */
5930 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5931 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5932 /* mulhhw - mulhhw. */
5933 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5934 tcg_gen_ext16s_tl(t0, t0);
5935 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5936 tcg_gen_ext16s_tl(t1, t1);
5937 break;
5938 case 0x00:
5939 /* machhwu - machhwu. - machhwuo - machhwuo. */
5940 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5941 /* mulhhwu - mulhhwu. */
5942 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5943 tcg_gen_ext16u_tl(t0, t0);
5944 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5945 tcg_gen_ext16u_tl(t1, t1);
5946 break;
5947 case 0x0D:
5948 /* maclhw - maclhw. - maclhwo - maclhwo. */
5949 /* maclhws - maclhws. - maclhwso - maclhwso. */
5950 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5951 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5952 /* mullhw - mullhw. */
5953 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5954 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5955 break;
5956 case 0x0C:
5957 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5958 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5959 /* mullhwu - mullhwu. */
5960 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5961 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5962 break;
5963 }
5964 if (opc2 & 0x04) {
5965 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5966 tcg_gen_mul_tl(t1, t0, t1);
5967 if (opc2 & 0x02) {
5968 /* nmultiply-and-accumulate (0x0E) */
5969 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5970 } else {
5971 /* multiply-and-accumulate (0x0C) */
5972 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5973 }
5974
5975 if (opc3 & 0x12) {
5976 /* Check overflow and/or saturate */
5977 int l1 = gen_new_label();
5978
5979 if (opc3 & 0x10) {
5980 /* Start with XER OV disabled, the most likely case */
5981 tcg_gen_movi_tl(cpu_ov, 0);
5982 }
5983 if (opc3 & 0x01) {
5984 /* Signed */
5985 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5986 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5987 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5988 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5989 if (opc3 & 0x02) {
5990 /* Saturate */
5991 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5992 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5993 }
5994 } else {
5995 /* Unsigned */
5996 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5997 if (opc3 & 0x02) {
5998 /* Saturate */
5999 tcg_gen_movi_tl(t0, UINT32_MAX);
6000 }
6001 }
6002 if (opc3 & 0x10) {
6003 /* Check overflow */
6004 tcg_gen_movi_tl(cpu_ov, 1);
6005 tcg_gen_movi_tl(cpu_so, 1);
6006 }
6007 gen_set_label(l1);
6008 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6009 }
6010 } else {
6011 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6012 }
6013 tcg_temp_free(t0);
6014 tcg_temp_free(t1);
6015 if (unlikely(Rc) != 0) {
6016 /* Update Rc0 */
6017 gen_set_Rc0(ctx, cpu_gpr[rt]);
6018 }
6019 }
6020
6021 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6022 static void glue(gen_, name)(DisasContext *ctx) \
6023 { \
6024 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6025 rD(ctx->opcode), Rc(ctx->opcode)); \
6026 }
6027
6028 /* macchw - macchw. */
6029 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6030 /* macchwo - macchwo. */
6031 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6032 /* macchws - macchws. */
6033 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6034 /* macchwso - macchwso. */
6035 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6036 /* macchwsu - macchwsu. */
6037 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6038 /* macchwsuo - macchwsuo. */
6039 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6040 /* macchwu - macchwu. */
6041 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6042 /* macchwuo - macchwuo. */
6043 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6044 /* machhw - machhw. */
6045 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6046 /* machhwo - machhwo. */
6047 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6048 /* machhws - machhws. */
6049 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6050 /* machhwso - machhwso. */
6051 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6052 /* machhwsu - machhwsu. */
6053 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6054 /* machhwsuo - machhwsuo. */
6055 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6056 /* machhwu - machhwu. */
6057 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6058 /* machhwuo - machhwuo. */
6059 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6060 /* maclhw - maclhw. */
6061 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6062 /* maclhwo - maclhwo. */
6063 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6064 /* maclhws - maclhws. */
6065 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6066 /* maclhwso - maclhwso. */
6067 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6068 /* maclhwu - maclhwu. */
6069 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6070 /* maclhwuo - maclhwuo. */
6071 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6072 /* maclhwsu - maclhwsu. */
6073 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6074 /* maclhwsuo - maclhwsuo. */
6075 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6076 /* nmacchw - nmacchw. */
6077 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6078 /* nmacchwo - nmacchwo. */
6079 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6080 /* nmacchws - nmacchws. */
6081 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6082 /* nmacchwso - nmacchwso. */
6083 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6084 /* nmachhw - nmachhw. */
6085 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6086 /* nmachhwo - nmachhwo. */
6087 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6088 /* nmachhws - nmachhws. */
6089 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6090 /* nmachhwso - nmachhwso. */
6091 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6092 /* nmaclhw - nmaclhw. */
6093 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6094 /* nmaclhwo - nmaclhwo. */
6095 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6096 /* nmaclhws - nmaclhws. */
6097 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6098 /* nmaclhwso - nmaclhwso. */
6099 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6100
6101 /* mulchw - mulchw. */
6102 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6103 /* mulchwu - mulchwu. */
6104 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6105 /* mulhhw - mulhhw. */
6106 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6107 /* mulhhwu - mulhhwu. */
6108 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6109 /* mullhw - mullhw. */
6110 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6111 /* mullhwu - mullhwu. */
6112 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6113
6114 /* mfdcr */
6115 static void gen_mfdcr(DisasContext *ctx)
6116 {
6117 #if defined(CONFIG_USER_ONLY)
6118 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6119 #else
6120 TCGv dcrn;
6121 if (unlikely(ctx->pr)) {
6122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6123 return;
6124 }
6125 /* NIP cannot be restored if the memory exception comes from an helper */
6126 gen_update_nip(ctx, ctx->nip - 4);
6127 dcrn = tcg_const_tl(SPR(ctx->opcode));
6128 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6129 tcg_temp_free(dcrn);
6130 #endif
6131 }
6132
6133 /* mtdcr */
6134 static void gen_mtdcr(DisasContext *ctx)
6135 {
6136 #if defined(CONFIG_USER_ONLY)
6137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6138 #else
6139 TCGv dcrn;
6140 if (unlikely(ctx->pr)) {
6141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6142 return;
6143 }
6144 /* NIP cannot be restored if the memory exception comes from an helper */
6145 gen_update_nip(ctx, ctx->nip - 4);
6146 dcrn = tcg_const_tl(SPR(ctx->opcode));
6147 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6148 tcg_temp_free(dcrn);
6149 #endif
6150 }
6151
6152 /* mfdcrx */
6153 /* XXX: not implemented on 440 ? */
6154 static void gen_mfdcrx(DisasContext *ctx)
6155 {
6156 #if defined(CONFIG_USER_ONLY)
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6158 #else
6159 if (unlikely(ctx->pr)) {
6160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6161 return;
6162 }
6163 /* NIP cannot be restored if the memory exception comes from an helper */
6164 gen_update_nip(ctx, ctx->nip - 4);
6165 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6166 cpu_gpr[rA(ctx->opcode)]);
6167 /* Note: Rc update flag set leads to undefined state of Rc0 */
6168 #endif
6169 }
6170
6171 /* mtdcrx */
6172 /* XXX: not implemented on 440 ? */
6173 static void gen_mtdcrx(DisasContext *ctx)
6174 {
6175 #if defined(CONFIG_USER_ONLY)
6176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6177 #else
6178 if (unlikely(ctx->pr)) {
6179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6180 return;
6181 }
6182 /* NIP cannot be restored if the memory exception comes from an helper */
6183 gen_update_nip(ctx, ctx->nip - 4);
6184 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6185 cpu_gpr[rS(ctx->opcode)]);
6186 /* Note: Rc update flag set leads to undefined state of Rc0 */
6187 #endif
6188 }
6189
6190 /* mfdcrux (PPC 460) : user-mode access to DCR */
6191 static void gen_mfdcrux(DisasContext *ctx)
6192 {
6193 /* NIP cannot be restored if the memory exception comes from an helper */
6194 gen_update_nip(ctx, ctx->nip - 4);
6195 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6196 cpu_gpr[rA(ctx->opcode)]);
6197 /* Note: Rc update flag set leads to undefined state of Rc0 */
6198 }
6199
6200 /* mtdcrux (PPC 460) : user-mode access to DCR */
6201 static void gen_mtdcrux(DisasContext *ctx)
6202 {
6203 /* NIP cannot be restored if the memory exception comes from an helper */
6204 gen_update_nip(ctx, ctx->nip - 4);
6205 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6206 cpu_gpr[rS(ctx->opcode)]);
6207 /* Note: Rc update flag set leads to undefined state of Rc0 */
6208 }
6209
6210 /* dccci */
6211 static void gen_dccci(DisasContext *ctx)
6212 {
6213 #if defined(CONFIG_USER_ONLY)
6214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6215 #else
6216 if (unlikely(ctx->pr)) {
6217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6218 return;
6219 }
6220 /* interpreted as no-op */
6221 #endif
6222 }
6223
6224 /* dcread */
6225 static void gen_dcread(DisasContext *ctx)
6226 {
6227 #if defined(CONFIG_USER_ONLY)
6228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6229 #else
6230 TCGv EA, val;
6231 if (unlikely(ctx->pr)) {
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 return;
6234 }
6235 gen_set_access_type(ctx, ACCESS_CACHE);
6236 EA = tcg_temp_new();
6237 gen_addr_reg_index(ctx, EA);
6238 val = tcg_temp_new();
6239 gen_qemu_ld32u(ctx, val, EA);
6240 tcg_temp_free(val);
6241 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6242 tcg_temp_free(EA);
6243 #endif
6244 }
6245
6246 /* icbt */
6247 static void gen_icbt_40x(DisasContext *ctx)
6248 {
6249 /* interpreted as no-op */
6250 /* XXX: specification say this is treated as a load by the MMU
6251 * but does not generate any exception
6252 */
6253 }
6254
6255 /* iccci */
6256 static void gen_iccci(DisasContext *ctx)
6257 {
6258 #if defined(CONFIG_USER_ONLY)
6259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6260 #else
6261 if (unlikely(ctx->pr)) {
6262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6263 return;
6264 }
6265 /* interpreted as no-op */
6266 #endif
6267 }
6268
6269 /* icread */
6270 static void gen_icread(DisasContext *ctx)
6271 {
6272 #if defined(CONFIG_USER_ONLY)
6273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6274 #else
6275 if (unlikely(ctx->pr)) {
6276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6277 return;
6278 }
6279 /* interpreted as no-op */
6280 #endif
6281 }
6282
6283 /* rfci (supervisor only) */
6284 static void gen_rfci_40x(DisasContext *ctx)
6285 {
6286 #if defined(CONFIG_USER_ONLY)
6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6288 #else
6289 if (unlikely(ctx->pr)) {
6290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6291 return;
6292 }
6293 /* Restore CPU state */
6294 gen_helper_40x_rfci(cpu_env);
6295 gen_sync_exception(ctx);
6296 #endif
6297 }
6298
6299 static void gen_rfci(DisasContext *ctx)
6300 {
6301 #if defined(CONFIG_USER_ONLY)
6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6303 #else
6304 if (unlikely(ctx->pr)) {
6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6306 return;
6307 }
6308 /* Restore CPU state */
6309 gen_helper_rfci(cpu_env);
6310 gen_sync_exception(ctx);
6311 #endif
6312 }
6313
6314 /* BookE specific */
6315
6316 /* XXX: not implemented on 440 ? */
6317 static void gen_rfdi(DisasContext *ctx)
6318 {
6319 #if defined(CONFIG_USER_ONLY)
6320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6321 #else
6322 if (unlikely(ctx->pr)) {
6323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6324 return;
6325 }
6326 /* Restore CPU state */
6327 gen_helper_rfdi(cpu_env);
6328 gen_sync_exception(ctx);
6329 #endif
6330 }
6331
6332 /* XXX: not implemented on 440 ? */
6333 static void gen_rfmci(DisasContext *ctx)
6334 {
6335 #if defined(CONFIG_USER_ONLY)
6336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6337 #else
6338 if (unlikely(ctx->pr)) {
6339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6340 return;
6341 }
6342 /* Restore CPU state */
6343 gen_helper_rfmci(cpu_env);
6344 gen_sync_exception(ctx);
6345 #endif
6346 }
6347
6348 /* TLB management - PowerPC 405 implementation */
6349
6350 /* tlbre */
6351 static void gen_tlbre_40x(DisasContext *ctx)
6352 {
6353 #if defined(CONFIG_USER_ONLY)
6354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6355 #else
6356 if (unlikely(ctx->pr)) {
6357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6358 return;
6359 }
6360 switch (rB(ctx->opcode)) {
6361 case 0:
6362 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6363 cpu_gpr[rA(ctx->opcode)]);
6364 break;
6365 case 1:
6366 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6367 cpu_gpr[rA(ctx->opcode)]);
6368 break;
6369 default:
6370 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6371 break;
6372 }
6373 #endif
6374 }
6375
6376 /* tlbsx - tlbsx. */
6377 static void gen_tlbsx_40x(DisasContext *ctx)
6378 {
6379 #if defined(CONFIG_USER_ONLY)
6380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6381 #else
6382 TCGv t0;
6383 if (unlikely(ctx->pr)) {
6384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6385 return;
6386 }
6387 t0 = tcg_temp_new();
6388 gen_addr_reg_index(ctx, t0);
6389 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6390 tcg_temp_free(t0);
6391 if (Rc(ctx->opcode)) {
6392 int l1 = gen_new_label();
6393 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6394 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6395 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6396 gen_set_label(l1);
6397 }
6398 #endif
6399 }
6400
6401 /* tlbwe */
6402 static void gen_tlbwe_40x(DisasContext *ctx)
6403 {
6404 #if defined(CONFIG_USER_ONLY)
6405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6406 #else
6407 if (unlikely(ctx->pr)) {
6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6409 return;
6410 }
6411 switch (rB(ctx->opcode)) {
6412 case 0:
6413 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6414 cpu_gpr[rS(ctx->opcode)]);
6415 break;
6416 case 1:
6417 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6418 cpu_gpr[rS(ctx->opcode)]);
6419 break;
6420 default:
6421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6422 break;
6423 }
6424 #endif
6425 }
6426
6427 /* TLB management - PowerPC 440 implementation */
6428
6429 /* tlbre */
6430 static void gen_tlbre_440(DisasContext *ctx)
6431 {
6432 #if defined(CONFIG_USER_ONLY)
6433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6434 #else
6435 if (unlikely(ctx->pr)) {
6436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6437 return;
6438 }
6439 switch (rB(ctx->opcode)) {
6440 case 0:
6441 case 1:
6442 case 2:
6443 {
6444 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6445 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6446 t0, cpu_gpr[rA(ctx->opcode)]);
6447 tcg_temp_free_i32(t0);
6448 }
6449 break;
6450 default:
6451 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6452 break;
6453 }
6454 #endif
6455 }
6456
6457 /* tlbsx - tlbsx. */
6458 static void gen_tlbsx_440(DisasContext *ctx)
6459 {
6460 #if defined(CONFIG_USER_ONLY)
6461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6462 #else
6463 TCGv t0;
6464 if (unlikely(ctx->pr)) {
6465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6466 return;
6467 }
6468 t0 = tcg_temp_new();
6469 gen_addr_reg_index(ctx, t0);
6470 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6471 tcg_temp_free(t0);
6472 if (Rc(ctx->opcode)) {
6473 int l1 = gen_new_label();
6474 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6475 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6476 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6477 gen_set_label(l1);
6478 }
6479 #endif
6480 }
6481
6482 /* tlbwe */
6483 static void gen_tlbwe_440(DisasContext *ctx)
6484 {
6485 #if defined(CONFIG_USER_ONLY)
6486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6487 #else
6488 if (unlikely(ctx->pr)) {
6489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6490 return;
6491 }
6492 switch (rB(ctx->opcode)) {
6493 case 0:
6494 case 1:
6495 case 2:
6496 {
6497 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6498 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6499 cpu_gpr[rS(ctx->opcode)]);
6500 tcg_temp_free_i32(t0);
6501 }
6502 break;
6503 default:
6504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6505 break;
6506 }
6507 #endif
6508 }
6509
6510 /* TLB management - PowerPC BookE 2.06 implementation */
6511
6512 /* tlbre */
6513 static void gen_tlbre_booke206(DisasContext *ctx)
6514 {
6515 #if defined(CONFIG_USER_ONLY)
6516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6517 #else
6518 if (unlikely(ctx->pr)) {
6519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6520 return;
6521 }
6522
6523 gen_helper_booke206_tlbre(cpu_env);
6524 #endif
6525 }
6526
6527 /* tlbsx - tlbsx. */
6528 static void gen_tlbsx_booke206(DisasContext *ctx)
6529 {
6530 #if defined(CONFIG_USER_ONLY)
6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6532 #else
6533 TCGv t0;
6534 if (unlikely(ctx->pr)) {
6535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6536 return;
6537 }
6538
6539 if (rA(ctx->opcode)) {
6540 t0 = tcg_temp_new();
6541 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6542 } else {
6543 t0 = tcg_const_tl(0);
6544 }
6545
6546 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6547 gen_helper_booke206_tlbsx(cpu_env, t0);
6548 tcg_temp_free(t0);
6549 #endif
6550 }
6551
6552 /* tlbwe */
6553 static void gen_tlbwe_booke206(DisasContext *ctx)
6554 {
6555 #if defined(CONFIG_USER_ONLY)
6556 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6557 #else
6558 if (unlikely(ctx->pr)) {
6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6560 return;
6561 }
6562 gen_update_nip(ctx, ctx->nip - 4);
6563 gen_helper_booke206_tlbwe(cpu_env);
6564 #endif
6565 }
6566
6567 static void gen_tlbivax_booke206(DisasContext *ctx)
6568 {
6569 #if defined(CONFIG_USER_ONLY)
6570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6571 #else
6572 TCGv t0;
6573 if (unlikely(ctx->pr)) {
6574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6575 return;
6576 }
6577
6578 t0 = tcg_temp_new();
6579 gen_addr_reg_index(ctx, t0);
6580
6581 gen_helper_booke206_tlbivax(cpu_env, t0);
6582 tcg_temp_free(t0);
6583 #endif
6584 }
6585
6586 static void gen_tlbilx_booke206(DisasContext *ctx)
6587 {
6588 #if defined(CONFIG_USER_ONLY)
6589 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6590 #else
6591 TCGv t0;
6592 if (unlikely(ctx->pr)) {
6593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6594 return;
6595 }
6596
6597 t0 = tcg_temp_new();
6598 gen_addr_reg_index(ctx, t0);
6599
6600 switch((ctx->opcode >> 21) & 0x3) {
6601 case 0:
6602 gen_helper_booke206_tlbilx0(cpu_env, t0);
6603 break;
6604 case 1:
6605 gen_helper_booke206_tlbilx1(cpu_env, t0);
6606 break;
6607 case 3:
6608 gen_helper_booke206_tlbilx3(cpu_env, t0);
6609 break;
6610 default:
6611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6612 break;
6613 }
6614
6615 tcg_temp_free(t0);
6616 #endif
6617 }
6618
6619
6620 /* wrtee */
6621 static void gen_wrtee(DisasContext *ctx)
6622 {
6623 #if defined(CONFIG_USER_ONLY)
6624 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6625 #else
6626 TCGv t0;
6627 if (unlikely(ctx->pr)) {
6628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6629 return;
6630 }
6631 t0 = tcg_temp_new();
6632 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6633 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6634 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6635 tcg_temp_free(t0);
6636 /* Stop translation to have a chance to raise an exception
6637 * if we just set msr_ee to 1
6638 */
6639 gen_stop_exception(ctx);
6640 #endif
6641 }
6642
6643 /* wrteei */
6644 static void gen_wrteei(DisasContext *ctx)
6645 {
6646 #if defined(CONFIG_USER_ONLY)
6647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6648 #else
6649 if (unlikely(ctx->pr)) {
6650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6651 return;
6652 }
6653 if (ctx->opcode & 0x00008000) {
6654 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6655 /* Stop translation to have a chance to raise an exception */
6656 gen_stop_exception(ctx);
6657 } else {
6658 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6659 }
6660 #endif
6661 }
6662
6663 /* PowerPC 440 specific instructions */
6664
6665 /* dlmzb */
6666 static void gen_dlmzb(DisasContext *ctx)
6667 {
6668 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6669 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6670 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6671 tcg_temp_free_i32(t0);
6672 }
6673
6674 /* mbar replaces eieio on 440 */
6675 static void gen_mbar(DisasContext *ctx)
6676 {
6677 /* interpreted as no-op */
6678 }
6679
6680 /* msync replaces sync on 440 */
6681 static void gen_msync_4xx(DisasContext *ctx)
6682 {
6683 /* interpreted as no-op */
6684 }
6685
6686 /* icbt */
6687 static void gen_icbt_440(DisasContext *ctx)
6688 {
6689 /* interpreted as no-op */
6690 /* XXX: specification say this is treated as a load by the MMU
6691 * but does not generate any exception
6692 */
6693 }
6694
6695 /* Embedded.Processor Control */
6696
6697 static void gen_msgclr(DisasContext *ctx)
6698 {
6699 #if defined(CONFIG_USER_ONLY)
6700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6701 #else
6702 if (unlikely(ctx->pr)) {
6703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6704 return;
6705 }
6706
6707 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6708 #endif
6709 }
6710
6711 static void gen_msgsnd(DisasContext *ctx)
6712 {
6713 #if defined(CONFIG_USER_ONLY)
6714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6715 #else
6716 if (unlikely(ctx->pr)) {
6717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6718 return;
6719 }
6720
6721 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6722 #endif
6723 }
6724
6725 /*** Altivec vector extension ***/
6726 /* Altivec registers moves */
6727
6728 static inline TCGv_ptr gen_avr_ptr(int reg)
6729 {
6730 TCGv_ptr r = tcg_temp_new_ptr();
6731 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6732 return r;
6733 }
6734
6735 #define GEN_VR_LDX(name, opc2, opc3) \
6736 static void glue(gen_, name)(DisasContext *ctx) \
6737 { \
6738 TCGv EA; \
6739 if (unlikely(!ctx->altivec_enabled)) { \
6740 gen_exception(ctx, POWERPC_EXCP_VPU); \
6741 return; \
6742 } \
6743 gen_set_access_type(ctx, ACCESS_INT); \
6744 EA = tcg_temp_new(); \
6745 gen_addr_reg_index(ctx, EA); \
6746 tcg_gen_andi_tl(EA, EA, ~0xf); \
6747 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6748 64-bit byteswap already. */ \
6749 if (ctx->le_mode) { \
6750 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6751 tcg_gen_addi_tl(EA, EA, 8); \
6752 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6753 } else { \
6754 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6755 tcg_gen_addi_tl(EA, EA, 8); \
6756 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6757 } \
6758 tcg_temp_free(EA); \
6759 }
6760
6761 #define GEN_VR_STX(name, opc2, opc3) \
6762 static void gen_st##name(DisasContext *ctx) \
6763 { \
6764 TCGv EA; \
6765 if (unlikely(!ctx->altivec_enabled)) { \
6766 gen_exception(ctx, POWERPC_EXCP_VPU); \
6767 return; \
6768 } \
6769 gen_set_access_type(ctx, ACCESS_INT); \
6770 EA = tcg_temp_new(); \
6771 gen_addr_reg_index(ctx, EA); \
6772 tcg_gen_andi_tl(EA, EA, ~0xf); \
6773 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6774 64-bit byteswap already. */ \
6775 if (ctx->le_mode) { \
6776 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6777 tcg_gen_addi_tl(EA, EA, 8); \
6778 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6779 } else { \
6780 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6781 tcg_gen_addi_tl(EA, EA, 8); \
6782 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6783 } \
6784 tcg_temp_free(EA); \
6785 }
6786
6787 #define GEN_VR_LVE(name, opc2, opc3, size) \
6788 static void gen_lve##name(DisasContext *ctx) \
6789 { \
6790 TCGv EA; \
6791 TCGv_ptr rs; \
6792 if (unlikely(!ctx->altivec_enabled)) { \
6793 gen_exception(ctx, POWERPC_EXCP_VPU); \
6794 return; \
6795 } \
6796 gen_set_access_type(ctx, ACCESS_INT); \
6797 EA = tcg_temp_new(); \
6798 gen_addr_reg_index(ctx, EA); \
6799 if (size > 1) { \
6800 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6801 } \
6802 rs = gen_avr_ptr(rS(ctx->opcode)); \
6803 gen_helper_lve##name(cpu_env, rs, EA); \
6804 tcg_temp_free(EA); \
6805 tcg_temp_free_ptr(rs); \
6806 }
6807
6808 #define GEN_VR_STVE(name, opc2, opc3, size) \
6809 static void gen_stve##name(DisasContext *ctx) \
6810 { \
6811 TCGv EA; \
6812 TCGv_ptr rs; \
6813 if (unlikely(!ctx->altivec_enabled)) { \
6814 gen_exception(ctx, POWERPC_EXCP_VPU); \
6815 return; \
6816 } \
6817 gen_set_access_type(ctx, ACCESS_INT); \
6818 EA = tcg_temp_new(); \
6819 gen_addr_reg_index(ctx, EA); \
6820 if (size > 1) { \
6821 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6822 } \
6823 rs = gen_avr_ptr(rS(ctx->opcode)); \
6824 gen_helper_stve##name(cpu_env, rs, EA); \
6825 tcg_temp_free(EA); \
6826 tcg_temp_free_ptr(rs); \
6827 }
6828
6829 GEN_VR_LDX(lvx, 0x07, 0x03);
6830 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6831 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6832
6833 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6834 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6835 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6836
6837 GEN_VR_STX(svx, 0x07, 0x07);
6838 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6839 GEN_VR_STX(svxl, 0x07, 0x0F);
6840
6841 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6842 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6843 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6844
6845 static void gen_lvsl(DisasContext *ctx)
6846 {
6847 TCGv_ptr rd;
6848 TCGv EA;
6849 if (unlikely(!ctx->altivec_enabled)) {
6850 gen_exception(ctx, POWERPC_EXCP_VPU);
6851 return;
6852 }
6853 EA = tcg_temp_new();
6854 gen_addr_reg_index(ctx, EA);
6855 rd = gen_avr_ptr(rD(ctx->opcode));
6856 gen_helper_lvsl(rd, EA);
6857 tcg_temp_free(EA);
6858 tcg_temp_free_ptr(rd);
6859 }
6860
6861 static void gen_lvsr(DisasContext *ctx)
6862 {
6863 TCGv_ptr rd;
6864 TCGv EA;
6865 if (unlikely(!ctx->altivec_enabled)) {
6866 gen_exception(ctx, POWERPC_EXCP_VPU);
6867 return;
6868 }
6869 EA = tcg_temp_new();
6870 gen_addr_reg_index(ctx, EA);
6871 rd = gen_avr_ptr(rD(ctx->opcode));
6872 gen_helper_lvsr(rd, EA);
6873 tcg_temp_free(EA);
6874 tcg_temp_free_ptr(rd);
6875 }
6876
6877 static void gen_mfvscr(DisasContext *ctx)
6878 {
6879 TCGv_i32 t;
6880 if (unlikely(!ctx->altivec_enabled)) {
6881 gen_exception(ctx, POWERPC_EXCP_VPU);
6882 return;
6883 }
6884 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6885 t = tcg_temp_new_i32();
6886 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6887 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6888 tcg_temp_free_i32(t);
6889 }
6890
6891 static void gen_mtvscr(DisasContext *ctx)
6892 {
6893 TCGv_ptr p;
6894 if (unlikely(!ctx->altivec_enabled)) {
6895 gen_exception(ctx, POWERPC_EXCP_VPU);
6896 return;
6897 }
6898 p = gen_avr_ptr(rB(ctx->opcode));
6899 gen_helper_mtvscr(cpu_env, p);
6900 tcg_temp_free_ptr(p);
6901 }
6902
6903 /* Logical operations */
6904 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6905 static void glue(gen_, name)(DisasContext *ctx) \
6906 { \
6907 if (unlikely(!ctx->altivec_enabled)) { \
6908 gen_exception(ctx, POWERPC_EXCP_VPU); \
6909 return; \
6910 } \
6911 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6912 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6913 }
6914
6915 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6916 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6917 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6918 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6919 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6920 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6921 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6922 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6923
6924 #define GEN_VXFORM(name, opc2, opc3) \
6925 static void glue(gen_, name)(DisasContext *ctx) \
6926 { \
6927 TCGv_ptr ra, rb, rd; \
6928 if (unlikely(!ctx->altivec_enabled)) { \
6929 gen_exception(ctx, POWERPC_EXCP_VPU); \
6930 return; \
6931 } \
6932 ra = gen_avr_ptr(rA(ctx->opcode)); \
6933 rb = gen_avr_ptr(rB(ctx->opcode)); \
6934 rd = gen_avr_ptr(rD(ctx->opcode)); \
6935 gen_helper_##name (rd, ra, rb); \
6936 tcg_temp_free_ptr(ra); \
6937 tcg_temp_free_ptr(rb); \
6938 tcg_temp_free_ptr(rd); \
6939 }
6940
6941 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6942 static void glue(gen_, name)(DisasContext *ctx) \
6943 { \
6944 TCGv_ptr ra, rb, rd; \
6945 if (unlikely(!ctx->altivec_enabled)) { \
6946 gen_exception(ctx, POWERPC_EXCP_VPU); \
6947 return; \
6948 } \
6949 ra = gen_avr_ptr(rA(ctx->opcode)); \
6950 rb = gen_avr_ptr(rB(ctx->opcode)); \
6951 rd = gen_avr_ptr(rD(ctx->opcode)); \
6952 gen_helper_##name(cpu_env, rd, ra, rb); \
6953 tcg_temp_free_ptr(ra); \
6954 tcg_temp_free_ptr(rb); \
6955 tcg_temp_free_ptr(rd); \
6956 }
6957
6958 #define GEN_VXFORM3(name, opc2, opc3) \
6959 static void glue(gen_, name)(DisasContext *ctx) \
6960 { \
6961 TCGv_ptr ra, rb, rc, rd; \
6962 if (unlikely(!ctx->altivec_enabled)) { \
6963 gen_exception(ctx, POWERPC_EXCP_VPU); \
6964 return; \
6965 } \
6966 ra = gen_avr_ptr(rA(ctx->opcode)); \
6967 rb = gen_avr_ptr(rB(ctx->opcode)); \
6968 rc = gen_avr_ptr(rC(ctx->opcode)); \
6969 rd = gen_avr_ptr(rD(ctx->opcode)); \
6970 gen_helper_##name(rd, ra, rb, rc); \
6971 tcg_temp_free_ptr(ra); \
6972 tcg_temp_free_ptr(rb); \
6973 tcg_temp_free_ptr(rc); \
6974 tcg_temp_free_ptr(rd); \
6975 }
6976
6977 /*
6978 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6979 * an opcode bit. In general, these pairs come from different
6980 * versions of the ISA, so we must also support a pair of flags for
6981 * each instruction.
6982 */
6983 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6984 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6985 { \
6986 if ((Rc(ctx->opcode) == 0) && \
6987 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6988 gen_##name0(ctx); \
6989 } else if ((Rc(ctx->opcode) == 1) && \
6990 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6991 gen_##name1(ctx); \
6992 } else { \
6993 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6994 } \
6995 }
6996
6997 GEN_VXFORM(vaddubm, 0, 0);
6998 GEN_VXFORM(vadduhm, 0, 1);
6999 GEN_VXFORM(vadduwm, 0, 2);
7000 GEN_VXFORM(vaddudm, 0, 3);
7001 GEN_VXFORM(vsububm, 0, 16);
7002 GEN_VXFORM(vsubuhm, 0, 17);
7003 GEN_VXFORM(vsubuwm, 0, 18);
7004 GEN_VXFORM(vsubudm, 0, 19);
7005 GEN_VXFORM(vmaxub, 1, 0);
7006 GEN_VXFORM(vmaxuh, 1, 1);
7007 GEN_VXFORM(vmaxuw, 1, 2);
7008 GEN_VXFORM(vmaxud, 1, 3);
7009 GEN_VXFORM(vmaxsb, 1, 4);
7010 GEN_VXFORM(vmaxsh, 1, 5);
7011 GEN_VXFORM(vmaxsw, 1, 6);
7012 GEN_VXFORM(vmaxsd, 1, 7);
7013 GEN_VXFORM(vminub, 1, 8);
7014 GEN_VXFORM(vminuh, 1, 9);
7015 GEN_VXFORM(vminuw, 1, 10);
7016 GEN_VXFORM(vminud, 1, 11);
7017 GEN_VXFORM(vminsb, 1, 12);
7018 GEN_VXFORM(vminsh, 1, 13);
7019 GEN_VXFORM(vminsw, 1, 14);
7020 GEN_VXFORM(vminsd, 1, 15);
7021 GEN_VXFORM(vavgub, 1, 16);
7022 GEN_VXFORM(vavguh, 1, 17);
7023 GEN_VXFORM(vavguw, 1, 18);
7024 GEN_VXFORM(vavgsb, 1, 20);
7025 GEN_VXFORM(vavgsh, 1, 21);
7026 GEN_VXFORM(vavgsw, 1, 22);
7027 GEN_VXFORM(vmrghb, 6, 0);
7028 GEN_VXFORM(vmrghh, 6, 1);
7029 GEN_VXFORM(vmrghw, 6, 2);
7030 GEN_VXFORM(vmrglb, 6, 4);
7031 GEN_VXFORM(vmrglh, 6, 5);
7032 GEN_VXFORM(vmrglw, 6, 6);
7033
7034 static void gen_vmrgew(DisasContext *ctx)
7035 {
7036 TCGv_i64 tmp;
7037 int VT, VA, VB;
7038 if (unlikely(!ctx->altivec_enabled)) {
7039 gen_exception(ctx, POWERPC_EXCP_VPU);
7040 return;
7041 }
7042 VT = rD(ctx->opcode);
7043 VA = rA(ctx->opcode);
7044 VB = rB(ctx->opcode);
7045 tmp = tcg_temp_new_i64();
7046 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7047 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7048 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7049 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7050 tcg_temp_free_i64(tmp);
7051 }
7052
7053 static void gen_vmrgow(DisasContext *ctx)
7054 {
7055 int VT, VA, VB;
7056 if (unlikely(!ctx->altivec_enabled)) {
7057 gen_exception(ctx, POWERPC_EXCP_VPU);
7058 return;
7059 }
7060 VT = rD(ctx->opcode);
7061 VA = rA(ctx->opcode);
7062 VB = rB(ctx->opcode);
7063
7064 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7065 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7066 }
7067
7068 GEN_VXFORM(vmuloub, 4, 0);
7069 GEN_VXFORM(vmulouh, 4, 1);
7070 GEN_VXFORM(vmulouw, 4, 2);
7071 GEN_VXFORM(vmuluwm, 4, 2);
7072 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7073 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7074 GEN_VXFORM(vmulosb, 4, 4);
7075 GEN_VXFORM(vmulosh, 4, 5);
7076 GEN_VXFORM(vmulosw, 4, 6);
7077 GEN_VXFORM(vmuleub, 4, 8);
7078 GEN_VXFORM(vmuleuh, 4, 9);
7079 GEN_VXFORM(vmuleuw, 4, 10);
7080 GEN_VXFORM(vmulesb, 4, 12);
7081 GEN_VXFORM(vmulesh, 4, 13);
7082 GEN_VXFORM(vmulesw, 4, 14);
7083 GEN_VXFORM(vslb, 2, 4);
7084 GEN_VXFORM(vslh, 2, 5);
7085 GEN_VXFORM(vslw, 2, 6);
7086 GEN_VXFORM(vsld, 2, 23);
7087 GEN_VXFORM(vsrb, 2, 8);
7088 GEN_VXFORM(vsrh, 2, 9);
7089 GEN_VXFORM(vsrw, 2, 10);
7090 GEN_VXFORM(vsrd, 2, 27);
7091 GEN_VXFORM(vsrab, 2, 12);
7092 GEN_VXFORM(vsrah, 2, 13);
7093 GEN_VXFORM(vsraw, 2, 14);
7094 GEN_VXFORM(vsrad, 2, 15);
7095 GEN_VXFORM(vslo, 6, 16);
7096 GEN_VXFORM(vsro, 6, 17);
7097 GEN_VXFORM(vaddcuw, 0, 6);
7098 GEN_VXFORM(vsubcuw, 0, 22);
7099 GEN_VXFORM_ENV(vaddubs, 0, 8);
7100 GEN_VXFORM_ENV(vadduhs, 0, 9);
7101 GEN_VXFORM_ENV(vadduws, 0, 10);
7102 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7103 GEN_VXFORM_ENV(vaddshs, 0, 13);
7104 GEN_VXFORM_ENV(vaddsws, 0, 14);
7105 GEN_VXFORM_ENV(vsububs, 0, 24);
7106 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7107 GEN_VXFORM_ENV(vsubuws, 0, 26);
7108 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7109 GEN_VXFORM_ENV(vsubshs, 0, 29);
7110 GEN_VXFORM_ENV(vsubsws, 0, 30);
7111 GEN_VXFORM(vadduqm, 0, 4);
7112 GEN_VXFORM(vaddcuq, 0, 5);
7113 GEN_VXFORM3(vaddeuqm, 30, 0);
7114 GEN_VXFORM3(vaddecuq, 30, 0);
7115 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7116 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7117 GEN_VXFORM(vsubuqm, 0, 20);
7118 GEN_VXFORM(vsubcuq, 0, 21);
7119 GEN_VXFORM3(vsubeuqm, 31, 0);
7120 GEN_VXFORM3(vsubecuq, 31, 0);
7121 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7122 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7123 GEN_VXFORM(vrlb, 2, 0);
7124 GEN_VXFORM(vrlh, 2, 1);
7125 GEN_VXFORM(vrlw, 2, 2);
7126 GEN_VXFORM(vrld, 2, 3);
7127 GEN_VXFORM(vsl, 2, 7);
7128 GEN_VXFORM(vsr, 2, 11);
7129 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7130 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7131 GEN_VXFORM_ENV(vpkudum, 7, 17);
7132 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7133 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7134 GEN_VXFORM_ENV(vpkudus, 7, 19);
7135 GEN_VXFORM_ENV(vpkshus, 7, 4);
7136 GEN_VXFORM_ENV(vpkswus, 7, 5);
7137 GEN_VXFORM_ENV(vpksdus, 7, 21);
7138 GEN_VXFORM_ENV(vpkshss, 7, 6);
7139 GEN_VXFORM_ENV(vpkswss, 7, 7);
7140 GEN_VXFORM_ENV(vpksdss, 7, 23);
7141 GEN_VXFORM(vpkpx, 7, 12);
7142 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7143 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7144 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7145 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7146 GEN_VXFORM_ENV(vsumsws, 4, 30);
7147 GEN_VXFORM_ENV(vaddfp, 5, 0);
7148 GEN_VXFORM_ENV(vsubfp, 5, 1);
7149 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7150 GEN_VXFORM_ENV(vminfp, 5, 17);
7151
7152 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7153 static void glue(gen_, name)(DisasContext *ctx) \
7154 { \
7155 TCGv_ptr ra, rb, rd; \
7156 if (unlikely(!ctx->altivec_enabled)) { \
7157 gen_exception(ctx, POWERPC_EXCP_VPU); \
7158 return; \
7159 } \
7160 ra = gen_avr_ptr(rA(ctx->opcode)); \
7161 rb = gen_avr_ptr(rB(ctx->opcode)); \
7162 rd = gen_avr_ptr(rD(ctx->opcode)); \
7163 gen_helper_##opname(cpu_env, rd, ra, rb); \
7164 tcg_temp_free_ptr(ra); \
7165 tcg_temp_free_ptr(rb); \
7166 tcg_temp_free_ptr(rd); \
7167 }
7168
7169 #define GEN_VXRFORM(name, opc2, opc3) \
7170 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7171 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7172
7173 /*
7174 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7175 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7176 * come from different versions of the ISA, so we must also support a
7177 * pair of flags for each instruction.
7178 */
7179 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7180 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7181 { \
7182 if ((Rc(ctx->opcode) == 0) && \
7183 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7184 if (Rc21(ctx->opcode) == 0) { \
7185 gen_##name0(ctx); \
7186 } else { \
7187 gen_##name0##_(ctx); \
7188 } \
7189 } else if ((Rc(ctx->opcode) == 1) && \
7190 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7191 if (Rc21(ctx->opcode) == 0) { \
7192 gen_##name1(ctx); \
7193 } else { \
7194 gen_##name1##_(ctx); \
7195 } \
7196 } else { \
7197 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7198 } \
7199 }
7200
7201 GEN_VXRFORM(vcmpequb, 3, 0)
7202 GEN_VXRFORM(vcmpequh, 3, 1)
7203 GEN_VXRFORM(vcmpequw, 3, 2)
7204 GEN_VXRFORM(vcmpequd, 3, 3)
7205 GEN_VXRFORM(vcmpgtsb, 3, 12)
7206 GEN_VXRFORM(vcmpgtsh, 3, 13)
7207 GEN_VXRFORM(vcmpgtsw, 3, 14)
7208 GEN_VXRFORM(vcmpgtsd, 3, 15)
7209 GEN_VXRFORM(vcmpgtub, 3, 8)
7210 GEN_VXRFORM(vcmpgtuh, 3, 9)
7211 GEN_VXRFORM(vcmpgtuw, 3, 10)
7212 GEN_VXRFORM(vcmpgtud, 3, 11)
7213 GEN_VXRFORM(vcmpeqfp, 3, 3)
7214 GEN_VXRFORM(vcmpgefp, 3, 7)
7215 GEN_VXRFORM(vcmpgtfp, 3, 11)
7216 GEN_VXRFORM(vcmpbfp, 3, 15)
7217
7218 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7219 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7220 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7221 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7222 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7223 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7224
7225 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7226 static void glue(gen_, name)(DisasContext *ctx) \
7227 { \
7228 TCGv_ptr rd; \
7229 TCGv_i32 simm; \
7230 if (unlikely(!ctx->altivec_enabled)) { \
7231 gen_exception(ctx, POWERPC_EXCP_VPU); \
7232 return; \
7233 } \
7234 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7235 rd = gen_avr_ptr(rD(ctx->opcode)); \
7236 gen_helper_##name (rd, simm); \
7237 tcg_temp_free_i32(simm); \
7238 tcg_temp_free_ptr(rd); \
7239 }
7240
7241 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7242 GEN_VXFORM_SIMM(vspltish, 6, 13);
7243 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7244
7245 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7246 static void glue(gen_, name)(DisasContext *ctx) \
7247 { \
7248 TCGv_ptr rb, rd; \
7249 if (unlikely(!ctx->altivec_enabled)) { \
7250 gen_exception(ctx, POWERPC_EXCP_VPU); \
7251 return; \
7252 } \
7253 rb = gen_avr_ptr(rB(ctx->opcode)); \
7254 rd = gen_avr_ptr(rD(ctx->opcode)); \
7255 gen_helper_##name (rd, rb); \
7256 tcg_temp_free_ptr(rb); \
7257 tcg_temp_free_ptr(rd); \
7258 }
7259
7260 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7261 static void glue(gen_, name)(DisasContext *ctx) \
7262 { \
7263 TCGv_ptr rb, rd; \
7264 \
7265 if (unlikely(!ctx->altivec_enabled)) { \
7266 gen_exception(ctx, POWERPC_EXCP_VPU); \
7267 return; \
7268 } \
7269 rb = gen_avr_ptr(rB(ctx->opcode)); \
7270 rd = gen_avr_ptr(rD(ctx->opcode)); \
7271 gen_helper_##name(cpu_env, rd, rb); \
7272 tcg_temp_free_ptr(rb); \
7273 tcg_temp_free_ptr(rd); \
7274 }
7275
7276 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7277 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7278 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7279 GEN_VXFORM_NOA(vupklsb, 7, 10);
7280 GEN_VXFORM_NOA(vupklsh, 7, 11);
7281 GEN_VXFORM_NOA(vupklsw, 7, 27);
7282 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7283 GEN_VXFORM_NOA(vupklpx, 7, 15);
7284 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7285 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7286 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7287 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7288 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7289 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7290 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7291 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7292
7293 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7294 static void glue(gen_, name)(DisasContext *ctx) \
7295 { \
7296 TCGv_ptr rd; \
7297 TCGv_i32 simm; \
7298 if (unlikely(!ctx->altivec_enabled)) { \
7299 gen_exception(ctx, POWERPC_EXCP_VPU); \
7300 return; \
7301 } \
7302 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7303 rd = gen_avr_ptr(rD(ctx->opcode)); \
7304 gen_helper_##name (rd, simm); \
7305 tcg_temp_free_i32(simm); \
7306 tcg_temp_free_ptr(rd); \
7307 }
7308
7309 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7310 static void glue(gen_, name)(DisasContext *ctx) \
7311 { \
7312 TCGv_ptr rb, rd; \
7313 TCGv_i32 uimm; \
7314 if (unlikely(!ctx->altivec_enabled)) { \
7315 gen_exception(ctx, POWERPC_EXCP_VPU); \
7316 return; \
7317 } \
7318 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7319 rb = gen_avr_ptr(rB(ctx->opcode)); \
7320 rd = gen_avr_ptr(rD(ctx->opcode)); \
7321 gen_helper_##name (rd, rb, uimm); \
7322 tcg_temp_free_i32(uimm); \
7323 tcg_temp_free_ptr(rb); \
7324 tcg_temp_free_ptr(rd); \
7325 }
7326
7327 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7328 static void glue(gen_, name)(DisasContext *ctx) \
7329 { \
7330 TCGv_ptr rb, rd; \
7331 TCGv_i32 uimm; \
7332 \
7333 if (unlikely(!ctx->altivec_enabled)) { \
7334 gen_exception(ctx, POWERPC_EXCP_VPU); \
7335 return; \
7336 } \
7337 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7338 rb = gen_avr_ptr(rB(ctx->opcode)); \
7339 rd = gen_avr_ptr(rD(ctx->opcode)); \
7340 gen_helper_##name(cpu_env, rd, rb, uimm); \
7341 tcg_temp_free_i32(uimm); \
7342 tcg_temp_free_ptr(rb); \
7343 tcg_temp_free_ptr(rd); \
7344 }
7345
7346 GEN_VXFORM_UIMM(vspltb, 6, 8);
7347 GEN_VXFORM_UIMM(vsplth, 6, 9);
7348 GEN_VXFORM_UIMM(vspltw, 6, 10);
7349 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7350 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7351 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7352 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7353
7354 static void gen_vsldoi(DisasContext *ctx)
7355 {
7356 TCGv_ptr ra, rb, rd;
7357 TCGv_i32 sh;
7358 if (unlikely(!ctx->altivec_enabled)) {
7359 gen_exception(ctx, POWERPC_EXCP_VPU);
7360 return;
7361 }
7362 ra = gen_avr_ptr(rA(ctx->opcode));
7363 rb = gen_avr_ptr(rB(ctx->opcode));
7364 rd = gen_avr_ptr(rD(ctx->opcode));
7365 sh = tcg_const_i32(VSH(ctx->opcode));
7366 gen_helper_vsldoi (rd, ra, rb, sh);
7367 tcg_temp_free_ptr(ra);
7368 tcg_temp_free_ptr(rb);
7369 tcg_temp_free_ptr(rd);
7370 tcg_temp_free_i32(sh);
7371 }
7372
7373 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7374 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7375 { \
7376 TCGv_ptr ra, rb, rc, rd; \
7377 if (unlikely(!ctx->altivec_enabled)) { \
7378 gen_exception(ctx, POWERPC_EXCP_VPU); \
7379 return; \
7380 } \
7381 ra = gen_avr_ptr(rA(ctx->opcode)); \
7382 rb = gen_avr_ptr(rB(ctx->opcode)); \
7383 rc = gen_avr_ptr(rC(ctx->opcode)); \
7384 rd = gen_avr_ptr(rD(ctx->opcode)); \
7385 if (Rc(ctx->opcode)) { \
7386 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7387 } else { \
7388 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7389 } \
7390 tcg_temp_free_ptr(ra); \
7391 tcg_temp_free_ptr(rb); \
7392 tcg_temp_free_ptr(rc); \
7393 tcg_temp_free_ptr(rd); \
7394 }
7395
7396 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7397
7398 static void gen_vmladduhm(DisasContext *ctx)
7399 {
7400 TCGv_ptr ra, rb, rc, rd;
7401 if (unlikely(!ctx->altivec_enabled)) {
7402 gen_exception(ctx, POWERPC_EXCP_VPU);
7403 return;
7404 }
7405 ra = gen_avr_ptr(rA(ctx->opcode));
7406 rb = gen_avr_ptr(rB(ctx->opcode));
7407 rc = gen_avr_ptr(rC(ctx->opcode));
7408 rd = gen_avr_ptr(rD(ctx->opcode));
7409 gen_helper_vmladduhm(rd, ra, rb, rc);
7410 tcg_temp_free_ptr(ra);
7411 tcg_temp_free_ptr(rb);
7412 tcg_temp_free_ptr(rc);
7413 tcg_temp_free_ptr(rd);
7414 }
7415
7416 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7417 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7418 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7419 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7420 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7421
7422 GEN_VXFORM_NOA(vclzb, 1, 28)
7423 GEN_VXFORM_NOA(vclzh, 1, 29)
7424 GEN_VXFORM_NOA(vclzw, 1, 30)
7425 GEN_VXFORM_NOA(vclzd, 1, 31)
7426 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7427 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7428 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7429 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7430 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7431 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7432 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7433 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7434 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7435 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7436 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7437 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7438 GEN_VXFORM(vbpermq, 6, 21);
7439 GEN_VXFORM_NOA(vgbbd, 6, 20);
7440 GEN_VXFORM(vpmsumb, 4, 16)
7441 GEN_VXFORM(vpmsumh, 4, 17)
7442 GEN_VXFORM(vpmsumw, 4, 18)
7443 GEN_VXFORM(vpmsumd, 4, 19)
7444
7445 #define GEN_BCD(op) \
7446 static void gen_##op(DisasContext *ctx) \
7447 { \
7448 TCGv_ptr ra, rb, rd; \
7449 TCGv_i32 ps; \
7450 \
7451 if (unlikely(!ctx->altivec_enabled)) { \
7452 gen_exception(ctx, POWERPC_EXCP_VPU); \
7453 return; \
7454 } \
7455 \
7456 ra = gen_avr_ptr(rA(ctx->opcode)); \
7457 rb = gen_avr_ptr(rB(ctx->opcode)); \
7458 rd = gen_avr_ptr(rD(ctx->opcode)); \
7459 \
7460 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7461 \
7462 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7463 \
7464 tcg_temp_free_ptr(ra); \
7465 tcg_temp_free_ptr(rb); \
7466 tcg_temp_free_ptr(rd); \
7467 tcg_temp_free_i32(ps); \
7468 }
7469
7470 GEN_BCD(bcdadd)
7471 GEN_BCD(bcdsub)
7472
7473 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7474 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7475 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7476 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7477 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7478 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7479 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7480 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7481
7482 static void gen_vsbox(DisasContext *ctx)
7483 {
7484 TCGv_ptr ra, rd;
7485 if (unlikely(!ctx->altivec_enabled)) {
7486 gen_exception(ctx, POWERPC_EXCP_VPU);
7487 return;
7488 }
7489 ra = gen_avr_ptr(rA(ctx->opcode));
7490 rd = gen_avr_ptr(rD(ctx->opcode));
7491 gen_helper_vsbox(rd, ra);
7492 tcg_temp_free_ptr(ra);
7493 tcg_temp_free_ptr(rd);
7494 }
7495
7496 GEN_VXFORM(vcipher, 4, 20)
7497 GEN_VXFORM(vcipherlast, 4, 20)
7498 GEN_VXFORM(vncipher, 4, 21)
7499 GEN_VXFORM(vncipherlast, 4, 21)
7500
7501 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7502 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7503 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7504 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7505
7506 #define VSHASIGMA(op) \
7507 static void gen_##op(DisasContext *ctx) \
7508 { \
7509 TCGv_ptr ra, rd; \
7510 TCGv_i32 st_six; \
7511 if (unlikely(!ctx->altivec_enabled)) { \
7512 gen_exception(ctx, POWERPC_EXCP_VPU); \
7513 return; \
7514 } \
7515 ra = gen_avr_ptr(rA(ctx->opcode)); \
7516 rd = gen_avr_ptr(rD(ctx->opcode)); \
7517 st_six = tcg_const_i32(rB(ctx->opcode)); \
7518 gen_helper_##op(rd, ra, st_six); \
7519 tcg_temp_free_ptr(ra); \
7520 tcg_temp_free_ptr(rd); \
7521 tcg_temp_free_i32(st_six); \
7522 }
7523
7524 VSHASIGMA(vshasigmaw)
7525 VSHASIGMA(vshasigmad)
7526
7527 GEN_VXFORM3(vpermxor, 22, 0xFF)
7528 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7529 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7530
7531 /*** VSX extension ***/
7532
7533 static inline TCGv_i64 cpu_vsrh(int n)
7534 {
7535 if (n < 32) {
7536 return cpu_fpr[n];
7537 } else {
7538 return cpu_avrh[n-32];
7539 }
7540 }
7541
7542 static inline TCGv_i64 cpu_vsrl(int n)
7543 {
7544 if (n < 32) {
7545 return cpu_vsr[n];
7546 } else {
7547 return cpu_avrl[n-32];
7548 }
7549 }
7550
7551 #define VSX_LOAD_SCALAR(name, operation) \
7552 static void gen_##name(DisasContext *ctx) \
7553 { \
7554 TCGv EA; \
7555 if (unlikely(!ctx->vsx_enabled)) { \
7556 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7557 return; \
7558 } \
7559 gen_set_access_type(ctx, ACCESS_INT); \
7560 EA = tcg_temp_new(); \
7561 gen_addr_reg_index(ctx, EA); \
7562 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7563 /* NOTE: cpu_vsrl is undefined */ \
7564 tcg_temp_free(EA); \
7565 }
7566
7567 VSX_LOAD_SCALAR(lxsdx, ld64)
7568 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7569 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7570 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7571
7572 static void gen_lxvd2x(DisasContext *ctx)
7573 {
7574 TCGv EA;
7575 if (unlikely(!ctx->vsx_enabled)) {
7576 gen_exception(ctx, POWERPC_EXCP_VSXU);
7577 return;
7578 }
7579 gen_set_access_type(ctx, ACCESS_INT);
7580 EA = tcg_temp_new();
7581 gen_addr_reg_index(ctx, EA);
7582 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7583 tcg_gen_addi_tl(EA, EA, 8);
7584 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7585 tcg_temp_free(EA);
7586 }
7587
7588 static void gen_lxvdsx(DisasContext *ctx)
7589 {
7590 TCGv EA;
7591 if (unlikely(!ctx->vsx_enabled)) {
7592 gen_exception(ctx, POWERPC_EXCP_VSXU);
7593 return;
7594 }
7595 gen_set_access_type(ctx, ACCESS_INT);
7596 EA = tcg_temp_new();
7597 gen_addr_reg_index(ctx, EA);
7598 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7599 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7600 tcg_temp_free(EA);
7601 }
7602
7603 static void gen_lxvw4x(DisasContext *ctx)
7604 {
7605 TCGv EA;
7606 TCGv_i64 tmp;
7607 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7608 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7609 if (unlikely(!ctx->vsx_enabled)) {
7610 gen_exception(ctx, POWERPC_EXCP_VSXU);
7611 return;
7612 }
7613 gen_set_access_type(ctx, ACCESS_INT);
7614 EA = tcg_temp_new();
7615 tmp = tcg_temp_new_i64();
7616
7617 gen_addr_reg_index(ctx, EA);
7618 gen_qemu_ld32u_i64(ctx, tmp, EA);
7619 tcg_gen_addi_tl(EA, EA, 4);
7620 gen_qemu_ld32u_i64(ctx, xth, EA);
7621 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7622
7623 tcg_gen_addi_tl(EA, EA, 4);
7624 gen_qemu_ld32u_i64(ctx, tmp, EA);
7625 tcg_gen_addi_tl(EA, EA, 4);
7626 gen_qemu_ld32u_i64(ctx, xtl, EA);
7627 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7628
7629 tcg_temp_free(EA);
7630 tcg_temp_free_i64(tmp);
7631 }
7632
7633 #define VSX_STORE_SCALAR(name, operation) \
7634 static void gen_##name(DisasContext *ctx) \
7635 { \
7636 TCGv EA; \
7637 if (unlikely(!ctx->vsx_enabled)) { \
7638 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7639 return; \
7640 } \
7641 gen_set_access_type(ctx, ACCESS_INT); \
7642 EA = tcg_temp_new(); \
7643 gen_addr_reg_index(ctx, EA); \
7644 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7645 tcg_temp_free(EA); \
7646 }
7647
7648 VSX_STORE_SCALAR(stxsdx, st64)
7649 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7650 VSX_STORE_SCALAR(stxsspx, st32fs)
7651
7652 static void gen_stxvd2x(DisasContext *ctx)
7653 {
7654 TCGv EA;
7655 if (unlikely(!ctx->vsx_enabled)) {
7656 gen_exception(ctx, POWERPC_EXCP_VSXU);
7657 return;
7658 }
7659 gen_set_access_type(ctx, ACCESS_INT);
7660 EA = tcg_temp_new();
7661 gen_addr_reg_index(ctx, EA);
7662 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7663 tcg_gen_addi_tl(EA, EA, 8);
7664 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7665 tcg_temp_free(EA);
7666 }
7667
7668 static void gen_stxvw4x(DisasContext *ctx)
7669 {
7670 TCGv_i64 tmp;
7671 TCGv EA;
7672 if (unlikely(!ctx->vsx_enabled)) {
7673 gen_exception(ctx, POWERPC_EXCP_VSXU);
7674 return;
7675 }
7676 gen_set_access_type(ctx, ACCESS_INT);
7677 EA = tcg_temp_new();
7678 gen_addr_reg_index(ctx, EA);
7679 tmp = tcg_temp_new_i64();
7680
7681 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7682 gen_qemu_st32_i64(ctx, tmp, EA);
7683 tcg_gen_addi_tl(EA, EA, 4);
7684 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7685
7686 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7687 tcg_gen_addi_tl(EA, EA, 4);
7688 gen_qemu_st32_i64(ctx, tmp, EA);
7689 tcg_gen_addi_tl(EA, EA, 4);
7690 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7691
7692 tcg_temp_free(EA);
7693 tcg_temp_free_i64(tmp);
7694 }
7695
7696 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7697 static void gen_##name(DisasContext *ctx) \
7698 { \
7699 if (xS(ctx->opcode) < 32) { \
7700 if (unlikely(!ctx->fpu_enabled)) { \
7701 gen_exception(ctx, POWERPC_EXCP_FPU); \
7702 return; \
7703 } \
7704 } else { \
7705 if (unlikely(!ctx->altivec_enabled)) { \
7706 gen_exception(ctx, POWERPC_EXCP_VPU); \
7707 return; \
7708 } \
7709 } \
7710 TCGv_i64 tmp = tcg_temp_new_i64(); \
7711 tcg_gen_##tcgop1(tmp, source); \
7712 tcg_gen_##tcgop2(target, tmp); \
7713 tcg_temp_free_i64(tmp); \
7714 }
7715
7716
7717 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7718 cpu_vsrh(xS(ctx->opcode)))
7719 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7720 cpu_gpr[rA(ctx->opcode)])
7721 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7722 cpu_gpr[rA(ctx->opcode)])
7723
7724 #if defined(TARGET_PPC64)
7725 #define MV_VSRD(name, target, source) \
7726 static void gen_##name(DisasContext *ctx) \
7727 { \
7728 if (xS(ctx->opcode) < 32) { \
7729 if (unlikely(!ctx->fpu_enabled)) { \
7730 gen_exception(ctx, POWERPC_EXCP_FPU); \
7731 return; \
7732 } \
7733 } else { \
7734 if (unlikely(!ctx->altivec_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_VPU); \
7736 return; \
7737 } \
7738 } \
7739 tcg_gen_mov_i64(target, source); \
7740 }
7741
7742 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7743 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7744
7745 #endif
7746
7747 static void gen_xxpermdi(DisasContext *ctx)
7748 {
7749 if (unlikely(!ctx->vsx_enabled)) {
7750 gen_exception(ctx, POWERPC_EXCP_VSXU);
7751 return;
7752 }
7753
7754 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7755 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7756 TCGv_i64 xh, xl;
7757
7758 xh = tcg_temp_new_i64();
7759 xl = tcg_temp_new_i64();
7760
7761 if ((DM(ctx->opcode) & 2) == 0) {
7762 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7763 } else {
7764 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7765 }
7766 if ((DM(ctx->opcode) & 1) == 0) {
7767 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7768 } else {
7769 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7770 }
7771
7772 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7773 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7774
7775 tcg_temp_free_i64(xh);
7776 tcg_temp_free_i64(xl);
7777 } else {
7778 if ((DM(ctx->opcode) & 2) == 0) {
7779 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7780 } else {
7781 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7782 }
7783 if ((DM(ctx->opcode) & 1) == 0) {
7784 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7785 } else {
7786 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7787 }
7788 }
7789 }
7790
7791 #define OP_ABS 1
7792 #define OP_NABS 2
7793 #define OP_NEG 3
7794 #define OP_CPSGN 4
7795 #define SGN_MASK_DP 0x8000000000000000ull
7796 #define SGN_MASK_SP 0x8000000080000000ull
7797
7798 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7799 static void glue(gen_, name)(DisasContext * ctx) \
7800 { \
7801 TCGv_i64 xb, sgm; \
7802 if (unlikely(!ctx->vsx_enabled)) { \
7803 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7804 return; \
7805 } \
7806 xb = tcg_temp_new_i64(); \
7807 sgm = tcg_temp_new_i64(); \
7808 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7809 tcg_gen_movi_i64(sgm, sgn_mask); \
7810 switch (op) { \
7811 case OP_ABS: { \
7812 tcg_gen_andc_i64(xb, xb, sgm); \
7813 break; \
7814 } \
7815 case OP_NABS: { \
7816 tcg_gen_or_i64(xb, xb, sgm); \
7817 break; \
7818 } \
7819 case OP_NEG: { \
7820 tcg_gen_xor_i64(xb, xb, sgm); \
7821 break; \
7822 } \
7823 case OP_CPSGN: { \
7824 TCGv_i64 xa = tcg_temp_new_i64(); \
7825 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7826 tcg_gen_and_i64(xa, xa, sgm); \
7827 tcg_gen_andc_i64(xb, xb, sgm); \
7828 tcg_gen_or_i64(xb, xb, xa); \
7829 tcg_temp_free_i64(xa); \
7830 break; \
7831 } \
7832 } \
7833 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7834 tcg_temp_free_i64(xb); \
7835 tcg_temp_free_i64(sgm); \
7836 }
7837
7838 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7839 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7840 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7841 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7842
7843 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7844 static void glue(gen_, name)(DisasContext * ctx) \
7845 { \
7846 TCGv_i64 xbh, xbl, sgm; \
7847 if (unlikely(!ctx->vsx_enabled)) { \
7848 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7849 return; \
7850 } \
7851 xbh = tcg_temp_new_i64(); \
7852 xbl = tcg_temp_new_i64(); \
7853 sgm = tcg_temp_new_i64(); \
7854 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7855 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7856 tcg_gen_movi_i64(sgm, sgn_mask); \
7857 switch (op) { \
7858 case OP_ABS: { \
7859 tcg_gen_andc_i64(xbh, xbh, sgm); \
7860 tcg_gen_andc_i64(xbl, xbl, sgm); \
7861 break; \
7862 } \
7863 case OP_NABS: { \
7864 tcg_gen_or_i64(xbh, xbh, sgm); \
7865 tcg_gen_or_i64(xbl, xbl, sgm); \
7866 break; \
7867 } \
7868 case OP_NEG: { \
7869 tcg_gen_xor_i64(xbh, xbh, sgm); \
7870 tcg_gen_xor_i64(xbl, xbl, sgm); \
7871 break; \
7872 } \
7873 case OP_CPSGN: { \
7874 TCGv_i64 xah = tcg_temp_new_i64(); \
7875 TCGv_i64 xal = tcg_temp_new_i64(); \
7876 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7877 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7878 tcg_gen_and_i64(xah, xah, sgm); \
7879 tcg_gen_and_i64(xal, xal, sgm); \
7880 tcg_gen_andc_i64(xbh, xbh, sgm); \
7881 tcg_gen_andc_i64(xbl, xbl, sgm); \
7882 tcg_gen_or_i64(xbh, xbh, xah); \
7883 tcg_gen_or_i64(xbl, xbl, xal); \
7884 tcg_temp_free_i64(xah); \
7885 tcg_temp_free_i64(xal); \
7886 break; \
7887 } \
7888 } \
7889 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7890 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7891 tcg_temp_free_i64(xbh); \
7892 tcg_temp_free_i64(xbl); \
7893 tcg_temp_free_i64(sgm); \
7894 }
7895
7896 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7897 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7898 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7899 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7900 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7901 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7902 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7903 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7904
7905 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7906 static void gen_##name(DisasContext * ctx) \
7907 { \
7908 TCGv_i32 opc; \
7909 if (unlikely(!ctx->vsx_enabled)) { \
7910 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7911 return; \
7912 } \
7913 /* NIP cannot be restored if the memory exception comes from an helper */ \
7914 gen_update_nip(ctx, ctx->nip - 4); \
7915 opc = tcg_const_i32(ctx->opcode); \
7916 gen_helper_##name(cpu_env, opc); \
7917 tcg_temp_free_i32(opc); \
7918 }
7919
7920 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7921 static void gen_##name(DisasContext * ctx) \
7922 { \
7923 if (unlikely(!ctx->vsx_enabled)) { \
7924 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7925 return; \
7926 } \
7927 /* NIP cannot be restored if the exception comes */ \
7928 /* from a helper. */ \
7929 gen_update_nip(ctx, ctx->nip - 4); \
7930 \
7931 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7932 cpu_vsrh(xB(ctx->opcode))); \
7933 }
7934
7935 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7958 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7960 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7972
7973 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7974 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7975 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7976 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7977 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7978 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7979 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7980 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7981 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7982 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7983 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7984 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7985 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7986 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7987 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7988 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7989 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7990
7991 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8027
8028 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8032 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8033 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8064
8065 #define VSX_LOGICAL(name, tcg_op) \
8066 static void glue(gen_, name)(DisasContext * ctx) \
8067 { \
8068 if (unlikely(!ctx->vsx_enabled)) { \
8069 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8070 return; \
8071 } \
8072 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8073 cpu_vsrh(xB(ctx->opcode))); \
8074 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8075 cpu_vsrl(xB(ctx->opcode))); \
8076 }
8077
8078 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8079 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8080 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8081 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8082 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8083 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8084 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8085 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8086
8087 #define VSX_XXMRG(name, high) \
8088 static void glue(gen_, name)(DisasContext * ctx) \
8089 { \
8090 TCGv_i64 a0, a1, b0, b1; \
8091 if (unlikely(!ctx->vsx_enabled)) { \
8092 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8093 return; \
8094 } \
8095 a0 = tcg_temp_new_i64(); \
8096 a1 = tcg_temp_new_i64(); \
8097 b0 = tcg_temp_new_i64(); \
8098 b1 = tcg_temp_new_i64(); \
8099 if (high) { \
8100 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8101 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8102 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8103 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8104 } else { \
8105 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8106 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8107 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8108 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8109 } \
8110 tcg_gen_shri_i64(a0, a0, 32); \
8111 tcg_gen_shri_i64(b0, b0, 32); \
8112 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8113 b0, a0, 32, 32); \
8114 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8115 b1, a1, 32, 32); \
8116 tcg_temp_free_i64(a0); \
8117 tcg_temp_free_i64(a1); \
8118 tcg_temp_free_i64(b0); \
8119 tcg_temp_free_i64(b1); \
8120 }
8121
8122 VSX_XXMRG(xxmrghw, 1)
8123 VSX_XXMRG(xxmrglw, 0)
8124
8125 static void gen_xxsel(DisasContext * ctx)
8126 {
8127 TCGv_i64 a, b, c;
8128 if (unlikely(!ctx->vsx_enabled)) {
8129 gen_exception(ctx, POWERPC_EXCP_VSXU);
8130 return;
8131 }
8132 a = tcg_temp_new_i64();
8133 b = tcg_temp_new_i64();
8134 c = tcg_temp_new_i64();
8135
8136 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8137 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8138 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8139
8140 tcg_gen_and_i64(b, b, c);
8141 tcg_gen_andc_i64(a, a, c);
8142 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8143
8144 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8145 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8146 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8147
8148 tcg_gen_and_i64(b, b, c);
8149 tcg_gen_andc_i64(a, a, c);
8150 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8151
8152 tcg_temp_free_i64(a);
8153 tcg_temp_free_i64(b);
8154 tcg_temp_free_i64(c);
8155 }
8156
8157 static void gen_xxspltw(DisasContext *ctx)
8158 {
8159 TCGv_i64 b, b2;
8160 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8161 cpu_vsrl(xB(ctx->opcode)) :
8162 cpu_vsrh(xB(ctx->opcode));
8163
8164 if (unlikely(!ctx->vsx_enabled)) {
8165 gen_exception(ctx, POWERPC_EXCP_VSXU);
8166 return;
8167 }
8168
8169 b = tcg_temp_new_i64();
8170 b2 = tcg_temp_new_i64();
8171
8172 if (UIM(ctx->opcode) & 1) {
8173 tcg_gen_ext32u_i64(b, vsr);
8174 } else {
8175 tcg_gen_shri_i64(b, vsr, 32);
8176 }
8177
8178 tcg_gen_shli_i64(b2, b, 32);
8179 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8180 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8181
8182 tcg_temp_free_i64(b);
8183 tcg_temp_free_i64(b2);
8184 }
8185
8186 static void gen_xxsldwi(DisasContext *ctx)
8187 {
8188 TCGv_i64 xth, xtl;
8189 if (unlikely(!ctx->vsx_enabled)) {
8190 gen_exception(ctx, POWERPC_EXCP_VSXU);
8191 return;
8192 }
8193 xth = tcg_temp_new_i64();
8194 xtl = tcg_temp_new_i64();
8195
8196 switch (SHW(ctx->opcode)) {
8197 case 0: {
8198 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8199 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8200 break;
8201 }
8202 case 1: {
8203 TCGv_i64 t0 = tcg_temp_new_i64();
8204 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8205 tcg_gen_shli_i64(xth, xth, 32);
8206 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8207 tcg_gen_shri_i64(t0, t0, 32);
8208 tcg_gen_or_i64(xth, xth, t0);
8209 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8210 tcg_gen_shli_i64(xtl, xtl, 32);
8211 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8212 tcg_gen_shri_i64(t0, t0, 32);
8213 tcg_gen_or_i64(xtl, xtl, t0);
8214 tcg_temp_free_i64(t0);
8215 break;
8216 }
8217 case 2: {
8218 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8219 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8220 break;
8221 }
8222 case 3: {
8223 TCGv_i64 t0 = tcg_temp_new_i64();
8224 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8225 tcg_gen_shli_i64(xth, xth, 32);
8226 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8227 tcg_gen_shri_i64(t0, t0, 32);
8228 tcg_gen_or_i64(xth, xth, t0);
8229 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8230 tcg_gen_shli_i64(xtl, xtl, 32);
8231 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8232 tcg_gen_shri_i64(t0, t0, 32);
8233 tcg_gen_or_i64(xtl, xtl, t0);
8234 tcg_temp_free_i64(t0);
8235 break;
8236 }
8237 }
8238
8239 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8240 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8241
8242 tcg_temp_free_i64(xth);
8243 tcg_temp_free_i64(xtl);
8244 }
8245
8246 /*** Decimal Floating Point ***/
8247
8248 static inline TCGv_ptr gen_fprp_ptr(int reg)
8249 {
8250 TCGv_ptr r = tcg_temp_new_ptr();
8251 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8252 return r;
8253 }
8254
8255 #define GEN_DFP_T_A_B_Rc(name) \
8256 static void gen_##name(DisasContext *ctx) \
8257 { \
8258 TCGv_ptr rd, ra, rb; \
8259 if (unlikely(!ctx->fpu_enabled)) { \
8260 gen_exception(ctx, POWERPC_EXCP_FPU); \
8261 return; \
8262 } \
8263 gen_update_nip(ctx, ctx->nip - 4); \
8264 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8265 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8266 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8267 gen_helper_##name(cpu_env, rd, ra, rb); \
8268 if (unlikely(Rc(ctx->opcode) != 0)) { \
8269 gen_set_cr1_from_fpscr(ctx); \
8270 } \
8271 tcg_temp_free_ptr(rd); \
8272 tcg_temp_free_ptr(ra); \
8273 tcg_temp_free_ptr(rb); \
8274 }
8275
8276 #define GEN_DFP_BF_A_B(name) \
8277 static void gen_##name(DisasContext *ctx) \
8278 { \
8279 TCGv_ptr ra, rb; \
8280 if (unlikely(!ctx->fpu_enabled)) { \
8281 gen_exception(ctx, POWERPC_EXCP_FPU); \
8282 return; \
8283 } \
8284 gen_update_nip(ctx, ctx->nip - 4); \
8285 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8286 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8287 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8288 cpu_env, ra, rb); \
8289 tcg_temp_free_ptr(ra); \
8290 tcg_temp_free_ptr(rb); \
8291 }
8292
8293 #define GEN_DFP_BF_A_DCM(name) \
8294 static void gen_##name(DisasContext *ctx) \
8295 { \
8296 TCGv_ptr ra; \
8297 TCGv_i32 dcm; \
8298 if (unlikely(!ctx->fpu_enabled)) { \
8299 gen_exception(ctx, POWERPC_EXCP_FPU); \
8300 return; \
8301 } \
8302 gen_update_nip(ctx, ctx->nip - 4); \
8303 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8304 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8305 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8306 cpu_env, ra, dcm); \
8307 tcg_temp_free_ptr(ra); \
8308 tcg_temp_free_i32(dcm); \
8309 }
8310
8311 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8312 static void gen_##name(DisasContext *ctx) \
8313 { \
8314 TCGv_ptr rt, rb; \
8315 TCGv_i32 u32_1, u32_2; \
8316 if (unlikely(!ctx->fpu_enabled)) { \
8317 gen_exception(ctx, POWERPC_EXCP_FPU); \
8318 return; \
8319 } \
8320 gen_update_nip(ctx, ctx->nip - 4); \
8321 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8322 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8323 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8324 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8325 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8326 if (unlikely(Rc(ctx->opcode) != 0)) { \
8327 gen_set_cr1_from_fpscr(ctx); \
8328 } \
8329 tcg_temp_free_ptr(rt); \
8330 tcg_temp_free_ptr(rb); \
8331 tcg_temp_free_i32(u32_1); \
8332 tcg_temp_free_i32(u32_2); \
8333 }
8334
8335 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8336 static void gen_##name(DisasContext *ctx) \
8337 { \
8338 TCGv_ptr rt, ra, rb; \
8339 TCGv_i32 i32; \
8340 if (unlikely(!ctx->fpu_enabled)) { \
8341 gen_exception(ctx, POWERPC_EXCP_FPU); \
8342 return; \
8343 } \
8344 gen_update_nip(ctx, ctx->nip - 4); \
8345 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8346 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8347 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8348 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8349 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8350 if (unlikely(Rc(ctx->opcode) != 0)) { \
8351 gen_set_cr1_from_fpscr(ctx); \
8352 } \
8353 tcg_temp_free_ptr(rt); \
8354 tcg_temp_free_ptr(rb); \
8355 tcg_temp_free_ptr(ra); \
8356 tcg_temp_free_i32(i32); \
8357 }
8358
8359 #define GEN_DFP_T_B_Rc(name) \
8360 static void gen_##name(DisasContext *ctx) \
8361 { \
8362 TCGv_ptr rt, rb; \
8363 if (unlikely(!ctx->fpu_enabled)) { \
8364 gen_exception(ctx, POWERPC_EXCP_FPU); \
8365 return; \
8366 } \
8367 gen_update_nip(ctx, ctx->nip - 4); \
8368 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8369 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8370 gen_helper_##name(cpu_env, rt, rb); \
8371 if (unlikely(Rc(ctx->opcode) != 0)) { \
8372 gen_set_cr1_from_fpscr(ctx); \
8373 } \
8374 tcg_temp_free_ptr(rt); \
8375 tcg_temp_free_ptr(rb); \
8376 }
8377
8378 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8379 static void gen_##name(DisasContext *ctx) \
8380 { \
8381 TCGv_ptr rt, rs; \
8382 TCGv_i32 i32; \
8383 if (unlikely(!ctx->fpu_enabled)) { \
8384 gen_exception(ctx, POWERPC_EXCP_FPU); \
8385 return; \
8386 } \
8387 gen_update_nip(ctx, ctx->nip - 4); \
8388 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8389 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8390 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8391 gen_helper_##name(cpu_env, rt, rs, i32); \
8392 if (unlikely(Rc(ctx->opcode) != 0)) { \
8393 gen_set_cr1_from_fpscr(ctx); \
8394 } \
8395 tcg_temp_free_ptr(rt); \
8396 tcg_temp_free_ptr(rs); \
8397 tcg_temp_free_i32(i32); \
8398 }
8399
8400 GEN_DFP_T_A_B_Rc(dadd)
8401 GEN_DFP_T_A_B_Rc(daddq)
8402 GEN_DFP_T_A_B_Rc(dsub)
8403 GEN_DFP_T_A_B_Rc(dsubq)
8404 GEN_DFP_T_A_B_Rc(dmul)
8405 GEN_DFP_T_A_B_Rc(dmulq)
8406 GEN_DFP_T_A_B_Rc(ddiv)
8407 GEN_DFP_T_A_B_Rc(ddivq)
8408 GEN_DFP_BF_A_B(dcmpu)
8409 GEN_DFP_BF_A_B(dcmpuq)
8410 GEN_DFP_BF_A_B(dcmpo)
8411 GEN_DFP_BF_A_B(dcmpoq)
8412 GEN_DFP_BF_A_DCM(dtstdc)
8413 GEN_DFP_BF_A_DCM(dtstdcq)
8414 GEN_DFP_BF_A_DCM(dtstdg)
8415 GEN_DFP_BF_A_DCM(dtstdgq)
8416 GEN_DFP_BF_A_B(dtstex)
8417 GEN_DFP_BF_A_B(dtstexq)
8418 GEN_DFP_BF_A_B(dtstsf)
8419 GEN_DFP_BF_A_B(dtstsfq)
8420 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8421 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8422 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8423 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8424 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8425 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8426 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8427 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8428 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8429 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8430 GEN_DFP_T_B_Rc(dctdp)
8431 GEN_DFP_T_B_Rc(dctqpq)
8432 GEN_DFP_T_B_Rc(drsp)
8433 GEN_DFP_T_B_Rc(drdpq)
8434 GEN_DFP_T_B_Rc(dcffix)
8435 GEN_DFP_T_B_Rc(dcffixq)
8436 GEN_DFP_T_B_Rc(dctfix)
8437 GEN_DFP_T_B_Rc(dctfixq)
8438 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8439 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8440 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8441 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8442 GEN_DFP_T_B_Rc(dxex)
8443 GEN_DFP_T_B_Rc(dxexq)
8444 GEN_DFP_T_A_B_Rc(diex)
8445 GEN_DFP_T_A_B_Rc(diexq)
8446 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8447 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8448 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8449 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8450
8451 /*** SPE extension ***/
8452 /* Register moves */
8453
8454 static inline void gen_evmra(DisasContext *ctx)
8455 {
8456
8457 if (unlikely(!ctx->spe_enabled)) {
8458 gen_exception(ctx, POWERPC_EXCP_SPEU);
8459 return;
8460 }
8461
8462 TCGv_i64 tmp = tcg_temp_new_i64();
8463
8464 /* tmp := rA_lo + rA_hi << 32 */
8465 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8466
8467 /* spe_acc := tmp */
8468 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8469 tcg_temp_free_i64(tmp);
8470
8471 /* rD := rA */
8472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8473 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8474 }
8475
8476 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8477 {
8478 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8479 }
8480
8481 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8482 {
8483 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8484 }
8485
8486 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8487 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8488 { \
8489 if (Rc(ctx->opcode)) \
8490 gen_##name1(ctx); \
8491 else \
8492 gen_##name0(ctx); \
8493 }
8494
8495 /* Handler for undefined SPE opcodes */
8496 static inline void gen_speundef(DisasContext *ctx)
8497 {
8498 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8499 }
8500
8501 /* SPE logic */
8502 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8503 static inline void gen_##name(DisasContext *ctx) \
8504 { \
8505 if (unlikely(!ctx->spe_enabled)) { \
8506 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8507 return; \
8508 } \
8509 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8510 cpu_gpr[rB(ctx->opcode)]); \
8511 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8512 cpu_gprh[rB(ctx->opcode)]); \
8513 }
8514
8515 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8516 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8517 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8518 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8519 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8520 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8521 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8522 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8523
8524 /* SPE logic immediate */
8525 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8526 static inline void gen_##name(DisasContext *ctx) \
8527 { \
8528 TCGv_i32 t0; \
8529 if (unlikely(!ctx->spe_enabled)) { \
8530 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8531 return; \
8532 } \
8533 t0 = tcg_temp_new_i32(); \
8534 \
8535 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8536 tcg_opi(t0, t0, rB(ctx->opcode)); \
8537 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8538 \
8539 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8540 tcg_opi(t0, t0, rB(ctx->opcode)); \
8541 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8542 \
8543 tcg_temp_free_i32(t0); \
8544 }
8545 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8546 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8547 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8548 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8549
8550 /* SPE arithmetic */
8551 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8552 static inline void gen_##name(DisasContext *ctx) \
8553 { \
8554 TCGv_i32 t0; \
8555 if (unlikely(!ctx->spe_enabled)) { \
8556 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8557 return; \
8558 } \
8559 t0 = tcg_temp_new_i32(); \
8560 \
8561 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8562 tcg_op(t0, t0); \
8563 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8564 \
8565 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8566 tcg_op(t0, t0); \
8567 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8568 \
8569 tcg_temp_free_i32(t0); \
8570 }
8571
8572 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8573 {
8574 int l1 = gen_new_label();
8575 int l2 = gen_new_label();
8576
8577 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8578 tcg_gen_neg_i32(ret, arg1);
8579 tcg_gen_br(l2);
8580 gen_set_label(l1);
8581 tcg_gen_mov_i32(ret, arg1);
8582 gen_set_label(l2);
8583 }
8584 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8585 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8586 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8587 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8588 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8589 {
8590 tcg_gen_addi_i32(ret, arg1, 0x8000);
8591 tcg_gen_ext16u_i32(ret, ret);
8592 }
8593 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8594 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8595 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8596
8597 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8598 static inline void gen_##name(DisasContext *ctx) \
8599 { \
8600 TCGv_i32 t0, t1; \
8601 if (unlikely(!ctx->spe_enabled)) { \
8602 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8603 return; \
8604 } \
8605 t0 = tcg_temp_new_i32(); \
8606 t1 = tcg_temp_new_i32(); \
8607 \
8608 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8609 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8610 tcg_op(t0, t0, t1); \
8611 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8612 \
8613 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8614 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8615 tcg_op(t0, t0, t1); \
8616 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8617 \
8618 tcg_temp_free_i32(t0); \
8619 tcg_temp_free_i32(t1); \
8620 }
8621
8622 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8623 {
8624 TCGv_i32 t0;
8625 int l1, l2;
8626
8627 l1 = gen_new_label();
8628 l2 = gen_new_label();
8629 t0 = tcg_temp_local_new_i32();
8630 /* No error here: 6 bits are used */
8631 tcg_gen_andi_i32(t0, arg2, 0x3F);
8632 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8633 tcg_gen_shr_i32(ret, arg1, t0);
8634 tcg_gen_br(l2);
8635 gen_set_label(l1);
8636 tcg_gen_movi_i32(ret, 0);
8637 gen_set_label(l2);
8638 tcg_temp_free_i32(t0);
8639 }
8640 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8641 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8642 {
8643 TCGv_i32 t0;
8644 int l1, l2;
8645
8646 l1 = gen_new_label();
8647 l2 = gen_new_label();
8648 t0 = tcg_temp_local_new_i32();
8649 /* No error here: 6 bits are used */
8650 tcg_gen_andi_i32(t0, arg2, 0x3F);
8651 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8652 tcg_gen_sar_i32(ret, arg1, t0);
8653 tcg_gen_br(l2);
8654 gen_set_label(l1);
8655 tcg_gen_movi_i32(ret, 0);
8656 gen_set_label(l2);
8657 tcg_temp_free_i32(t0);
8658 }
8659 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8660 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8661 {
8662 TCGv_i32 t0;
8663 int l1, l2;
8664
8665 l1 = gen_new_label();
8666 l2 = gen_new_label();
8667 t0 = tcg_temp_local_new_i32();
8668 /* No error here: 6 bits are used */
8669 tcg_gen_andi_i32(t0, arg2, 0x3F);
8670 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8671 tcg_gen_shl_i32(ret, arg1, t0);
8672 tcg_gen_br(l2);
8673 gen_set_label(l1);
8674 tcg_gen_movi_i32(ret, 0);
8675 gen_set_label(l2);
8676 tcg_temp_free_i32(t0);
8677 }
8678 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8679 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8680 {
8681 TCGv_i32 t0 = tcg_temp_new_i32();
8682 tcg_gen_andi_i32(t0, arg2, 0x1F);
8683 tcg_gen_rotl_i32(ret, arg1, t0);
8684 tcg_temp_free_i32(t0);
8685 }
8686 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8687 static inline void gen_evmergehi(DisasContext *ctx)
8688 {
8689 if (unlikely(!ctx->spe_enabled)) {
8690 gen_exception(ctx, POWERPC_EXCP_SPEU);
8691 return;
8692 }
8693 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8694 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8695 }
8696 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8697 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8698 {
8699 tcg_gen_sub_i32(ret, arg2, arg1);
8700 }
8701 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8702
8703 /* SPE arithmetic immediate */
8704 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8705 static inline void gen_##name(DisasContext *ctx) \
8706 { \
8707 TCGv_i32 t0; \
8708 if (unlikely(!ctx->spe_enabled)) { \
8709 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8710 return; \
8711 } \
8712 t0 = tcg_temp_new_i32(); \
8713 \
8714 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8715 tcg_op(t0, t0, rA(ctx->opcode)); \
8716 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8717 \
8718 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8719 tcg_op(t0, t0, rA(ctx->opcode)); \
8720 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8721 \
8722 tcg_temp_free_i32(t0); \
8723 }
8724 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8725 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8726
8727 /* SPE comparison */
8728 #define GEN_SPEOP_COMP(name, tcg_cond) \
8729 static inline void gen_##name(DisasContext *ctx) \
8730 { \
8731 if (unlikely(!ctx->spe_enabled)) { \
8732 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8733 return; \
8734 } \
8735 int l1 = gen_new_label(); \
8736 int l2 = gen_new_label(); \
8737 int l3 = gen_new_label(); \
8738 int l4 = gen_new_label(); \
8739 \
8740 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8741 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8742 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8743 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8744 \
8745 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8746 cpu_gpr[rB(ctx->opcode)], l1); \
8747 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8748 tcg_gen_br(l2); \
8749 gen_set_label(l1); \
8750 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8751 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8752 gen_set_label(l2); \
8753 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8754 cpu_gprh[rB(ctx->opcode)], l3); \
8755 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8756 ~(CRF_CH | CRF_CH_AND_CL)); \
8757 tcg_gen_br(l4); \
8758 gen_set_label(l3); \
8759 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8760 CRF_CH | CRF_CH_OR_CL); \
8761 gen_set_label(l4); \
8762 }
8763 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8764 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8765 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8766 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8767 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8768
8769 /* SPE misc */
8770 static inline void gen_brinc(DisasContext *ctx)
8771 {
8772 /* Note: brinc is usable even if SPE is disabled */
8773 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8774 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8775 }
8776 static inline void gen_evmergelo(DisasContext *ctx)
8777 {
8778 if (unlikely(!ctx->spe_enabled)) {
8779 gen_exception(ctx, POWERPC_EXCP_SPEU);
8780 return;
8781 }
8782 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8783 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8784 }
8785 static inline void gen_evmergehilo(DisasContext *ctx)
8786 {
8787 if (unlikely(!ctx->spe_enabled)) {
8788 gen_exception(ctx, POWERPC_EXCP_SPEU);
8789 return;
8790 }
8791 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8792 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8793 }
8794 static inline void gen_evmergelohi(DisasContext *ctx)
8795 {
8796 if (unlikely(!ctx->spe_enabled)) {
8797 gen_exception(ctx, POWERPC_EXCP_SPEU);
8798 return;
8799 }
8800 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8801 TCGv tmp = tcg_temp_new();
8802 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8803 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8804 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8805 tcg_temp_free(tmp);
8806 } else {
8807 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8808 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8809 }
8810 }
8811 static inline void gen_evsplati(DisasContext *ctx)
8812 {
8813 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8814
8815 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8816 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8817 }
8818 static inline void gen_evsplatfi(DisasContext *ctx)
8819 {
8820 uint64_t imm = rA(ctx->opcode) << 27;
8821
8822 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8823 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8824 }
8825
8826 static inline void gen_evsel(DisasContext *ctx)
8827 {
8828 int l1 = gen_new_label();
8829 int l2 = gen_new_label();
8830 int l3 = gen_new_label();
8831 int l4 = gen_new_label();
8832 TCGv_i32 t0 = tcg_temp_local_new_i32();
8833 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8834 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8835 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8836 tcg_gen_br(l2);
8837 gen_set_label(l1);
8838 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8839 gen_set_label(l2);
8840 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8843 tcg_gen_br(l4);
8844 gen_set_label(l3);
8845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8846 gen_set_label(l4);
8847 tcg_temp_free_i32(t0);
8848 }
8849
8850 static void gen_evsel0(DisasContext *ctx)
8851 {
8852 gen_evsel(ctx);
8853 }
8854
8855 static void gen_evsel1(DisasContext *ctx)
8856 {
8857 gen_evsel(ctx);
8858 }
8859
8860 static void gen_evsel2(DisasContext *ctx)
8861 {
8862 gen_evsel(ctx);
8863 }
8864
8865 static void gen_evsel3(DisasContext *ctx)
8866 {
8867 gen_evsel(ctx);
8868 }
8869
8870 /* Multiply */
8871
8872 static inline void gen_evmwumi(DisasContext *ctx)
8873 {
8874 TCGv_i64 t0, t1;
8875
8876 if (unlikely(!ctx->spe_enabled)) {
8877 gen_exception(ctx, POWERPC_EXCP_SPEU);
8878 return;
8879 }
8880
8881 t0 = tcg_temp_new_i64();
8882 t1 = tcg_temp_new_i64();
8883
8884 /* t0 := rA; t1 := rB */
8885 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8886 tcg_gen_ext32u_i64(t0, t0);
8887 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8888 tcg_gen_ext32u_i64(t1, t1);
8889
8890 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8891
8892 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8893
8894 tcg_temp_free_i64(t0);
8895 tcg_temp_free_i64(t1);
8896 }
8897
8898 static inline void gen_evmwumia(DisasContext *ctx)
8899 {
8900 TCGv_i64 tmp;
8901
8902 if (unlikely(!ctx->spe_enabled)) {
8903 gen_exception(ctx, POWERPC_EXCP_SPEU);
8904 return;
8905 }
8906
8907 gen_evmwumi(ctx); /* rD := rA * rB */
8908
8909 tmp = tcg_temp_new_i64();
8910
8911 /* acc := rD */
8912 gen_load_gpr64(tmp, rD(ctx->opcode));
8913 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8914 tcg_temp_free_i64(tmp);
8915 }
8916
8917 static inline void gen_evmwumiaa(DisasContext *ctx)
8918 {
8919 TCGv_i64 acc;
8920 TCGv_i64 tmp;
8921
8922 if (unlikely(!ctx->spe_enabled)) {
8923 gen_exception(ctx, POWERPC_EXCP_SPEU);
8924 return;
8925 }
8926
8927 gen_evmwumi(ctx); /* rD := rA * rB */
8928
8929 acc = tcg_temp_new_i64();
8930 tmp = tcg_temp_new_i64();
8931
8932 /* tmp := rD */
8933 gen_load_gpr64(tmp, rD(ctx->opcode));
8934
8935 /* Load acc */
8936 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8937
8938 /* acc := tmp + acc */
8939 tcg_gen_add_i64(acc, acc, tmp);
8940
8941 /* Store acc */
8942 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8943
8944 /* rD := acc */
8945 gen_store_gpr64(rD(ctx->opcode), acc);
8946
8947 tcg_temp_free_i64(acc);
8948 tcg_temp_free_i64(tmp);
8949 }
8950
8951 static inline void gen_evmwsmi(DisasContext *ctx)
8952 {
8953 TCGv_i64 t0, t1;
8954
8955 if (unlikely(!ctx->spe_enabled)) {
8956 gen_exception(ctx, POWERPC_EXCP_SPEU);
8957 return;
8958 }
8959
8960 t0 = tcg_temp_new_i64();
8961 t1 = tcg_temp_new_i64();
8962
8963 /* t0 := rA; t1 := rB */
8964 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8965 tcg_gen_ext32s_i64(t0, t0);
8966 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8967 tcg_gen_ext32s_i64(t1, t1);
8968
8969 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8970
8971 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8972
8973 tcg_temp_free_i64(t0);
8974 tcg_temp_free_i64(t1);
8975 }
8976
8977 static inline void gen_evmwsmia(DisasContext *ctx)
8978 {
8979 TCGv_i64 tmp;
8980
8981 gen_evmwsmi(ctx); /* rD := rA * rB */
8982
8983 tmp = tcg_temp_new_i64();
8984
8985 /* acc := rD */
8986 gen_load_gpr64(tmp, rD(ctx->opcode));
8987 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8988
8989 tcg_temp_free_i64(tmp);
8990 }
8991
8992 static inline void gen_evmwsmiaa(DisasContext *ctx)
8993 {
8994 TCGv_i64 acc = tcg_temp_new_i64();
8995 TCGv_i64 tmp = tcg_temp_new_i64();
8996
8997 gen_evmwsmi(ctx); /* rD := rA * rB */
8998
8999 acc = tcg_temp_new_i64();
9000 tmp = tcg_temp_new_i64();
9001
9002 /* tmp := rD */
9003 gen_load_gpr64(tmp, rD(ctx->opcode));
9004
9005 /* Load acc */
9006 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9007
9008 /* acc := tmp + acc */
9009 tcg_gen_add_i64(acc, acc, tmp);
9010
9011 /* Store acc */
9012 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9013
9014 /* rD := acc */
9015 gen_store_gpr64(rD(ctx->opcode), acc);
9016
9017 tcg_temp_free_i64(acc);
9018 tcg_temp_free_i64(tmp);
9019 }
9020
9021 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9022 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9023 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9024 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9025 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9026 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9027 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9028 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9029 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9030 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9031 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9032 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9033 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9034 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9035 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9036 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9037 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9038 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9039 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9040 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9041 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9042 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9043 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9044 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9045 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9046 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9047 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9048 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9049 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9050
9051 /* SPE load and stores */
9052 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9053 {
9054 target_ulong uimm = rB(ctx->opcode);
9055
9056 if (rA(ctx->opcode) == 0) {
9057 tcg_gen_movi_tl(EA, uimm << sh);
9058 } else {
9059 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9060 if (NARROW_MODE(ctx)) {
9061 tcg_gen_ext32u_tl(EA, EA);
9062 }
9063 }
9064 }
9065
9066 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9067 {
9068 TCGv_i64 t0 = tcg_temp_new_i64();
9069 gen_qemu_ld64(ctx, t0, addr);
9070 gen_store_gpr64(rD(ctx->opcode), t0);
9071 tcg_temp_free_i64(t0);
9072 }
9073
9074 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9075 {
9076 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9077 gen_addr_add(ctx, addr, addr, 4);
9078 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9079 }
9080
9081 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9082 {
9083 TCGv t0 = tcg_temp_new();
9084 gen_qemu_ld16u(ctx, t0, addr);
9085 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9086 gen_addr_add(ctx, addr, addr, 2);
9087 gen_qemu_ld16u(ctx, t0, addr);
9088 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9089 gen_addr_add(ctx, addr, addr, 2);
9090 gen_qemu_ld16u(ctx, t0, addr);
9091 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9092 gen_addr_add(ctx, addr, addr, 2);
9093 gen_qemu_ld16u(ctx, t0, addr);
9094 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9095 tcg_temp_free(t0);
9096 }
9097
9098 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9099 {
9100 TCGv t0 = tcg_temp_new();
9101 gen_qemu_ld16u(ctx, t0, addr);
9102 tcg_gen_shli_tl(t0, t0, 16);
9103 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9104 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9105 tcg_temp_free(t0);
9106 }
9107
9108 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9109 {
9110 TCGv t0 = tcg_temp_new();
9111 gen_qemu_ld16u(ctx, t0, addr);
9112 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9114 tcg_temp_free(t0);
9115 }
9116
9117 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9118 {
9119 TCGv t0 = tcg_temp_new();
9120 gen_qemu_ld16s(ctx, t0, addr);
9121 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9123 tcg_temp_free(t0);
9124 }
9125
9126 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9127 {
9128 TCGv t0 = tcg_temp_new();
9129 gen_qemu_ld16u(ctx, t0, addr);
9130 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9131 gen_addr_add(ctx, addr, addr, 2);
9132 gen_qemu_ld16u(ctx, t0, addr);
9133 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9134 tcg_temp_free(t0);
9135 }
9136
9137 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9138 {
9139 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9140 gen_addr_add(ctx, addr, addr, 2);
9141 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9142 }
9143
9144 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9145 {
9146 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9147 gen_addr_add(ctx, addr, addr, 2);
9148 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9149 }
9150
9151 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9152 {
9153 TCGv t0 = tcg_temp_new();
9154 gen_qemu_ld32u(ctx, t0, addr);
9155 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9156 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9157 tcg_temp_free(t0);
9158 }
9159
9160 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9161 {
9162 TCGv t0 = tcg_temp_new();
9163 gen_qemu_ld16u(ctx, t0, addr);
9164 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9165 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9166 gen_addr_add(ctx, addr, addr, 2);
9167 gen_qemu_ld16u(ctx, t0, addr);
9168 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9169 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9170 tcg_temp_free(t0);
9171 }
9172
9173 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9174 {
9175 TCGv_i64 t0 = tcg_temp_new_i64();
9176 gen_load_gpr64(t0, rS(ctx->opcode));
9177 gen_qemu_st64(ctx, t0, addr);
9178 tcg_temp_free_i64(t0);
9179 }
9180
9181 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9182 {
9183 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9184 gen_addr_add(ctx, addr, addr, 4);
9185 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9186 }
9187
9188 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9189 {
9190 TCGv t0 = tcg_temp_new();
9191 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9192 gen_qemu_st16(ctx, t0, addr);
9193 gen_addr_add(ctx, addr, addr, 2);
9194 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9195 gen_addr_add(ctx, addr, addr, 2);
9196 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9197 gen_qemu_st16(ctx, t0, addr);
9198 tcg_temp_free(t0);
9199 gen_addr_add(ctx, addr, addr, 2);
9200 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9201 }
9202
9203 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9204 {
9205 TCGv t0 = tcg_temp_new();
9206 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9207 gen_qemu_st16(ctx, t0, addr);
9208 gen_addr_add(ctx, addr, addr, 2);
9209 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9210 gen_qemu_st16(ctx, t0, addr);
9211 tcg_temp_free(t0);
9212 }
9213
9214 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9215 {
9216 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9217 gen_addr_add(ctx, addr, addr, 2);
9218 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9219 }
9220
9221 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9222 {
9223 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9224 }
9225
9226 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9227 {
9228 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9229 }
9230
9231 #define GEN_SPEOP_LDST(name, opc2, sh) \
9232 static void glue(gen_, name)(DisasContext *ctx) \
9233 { \
9234 TCGv t0; \
9235 if (unlikely(!ctx->spe_enabled)) { \
9236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9237 return; \
9238 } \
9239 gen_set_access_type(ctx, ACCESS_INT); \
9240 t0 = tcg_temp_new(); \
9241 if (Rc(ctx->opcode)) { \
9242 gen_addr_spe_imm_index(ctx, t0, sh); \
9243 } else { \
9244 gen_addr_reg_index(ctx, t0); \
9245 } \
9246 gen_op_##name(ctx, t0); \
9247 tcg_temp_free(t0); \
9248 }
9249
9250 GEN_SPEOP_LDST(evldd, 0x00, 3);
9251 GEN_SPEOP_LDST(evldw, 0x01, 3);
9252 GEN_SPEOP_LDST(evldh, 0x02, 3);
9253 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9254 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9255 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9256 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9257 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9258 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9259 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9260 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9261
9262 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9263 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9264 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9265 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9266 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9267 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9268 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9269
9270 /* Multiply and add - TODO */
9271 #if 0
9272 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9273 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9275 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9281 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9282 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9283 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284
9285 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9286 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9287 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9290 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9292 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9293 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9294 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297
9298 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9299 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9300 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9301 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9302 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9303
9304 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9305 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9306 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9307 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9308 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9309 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9310 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9311 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9312 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9313 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9314 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9315 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316
9317 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9318 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9319 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9323 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9325 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9327 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9329 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9331 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9333 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334
9335 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9337 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9338 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9339 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9340 #endif
9341
9342 /*** SPE floating-point extension ***/
9343 #define GEN_SPEFPUOP_CONV_32_32(name) \
9344 static inline void gen_##name(DisasContext *ctx) \
9345 { \
9346 TCGv_i32 t0 = tcg_temp_new_i32(); \
9347 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9348 gen_helper_##name(t0, cpu_env, t0); \
9349 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9350 tcg_temp_free_i32(t0); \
9351 }
9352 #define GEN_SPEFPUOP_CONV_32_64(name) \
9353 static inline void gen_##name(DisasContext *ctx) \
9354 { \
9355 TCGv_i64 t0 = tcg_temp_new_i64(); \
9356 TCGv_i32 t1 = tcg_temp_new_i32(); \
9357 gen_load_gpr64(t0, rB(ctx->opcode)); \
9358 gen_helper_##name(t1, cpu_env, t0); \
9359 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9360 tcg_temp_free_i64(t0); \
9361 tcg_temp_free_i32(t1); \
9362 }
9363 #define GEN_SPEFPUOP_CONV_64_32(name) \
9364 static inline void gen_##name(DisasContext *ctx) \
9365 { \
9366 TCGv_i64 t0 = tcg_temp_new_i64(); \
9367 TCGv_i32 t1 = tcg_temp_new_i32(); \
9368 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9369 gen_helper_##name(t0, cpu_env, t1); \
9370 gen_store_gpr64(rD(ctx->opcode), t0); \
9371 tcg_temp_free_i64(t0); \
9372 tcg_temp_free_i32(t1); \
9373 }
9374 #define GEN_SPEFPUOP_CONV_64_64(name) \
9375 static inline void gen_##name(DisasContext *ctx) \
9376 { \
9377 TCGv_i64 t0 = tcg_temp_new_i64(); \
9378 gen_load_gpr64(t0, rB(ctx->opcode)); \
9379 gen_helper_##name(t0, cpu_env, t0); \
9380 gen_store_gpr64(rD(ctx->opcode), t0); \
9381 tcg_temp_free_i64(t0); \
9382 }
9383 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9384 static inline void gen_##name(DisasContext *ctx) \
9385 { \
9386 TCGv_i32 t0, t1; \
9387 if (unlikely(!ctx->spe_enabled)) { \
9388 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9389 return; \
9390 } \
9391 t0 = tcg_temp_new_i32(); \
9392 t1 = tcg_temp_new_i32(); \
9393 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9394 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9395 gen_helper_##name(t0, cpu_env, t0, t1); \
9396 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9397 \
9398 tcg_temp_free_i32(t0); \
9399 tcg_temp_free_i32(t1); \
9400 }
9401 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9402 static inline void gen_##name(DisasContext *ctx) \
9403 { \
9404 TCGv_i64 t0, t1; \
9405 if (unlikely(!ctx->spe_enabled)) { \
9406 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9407 return; \
9408 } \
9409 t0 = tcg_temp_new_i64(); \
9410 t1 = tcg_temp_new_i64(); \
9411 gen_load_gpr64(t0, rA(ctx->opcode)); \
9412 gen_load_gpr64(t1, rB(ctx->opcode)); \
9413 gen_helper_##name(t0, cpu_env, t0, t1); \
9414 gen_store_gpr64(rD(ctx->opcode), t0); \
9415 tcg_temp_free_i64(t0); \
9416 tcg_temp_free_i64(t1); \
9417 }
9418 #define GEN_SPEFPUOP_COMP_32(name) \
9419 static inline void gen_##name(DisasContext *ctx) \
9420 { \
9421 TCGv_i32 t0, t1; \
9422 if (unlikely(!ctx->spe_enabled)) { \
9423 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9424 return; \
9425 } \
9426 t0 = tcg_temp_new_i32(); \
9427 t1 = tcg_temp_new_i32(); \
9428 \
9429 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9430 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9431 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9432 \
9433 tcg_temp_free_i32(t0); \
9434 tcg_temp_free_i32(t1); \
9435 }
9436 #define GEN_SPEFPUOP_COMP_64(name) \
9437 static inline void gen_##name(DisasContext *ctx) \
9438 { \
9439 TCGv_i64 t0, t1; \
9440 if (unlikely(!ctx->spe_enabled)) { \
9441 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9442 return; \
9443 } \
9444 t0 = tcg_temp_new_i64(); \
9445 t1 = tcg_temp_new_i64(); \
9446 gen_load_gpr64(t0, rA(ctx->opcode)); \
9447 gen_load_gpr64(t1, rB(ctx->opcode)); \
9448 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9449 tcg_temp_free_i64(t0); \
9450 tcg_temp_free_i64(t1); \
9451 }
9452
9453 /* Single precision floating-point vectors operations */
9454 /* Arithmetic */
9455 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9456 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9457 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9458 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9459 static inline void gen_evfsabs(DisasContext *ctx)
9460 {
9461 if (unlikely(!ctx->spe_enabled)) {
9462 gen_exception(ctx, POWERPC_EXCP_SPEU);
9463 return;
9464 }
9465 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9466 ~0x80000000);
9467 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9468 ~0x80000000);
9469 }
9470 static inline void gen_evfsnabs(DisasContext *ctx)
9471 {
9472 if (unlikely(!ctx->spe_enabled)) {
9473 gen_exception(ctx, POWERPC_EXCP_SPEU);
9474 return;
9475 }
9476 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9477 0x80000000);
9478 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9479 0x80000000);
9480 }
9481 static inline void gen_evfsneg(DisasContext *ctx)
9482 {
9483 if (unlikely(!ctx->spe_enabled)) {
9484 gen_exception(ctx, POWERPC_EXCP_SPEU);
9485 return;
9486 }
9487 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9488 0x80000000);
9489 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9490 0x80000000);
9491 }
9492
9493 /* Conversion */
9494 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9495 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9496 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9497 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9498 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9499 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9500 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9501 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9502 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9503 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9504
9505 /* Comparison */
9506 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9507 GEN_SPEFPUOP_COMP_64(evfscmplt);
9508 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9509 GEN_SPEFPUOP_COMP_64(evfststgt);
9510 GEN_SPEFPUOP_COMP_64(evfststlt);
9511 GEN_SPEFPUOP_COMP_64(evfststeq);
9512
9513 /* Opcodes definitions */
9514 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9515 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9516 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9517 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9518 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9519 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9520 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9521 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9522 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9523 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9524 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9526 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9527 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9528
9529 /* Single precision floating-point operations */
9530 /* Arithmetic */
9531 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9532 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9533 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9534 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9535 static inline void gen_efsabs(DisasContext *ctx)
9536 {
9537 if (unlikely(!ctx->spe_enabled)) {
9538 gen_exception(ctx, POWERPC_EXCP_SPEU);
9539 return;
9540 }
9541 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9542 }
9543 static inline void gen_efsnabs(DisasContext *ctx)
9544 {
9545 if (unlikely(!ctx->spe_enabled)) {
9546 gen_exception(ctx, POWERPC_EXCP_SPEU);
9547 return;
9548 }
9549 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9550 }
9551 static inline void gen_efsneg(DisasContext *ctx)
9552 {
9553 if (unlikely(!ctx->spe_enabled)) {
9554 gen_exception(ctx, POWERPC_EXCP_SPEU);
9555 return;
9556 }
9557 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9558 }
9559
9560 /* Conversion */
9561 GEN_SPEFPUOP_CONV_32_32(efscfui);
9562 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9563 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9564 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9565 GEN_SPEFPUOP_CONV_32_32(efsctui);
9566 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9567 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9568 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9569 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9570 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9571 GEN_SPEFPUOP_CONV_32_64(efscfd);
9572
9573 /* Comparison */
9574 GEN_SPEFPUOP_COMP_32(efscmpgt);
9575 GEN_SPEFPUOP_COMP_32(efscmplt);
9576 GEN_SPEFPUOP_COMP_32(efscmpeq);
9577 GEN_SPEFPUOP_COMP_32(efststgt);
9578 GEN_SPEFPUOP_COMP_32(efststlt);
9579 GEN_SPEFPUOP_COMP_32(efststeq);
9580
9581 /* Opcodes definitions */
9582 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9583 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9584 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9585 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9586 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9587 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9588 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9589 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9590 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9591 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9592 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9593 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9594 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9595 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9596
9597 /* Double precision floating-point operations */
9598 /* Arithmetic */
9599 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9600 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9601 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9602 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9603 static inline void gen_efdabs(DisasContext *ctx)
9604 {
9605 if (unlikely(!ctx->spe_enabled)) {
9606 gen_exception(ctx, POWERPC_EXCP_SPEU);
9607 return;
9608 }
9609 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9610 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9611 ~0x80000000);
9612 }
9613 static inline void gen_efdnabs(DisasContext *ctx)
9614 {
9615 if (unlikely(!ctx->spe_enabled)) {
9616 gen_exception(ctx, POWERPC_EXCP_SPEU);
9617 return;
9618 }
9619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9620 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9621 0x80000000);
9622 }
9623 static inline void gen_efdneg(DisasContext *ctx)
9624 {
9625 if (unlikely(!ctx->spe_enabled)) {
9626 gen_exception(ctx, POWERPC_EXCP_SPEU);
9627 return;
9628 }
9629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9630 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9631 0x80000000);
9632 }
9633
9634 /* Conversion */
9635 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9636 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9637 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9638 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9639 GEN_SPEFPUOP_CONV_32_64(efdctui);
9640 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9641 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9642 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9643 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9644 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9645 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9646 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9647 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9648 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9649 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9650
9651 /* Comparison */
9652 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9653 GEN_SPEFPUOP_COMP_64(efdcmplt);
9654 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9655 GEN_SPEFPUOP_COMP_64(efdtstgt);
9656 GEN_SPEFPUOP_COMP_64(efdtstlt);
9657 GEN_SPEFPUOP_COMP_64(efdtsteq);
9658
9659 /* Opcodes definitions */
9660 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9661 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9662 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9663 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9664 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9665 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9666 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9667 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9668 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9669 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9670 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9672 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9673 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9674 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9675 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9676
9677 static void gen_tbegin(DisasContext *ctx)
9678 {
9679 if (unlikely(!ctx->tm_enabled)) {
9680 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9681 return;
9682 }
9683 gen_helper_tbegin(cpu_env);
9684 }
9685
9686 #define GEN_TM_NOOP(name) \
9687 static inline void gen_##name(DisasContext *ctx) \
9688 { \
9689 if (unlikely(!ctx->tm_enabled)) { \
9690 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9691 return; \
9692 } \
9693 /* Because tbegin always fails in QEMU, these user \
9694 * space instructions all have a simple implementation: \
9695 * \
9696 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9697 * = 0b0 || 0b00 || 0b0 \
9698 */ \
9699 tcg_gen_movi_i32(cpu_crf[0], 0); \
9700 }
9701
9702 GEN_TM_NOOP(tend);
9703 GEN_TM_NOOP(tabort);
9704 GEN_TM_NOOP(tabortwc);
9705 GEN_TM_NOOP(tabortwci);
9706 GEN_TM_NOOP(tabortdc);
9707 GEN_TM_NOOP(tabortdci);
9708 GEN_TM_NOOP(tsr);
9709
9710 static opcode_t opcodes[] = {
9711 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9712 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9713 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9714 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9715 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9716 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9717 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9718 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9719 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9720 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9721 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9722 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9723 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9724 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9725 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9726 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9727 #if defined(TARGET_PPC64)
9728 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9729 #endif
9730 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9731 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9732 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9733 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9734 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9735 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9736 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9737 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9738 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9739 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9740 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9741 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9742 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9743 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9744 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9745 #if defined(TARGET_PPC64)
9746 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9747 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9748 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9749 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9750 #endif
9751 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9752 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9753 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9754 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9755 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9756 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9757 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9758 #if defined(TARGET_PPC64)
9759 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9760 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9761 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9762 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9763 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9764 #endif
9765 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9766 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9767 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9768 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9769 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9770 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9771 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9772 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9773 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9774 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9775 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9776 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9777 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9778 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9779 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9780 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9781 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9782 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9783 #if defined(TARGET_PPC64)
9784 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9785 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9786 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9787 #endif
9788 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9789 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9790 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9791 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9792 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9793 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9794 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9795 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9796 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9797 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9798 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9799 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9800 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9801 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9802 #if defined(TARGET_PPC64)
9803 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9804 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9805 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9806 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9807 #endif
9808 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9809 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9810 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9811 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9812 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9813 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9814 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9815 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9816 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9817 #if defined(TARGET_PPC64)
9818 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9819 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9820 #endif
9821 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9822 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9823 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9824 #if defined(TARGET_PPC64)
9825 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9826 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9827 #endif
9828 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9829 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9830 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9831 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9832 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9833 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9834 #if defined(TARGET_PPC64)
9835 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9836 #endif
9837 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9838 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9839 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9840 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9841 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9842 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9843 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9844 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9845 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9846 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9847 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9848 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9849 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9850 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9851 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9852 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9853 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9854 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9855 #if defined(TARGET_PPC64)
9856 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9857 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9858 PPC_SEGMENT_64B),
9859 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9860 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9861 PPC_SEGMENT_64B),
9862 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9863 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9864 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9865 #endif
9866 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9867 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9868 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9869 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9870 #if defined(TARGET_PPC64)
9871 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9872 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9873 #endif
9874 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9875 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9876 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9877 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9878 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9879 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9880 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9881 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9882 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9883 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9884 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9885 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9886 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9887 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9888 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9889 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9890 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9891 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9892 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9893 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9894 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9895 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9896 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9897 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9898 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9899 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9900 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9901 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9902 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9903 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9904 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9905 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9906 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9907 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9908 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9909 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9910 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9911 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9912 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9913 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9914 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9915 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9916 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9917 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9918 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9919 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9920 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9921 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9922 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9923 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9924 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9925 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9926 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9927 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9928 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9929 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9930 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9931 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9932 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9933 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9934 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9935 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9936 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9937 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9938 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9939 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9940 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9941 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9942 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9943 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9944 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9945 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9946 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9947 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9948 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9949 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9950 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9951 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9952 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9953 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9954 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9955 PPC_NONE, PPC2_BOOKE206),
9956 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9957 PPC_NONE, PPC2_BOOKE206),
9958 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9959 PPC_NONE, PPC2_BOOKE206),
9960 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9961 PPC_NONE, PPC2_BOOKE206),
9962 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9963 PPC_NONE, PPC2_BOOKE206),
9964 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9965 PPC_NONE, PPC2_PRCNTL),
9966 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9967 PPC_NONE, PPC2_PRCNTL),
9968 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9969 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9970 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9971 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9972 PPC_BOOKE, PPC2_BOOKE206),
9973 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9974 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9975 PPC_BOOKE, PPC2_BOOKE206),
9976 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9977 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9978 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9979 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9980 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9981 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9982 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9983 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9984 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9985
9986 #undef GEN_INT_ARITH_ADD
9987 #undef GEN_INT_ARITH_ADD_CONST
9988 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9989 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9990 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9991 add_ca, compute_ca, compute_ov) \
9992 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9993 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9994 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9995 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9996 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9997 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9998 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9999 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10000 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10001 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10002 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10003
10004 #undef GEN_INT_ARITH_DIVW
10005 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10006 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10009 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10010 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10011 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10012 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10013 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10014 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10015
10016 #if defined(TARGET_PPC64)
10017 #undef GEN_INT_ARITH_DIVD
10018 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10019 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10020 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10021 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10022 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10023 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10024
10025 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10026 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10027 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10028 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10029
10030 #undef GEN_INT_ARITH_MUL_HELPER
10031 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10032 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10033 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10034 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10035 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10036 #endif
10037
10038 #undef GEN_INT_ARITH_SUBF
10039 #undef GEN_INT_ARITH_SUBF_CONST
10040 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10041 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10042 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10043 add_ca, compute_ca, compute_ov) \
10044 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10045 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10046 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10047 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10048 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10049 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10050 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10051 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10052 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10053 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10054 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10055
10056 #undef GEN_LOGICAL1
10057 #undef GEN_LOGICAL2
10058 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10059 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10060 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10061 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10062 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10063 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10064 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10065 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10066 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10067 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10068 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10069 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10070 #if defined(TARGET_PPC64)
10071 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10072 #endif
10073
10074 #if defined(TARGET_PPC64)
10075 #undef GEN_PPC64_R2
10076 #undef GEN_PPC64_R4
10077 #define GEN_PPC64_R2(name, opc1, opc2) \
10078 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10079 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10080 PPC_64B)
10081 #define GEN_PPC64_R4(name, opc1, opc2) \
10082 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10083 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10084 PPC_64B), \
10085 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10086 PPC_64B), \
10087 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10088 PPC_64B)
10089 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10090 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10091 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10092 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10093 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10094 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10095 #endif
10096
10097 #undef _GEN_FLOAT_ACB
10098 #undef GEN_FLOAT_ACB
10099 #undef _GEN_FLOAT_AB
10100 #undef GEN_FLOAT_AB
10101 #undef _GEN_FLOAT_AC
10102 #undef GEN_FLOAT_AC
10103 #undef GEN_FLOAT_B
10104 #undef GEN_FLOAT_BS
10105 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10106 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10107 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10108 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10109 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10110 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10111 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10112 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10113 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10114 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10115 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10116 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10117 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10118 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10119 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10120 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10121 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10122 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10123 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10124
10125 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10126 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10127 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10128 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10129 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10130 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10131 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10132 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10133 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10134 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10135 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10136 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10137 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10138 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10139 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10140 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10141 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10142 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10143 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10144 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10145 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10146 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10147 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10148 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10149 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10150 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10151 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10152 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10153 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10154 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10155 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10156
10157 #undef GEN_LD
10158 #undef GEN_LDU
10159 #undef GEN_LDUX
10160 #undef GEN_LDX_E
10161 #undef GEN_LDS
10162 #define GEN_LD(name, ldop, opc, type) \
10163 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10164 #define GEN_LDU(name, ldop, opc, type) \
10165 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10166 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10167 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10168 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10169 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10170 #define GEN_LDS(name, ldop, op, type) \
10171 GEN_LD(name, ldop, op | 0x20, type) \
10172 GEN_LDU(name, ldop, op | 0x21, type) \
10173 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10174 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10175
10176 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10177 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10178 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10179 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10180 #if defined(TARGET_PPC64)
10181 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10182 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10183 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10184 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10185 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10186 #endif
10187 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10188 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10189
10190 #undef GEN_ST
10191 #undef GEN_STU
10192 #undef GEN_STUX
10193 #undef GEN_STX_E
10194 #undef GEN_STS
10195 #define GEN_ST(name, stop, opc, type) \
10196 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10197 #define GEN_STU(name, stop, opc, type) \
10198 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10199 #define GEN_STUX(name, stop, opc2, opc3, type) \
10200 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10201 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10202 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10203 #define GEN_STS(name, stop, op, type) \
10204 GEN_ST(name, stop, op | 0x20, type) \
10205 GEN_STU(name, stop, op | 0x21, type) \
10206 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10207 GEN_STX(name, stop, 0x17, op | 0x00, type)
10208
10209 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10210 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10211 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10212 #if defined(TARGET_PPC64)
10213 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10214 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10215 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10216 #endif
10217 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10218 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10219
10220 #undef GEN_LDF
10221 #undef GEN_LDUF
10222 #undef GEN_LDUXF
10223 #undef GEN_LDXF
10224 #undef GEN_LDFS
10225 #define GEN_LDF(name, ldop, opc, type) \
10226 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10227 #define GEN_LDUF(name, ldop, opc, type) \
10228 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10229 #define GEN_LDUXF(name, ldop, opc, type) \
10230 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10231 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10232 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10233 #define GEN_LDFS(name, ldop, op, type) \
10234 GEN_LDF(name, ldop, op | 0x20, type) \
10235 GEN_LDUF(name, ldop, op | 0x21, type) \
10236 GEN_LDUXF(name, ldop, op | 0x01, type) \
10237 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10238
10239 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10240 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10241 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10242 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10243 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10244 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10245
10246 #undef GEN_STF
10247 #undef GEN_STUF
10248 #undef GEN_STUXF
10249 #undef GEN_STXF
10250 #undef GEN_STFS
10251 #define GEN_STF(name, stop, opc, type) \
10252 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10253 #define GEN_STUF(name, stop, opc, type) \
10254 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10255 #define GEN_STUXF(name, stop, opc, type) \
10256 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10257 #define GEN_STXF(name, stop, opc2, opc3, type) \
10258 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10259 #define GEN_STFS(name, stop, op, type) \
10260 GEN_STF(name, stop, op | 0x20, type) \
10261 GEN_STUF(name, stop, op | 0x21, type) \
10262 GEN_STUXF(name, stop, op | 0x01, type) \
10263 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10264
10265 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10266 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10267 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10268 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10269 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10270
10271 #undef GEN_CRLOGIC
10272 #define GEN_CRLOGIC(name, tcg_op, opc) \
10273 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10274 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10275 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10276 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10277 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10278 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10279 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10280 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10281 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10282
10283 #undef GEN_MAC_HANDLER
10284 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10285 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10286 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10287 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10288 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10289 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10290 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10291 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10292 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10293 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10294 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10295 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10296 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10297 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10298 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10299 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10300 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10301 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10302 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10303 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10304 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10305 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10306 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10307 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10308 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10309 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10310 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10311 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10312 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10313 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10314 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10315 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10316 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10317 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10318 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10319 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10320 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10321 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10322 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10323 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10324 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10325 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10326 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10327 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10328
10329 #undef GEN_VR_LDX
10330 #undef GEN_VR_STX
10331 #undef GEN_VR_LVE
10332 #undef GEN_VR_STVE
10333 #define GEN_VR_LDX(name, opc2, opc3) \
10334 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10335 #define GEN_VR_STX(name, opc2, opc3) \
10336 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10337 #define GEN_VR_LVE(name, opc2, opc3) \
10338 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10339 #define GEN_VR_STVE(name, opc2, opc3) \
10340 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10341 GEN_VR_LDX(lvx, 0x07, 0x03),
10342 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10343 GEN_VR_LVE(bx, 0x07, 0x00),
10344 GEN_VR_LVE(hx, 0x07, 0x01),
10345 GEN_VR_LVE(wx, 0x07, 0x02),
10346 GEN_VR_STX(svx, 0x07, 0x07),
10347 GEN_VR_STX(svxl, 0x07, 0x0F),
10348 GEN_VR_STVE(bx, 0x07, 0x04),
10349 GEN_VR_STVE(hx, 0x07, 0x05),
10350 GEN_VR_STVE(wx, 0x07, 0x06),
10351
10352 #undef GEN_VX_LOGICAL
10353 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10354 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10355
10356 #undef GEN_VX_LOGICAL_207
10357 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10358 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10359
10360 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10361 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10362 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10363 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10364 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10365 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10366 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10367 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10368
10369 #undef GEN_VXFORM
10370 #define GEN_VXFORM(name, opc2, opc3) \
10371 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10372
10373 #undef GEN_VXFORM_207
10374 #define GEN_VXFORM_207(name, opc2, opc3) \
10375 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10376
10377 #undef GEN_VXFORM_DUAL
10378 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10379 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10380
10381 #undef GEN_VXRFORM_DUAL
10382 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10383 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10384 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10385
10386 GEN_VXFORM(vaddubm, 0, 0),
10387 GEN_VXFORM(vadduhm, 0, 1),
10388 GEN_VXFORM(vadduwm, 0, 2),
10389 GEN_VXFORM_207(vaddudm, 0, 3),
10390 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10391 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10392 GEN_VXFORM(vsubuwm, 0, 18),
10393 GEN_VXFORM_207(vsubudm, 0, 19),
10394 GEN_VXFORM(vmaxub, 1, 0),
10395 GEN_VXFORM(vmaxuh, 1, 1),
10396 GEN_VXFORM(vmaxuw, 1, 2),
10397 GEN_VXFORM_207(vmaxud, 1, 3),
10398 GEN_VXFORM(vmaxsb, 1, 4),
10399 GEN_VXFORM(vmaxsh, 1, 5),
10400 GEN_VXFORM(vmaxsw, 1, 6),
10401 GEN_VXFORM_207(vmaxsd, 1, 7),
10402 GEN_VXFORM(vminub, 1, 8),
10403 GEN_VXFORM(vminuh, 1, 9),
10404 GEN_VXFORM(vminuw, 1, 10),
10405 GEN_VXFORM_207(vminud, 1, 11),
10406 GEN_VXFORM(vminsb, 1, 12),
10407 GEN_VXFORM(vminsh, 1, 13),
10408 GEN_VXFORM(vminsw, 1, 14),
10409 GEN_VXFORM_207(vminsd, 1, 15),
10410 GEN_VXFORM(vavgub, 1, 16),
10411 GEN_VXFORM(vavguh, 1, 17),
10412 GEN_VXFORM(vavguw, 1, 18),
10413 GEN_VXFORM(vavgsb, 1, 20),
10414 GEN_VXFORM(vavgsh, 1, 21),
10415 GEN_VXFORM(vavgsw, 1, 22),
10416 GEN_VXFORM(vmrghb, 6, 0),
10417 GEN_VXFORM(vmrghh, 6, 1),
10418 GEN_VXFORM(vmrghw, 6, 2),
10419 GEN_VXFORM(vmrglb, 6, 4),
10420 GEN_VXFORM(vmrglh, 6, 5),
10421 GEN_VXFORM(vmrglw, 6, 6),
10422 GEN_VXFORM_207(vmrgew, 6, 30),
10423 GEN_VXFORM_207(vmrgow, 6, 26),
10424 GEN_VXFORM(vmuloub, 4, 0),
10425 GEN_VXFORM(vmulouh, 4, 1),
10426 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10427 GEN_VXFORM(vmulosb, 4, 4),
10428 GEN_VXFORM(vmulosh, 4, 5),
10429 GEN_VXFORM_207(vmulosw, 4, 6),
10430 GEN_VXFORM(vmuleub, 4, 8),
10431 GEN_VXFORM(vmuleuh, 4, 9),
10432 GEN_VXFORM_207(vmuleuw, 4, 10),
10433 GEN_VXFORM(vmulesb, 4, 12),
10434 GEN_VXFORM(vmulesh, 4, 13),
10435 GEN_VXFORM_207(vmulesw, 4, 14),
10436 GEN_VXFORM(vslb, 2, 4),
10437 GEN_VXFORM(vslh, 2, 5),
10438 GEN_VXFORM(vslw, 2, 6),
10439 GEN_VXFORM_207(vsld, 2, 23),
10440 GEN_VXFORM(vsrb, 2, 8),
10441 GEN_VXFORM(vsrh, 2, 9),
10442 GEN_VXFORM(vsrw, 2, 10),
10443 GEN_VXFORM_207(vsrd, 2, 27),
10444 GEN_VXFORM(vsrab, 2, 12),
10445 GEN_VXFORM(vsrah, 2, 13),
10446 GEN_VXFORM(vsraw, 2, 14),
10447 GEN_VXFORM_207(vsrad, 2, 15),
10448 GEN_VXFORM(vslo, 6, 16),
10449 GEN_VXFORM(vsro, 6, 17),
10450 GEN_VXFORM(vaddcuw, 0, 6),
10451 GEN_VXFORM(vsubcuw, 0, 22),
10452 GEN_VXFORM(vaddubs, 0, 8),
10453 GEN_VXFORM(vadduhs, 0, 9),
10454 GEN_VXFORM(vadduws, 0, 10),
10455 GEN_VXFORM(vaddsbs, 0, 12),
10456 GEN_VXFORM(vaddshs, 0, 13),
10457 GEN_VXFORM(vaddsws, 0, 14),
10458 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10459 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10460 GEN_VXFORM(vsubuws, 0, 26),
10461 GEN_VXFORM(vsubsbs, 0, 28),
10462 GEN_VXFORM(vsubshs, 0, 29),
10463 GEN_VXFORM(vsubsws, 0, 30),
10464 GEN_VXFORM_207(vadduqm, 0, 4),
10465 GEN_VXFORM_207(vaddcuq, 0, 5),
10466 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10467 GEN_VXFORM_207(vsubuqm, 0, 20),
10468 GEN_VXFORM_207(vsubcuq, 0, 21),
10469 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10470 GEN_VXFORM(vrlb, 2, 0),
10471 GEN_VXFORM(vrlh, 2, 1),
10472 GEN_VXFORM(vrlw, 2, 2),
10473 GEN_VXFORM_207(vrld, 2, 3),
10474 GEN_VXFORM(vsl, 2, 7),
10475 GEN_VXFORM(vsr, 2, 11),
10476 GEN_VXFORM(vpkuhum, 7, 0),
10477 GEN_VXFORM(vpkuwum, 7, 1),
10478 GEN_VXFORM_207(vpkudum, 7, 17),
10479 GEN_VXFORM(vpkuhus, 7, 2),
10480 GEN_VXFORM(vpkuwus, 7, 3),
10481 GEN_VXFORM_207(vpkudus, 7, 19),
10482 GEN_VXFORM(vpkshus, 7, 4),
10483 GEN_VXFORM(vpkswus, 7, 5),
10484 GEN_VXFORM_207(vpksdus, 7, 21),
10485 GEN_VXFORM(vpkshss, 7, 6),
10486 GEN_VXFORM(vpkswss, 7, 7),
10487 GEN_VXFORM_207(vpksdss, 7, 23),
10488 GEN_VXFORM(vpkpx, 7, 12),
10489 GEN_VXFORM(vsum4ubs, 4, 24),
10490 GEN_VXFORM(vsum4sbs, 4, 28),
10491 GEN_VXFORM(vsum4shs, 4, 25),
10492 GEN_VXFORM(vsum2sws, 4, 26),
10493 GEN_VXFORM(vsumsws, 4, 30),
10494 GEN_VXFORM(vaddfp, 5, 0),
10495 GEN_VXFORM(vsubfp, 5, 1),
10496 GEN_VXFORM(vmaxfp, 5, 16),
10497 GEN_VXFORM(vminfp, 5, 17),
10498
10499 #undef GEN_VXRFORM1
10500 #undef GEN_VXRFORM
10501 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10502 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10503 #define GEN_VXRFORM(name, opc2, opc3) \
10504 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10505 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10506 GEN_VXRFORM(vcmpequb, 3, 0)
10507 GEN_VXRFORM(vcmpequh, 3, 1)
10508 GEN_VXRFORM(vcmpequw, 3, 2)
10509 GEN_VXRFORM(vcmpgtsb, 3, 12)
10510 GEN_VXRFORM(vcmpgtsh, 3, 13)
10511 GEN_VXRFORM(vcmpgtsw, 3, 14)
10512 GEN_VXRFORM(vcmpgtub, 3, 8)
10513 GEN_VXRFORM(vcmpgtuh, 3, 9)
10514 GEN_VXRFORM(vcmpgtuw, 3, 10)
10515 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10516 GEN_VXRFORM(vcmpgefp, 3, 7)
10517 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10518 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10519
10520 #undef GEN_VXFORM_SIMM
10521 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10522 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10523 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10524 GEN_VXFORM_SIMM(vspltish, 6, 13),
10525 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10526
10527 #undef GEN_VXFORM_NOA
10528 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10529 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10530 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10531 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10532 GEN_VXFORM_207(vupkhsw, 7, 25),
10533 GEN_VXFORM_NOA(vupklsb, 7, 10),
10534 GEN_VXFORM_NOA(vupklsh, 7, 11),
10535 GEN_VXFORM_207(vupklsw, 7, 27),
10536 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10537 GEN_VXFORM_NOA(vupklpx, 7, 15),
10538 GEN_VXFORM_NOA(vrefp, 5, 4),
10539 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10540 GEN_VXFORM_NOA(vexptefp, 5, 6),
10541 GEN_VXFORM_NOA(vlogefp, 5, 7),
10542 GEN_VXFORM_NOA(vrfim, 5, 11),
10543 GEN_VXFORM_NOA(vrfin, 5, 8),
10544 GEN_VXFORM_NOA(vrfip, 5, 10),
10545 GEN_VXFORM_NOA(vrfiz, 5, 9),
10546
10547 #undef GEN_VXFORM_UIMM
10548 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10549 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10550 GEN_VXFORM_UIMM(vspltb, 6, 8),
10551 GEN_VXFORM_UIMM(vsplth, 6, 9),
10552 GEN_VXFORM_UIMM(vspltw, 6, 10),
10553 GEN_VXFORM_UIMM(vcfux, 5, 12),
10554 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10555 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10556 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10557
10558 #undef GEN_VAFORM_PAIRED
10559 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10560 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10561 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10562 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10563 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10564 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10565 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10566 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10567
10568 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10569 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10570 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10571 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10572
10573 GEN_VXFORM_207(vbpermq, 6, 21),
10574 GEN_VXFORM_207(vgbbd, 6, 20),
10575 GEN_VXFORM_207(vpmsumb, 4, 16),
10576 GEN_VXFORM_207(vpmsumh, 4, 17),
10577 GEN_VXFORM_207(vpmsumw, 4, 18),
10578 GEN_VXFORM_207(vpmsumd, 4, 19),
10579
10580 GEN_VXFORM_207(vsbox, 4, 23),
10581
10582 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10583 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10584
10585 GEN_VXFORM_207(vshasigmaw, 1, 26),
10586 GEN_VXFORM_207(vshasigmad, 1, 27),
10587
10588 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10589
10590 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10591 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10592 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10593 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10594 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10595 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10596 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10597
10598 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10599 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10600 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10601 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10602 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10603
10604 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10605 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10606 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10607 #if defined(TARGET_PPC64)
10608 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10609 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10610 #endif
10611
10612 #undef GEN_XX2FORM
10613 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10614 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10615 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10616
10617 #undef GEN_XX3FORM
10618 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10619 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10620 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10621 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10622 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10623
10624 #undef GEN_XX3_RC_FORM
10625 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10626 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10627 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10628 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10629 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10630 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10631 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10632 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10633 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10634
10635 #undef GEN_XX3FORM_DM
10636 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10637 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10638 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10639 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10640 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10641 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10642 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10643 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10644 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10645 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10646 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10647 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10648 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10649 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10650 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10651 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10652 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10653
10654 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10655 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10656 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10657 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10658
10659 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10660 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10661 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10662 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10663 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10664 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10665 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10666 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10667
10668 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10669 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10670 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10671 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10672 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10673 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10674 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10675 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10676 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10677 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10678 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10679 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10680 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10681 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10682 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10683 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10684 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10685 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10686 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10687 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10688 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10689 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10690 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10691 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10692 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10693 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10694 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10695 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10696 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10697 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10698 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10699 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10700 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10701 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10702 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10703 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10704
10705 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10706 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10707 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10708 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10709 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10710 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10711 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10712 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10713 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10714 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10715 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10716 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10717 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10718 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10719 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10720 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10721 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10722 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10723
10724 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10725 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10726 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10727 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10728 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10729 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10730 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10731 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10732 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10733 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10734 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10735 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10736 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10737 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10738 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10739 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10740 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10741 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10742 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10743 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10744 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10745 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10746 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10747 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10748 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10749 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10750 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10751 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10752 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10753 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10754 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10755 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10756 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10757 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10758 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10759 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10760
10761 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10762 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10763 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10764 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10765 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10766 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10767 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10768 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10769 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10770 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10771 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10772 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10773 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10774 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10775 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10776 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10777 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10778 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10779 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10780 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10781 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10782 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10783 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10784 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10785 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10786 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10787 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10788 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10789 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10790 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10791 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10792 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10793 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10794 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10795 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10796 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10797
10798 #undef VSX_LOGICAL
10799 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10800 GEN_XX3FORM(name, opc2, opc3, fl2)
10801
10802 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10803 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10804 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10805 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10806 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10807 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10808 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10809 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10810 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10811 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10812 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10813 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10814
10815 #define GEN_XXSEL_ROW(opc3) \
10816 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10817 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10818 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10819 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10820 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10821 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10822 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10823 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10824
10825 GEN_XXSEL_ROW(0x00)
10826 GEN_XXSEL_ROW(0x01)
10827 GEN_XXSEL_ROW(0x02)
10828 GEN_XXSEL_ROW(0x03)
10829 GEN_XXSEL_ROW(0x04)
10830 GEN_XXSEL_ROW(0x05)
10831 GEN_XXSEL_ROW(0x06)
10832 GEN_XXSEL_ROW(0x07)
10833 GEN_XXSEL_ROW(0x08)
10834 GEN_XXSEL_ROW(0x09)
10835 GEN_XXSEL_ROW(0x0A)
10836 GEN_XXSEL_ROW(0x0B)
10837 GEN_XXSEL_ROW(0x0C)
10838 GEN_XXSEL_ROW(0x0D)
10839 GEN_XXSEL_ROW(0x0E)
10840 GEN_XXSEL_ROW(0x0F)
10841 GEN_XXSEL_ROW(0x10)
10842 GEN_XXSEL_ROW(0x11)
10843 GEN_XXSEL_ROW(0x12)
10844 GEN_XXSEL_ROW(0x13)
10845 GEN_XXSEL_ROW(0x14)
10846 GEN_XXSEL_ROW(0x15)
10847 GEN_XXSEL_ROW(0x16)
10848 GEN_XXSEL_ROW(0x17)
10849 GEN_XXSEL_ROW(0x18)
10850 GEN_XXSEL_ROW(0x19)
10851 GEN_XXSEL_ROW(0x1A)
10852 GEN_XXSEL_ROW(0x1B)
10853 GEN_XXSEL_ROW(0x1C)
10854 GEN_XXSEL_ROW(0x1D)
10855 GEN_XXSEL_ROW(0x1E)
10856 GEN_XXSEL_ROW(0x1F)
10857
10858 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10859
10860 #undef GEN_DFP_T_A_B_Rc
10861 #undef GEN_DFP_BF_A_B
10862 #undef GEN_DFP_BF_A_DCM
10863 #undef GEN_DFP_T_B_U32_U32_Rc
10864 #undef GEN_DFP_T_A_B_I32_Rc
10865 #undef GEN_DFP_T_B_Rc
10866 #undef GEN_DFP_T_FPR_I32_Rc
10867
10868 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10869 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10870
10871 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10872 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10873 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10874
10875 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10876 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10877 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10878 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10879 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10880
10881 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10882 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10883
10884 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10885 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10886 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10887
10888 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10889 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10890 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10891 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10892 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10893
10894 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10895 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10896
10897 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10898 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10899
10900 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10901 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10902
10903 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10904 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10905
10906 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10907 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10908
10909 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10910 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10911
10912 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10913 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10914
10915 #define GEN_DFP_BF_A_B(name, op1, op2) \
10916 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10917
10918 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10919 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10920
10921 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10922 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10923
10924 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10925 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10926
10927 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10928 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10929
10930 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10931 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10932
10933 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10934 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10935
10936 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10937 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10938
10939 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10940 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10941
10942 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10943 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10944
10945 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10946 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10947
10948 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10949 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10950
10951 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10952 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10953
10954 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10955 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10956
10957 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10958 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10959
10960 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10961 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10962
10963 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10964 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10965
10966 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10967 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10968
10969 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10970 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10971 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10972 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10973 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10974 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10975 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10976 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10977 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10978 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10979 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10980 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10981 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10982 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10983 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10984 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10985 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10986 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10987 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10988 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10989 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10990 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10991 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10992 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10993 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10994 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10995 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10996 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10997 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10998 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10999 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11000 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11001 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11002 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11003 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11004 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11005 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11006 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11007 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11008 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11009 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11010 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11011 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11012 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11013 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11014 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11015 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11016 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11017 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11018 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11019
11020 #undef GEN_SPE
11021 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11022 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11023 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11024 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11025 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11026 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11027 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11028 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11029 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11030 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11031 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11032 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11033 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11034 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11035 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11036 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11037 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11038 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11039 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11040 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11041 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11042 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11043 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11044 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11045 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11046 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11047 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11048 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11049 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11050 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11051 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11052
11053 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11054 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11055 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11056 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11057 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11058 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11059 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11060 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11061 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11062 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11063 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11064 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11065 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11066 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11067
11068 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11069 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11070 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11071 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11072 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11073 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11074 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11075 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11076 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11077 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11078 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11079 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11080 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11081 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11082
11083 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11084 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11085 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11086 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11087 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11088 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11089 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11090 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11091 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11092 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11093 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11094 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11095 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11096 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11097 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11098 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11099
11100 #undef GEN_SPEOP_LDST
11101 #define GEN_SPEOP_LDST(name, opc2, sh) \
11102 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11103 GEN_SPEOP_LDST(evldd, 0x00, 3),
11104 GEN_SPEOP_LDST(evldw, 0x01, 3),
11105 GEN_SPEOP_LDST(evldh, 0x02, 3),
11106 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11107 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11108 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11109 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11110 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11111 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11112 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11113 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11114
11115 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11116 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11117 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11118 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11119 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11120 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11121 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11122
11123 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11124 PPC_NONE, PPC2_TM),
11125 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11126 PPC_NONE, PPC2_TM),
11127 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11128 PPC_NONE, PPC2_TM),
11129 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11130 PPC_NONE, PPC2_TM),
11131 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11132 PPC_NONE, PPC2_TM),
11133 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11134 PPC_NONE, PPC2_TM),
11135 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11136 PPC_NONE, PPC2_TM),
11137 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11138 PPC_NONE, PPC2_TM),
11139 };
11140
11141 #include "helper_regs.h"
11142 #include "translate_init.c"
11143
11144 /*****************************************************************************/
11145 /* Misc PowerPC helpers */
11146 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11147 int flags)
11148 {
11149 #define RGPL 4
11150 #define RFPL 4
11151
11152 PowerPCCPU *cpu = POWERPC_CPU(cs);
11153 CPUPPCState *env = &cpu->env;
11154 int i;
11155
11156 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11157 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11158 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11159 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11160 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11161 env->hflags, env->mmu_idx);
11162 #if !defined(NO_TIMER_DUMP)
11163 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11164 #if !defined(CONFIG_USER_ONLY)
11165 " DECR %08" PRIu32
11166 #endif
11167 "\n",
11168 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11169 #if !defined(CONFIG_USER_ONLY)
11170 , cpu_ppc_load_decr(env)
11171 #endif
11172 );
11173 #endif
11174 for (i = 0; i < 32; i++) {
11175 if ((i & (RGPL - 1)) == 0)
11176 cpu_fprintf(f, "GPR%02d", i);
11177 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11178 if ((i & (RGPL - 1)) == (RGPL - 1))
11179 cpu_fprintf(f, "\n");
11180 }
11181 cpu_fprintf(f, "CR ");
11182 for (i = 0; i < 8; i++)
11183 cpu_fprintf(f, "%01x", env->crf[i]);
11184 cpu_fprintf(f, " [");
11185 for (i = 0; i < 8; i++) {
11186 char a = '-';
11187 if (env->crf[i] & 0x08)
11188 a = 'L';
11189 else if (env->crf[i] & 0x04)
11190 a = 'G';
11191 else if (env->crf[i] & 0x02)
11192 a = 'E';
11193 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11194 }
11195 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11196 env->reserve_addr);
11197 for (i = 0; i < 32; i++) {
11198 if ((i & (RFPL - 1)) == 0)
11199 cpu_fprintf(f, "FPR%02d", i);
11200 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11201 if ((i & (RFPL - 1)) == (RFPL - 1))
11202 cpu_fprintf(f, "\n");
11203 }
11204 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11205 #if !defined(CONFIG_USER_ONLY)
11206 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11207 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11208 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11209 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11210
11211 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11212 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11213 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11214 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11215
11216 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11217 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11218 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11219 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11220
11221 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11222 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11223 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11224 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11225 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11226
11227 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11228 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11229 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11230 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11231
11232 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11233 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11234 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11235 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11236
11237 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11238 " EPR " TARGET_FMT_lx "\n",
11239 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11240 env->spr[SPR_BOOKE_EPR]);
11241
11242 /* FSL-specific */
11243 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11244 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11245 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11246 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11247
11248 /*
11249 * IVORs are left out as they are large and do not change often --
11250 * they can be read with "p $ivor0", "p $ivor1", etc.
11251 */
11252 }
11253
11254 #if defined(TARGET_PPC64)
11255 if (env->flags & POWERPC_FLAG_CFAR) {
11256 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11257 }
11258 #endif
11259
11260 switch (env->mmu_model) {
11261 case POWERPC_MMU_32B:
11262 case POWERPC_MMU_601:
11263 case POWERPC_MMU_SOFT_6xx:
11264 case POWERPC_MMU_SOFT_74xx:
11265 #if defined(TARGET_PPC64)
11266 case POWERPC_MMU_64B:
11267 case POWERPC_MMU_2_06:
11268 case POWERPC_MMU_2_06a:
11269 case POWERPC_MMU_2_06d:
11270 #endif
11271 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11272 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11273 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11274 break;
11275 case POWERPC_MMU_BOOKE206:
11276 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11277 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11278 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11279 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11280
11281 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11282 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11283 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11284 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11285
11286 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11287 " TLB1CFG " TARGET_FMT_lx "\n",
11288 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11289 env->spr[SPR_BOOKE_TLB1CFG]);
11290 break;
11291 default:
11292 break;
11293 }
11294 #endif
11295
11296 #undef RGPL
11297 #undef RFPL
11298 }
11299
11300 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11301 fprintf_function cpu_fprintf, int flags)
11302 {
11303 #if defined(DO_PPC_STATISTICS)
11304 PowerPCCPU *cpu = POWERPC_CPU(cs);
11305 opc_handler_t **t1, **t2, **t3, *handler;
11306 int op1, op2, op3;
11307
11308 t1 = cpu->env.opcodes;
11309 for (op1 = 0; op1 < 64; op1++) {
11310 handler = t1[op1];
11311 if (is_indirect_opcode(handler)) {
11312 t2 = ind_table(handler);
11313 for (op2 = 0; op2 < 32; op2++) {
11314 handler = t2[op2];
11315 if (is_indirect_opcode(handler)) {
11316 t3 = ind_table(handler);
11317 for (op3 = 0; op3 < 32; op3++) {
11318 handler = t3[op3];
11319 if (handler->count == 0)
11320 continue;
11321 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11322 "%016" PRIx64 " %" PRId64 "\n",
11323 op1, op2, op3, op1, (op3 << 5) | op2,
11324 handler->oname,
11325 handler->count, handler->count);
11326 }
11327 } else {
11328 if (handler->count == 0)
11329 continue;
11330 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11331 "%016" PRIx64 " %" PRId64 "\n",
11332 op1, op2, op1, op2, handler->oname,
11333 handler->count, handler->count);
11334 }
11335 }
11336 } else {
11337 if (handler->count == 0)
11338 continue;
11339 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11340 " %" PRId64 "\n",
11341 op1, op1, handler->oname,
11342 handler->count, handler->count);
11343 }
11344 }
11345 #endif
11346 }
11347
11348 /*****************************************************************************/
11349 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11350 TranslationBlock *tb,
11351 bool search_pc)
11352 {
11353 CPUState *cs = CPU(cpu);
11354 CPUPPCState *env = &cpu->env;
11355 DisasContext ctx, *ctxp = &ctx;
11356 opc_handler_t **table, *handler;
11357 target_ulong pc_start;
11358 uint16_t *gen_opc_end;
11359 CPUBreakpoint *bp;
11360 int j, lj = -1;
11361 int num_insns;
11362 int max_insns;
11363
11364 pc_start = tb->pc;
11365 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11366 ctx.nip = pc_start;
11367 ctx.tb = tb;
11368 ctx.exception = POWERPC_EXCP_NONE;
11369 ctx.spr_cb = env->spr_cb;
11370 ctx.pr = msr_pr;
11371 ctx.hv = !msr_pr && msr_hv;
11372 ctx.mem_idx = env->mmu_idx;
11373 ctx.insns_flags = env->insns_flags;
11374 ctx.insns_flags2 = env->insns_flags2;
11375 ctx.access_type = -1;
11376 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11377 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11378 #if defined(TARGET_PPC64)
11379 ctx.sf_mode = msr_is_64bit(env, env->msr);
11380 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11381 #endif
11382 ctx.fpu_enabled = msr_fp;
11383 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11384 ctx.spe_enabled = msr_spe;
11385 else
11386 ctx.spe_enabled = 0;
11387 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11388 ctx.altivec_enabled = msr_vr;
11389 else
11390 ctx.altivec_enabled = 0;
11391 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11392 ctx.vsx_enabled = msr_vsx;
11393 } else {
11394 ctx.vsx_enabled = 0;
11395 }
11396 #if defined(TARGET_PPC64)
11397 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11398 ctx.tm_enabled = msr_tm;
11399 } else {
11400 ctx.tm_enabled = 0;
11401 }
11402 #endif
11403 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11404 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11405 else
11406 ctx.singlestep_enabled = 0;
11407 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11408 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11409 if (unlikely(cs->singlestep_enabled)) {
11410 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11411 }
11412 #if defined (DO_SINGLE_STEP) && 0
11413 /* Single step trace mode */
11414 msr_se = 1;
11415 #endif
11416 num_insns = 0;
11417 max_insns = tb->cflags & CF_COUNT_MASK;
11418 if (max_insns == 0)
11419 max_insns = CF_COUNT_MASK;
11420
11421 gen_tb_start();
11422 tcg_clear_temp_count();
11423 /* Set env in case of segfault during code fetch */
11424 while (ctx.exception == POWERPC_EXCP_NONE
11425 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11426 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11427 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11428 if (bp->pc == ctx.nip) {
11429 gen_debug_exception(ctxp);
11430 break;
11431 }
11432 }
11433 }
11434 if (unlikely(search_pc)) {
11435 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11436 if (lj < j) {
11437 lj++;
11438 while (lj < j)
11439 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11440 }
11441 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11442 tcg_ctx.gen_opc_instr_start[lj] = 1;
11443 tcg_ctx.gen_opc_icount[lj] = num_insns;
11444 }
11445 LOG_DISAS("----------------\n");
11446 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11447 ctx.nip, ctx.mem_idx, (int)msr_ir);
11448 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11449 gen_io_start();
11450 if (unlikely(need_byteswap(&ctx))) {
11451 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11452 } else {
11453 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11454 }
11455 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11456 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11457 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11458 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11459 tcg_gen_debug_insn_start(ctx.nip);
11460 }
11461 ctx.nip += 4;
11462 table = env->opcodes;
11463 num_insns++;
11464 handler = table[opc1(ctx.opcode)];
11465 if (is_indirect_opcode(handler)) {
11466 table = ind_table(handler);
11467 handler = table[opc2(ctx.opcode)];
11468 if (is_indirect_opcode(handler)) {
11469 table = ind_table(handler);
11470 handler = table[opc3(ctx.opcode)];
11471 }
11472 }
11473 /* Is opcode *REALLY* valid ? */
11474 if (unlikely(handler->handler == &gen_invalid)) {
11475 if (qemu_log_enabled()) {
11476 qemu_log("invalid/unsupported opcode: "
11477 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11478 opc1(ctx.opcode), opc2(ctx.opcode),
11479 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11480 }
11481 } else {
11482 uint32_t inval;
11483
11484 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11485 inval = handler->inval2;
11486 } else {
11487 inval = handler->inval1;
11488 }
11489
11490 if (unlikely((ctx.opcode & inval) != 0)) {
11491 if (qemu_log_enabled()) {
11492 qemu_log("invalid bits: %08x for opcode: "
11493 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11494 ctx.opcode & inval, opc1(ctx.opcode),
11495 opc2(ctx.opcode), opc3(ctx.opcode),
11496 ctx.opcode, ctx.nip - 4);
11497 }
11498 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11499 break;
11500 }
11501 }
11502 (*(handler->handler))(&ctx);
11503 #if defined(DO_PPC_STATISTICS)
11504 handler->count++;
11505 #endif
11506 /* Check trace mode exceptions */
11507 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11508 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11509 ctx.exception != POWERPC_SYSCALL &&
11510 ctx.exception != POWERPC_EXCP_TRAP &&
11511 ctx.exception != POWERPC_EXCP_BRANCH)) {
11512 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11513 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11514 (cs->singlestep_enabled) ||
11515 singlestep ||
11516 num_insns >= max_insns)) {
11517 /* if we reach a page boundary or are single stepping, stop
11518 * generation
11519 */
11520 break;
11521 }
11522 if (tcg_check_temp_count()) {
11523 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11524 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11525 ctx.opcode);
11526 exit(1);
11527 }
11528 }
11529 if (tb->cflags & CF_LAST_IO)
11530 gen_io_end();
11531 if (ctx.exception == POWERPC_EXCP_NONE) {
11532 gen_goto_tb(&ctx, 0, ctx.nip);
11533 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11534 if (unlikely(cs->singlestep_enabled)) {
11535 gen_debug_exception(ctxp);
11536 }
11537 /* Generate the return instruction */
11538 tcg_gen_exit_tb(0);
11539 }
11540 gen_tb_end(tb, num_insns);
11541 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11542 if (unlikely(search_pc)) {
11543 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11544 lj++;
11545 while (lj <= j)
11546 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11547 } else {
11548 tb->size = ctx.nip - pc_start;
11549 tb->icount = num_insns;
11550 }
11551 #if defined(DEBUG_DISAS)
11552 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11553 int flags;
11554 flags = env->bfd_mach;
11555 flags |= ctx.le_mode << 16;
11556 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11557 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11558 qemu_log("\n");
11559 }
11560 #endif
11561 }
11562
11563 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11564 {
11565 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11566 }
11567
11568 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11569 {
11570 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11571 }
11572
11573 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11574 {
11575 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11576 }
AR7 emulation for QEMU