hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "hw/cpu/core.h"
  11 #include "hw/ppc/spapr_cpu_core.h"
  12 #include "target/ppc/cpu.h"
  13 #include "hw/ppc/spapr.h"
  14 #include "hw/boards.h"
  15 #include "qapi/error.h"
  16 #include "sysemu/cpus.h"
  17 #include "sysemu/kvm.h"
  18 #include "target/ppc/kvm_ppc.h"
  19 #include "hw/ppc/ppc.h"
  20 #include "target/ppc/mmu-hash64.h"
  21 #include "sysemu/numa.h"
  22 #include "sysemu/hw_accel.h"
  23 #include "qemu/error-report.h"
  24
  25 static void spapr_cpu_reset(void *opaque)
  26 {
  27     PowerPCCPU *cpu = opaque;
  28     CPUState *cs = CPU(cpu);
  29     CPUPPCState *env = &cpu->env;
  30     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  31     target_ulong lpcr;
  32
  33     cpu_reset(cs);
  34
  35     /* Set compatibility mode to match the boot CPU, which was either set
  36      * by the machine reset code or by CAS. This should never fail.
  37      */
  38     ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
  39
  40     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  41      * reset code and the rest are explicitly started up by the guest
  42      * using an RTAS call */
  43     cs->halted = 1;
  44
  45     env->spr[SPR_HIOR] = 0;
  46
  47     lpcr = env->spr[SPR_LPCR];
  48
  49     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  50      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  51      * the settings below ensure proper operations with TCG in absence of
  52      * a real hypervisor.
  53      *
  54      * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
  55      * real mode accesses, which thankfully defaults to 0 and isn't
  56      * accessible in guest mode.
  57      *
  58      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  59      * we don't get spurious wakups before an RTAS start-cpu call.
  60      */
  61     lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  62     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  63
  64     /* Set RMLS to the max (ie, 16G) */
  65     lpcr &= ~LPCR_RMLS;
  66     lpcr |= 1ull << LPCR_RMLS_SHIFT;
  67
  68     ppc_store_lpcr(cpu, lpcr);
  69
  70     /* Set a full AMOR so guest can use the AMR as it sees fit */
  71     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  72 }
  73
  74 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
  75 {
  76     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  77     CPUPPCState *env = &cpu->env;
  78
  79     env->nip = nip;
  80     env->gpr[3] = r3;
  81     CPU(cpu)->halted = 0;
  82     /* Enable Power-saving mode Exit Cause exceptions */
  83     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
  84 }
  85
  86 static void spapr_cpu_destroy(PowerPCCPU *cpu)
  87 {
  88     qemu_unregister_reset(spapr_cpu_reset, cpu);
  89 }
  90
  91 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
  92                            Error **errp)
  93 {
  94     CPUPPCState *env = &cpu->env;
  95
  96     /* Set time-base frequency to 512 MHz */
  97     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
  98
  99     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 100     kvmppc_set_papr(cpu);
 101
 102     qemu_register_reset(spapr_cpu_reset, cpu);
 103     spapr_cpu_reset(cpu);
 104 }
 105
 106 /*
 107  * Return the sPAPR CPU core type for @model which essentially is the CPU
 108  * model specified with -cpu cmdline option.
 109  */
 110 const char *spapr_get_cpu_core_type(const char *cpu_type)
 111 {
 112     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 113     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 114                                       len, cpu_type);
 115     ObjectClass *oc = object_class_by_name(core_type);
 116
 117     g_free(core_type);
 118     if (!oc) {
 119         return NULL;
 120     }
 121
 122     return object_class_get_name(oc);
 123 }
 124
 125 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
 126 {
 127     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 128     CPUCore *cc = CPU_CORE(dev);
 129     int i;
 130
 131     for (i = 0; i < cc->nr_threads; i++) {
 132         Object *obj = OBJECT(sc->threads[i]);
 133         DeviceState *dev = DEVICE(obj);
 134         CPUState *cs = CPU(dev);
 135         PowerPCCPU *cpu = POWERPC_CPU(cs);
 136
 137         spapr_cpu_destroy(cpu);
 138         object_unparent(cpu->intc);
 139         cpu_remove_sync(cs);
 140         object_unparent(obj);
 141     }
 142     g_free(sc->threads);
 143 }
 144
 145 static void spapr_cpu_core_realize_child(Object *child,
 146                                          sPAPRMachineState *spapr, Error **errp)
 147 {
 148     Error *local_err = NULL;
 149     CPUState *cs = CPU(child);
 150     PowerPCCPU *cpu = POWERPC_CPU(cs);
 151
 152     object_property_set_bool(child, true, "realized", &local_err);
 153     if (local_err) {
 154         goto error;
 155     }
 156
 157     spapr_cpu_init(spapr, cpu, &local_err);
 158     if (local_err) {
 159         goto error;
 160     }
 161
 162     cpu->intc = icp_create(child, spapr->icp_type, XICS_FABRIC(spapr),
 163                            &local_err);
 164     if (local_err) {
 165         goto error;
 166     }
 167
 168     return;
 169
 170 error:
 171     error_propagate(errp, local_err);
 172 }
 173
 174 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 175 {
 176     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 177      * tries to add a sPAPR CPU core to a non-pseries machine.
 178      */
 179     sPAPRMachineState *spapr =
 180         (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
 181                                                   TYPE_SPAPR_MACHINE);
 182     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 183     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
 184     CPUCore *cc = CPU_CORE(OBJECT(dev));
 185     Error *local_err = NULL;
 186     Object *obj;
 187     int i, j;
 188
 189     if (!spapr) {
 190         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 191         return;
 192     }
 193
 194     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 195     for (i = 0; i < cc->nr_threads; i++) {
 196         char id[32];
 197         CPUState *cs;
 198         PowerPCCPU *cpu;
 199
 200         obj = object_new(scc->cpu_type);
 201
 202         cs = CPU(obj);
 203         cpu = sc->threads[i] = POWERPC_CPU(obj);
 204         cs->cpu_index = cc->core_id + i;
 205         spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 206         if (local_err) {
 207             goto err;
 208         }
 209
 210
 211         /* Set NUMA node for the threads belonged to core  */
 212         cpu->node_id = sc->node_id;
 213
 214         snprintf(id, sizeof(id), "thread[%d]", i);
 215         object_property_add_child(OBJECT(sc), id, obj, &local_err);
 216         if (local_err) {
 217             goto err;
 218         }
 219         object_unref(obj);
 220     }
 221
 222     for (j = 0; j < cc->nr_threads; j++) {
 223         obj = OBJECT(sc->threads[j]);
 224
 225         spapr_cpu_core_realize_child(obj, spapr, &local_err);
 226         if (local_err) {
 227             goto err;
 228         }
 229     }
 230     return;
 231
 232 err:
 233     while (--i >= 0) {
 234         obj = OBJECT(sc->threads[i]);
 235         object_unparent(obj);
 236     }
 237     g_free(sc->threads);
 238     error_propagate(errp, local_err);
 239 }
 240
 241 static Property spapr_cpu_core_properties[] = {
 242     DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 243     DEFINE_PROP_END_OF_LIST()
 244 };
 245
 246 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 247 {
 248     DeviceClass *dc = DEVICE_CLASS(oc);
 249     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 250
 251     dc->realize = spapr_cpu_core_realize;
 252     dc->unrealize = spapr_cpu_core_unrealizefn;
 253     dc->props = spapr_cpu_core_properties;
 254     scc->cpu_type = data;
 255 }
 256
 257 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 258     {                                                   \
 259         .parent = TYPE_SPAPR_CPU_CORE,                  \
 260         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 261         .class_init = spapr_cpu_core_class_init,        \
 262         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 263     }
 264
 265 static const TypeInfo spapr_cpu_core_type_infos[] = {
 266     {
 267         .name = TYPE_SPAPR_CPU_CORE,
 268         .parent = TYPE_CPU_CORE,
 269         .abstract = true,
 270         .instance_size = sizeof(sPAPRCPUCore),
 271         .class_size = sizeof(sPAPRCPUCoreClass),
 272     },
 273     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 274     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 275     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 276     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 277     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 278     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 279     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 280     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 281     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 282     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 283     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 284 #ifdef CONFIG_KVM
 285     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 286 #endif
 287 };
 288
 289 DEFINE_TYPES(spapr_cpu_core_type_infos)