hw/hppa/dino.c

   1 /*
   2  * HP-PARISC Dino PCI chipset emulation.
   3  *
   4  * (C) 2017 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
  10  * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "cpu.h"
  16 #include "hw/hw.h"
  17 #include "hw/devices.h"
  18 #include "sysemu/sysemu.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/pci/pci_bus.h"
  21 #include "hppa_sys.h"
  22 #include "exec/address-spaces.h"
  23
  24
  25 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
  26
  27 #define DINO_IAR0               0x004
  28 #define DINO_IODC               0x008
  29 #define DINO_IRR0               0x00C  /* RO */
  30 #define DINO_IAR1               0x010
  31 #define DINO_IRR1               0x014  /* RO */
  32 #define DINO_IMR                0x018
  33 #define DINO_IPR                0x01C
  34 #define DINO_TOC_ADDR           0x020
  35 #define DINO_ICR                0x024
  36 #define DINO_ILR                0x028  /* RO */
  37 #define DINO_IO_COMMAND         0x030  /* WO */
  38 #define DINO_IO_STATUS          0x034  /* RO */
  39 #define DINO_IO_CONTROL         0x038
  40 #define DINO_IO_GSC_ERR_RESP    0x040  /* RO */
  41 #define DINO_IO_ERR_INFO        0x044  /* RO */
  42 #define DINO_IO_PCI_ERR_RESP    0x048  /* RO */
  43 #define DINO_IO_FBB_EN          0x05c
  44 #define DINO_IO_ADDR_EN         0x060
  45 #define DINO_PCI_CONFIG_ADDR    0x064
  46 #define DINO_PCI_CONFIG_DATA    0x068
  47 #define DINO_PCI_IO_DATA        0x06c
  48 #define DINO_PCI_MEM_DATA       0x070  /* Dino 3.x only */
  49 #define DINO_GSC2X_CONFIG       0x7b4  /* RO */
  50 #define DINO_GMASK              0x800
  51 #define DINO_PAMR               0x804
  52 #define DINO_PAPR               0x808
  53 #define DINO_DAMODE             0x80c
  54 #define DINO_PCICMD             0x810
  55 #define DINO_PCISTS             0x814  /* R/WC */
  56 #define DINO_MLTIM              0x81c
  57 #define DINO_BRDG_FEAT          0x820
  58 #define DINO_PCIROR             0x824
  59 #define DINO_PCIWOR             0x828
  60 #define DINO_TLTIM              0x830
  61
  62 #define DINO_IRQS         11      /* bits 0-10 are architected */
  63 #define DINO_IRR_MASK     0x5ff   /* only 10 bits are implemented */
  64 #define DINO_LOCAL_IRQS   (DINO_IRQS + 1)
  65 #define DINO_MASK_IRQ(x)  (1 << (x))
  66
  67 #define PCIINTA   0x001
  68 #define PCIINTB   0x002
  69 #define PCIINTC   0x004
  70 #define PCIINTD   0x008
  71 #define PCIINTE   0x010
  72 #define PCIINTF   0x020
  73 #define GSCEXTINT 0x040
  74 /* #define xxx       0x080 - bit 7 is "default" */
  75 /* #define xxx    0x100 - bit 8 not used */
  76 /* #define xxx    0x200 - bit 9 not used */
  77 #define RS232INT  0x400
  78
  79 #define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */
  80
  81 #define DINO_PCI_HOST_BRIDGE(obj) \
  82     OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
  83
  84 typedef struct DinoState {
  85     PCIHostState parent_obj;
  86
  87     /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
  88        so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops.  */
  89
  90     uint32_t iar0;
  91     uint32_t iar1;
  92     uint32_t imr;
  93     uint32_t ipr;
  94     uint32_t icr;
  95     uint32_t ilr;
  96     uint32_t io_addr_en;
  97     uint32_t io_control;
  98
  99     MemoryRegion this_mem;
 100     MemoryRegion pci_mem;
 101     MemoryRegion pci_mem_alias[32];
 102
 103     AddressSpace bm_as;
 104     MemoryRegion bm;
 105     MemoryRegion bm_ram_alias;
 106     MemoryRegion bm_pci_alias;
 107
 108     MemoryRegion cpu0_eir_mem;
 109 } DinoState;
 110
 111 /*
 112  * Dino can forward memory accesses from the CPU in the range between
 113  * 0xf0800000 and 0xff000000 to the PCI bus.
 114  */
 115 static void gsc_to_pci_forwarding(DinoState *s)
 116 {
 117     uint32_t io_addr_en, tmp;
 118     int enabled, i;
 119
 120     tmp = extract32(s->io_control, 7, 2);
 121     enabled = (tmp == 0x01);
 122     io_addr_en = s->io_addr_en;
 123
 124     memory_region_transaction_begin();
 125     for (i = 1; i < 31; i++) {
 126         MemoryRegion *mem = &s->pci_mem_alias[i];
 127         if (enabled && (io_addr_en & (1U << i))) {
 128             if (!memory_region_is_mapped(mem)) {
 129                 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 130                 memory_region_add_subregion(get_system_memory(), addr, mem);
 131             }
 132         } else if (memory_region_is_mapped(mem)) {
 133             memory_region_del_subregion(get_system_memory(), mem);
 134         }
 135     }
 136     memory_region_transaction_commit();
 137 }
 138
 139 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
 140                                 unsigned size, bool is_write)
 141 {
 142     switch (addr) {
 143     case DINO_IAR0:
 144     case DINO_IAR1:
 145     case DINO_IRR0:
 146     case DINO_IRR1:
 147     case DINO_IMR:
 148     case DINO_IPR:
 149     case DINO_ICR:
 150     case DINO_ILR:
 151     case DINO_IO_CONTROL:
 152     case DINO_IO_ADDR_EN:
 153     case DINO_PCI_IO_DATA:
 154         return true;
 155     case DINO_PCI_IO_DATA + 2:
 156         return size <= 2;
 157     case DINO_PCI_IO_DATA + 1:
 158     case DINO_PCI_IO_DATA + 3:
 159         return size == 1;
 160     }
 161     return false;
 162 }
 163
 164 static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
 165                                              uint64_t *data, unsigned size,
 166                                              MemTxAttrs attrs)
 167 {
 168     DinoState *s = opaque;
 169     MemTxResult ret = MEMTX_OK;
 170     AddressSpace *io;
 171     uint16_t ioaddr;
 172     uint32_t val;
 173
 174     switch (addr) {
 175     case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
 176         /* Read from PCI IO space. */
 177         io = &address_space_io;
 178         ioaddr = s->parent_obj.config_reg;
 179         switch (size) {
 180         case 1:
 181             val = address_space_ldub(io, ioaddr, attrs, &ret);
 182             break;
 183         case 2:
 184             val = address_space_lduw_be(io, ioaddr, attrs, &ret);
 185             break;
 186         case 4:
 187             val = address_space_ldl_be(io, ioaddr, attrs, &ret);
 188             break;
 189         default:
 190             g_assert_not_reached();
 191         }
 192         break;
 193
 194     case DINO_IO_ADDR_EN:
 195         val = s->io_addr_en;
 196         break;
 197     case DINO_IO_CONTROL:
 198         val = s->io_control;
 199         break;
 200
 201     case DINO_IAR0:
 202         val = s->iar0;
 203         break;
 204     case DINO_IAR1:
 205         val = s->iar1;
 206         break;
 207     case DINO_IMR:
 208         val = s->imr;
 209         break;
 210     case DINO_ICR:
 211         val = s->icr;
 212         break;
 213     case DINO_IPR:
 214         val = s->ipr;
 215         /* Any read to IPR clears the register.  */
 216         s->ipr = 0;
 217         break;
 218     case DINO_ILR:
 219         val = s->ilr;
 220         break;
 221     case DINO_IRR0:
 222         val = s->ilr & s->imr & ~s->icr;
 223         break;
 224     case DINO_IRR1:
 225         val = s->ilr & s->imr & s->icr;
 226         break;
 227
 228     default:
 229         /* Controlled by dino_chip_mem_valid above.  */
 230         g_assert_not_reached();
 231     }
 232
 233     *data = val;
 234     return ret;
 235 }
 236
 237 static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
 238                                               uint64_t val, unsigned size,
 239                                               MemTxAttrs attrs)
 240 {
 241     DinoState *s = opaque;
 242     AddressSpace *io;
 243     MemTxResult ret;
 244     uint16_t ioaddr;
 245
 246     switch (addr) {
 247     case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
 248         /* Write into PCI IO space.  */
 249         io = &address_space_io;
 250         ioaddr = s->parent_obj.config_reg;
 251         switch (size) {
 252         case 1:
 253             address_space_stb(io, ioaddr, val, attrs, &ret);
 254             break;
 255         case 2:
 256             address_space_stw_be(io, ioaddr, val, attrs, &ret);
 257             break;
 258         case 4:
 259             address_space_stl_be(io, ioaddr, val, attrs, &ret);
 260             break;
 261         default:
 262             g_assert_not_reached();
 263         }
 264         return ret;
 265
 266     case DINO_IO_ADDR_EN:
 267         /* Never allow first (=firmware) and last (=Dino) areas.  */
 268         s->io_addr_en = val & 0x7ffffffe;
 269         gsc_to_pci_forwarding(s);
 270         break;
 271     case DINO_IO_CONTROL:
 272         s->io_control = val;
 273         gsc_to_pci_forwarding(s);
 274         break;
 275
 276     case DINO_IAR0:
 277         s->iar0 = val;
 278         break;
 279     case DINO_IAR1:
 280         s->iar1 = val;
 281         break;
 282     case DINO_IMR:
 283         s->imr = val;
 284         break;
 285     case DINO_ICR:
 286         s->icr = val;
 287         break;
 288     case DINO_IPR:
 289         /* Any write to IPR clears the register.  */
 290         s->ipr = 0;
 291         break;
 292
 293     case DINO_ILR:
 294     case DINO_IRR0:
 295     case DINO_IRR1:
 296         /* These registers are read-only.  */
 297         break;
 298
 299     default:
 300         /* Controlled by dino_chip_mem_valid above.  */
 301         g_assert_not_reached();
 302     }
 303     return MEMTX_OK;
 304 }
 305
 306 static const MemoryRegionOps dino_chip_ops = {
 307     .read_with_attrs = dino_chip_read_with_attrs,
 308     .write_with_attrs = dino_chip_write_with_attrs,
 309     .endianness = DEVICE_BIG_ENDIAN,
 310     .valid = {
 311         .min_access_size = 1,
 312         .max_access_size = 4,
 313         .accepts = dino_chip_mem_valid,
 314     },
 315     .impl = {
 316         .min_access_size = 1,
 317         .max_access_size = 4,
 318     },
 319 };
 320
 321 static const VMStateDescription vmstate_dino = {
 322     .name = "Dino",
 323     .version_id = 1,
 324     .minimum_version_id = 1,
 325     .fields = (VMStateField[]) {
 326         VMSTATE_UINT32(iar0, DinoState),
 327         VMSTATE_UINT32(iar1, DinoState),
 328         VMSTATE_UINT32(imr, DinoState),
 329         VMSTATE_UINT32(ipr, DinoState),
 330         VMSTATE_UINT32(icr, DinoState),
 331         VMSTATE_UINT32(ilr, DinoState),
 332         VMSTATE_UINT32(io_addr_en, DinoState),
 333         VMSTATE_UINT32(io_control, DinoState),
 334         VMSTATE_END_OF_LIST()
 335     }
 336 };
 337
 338
 339 /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
 340
 341 static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
 342 {
 343     PCIHostState *s = opaque;
 344     return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 345 }
 346
 347 static void dino_config_data_write(void *opaque, hwaddr addr,
 348                                    uint64_t val, unsigned len)
 349 {
 350     PCIHostState *s = opaque;
 351     pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 352 }
 353
 354 static const MemoryRegionOps dino_config_data_ops = {
 355     .read = dino_config_data_read,
 356     .write = dino_config_data_write,
 357     .endianness = DEVICE_LITTLE_ENDIAN,
 358 };
 359
 360 static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
 361                                             int devfn)
 362 {
 363     DinoState *s = opaque;
 364
 365     return &s->bm_as;
 366 }
 367
 368 /*
 369  * Dino interrupts are connected as shown on Page 78, Table 23
 370  * (Little-endian bit numbers)
 371  *    0   PCI INTA
 372  *    1   PCI INTB
 373  *    2   PCI INTC
 374  *    3   PCI INTD
 375  *    4   PCI INTE
 376  *    5   PCI INTF
 377  *    6   GSC External Interrupt
 378  *    7   Bus Error for "less than fatal" mode
 379  *    8   PS2
 380  *    9   Unused
 381  *    10  RS232
 382  */
 383
 384 static void dino_set_irq(void *opaque, int irq, int level)
 385 {
 386     DinoState *s = opaque;
 387     uint32_t bit = 1u << irq;
 388     uint32_t old_ilr = s->ilr;
 389
 390     if (level) {
 391         uint32_t ena = bit & ~old_ilr;
 392         s->ipr |= ena;
 393         s->ilr = old_ilr | bit;
 394         if (ena & s->imr) {
 395             uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
 396             stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 397         }
 398     } else {
 399         s->ilr = old_ilr & ~bit;
 400     }
 401 }
 402
 403 static int dino_pci_map_irq(PCIDevice *d, int irq_num)
 404 {
 405     int slot = d->devfn >> 3;
 406     int local_irq;
 407
 408     assert(irq_num >= 0 && irq_num <= 3);
 409
 410     local_irq = slot & 0x03;
 411
 412     return local_irq;
 413 }
 414
 415 static void dino_set_timer_irq(void *opaque, int irq, int level)
 416 {
 417     /* ??? Not connected.  */
 418 }
 419
 420 static void dino_set_serial_irq(void *opaque, int irq, int level)
 421 {
 422     dino_set_irq(opaque, 10, level);
 423 }
 424
 425 PCIBus *dino_init(MemoryRegion *addr_space,
 426                   qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
 427 {
 428     DeviceState *dev;
 429     DinoState *s;
 430     PCIBus *b;
 431     int i;
 432
 433     dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
 434     s = DINO_PCI_HOST_BRIDGE(dev);
 435
 436     /* Dino PCI access from main memory.  */
 437     memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
 438                           s, "dino", 4096);
 439     memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
 440
 441     /* Dino PCI config. */
 442     memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
 443                           &pci_host_conf_be_ops, dev, "pci-conf-idx", 4);
 444     memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
 445                           &dino_config_data_ops, dev, "pci-conf-data", 4);
 446     memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
 447                                 &s->parent_obj.conf_mem);
 448     memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
 449                                 &s->parent_obj.data_mem);
 450
 451     /* Dino PCI bus memory.  */
 452     memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);
 453
 454     b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
 455                               &s->pci_mem, get_system_io(),
 456                               PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
 457     s->parent_obj.bus = b;
 458     qdev_init_nofail(dev);
 459
 460     /* Set up windows into PCI bus memory.  */
 461     for (i = 1; i < 31; i++) {
 462         uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 463         char *name = g_strdup_printf("PCI Outbound Window %d", i);
 464         memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
 465                                  name, &s->pci_mem, addr,
 466                                  DINO_MEM_CHUNK_SIZE);
 467     }
 468
 469     /* Set up PCI view of memory: Bus master address space.  */
 470     memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
 471     memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
 472                              "bm-system", addr_space, 0,
 473                              0xf0000000 + DINO_MEM_CHUNK_SIZE);
 474     memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
 475                              "bm-pci", &s->pci_mem,
 476                              0xf0000000 + DINO_MEM_CHUNK_SIZE,
 477                              31 * DINO_MEM_CHUNK_SIZE);
 478     memory_region_add_subregion(&s->bm, 0,
 479                                 &s->bm_ram_alias);
 480     memory_region_add_subregion(&s->bm,
 481                                 0xf0000000 + DINO_MEM_CHUNK_SIZE,
 482                                 &s->bm_pci_alias);
 483     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 484     pci_setup_iommu(b, dino_pcihost_set_iommu, s);
 485
 486     *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
 487     *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
 488
 489     return b;
 490 }
 491
 492 static int dino_pcihost_init(SysBusDevice *dev)
 493 {
 494     return 0;
 495 }
 496
 497 static void dino_pcihost_class_init(ObjectClass *klass, void *data)
 498 {
 499     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 500     DeviceClass *dc = DEVICE_CLASS(klass);
 501
 502     k->init = dino_pcihost_init;
 503     dc->vmsd = &vmstate_dino;
 504 }
 505
 506 static const TypeInfo dino_pcihost_info = {
 507     .name          = TYPE_DINO_PCI_HOST_BRIDGE,
 508     .parent        = TYPE_PCI_HOST_BRIDGE,
 509     .instance_size = sizeof(DinoState),
 510     .class_init    = dino_pcihost_class_init,
 511 };
 512
 513 static void dino_register_types(void)
 514 {
 515     type_register_static(&dino_pcihost_info);
 516 }
 517
 518 type_init(dino_register_types)