hw/display/vga_regs.h

   1 /*
   2  * linux/include/video/vga.h -- standard VGA chipset interaction
   3  *
   4  * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
   5  *
   6  * Copyright history from vga16fb.c:
   7  *      Copyright 1999 Ben Pfaff and Petr Vandrovec
   8  *      Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
   9  *      Based on VESA framebuffer (c) 1998 Gerd Knorr
  10  *
  11  * This file is subject to the terms and conditions of the GNU General
  12  * Public License.  See the file COPYING in the main directory of this
  13  * archive for more details.
  14  *
  15  */
  16
  17 #ifndef HW_VGA_REGS_H
  18 #define HW_VGA_REGS_H
  19
  20 /* Some of the code below is taken from SVGAlib.  The original,
  21    unmodified copyright notice for that code is below. */
  22 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen                    */
  23 /*                                                                 */
  24 /* This library is free software; you can redistribute it and/or   */
  25 /* modify it without any restrictions. This library is distributed */
  26 /* in the hope that it will be useful, but without any warranty.   */
  27
  28 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
  29 /* partially copyrighted (C) 1993 by Hartmut Schirmer */
  30
  31 /* VGA data register ports */
  32 #define VGA_CRT_DC      0x3D5   /* CRT Controller Data Register - color emulation */
  33 #define VGA_CRT_DM      0x3B5   /* CRT Controller Data Register - mono emulation */
  34 #define VGA_ATT_R       0x3C1   /* Attribute Controller Data Read Register */
  35 #define VGA_ATT_W       0x3C0   /* Attribute Controller Data Write Register */
  36 #define VGA_GFX_D       0x3CF   /* Graphics Controller Data Register */
  37 #define VGA_SEQ_D       0x3C5   /* Sequencer Data Register */
  38 #define VGA_MIS_R       0x3CC   /* Misc Output Read Register */
  39 #define VGA_MIS_W       0x3C2   /* Misc Output Write Register */
  40 #define VGA_FTC_R       0x3CA   /* Feature Control Read Register */
  41 #define VGA_IS1_RC      0x3DA   /* Input Status Register 1 - color emulation */
  42 #define VGA_IS1_RM      0x3BA   /* Input Status Register 1 - mono emulation */
  43 #define VGA_PEL_D       0x3C9   /* PEL Data Register */
  44 #define VGA_PEL_MSK     0x3C6   /* PEL mask register */
  45
  46 /* EGA-specific registers */
  47 #define EGA_GFX_E0      0x3CC   /* Graphics enable processor 0 */
  48 #define EGA_GFX_E1      0x3CA   /* Graphics enable processor 1 */
  49
  50 /* VGA index register ports */
  51 #define VGA_CRT_IC      0x3D4   /* CRT Controller Index - color emulation */
  52 #define VGA_CRT_IM      0x3B4   /* CRT Controller Index - mono emulation */
  53 #define VGA_ATT_IW      0x3C0   /* Attribute Controller Index & Data Write Register */
  54 #define VGA_GFX_I       0x3CE   /* Graphics Controller Index */
  55 #define VGA_SEQ_I       0x3C4   /* Sequencer Index */
  56 #define VGA_PEL_IW      0x3C8   /* PEL Write Index */
  57 #define VGA_PEL_IR      0x3C7   /* PEL Read Index */
  58
  59 /* standard VGA indexes max counts */
  60 #define VGA_CRT_C       0x19    /* Number of CRT Controller Registers */
  61 #define VGA_ATT_C       0x15    /* Number of Attribute Controller Registers */
  62 #define VGA_GFX_C       0x09    /* Number of Graphics Controller Registers */
  63 #define VGA_SEQ_C       0x05    /* Number of Sequencer Registers */
  64 #define VGA_MIS_C       0x01    /* Number of Misc Output Register */
  65
  66 /* VGA misc register bit masks */
  67 #define VGA_MIS_COLOR           0x01
  68 #define VGA_MIS_ENB_MEM_ACCESS  0x02
  69 #define VGA_MIS_DCLK_28322_720  0x04
  70 #define VGA_MIS_ENB_PLL_LOAD    (0x04 | 0x08)
  71 #define VGA_MIS_SEL_HIGH_PAGE   0x20
  72
  73 /* VGA CRT controller register indices */
  74 #define VGA_CRTC_H_TOTAL        0
  75 #define VGA_CRTC_H_DISP         1
  76 #define VGA_CRTC_H_BLANK_START  2
  77 #define VGA_CRTC_H_BLANK_END    3
  78 #define VGA_CRTC_H_SYNC_START   4
  79 #define VGA_CRTC_H_SYNC_END     5
  80 #define VGA_CRTC_V_TOTAL        6
  81 #define VGA_CRTC_OVERFLOW       7
  82 #define VGA_CRTC_PRESET_ROW     8
  83 #define VGA_CRTC_MAX_SCAN       9
  84 #define VGA_CRTC_CURSOR_START   0x0A
  85 #define VGA_CRTC_CURSOR_END     0x0B
  86 #define VGA_CRTC_START_HI       0x0C
  87 #define VGA_CRTC_START_LO       0x0D
  88 #define VGA_CRTC_CURSOR_HI      0x0E
  89 #define VGA_CRTC_CURSOR_LO      0x0F
  90 #define VGA_CRTC_V_SYNC_START   0x10
  91 #define VGA_CRTC_V_SYNC_END     0x11
  92 #define VGA_CRTC_V_DISP_END     0x12
  93 #define VGA_CRTC_OFFSET         0x13
  94 #define VGA_CRTC_UNDERLINE      0x14
  95 #define VGA_CRTC_V_BLANK_START  0x15
  96 #define VGA_CRTC_V_BLANK_END    0x16
  97 #define VGA_CRTC_MODE           0x17
  98 #define VGA_CRTC_LINE_COMPARE   0x18
  99 #define VGA_CRTC_REGS           VGA_CRT_C
 100
 101 /* VGA CRT controller bit masks */
 102 #define VGA_CR11_LOCK_CR0_CR7   0x80 /* lock writes to CR0 - CR7 */
 103 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
 104
 105 /* VGA attribute controller register indices */
 106 #define VGA_ATC_PALETTE0        0x00
 107 #define VGA_ATC_PALETTE1        0x01
 108 #define VGA_ATC_PALETTE2        0x02
 109 #define VGA_ATC_PALETTE3        0x03
 110 #define VGA_ATC_PALETTE4        0x04
 111 #define VGA_ATC_PALETTE5        0x05
 112 #define VGA_ATC_PALETTE6        0x06
 113 #define VGA_ATC_PALETTE7        0x07
 114 #define VGA_ATC_PALETTE8        0x08
 115 #define VGA_ATC_PALETTE9        0x09
 116 #define VGA_ATC_PALETTEA        0x0A
 117 #define VGA_ATC_PALETTEB        0x0B
 118 #define VGA_ATC_PALETTEC        0x0C
 119 #define VGA_ATC_PALETTED        0x0D
 120 #define VGA_ATC_PALETTEE        0x0E
 121 #define VGA_ATC_PALETTEF        0x0F
 122 #define VGA_ATC_MODE            0x10
 123 #define VGA_ATC_OVERSCAN        0x11
 124 #define VGA_ATC_PLANE_ENABLE    0x12
 125 #define VGA_ATC_PEL             0x13
 126 #define VGA_ATC_COLOR_PAGE      0x14
 127
 128 #define VGA_AR_ENABLE_DISPLAY   0x20
 129
 130 /* VGA sequencer register indices */
 131 #define VGA_SEQ_RESET           0x00
 132 #define VGA_SEQ_CLOCK_MODE      0x01
 133 #define VGA_SEQ_PLANE_WRITE     0x02
 134 #define VGA_SEQ_CHARACTER_MAP   0x03
 135 #define VGA_SEQ_MEMORY_MODE     0x04
 136
 137 /* VGA sequencer register bit masks */
 138 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
 139 #define VGA_SR01_SCREEN_OFF     0x20 /* bit 5: Screen is off */
 140 #define VGA_SR02_ALL_PLANES     0x0F /* bits 3-0: enable access to all planes */
 141 #define VGA_SR04_EXT_MEM        0x02 /* bit 1: allows complete mem access to 256K */
 142 #define VGA_SR04_SEQ_MODE       0x04 /* bit 2: directs system to use a sequential addressing mode */
 143 #define VGA_SR04_CHN_4M         0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
 144
 145 /* VGA graphics controller register indices */
 146 #define VGA_GFX_SR_VALUE        0x00
 147 #define VGA_GFX_SR_ENABLE       0x01
 148 #define VGA_GFX_COMPARE_VALUE   0x02
 149 #define VGA_GFX_DATA_ROTATE     0x03
 150 #define VGA_GFX_PLANE_READ      0x04
 151 #define VGA_GFX_MODE            0x05
 152 #define VGA_GFX_MISC            0x06
 153 #define VGA_GFX_COMPARE_MASK    0x07
 154 #define VGA_GFX_BIT_MASK        0x08
 155
 156 /* VGA graphics controller bit masks */
 157 #define VGA_GR06_GRAPHICS_MODE  0x01
 158
 159 #endif /* HW_VGA_REGS_H */