hw/scsi/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "hw/irq.h"
  30 #include "hw/scsi/esp.h"
  31 #include "trace.h"
  32 #include "qemu/log.h"
  33 #include "qemu/module.h"
  34
  35 /*
  36  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  37  * also produced as NCR89C100. See
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  39  * and
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  41  *
  42  * On Macintosh Quadra it is a NCR53C96.
  43  */
  44
  45 static void esp_raise_irq(ESPState *s)
  46 {
  47     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  48         s->rregs[ESP_RSTAT] |= STAT_INT;
  49         qemu_irq_raise(s->irq);
  50         trace_esp_raise_irq();
  51     }
  52 }
  53
  54 static void esp_lower_irq(ESPState *s)
  55 {
  56     if (s->rregs[ESP_RSTAT] & STAT_INT) {
  57         s->rregs[ESP_RSTAT] &= ~STAT_INT;
  58         qemu_irq_lower(s->irq);
  59         trace_esp_lower_irq();
  60     }
  61 }
  62
  63 static void esp_raise_drq(ESPState *s)
  64 {
  65     qemu_irq_raise(s->irq_data);
  66     trace_esp_raise_drq();
  67 }
  68
  69 static void esp_lower_drq(ESPState *s)
  70 {
  71     qemu_irq_lower(s->irq_data);
  72     trace_esp_lower_drq();
  73 }
  74
  75 void esp_dma_enable(ESPState *s, int irq, int level)
  76 {
  77     if (level) {
  78         s->dma_enabled = 1;
  79         trace_esp_dma_enable();
  80         if (s->dma_cb) {
  81             s->dma_cb(s);
  82             s->dma_cb = NULL;
  83         }
  84     } else {
  85         trace_esp_dma_disable();
  86         s->dma_enabled = 0;
  87     }
  88 }
  89
  90 void esp_request_cancelled(SCSIRequest *req)
  91 {
  92     ESPState *s = req->hba_private;
  93
  94     if (req == s->current_req) {
  95         scsi_req_unref(s->current_req);
  96         s->current_req = NULL;
  97         s->current_dev = NULL;
  98         s->async_len = 0;
  99     }
 100 }
 101
 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val)
 103 {
 104     if (fifo8_num_used(fifo) == fifo->capacity) {
 105         trace_esp_error_fifo_overrun();
 106         return;
 107     }
 108
 109     fifo8_push(fifo, val);
 110 }
 111
 112 static uint8_t esp_fifo_pop(Fifo8 *fifo)
 113 {
 114     if (fifo8_is_empty(fifo)) {
 115         return 0;
 116     }
 117
 118     return fifo8_pop(fifo);
 119 }
 120
 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen)
 122 {
 123     const uint8_t *buf;
 124     uint32_t n;
 125
 126     if (maxlen == 0) {
 127         return 0;
 128     }
 129
 130     buf = fifo8_pop_buf(fifo, maxlen, &n);
 131     if (dest) {
 132         memcpy(dest, buf, n);
 133     }
 134
 135     return n;
 136 }
 137
 138 static uint32_t esp_get_tc(ESPState *s)
 139 {
 140     uint32_t dmalen;
 141
 142     dmalen = s->rregs[ESP_TCLO];
 143     dmalen |= s->rregs[ESP_TCMID] << 8;
 144     dmalen |= s->rregs[ESP_TCHI] << 16;
 145
 146     return dmalen;
 147 }
 148
 149 static void esp_set_tc(ESPState *s, uint32_t dmalen)
 150 {
 151     s->rregs[ESP_TCLO] = dmalen;
 152     s->rregs[ESP_TCMID] = dmalen >> 8;
 153     s->rregs[ESP_TCHI] = dmalen >> 16;
 154 }
 155
 156 static uint32_t esp_get_stc(ESPState *s)
 157 {
 158     uint32_t dmalen;
 159
 160     dmalen = s->wregs[ESP_TCLO];
 161     dmalen |= s->wregs[ESP_TCMID] << 8;
 162     dmalen |= s->wregs[ESP_TCHI] << 16;
 163
 164     return dmalen;
 165 }
 166
 167 static uint8_t esp_pdma_read(ESPState *s)
 168 {
 169     uint8_t val;
 170
 171     if (s->do_cmd) {
 172         val = esp_fifo_pop(&s->cmdfifo);
 173     } else {
 174         val = esp_fifo_pop(&s->fifo);
 175     }
 176
 177     return val;
 178 }
 179
 180 static void esp_pdma_write(ESPState *s, uint8_t val)
 181 {
 182     uint32_t dmalen = esp_get_tc(s);
 183
 184     if (dmalen == 0) {
 185         return;
 186     }
 187
 188     if (s->do_cmd) {
 189         esp_fifo_push(&s->cmdfifo, val);
 190     } else {
 191         esp_fifo_push(&s->fifo, val);
 192     }
 193
 194     dmalen--;
 195     esp_set_tc(s, dmalen);
 196 }
 197
 198 static int esp_select(ESPState *s)
 199 {
 200     int target;
 201
 202     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 203
 204     s->ti_size = 0;
 205     fifo8_reset(&s->fifo);
 206
 207     if (s->current_req) {
 208         /* Started a new command before the old one finished.  Cancel it.  */
 209         scsi_req_cancel(s->current_req);
 210     }
 211
 212     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 213     if (!s->current_dev) {
 214         /* No such drive */
 215         s->rregs[ESP_RSTAT] = 0;
 216         s->rregs[ESP_RINTR] |= INTR_DC;
 217         s->rregs[ESP_RSEQ] = SEQ_0;
 218         esp_raise_irq(s);
 219         return -1;
 220     }
 221
 222     /*
 223      * Note that we deliberately don't raise the IRQ here: this will be done
 224      * either in do_busid_cmd() for DATA OUT transfers or by the deferred
 225      * IRQ mechanism in esp_transfer_data() for DATA IN transfers
 226      */
 227     s->rregs[ESP_RINTR] |= INTR_FC;
 228     s->rregs[ESP_RSEQ] = SEQ_CD;
 229     return 0;
 230 }
 231
 232 static uint32_t get_cmd(ESPState *s, uint32_t maxlen)
 233 {
 234     uint8_t buf[ESP_CMDFIFO_SZ];
 235     uint32_t dmalen, n;
 236     int target;
 237
 238     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 239     if (s->dma) {
 240         dmalen = MIN(esp_get_tc(s), maxlen);
 241         if (dmalen == 0) {
 242             return 0;
 243         }
 244         if (s->dma_memory_read) {
 245             s->dma_memory_read(s->dma_opaque, buf, dmalen);
 246             dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen);
 247             fifo8_push_all(&s->cmdfifo, buf, dmalen);
 248         } else {
 249             if (esp_select(s) < 0) {
 250                 fifo8_reset(&s->cmdfifo);
 251                 return -1;
 252             }
 253             esp_raise_drq(s);
 254             fifo8_reset(&s->cmdfifo);
 255             return 0;
 256         }
 257     } else {
 258         dmalen = MIN(fifo8_num_used(&s->fifo), maxlen);
 259         if (dmalen == 0) {
 260             return 0;
 261         }
 262         n = esp_fifo_pop_buf(&s->fifo, buf, dmalen);
 263         if (n >= 3) {
 264             buf[0] = buf[2] >> 5;
 265         }
 266         n = MIN(fifo8_num_free(&s->cmdfifo), n);
 267         fifo8_push_all(&s->cmdfifo, buf, n);
 268     }
 269     trace_esp_get_cmd(dmalen, target);
 270
 271     if (esp_select(s) < 0) {
 272         fifo8_reset(&s->cmdfifo);
 273         return -1;
 274     }
 275     return dmalen;
 276 }
 277
 278 static void do_busid_cmd(ESPState *s, uint8_t busid)
 279 {
 280     uint32_t cmdlen;
 281     int32_t datalen;
 282     int lun;
 283     SCSIDevice *current_lun;
 284     uint8_t buf[ESP_CMDFIFO_SZ];
 285
 286     trace_esp_do_busid_cmd(busid);
 287     lun = busid & 7;
 288     cmdlen = fifo8_num_used(&s->cmdfifo);
 289     if (!cmdlen || !s->current_dev) {
 290         return;
 291     }
 292     esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen);
 293
 294     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 295     s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
 296     datalen = scsi_req_enqueue(s->current_req);
 297     s->ti_size = datalen;
 298     fifo8_reset(&s->cmdfifo);
 299     if (datalen != 0) {
 300         s->rregs[ESP_RSTAT] = STAT_TC;
 301         s->rregs[ESP_RSEQ] = SEQ_CD;
 302         s->ti_cmd = 0;
 303         esp_set_tc(s, 0);
 304         if (datalen > 0) {
 305             /*
 306              * Switch to DATA IN phase but wait until initial data xfer is
 307              * complete before raising the command completion interrupt
 308              */
 309             s->data_in_ready = false;
 310             s->rregs[ESP_RSTAT] |= STAT_DI;
 311         } else {
 312             s->rregs[ESP_RSTAT] |= STAT_DO;
 313             s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 314             esp_raise_irq(s);
 315             esp_lower_drq(s);
 316         }
 317         scsi_req_continue(s->current_req);
 318         return;
 319     }
 320 }
 321
 322 static void do_cmd(ESPState *s)
 323 {
 324     uint8_t busid = esp_fifo_pop(&s->cmdfifo);
 325     int len;
 326
 327     s->cmdfifo_cdb_offset--;
 328
 329     /* Ignore extended messages for now */
 330     if (s->cmdfifo_cdb_offset) {
 331         len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo));
 332         esp_fifo_pop_buf(&s->cmdfifo, NULL, len);
 333         s->cmdfifo_cdb_offset = 0;
 334     }
 335
 336     do_busid_cmd(s, busid);
 337 }
 338
 339 static void satn_pdma_cb(ESPState *s)
 340 {
 341     s->do_cmd = 0;
 342     if (!fifo8_is_empty(&s->cmdfifo)) {
 343         s->cmdfifo_cdb_offset = 1;
 344         do_cmd(s);
 345     }
 346 }
 347
 348 static void handle_satn(ESPState *s)
 349 {
 350     int32_t cmdlen;
 351
 352     if (s->dma && !s->dma_enabled) {
 353         s->dma_cb = handle_satn;
 354         return;
 355     }
 356     s->pdma_cb = satn_pdma_cb;
 357     cmdlen = get_cmd(s, ESP_CMDFIFO_SZ);
 358     if (cmdlen > 0) {
 359         s->cmdfifo_cdb_offset = 1;
 360         s->do_cmd = 0;
 361         do_cmd(s);
 362     } else if (cmdlen == 0) {
 363         s->do_cmd = 1;
 364         /* Target present, but no cmd yet - switch to command phase */
 365         s->rregs[ESP_RSEQ] = SEQ_CD;
 366         s->rregs[ESP_RSTAT] = STAT_CD;
 367     }
 368 }
 369
 370 static void s_without_satn_pdma_cb(ESPState *s)
 371 {
 372     uint32_t len;
 373
 374     s->do_cmd = 0;
 375     len = fifo8_num_used(&s->cmdfifo);
 376     if (len) {
 377         s->cmdfifo_cdb_offset = 0;
 378         do_busid_cmd(s, 0);
 379     }
 380 }
 381
 382 static void handle_s_without_atn(ESPState *s)
 383 {
 384     int32_t cmdlen;
 385
 386     if (s->dma && !s->dma_enabled) {
 387         s->dma_cb = handle_s_without_atn;
 388         return;
 389     }
 390     s->pdma_cb = s_without_satn_pdma_cb;
 391     cmdlen = get_cmd(s, ESP_CMDFIFO_SZ);
 392     if (cmdlen > 0) {
 393         s->cmdfifo_cdb_offset = 0;
 394         s->do_cmd = 0;
 395         do_busid_cmd(s, 0);
 396     } else if (cmdlen == 0) {
 397         s->do_cmd = 1;
 398         /* Target present, but no cmd yet - switch to command phase */
 399         s->rregs[ESP_RSEQ] = SEQ_CD;
 400         s->rregs[ESP_RSTAT] = STAT_CD;
 401     }
 402 }
 403
 404 static void satn_stop_pdma_cb(ESPState *s)
 405 {
 406     s->do_cmd = 0;
 407     if (!fifo8_is_empty(&s->cmdfifo)) {
 408         trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo));
 409         s->do_cmd = 1;
 410         s->cmdfifo_cdb_offset = 1;
 411         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 412         s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 413         s->rregs[ESP_RSEQ] = SEQ_CD;
 414         esp_raise_irq(s);
 415     }
 416 }
 417
 418 static void handle_satn_stop(ESPState *s)
 419 {
 420     int32_t cmdlen;
 421
 422     if (s->dma && !s->dma_enabled) {
 423         s->dma_cb = handle_satn_stop;
 424         return;
 425     }
 426     s->pdma_cb = satn_stop_pdma_cb;
 427     cmdlen = get_cmd(s, 1);
 428     if (cmdlen > 0) {
 429         trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo));
 430         s->do_cmd = 1;
 431         s->cmdfifo_cdb_offset = 1;
 432         s->rregs[ESP_RSTAT] = STAT_MO;
 433         s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 434         s->rregs[ESP_RSEQ] = SEQ_MO;
 435         esp_raise_irq(s);
 436     } else if (cmdlen == 0) {
 437         s->do_cmd = 1;
 438         /* Target present, switch to message out phase */
 439         s->rregs[ESP_RSEQ] = SEQ_MO;
 440         s->rregs[ESP_RSTAT] = STAT_MO;
 441     }
 442 }
 443
 444 static void write_response_pdma_cb(ESPState *s)
 445 {
 446     s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 447     s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 448     s->rregs[ESP_RSEQ] = SEQ_CD;
 449     esp_raise_irq(s);
 450 }
 451
 452 static void write_response(ESPState *s)
 453 {
 454     uint8_t buf[2];
 455
 456     trace_esp_write_response(s->status);
 457
 458     buf[0] = s->status;
 459     buf[1] = 0;
 460
 461     if (s->dma) {
 462         if (s->dma_memory_write) {
 463             s->dma_memory_write(s->dma_opaque, buf, 2);
 464             s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 465             s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 466             s->rregs[ESP_RSEQ] = SEQ_CD;
 467         } else {
 468             s->pdma_cb = write_response_pdma_cb;
 469             esp_raise_drq(s);
 470             return;
 471         }
 472     } else {
 473         fifo8_reset(&s->fifo);
 474         fifo8_push_all(&s->fifo, buf, 2);
 475         s->rregs[ESP_RFLAGS] = 2;
 476     }
 477     esp_raise_irq(s);
 478 }
 479
 480 static void esp_dma_done(ESPState *s)
 481 {
 482     s->rregs[ESP_RSTAT] |= STAT_TC;
 483     s->rregs[ESP_RINTR] |= INTR_BS;
 484     s->rregs[ESP_RSEQ] = 0;
 485     s->rregs[ESP_RFLAGS] = 0;
 486     esp_set_tc(s, 0);
 487     esp_raise_irq(s);
 488 }
 489
 490 static void do_dma_pdma_cb(ESPState *s)
 491 {
 492     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 493     int len;
 494     uint32_t n;
 495
 496     if (s->do_cmd) {
 497         s->ti_size = 0;
 498         s->do_cmd = 0;
 499         do_cmd(s);
 500         esp_lower_drq(s);
 501         return;
 502     }
 503
 504     if (!s->current_req) {
 505         return;
 506     }
 507
 508     if (to_device) {
 509         /* Copy FIFO data to device */
 510         len = MIN(s->async_len, ESP_FIFO_SZ);
 511         len = MIN(len, fifo8_num_used(&s->fifo));
 512         n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
 513         s->async_buf += n;
 514         s->async_len -= n;
 515         s->ti_size += n;
 516
 517         if (n < len) {
 518             /* Unaligned accesses can cause FIFO wraparound */
 519             len = len - n;
 520             n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
 521             s->async_buf += n;
 522             s->async_len -= n;
 523             s->ti_size += n;
 524         }
 525
 526         if (s->async_len == 0) {
 527             scsi_req_continue(s->current_req);
 528             return;
 529         }
 530
 531         if (esp_get_tc(s) == 0) {
 532             esp_lower_drq(s);
 533             esp_dma_done(s);
 534         }
 535
 536         return;
 537     } else {
 538         if (s->async_len == 0) {
 539             /* Defer until the scsi layer has completed */
 540             scsi_req_continue(s->current_req);
 541             s->data_in_ready = false;
 542             return;
 543         }
 544
 545         if (esp_get_tc(s) != 0) {
 546             /* Copy device data to FIFO */
 547             len = MIN(s->async_len, esp_get_tc(s));
 548             len = MIN(len, fifo8_num_free(&s->fifo));
 549             fifo8_push_all(&s->fifo, s->async_buf, len);
 550             s->async_buf += len;
 551             s->async_len -= len;
 552             s->ti_size -= len;
 553             esp_set_tc(s, esp_get_tc(s) - len);
 554
 555             if (esp_get_tc(s) == 0) {
 556                 /* Indicate transfer to FIFO is complete */
 557                  s->rregs[ESP_RSTAT] |= STAT_TC;
 558             }
 559             return;
 560         }
 561
 562         /* Partially filled a scsi buffer. Complete immediately.  */
 563         esp_lower_drq(s);
 564         esp_dma_done(s);
 565     }
 566 }
 567
 568 static void esp_do_dma(ESPState *s)
 569 {
 570     uint32_t len, cmdlen;
 571     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 572     uint8_t buf[ESP_CMDFIFO_SZ];
 573
 574     len = esp_get_tc(s);
 575     if (s->do_cmd) {
 576         /*
 577          * handle_ti_cmd() case: esp_do_dma() is called only from
 578          * handle_ti_cmd() with do_cmd != NULL (see the assert())
 579          */
 580         cmdlen = fifo8_num_used(&s->cmdfifo);
 581         trace_esp_do_dma(cmdlen, len);
 582         if (s->dma_memory_read) {
 583             len = MIN(len, fifo8_num_free(&s->cmdfifo));
 584             s->dma_memory_read(s->dma_opaque, buf, len);
 585             fifo8_push_all(&s->cmdfifo, buf, len);
 586         } else {
 587             s->pdma_cb = do_dma_pdma_cb;
 588             esp_raise_drq(s);
 589             return;
 590         }
 591         trace_esp_handle_ti_cmd(cmdlen);
 592         s->ti_size = 0;
 593         if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) {
 594             /* No command received */
 595             if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) {
 596                 return;
 597             }
 598
 599             /* Command has been received */
 600             s->do_cmd = 0;
 601             do_cmd(s);
 602         } else {
 603             /*
 604              * Extra message out bytes received: update cmdfifo_cdb_offset
 605              * and then switch to commmand phase
 606              */
 607             s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
 608             s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 609             s->rregs[ESP_RSEQ] = SEQ_CD;
 610             s->rregs[ESP_RINTR] |= INTR_BS;
 611             esp_raise_irq(s);
 612         }
 613         return;
 614     }
 615     if (!s->current_req) {
 616         return;
 617     }
 618     if (s->async_len == 0) {
 619         /* Defer until data is available.  */
 620         return;
 621     }
 622     if (len > s->async_len) {
 623         len = s->async_len;
 624     }
 625     if (to_device) {
 626         if (s->dma_memory_read) {
 627             s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 628         } else {
 629             s->pdma_cb = do_dma_pdma_cb;
 630             esp_raise_drq(s);
 631             return;
 632         }
 633     } else {
 634         if (s->dma_memory_write) {
 635             s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 636         } else {
 637             /* Adjust TC for any leftover data in the FIFO */
 638             if (!fifo8_is_empty(&s->fifo)) {
 639                 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo));
 640             }
 641
 642             /* Copy device data to FIFO */
 643             len = MIN(len, fifo8_num_free(&s->fifo));
 644             fifo8_push_all(&s->fifo, s->async_buf, len);
 645             s->async_buf += len;
 646             s->async_len -= len;
 647             s->ti_size -= len;
 648
 649             /*
 650              * MacOS toolbox uses a TI length of 16 bytes for all commands, so
 651              * commands shorter than this must be padded accordingly
 652              */
 653             if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) {
 654                 while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) {
 655                     esp_fifo_push(&s->fifo, 0);
 656                     len++;
 657                 }
 658             }
 659
 660             esp_set_tc(s, esp_get_tc(s) - len);
 661             s->pdma_cb = do_dma_pdma_cb;
 662             esp_raise_drq(s);
 663
 664             /* Indicate transfer to FIFO is complete */
 665             s->rregs[ESP_RSTAT] |= STAT_TC;
 666             return;
 667         }
 668     }
 669     esp_set_tc(s, esp_get_tc(s) - len);
 670     s->async_buf += len;
 671     s->async_len -= len;
 672     if (to_device) {
 673         s->ti_size += len;
 674     } else {
 675         s->ti_size -= len;
 676     }
 677     if (s->async_len == 0) {
 678         scsi_req_continue(s->current_req);
 679         /*
 680          * If there is still data to be read from the device then
 681          * complete the DMA operation immediately.  Otherwise defer
 682          * until the scsi layer has completed.
 683          */
 684         if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) {
 685             return;
 686         }
 687     }
 688
 689     /* Partially filled a scsi buffer. Complete immediately.  */
 690     esp_dma_done(s);
 691     esp_lower_drq(s);
 692 }
 693
 694 static void esp_do_nodma(ESPState *s)
 695 {
 696     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 697     uint32_t cmdlen;
 698     int len;
 699
 700     if (s->do_cmd) {
 701         cmdlen = fifo8_num_used(&s->cmdfifo);
 702         trace_esp_handle_ti_cmd(cmdlen);
 703         s->ti_size = 0;
 704         if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) {
 705             /* No command received */
 706             if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) {
 707                 return;
 708             }
 709
 710             /* Command has been received */
 711             s->do_cmd = 0;
 712             do_cmd(s);
 713         } else {
 714             /*
 715              * Extra message out bytes received: update cmdfifo_cdb_offset
 716              * and then switch to commmand phase
 717              */
 718             s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
 719             s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 720             s->rregs[ESP_RSEQ] = SEQ_CD;
 721             s->rregs[ESP_RINTR] |= INTR_BS;
 722             esp_raise_irq(s);
 723         }
 724         return;
 725     }
 726
 727     if (!s->current_req) {
 728         return;
 729     }
 730
 731     if (s->async_len == 0) {
 732         /* Defer until data is available.  */
 733         return;
 734     }
 735
 736     if (to_device) {
 737         len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ);
 738         esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
 739         s->async_buf += len;
 740         s->async_len -= len;
 741         s->ti_size += len;
 742     } else {
 743         len = MIN(s->ti_size, s->async_len);
 744         len = MIN(len, fifo8_num_free(&s->fifo));
 745         fifo8_push_all(&s->fifo, s->async_buf, len);
 746         s->async_buf += len;
 747         s->async_len -= len;
 748         s->ti_size -= len;
 749     }
 750
 751     if (s->async_len == 0) {
 752         scsi_req_continue(s->current_req);
 753
 754         if (to_device || s->ti_size == 0) {
 755             return;
 756         }
 757     }
 758
 759     s->rregs[ESP_RINTR] |= INTR_BS;
 760     esp_raise_irq(s);
 761 }
 762
 763 void esp_command_complete(SCSIRequest *req, size_t resid)
 764 {
 765     ESPState *s = req->hba_private;
 766
 767     trace_esp_command_complete();
 768     if (s->ti_size != 0) {
 769         trace_esp_command_complete_unexpected();
 770     }
 771     s->ti_size = 0;
 772     s->async_len = 0;
 773     if (req->status) {
 774         trace_esp_command_complete_fail();
 775     }
 776     s->status = req->status;
 777     s->rregs[ESP_RSTAT] = STAT_ST;
 778     esp_dma_done(s);
 779     esp_lower_drq(s);
 780     if (s->current_req) {
 781         scsi_req_unref(s->current_req);
 782         s->current_req = NULL;
 783         s->current_dev = NULL;
 784     }
 785 }
 786
 787 void esp_transfer_data(SCSIRequest *req, uint32_t len)
 788 {
 789     ESPState *s = req->hba_private;
 790     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 791     uint32_t dmalen = esp_get_tc(s);
 792
 793     assert(!s->do_cmd);
 794     trace_esp_transfer_data(dmalen, s->ti_size);
 795     s->async_len = len;
 796     s->async_buf = scsi_req_get_buf(req);
 797
 798     if (!to_device && !s->data_in_ready) {
 799         /*
 800          * Initial incoming data xfer is complete so raise command
 801          * completion interrupt
 802          */
 803         s->data_in_ready = true;
 804         s->rregs[ESP_RSTAT] |= STAT_TC;
 805         s->rregs[ESP_RINTR] |= INTR_BS;
 806         esp_raise_irq(s);
 807
 808         /*
 809          * If data is ready to transfer and the TI command has already
 810          * been executed, start DMA immediately. Otherwise DMA will start
 811          * when host sends the TI command
 812          */
 813         if (s->ti_size && (s->rregs[ESP_CMD] == (CMD_TI | CMD_DMA))) {
 814             esp_do_dma(s);
 815         }
 816         return;
 817     }
 818
 819     if (s->ti_cmd == 0) {
 820         /*
 821          * Always perform the initial transfer upon reception of the next TI
 822          * command to ensure the DMA/non-DMA status of the command is correct.
 823          * It is not possible to use s->dma directly in the section below as
 824          * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the
 825          * async data transfer is delayed then s->dma is set incorrectly.
 826          */
 827         return;
 828     }
 829
 830     if (s->ti_cmd & CMD_DMA) {
 831         if (dmalen) {
 832             esp_do_dma(s);
 833         } else if (s->ti_size <= 0) {
 834             /*
 835              * If this was the last part of a DMA transfer then the
 836              * completion interrupt is deferred to here.
 837              */
 838             esp_dma_done(s);
 839             esp_lower_drq(s);
 840         }
 841     } else {
 842         esp_do_nodma(s);
 843     }
 844 }
 845
 846 static void handle_ti(ESPState *s)
 847 {
 848     uint32_t dmalen;
 849
 850     if (s->dma && !s->dma_enabled) {
 851         s->dma_cb = handle_ti;
 852         return;
 853     }
 854
 855     s->ti_cmd = s->rregs[ESP_CMD];
 856     if (s->dma) {
 857         dmalen = esp_get_tc(s);
 858         trace_esp_handle_ti(dmalen);
 859         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 860         esp_do_dma(s);
 861     } else {
 862         trace_esp_handle_ti(s->ti_size);
 863         esp_do_nodma(s);
 864     }
 865 }
 866
 867 void esp_hard_reset(ESPState *s)
 868 {
 869     memset(s->rregs, 0, ESP_REGS);
 870     memset(s->wregs, 0, ESP_REGS);
 871     s->tchi_written = 0;
 872     s->ti_size = 0;
 873     fifo8_reset(&s->fifo);
 874     fifo8_reset(&s->cmdfifo);
 875     s->dma = 0;
 876     s->do_cmd = 0;
 877     s->dma_cb = NULL;
 878
 879     s->rregs[ESP_CFG1] = 7;
 880 }
 881
 882 static void esp_soft_reset(ESPState *s)
 883 {
 884     qemu_irq_lower(s->irq);
 885     qemu_irq_lower(s->irq_data);
 886     esp_hard_reset(s);
 887 }
 888
 889 static void parent_esp_reset(ESPState *s, int irq, int level)
 890 {
 891     if (level) {
 892         esp_soft_reset(s);
 893     }
 894 }
 895
 896 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
 897 {
 898     uint32_t val;
 899
 900     switch (saddr) {
 901     case ESP_FIFO:
 902         if (s->dma_memory_read && s->dma_memory_write &&
 903                 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 904             /* Data out.  */
 905             qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
 906             s->rregs[ESP_FIFO] = 0;
 907         } else {
 908             s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo);
 909         }
 910         val = s->rregs[ESP_FIFO];
 911         break;
 912     case ESP_RINTR:
 913         /*
 914          * Clear sequence step, interrupt register and all status bits
 915          * except TC
 916          */
 917         val = s->rregs[ESP_RINTR];
 918         s->rregs[ESP_RINTR] = 0;
 919         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 920         s->rregs[ESP_RSEQ] = SEQ_0;
 921         esp_lower_irq(s);
 922         break;
 923     case ESP_TCHI:
 924         /* Return the unique id if the value has never been written */
 925         if (!s->tchi_written) {
 926             val = s->chip_id;
 927         } else {
 928             val = s->rregs[saddr];
 929         }
 930         break;
 931      case ESP_RFLAGS:
 932         /* Bottom 5 bits indicate number of bytes in FIFO */
 933         val = fifo8_num_used(&s->fifo);
 934         break;
 935     default:
 936         val = s->rregs[saddr];
 937         break;
 938     }
 939
 940     trace_esp_mem_readb(saddr, val);
 941     return val;
 942 }
 943
 944 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 945 {
 946     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 947     switch (saddr) {
 948     case ESP_TCHI:
 949         s->tchi_written = true;
 950         /* fall through */
 951     case ESP_TCLO:
 952     case ESP_TCMID:
 953         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 954         break;
 955     case ESP_FIFO:
 956         if (s->do_cmd) {
 957             esp_fifo_push(&s->cmdfifo, val);
 958         } else {
 959             esp_fifo_push(&s->fifo, val);
 960         }
 961
 962         /* Non-DMA transfers raise an interrupt after every byte */
 963         if (s->rregs[ESP_CMD] == CMD_TI) {
 964             s->rregs[ESP_RINTR] |= INTR_FC | INTR_BS;
 965             esp_raise_irq(s);
 966         }
 967         break;
 968     case ESP_CMD:
 969         s->rregs[saddr] = val;
 970         if (val & CMD_DMA) {
 971             s->dma = 1;
 972             /* Reload DMA counter.  */
 973             if (esp_get_stc(s) == 0) {
 974                 esp_set_tc(s, 0x10000);
 975             } else {
 976                 esp_set_tc(s, esp_get_stc(s));
 977             }
 978         } else {
 979             s->dma = 0;
 980         }
 981         switch (val & CMD_CMD) {
 982         case CMD_NOP:
 983             trace_esp_mem_writeb_cmd_nop(val);
 984             break;
 985         case CMD_FLUSH:
 986             trace_esp_mem_writeb_cmd_flush(val);
 987             fifo8_reset(&s->fifo);
 988             break;
 989         case CMD_RESET:
 990             trace_esp_mem_writeb_cmd_reset(val);
 991             esp_soft_reset(s);
 992             break;
 993         case CMD_BUSRESET:
 994             trace_esp_mem_writeb_cmd_bus_reset(val);
 995             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 996                 s->rregs[ESP_RINTR] |= INTR_RST;
 997                 esp_raise_irq(s);
 998             }
 999             break;
1000         case CMD_TI:
1001             trace_esp_mem_writeb_cmd_ti(val);
1002             handle_ti(s);
1003             break;
1004         case CMD_ICCS:
1005             trace_esp_mem_writeb_cmd_iccs(val);
1006             write_response(s);
1007             s->rregs[ESP_RINTR] |= INTR_FC;
1008             s->rregs[ESP_RSTAT] |= STAT_MI;
1009             break;
1010         case CMD_MSGACC:
1011             trace_esp_mem_writeb_cmd_msgacc(val);
1012             s->rregs[ESP_RINTR] |= INTR_DC;
1013             s->rregs[ESP_RSEQ] = 0;
1014             s->rregs[ESP_RFLAGS] = 0;
1015             esp_raise_irq(s);
1016             break;
1017         case CMD_PAD:
1018             trace_esp_mem_writeb_cmd_pad(val);
1019             s->rregs[ESP_RSTAT] = STAT_TC;
1020             s->rregs[ESP_RINTR] |= INTR_FC;
1021             s->rregs[ESP_RSEQ] = 0;
1022             break;
1023         case CMD_SATN:
1024             trace_esp_mem_writeb_cmd_satn(val);
1025             break;
1026         case CMD_RSTATN:
1027             trace_esp_mem_writeb_cmd_rstatn(val);
1028             break;
1029         case CMD_SEL:
1030             trace_esp_mem_writeb_cmd_sel(val);
1031             handle_s_without_atn(s);
1032             break;
1033         case CMD_SELATN:
1034             trace_esp_mem_writeb_cmd_selatn(val);
1035             handle_satn(s);
1036             break;
1037         case CMD_SELATNS:
1038             trace_esp_mem_writeb_cmd_selatns(val);
1039             handle_satn_stop(s);
1040             break;
1041         case CMD_ENSEL:
1042             trace_esp_mem_writeb_cmd_ensel(val);
1043             s->rregs[ESP_RINTR] = 0;
1044             break;
1045         case CMD_DISSEL:
1046             trace_esp_mem_writeb_cmd_dissel(val);
1047             s->rregs[ESP_RINTR] = 0;
1048             esp_raise_irq(s);
1049             break;
1050         default:
1051             trace_esp_error_unhandled_command(val);
1052             break;
1053         }
1054         break;
1055     case ESP_WBUSID ... ESP_WSYNO:
1056         break;
1057     case ESP_CFG1:
1058     case ESP_CFG2: case ESP_CFG3:
1059     case ESP_RES3: case ESP_RES4:
1060         s->rregs[saddr] = val;
1061         break;
1062     case ESP_WCCF ... ESP_WTEST:
1063         break;
1064     default:
1065         trace_esp_error_invalid_write(val, saddr);
1066         return;
1067     }
1068     s->wregs[saddr] = val;
1069 }
1070
1071 static bool esp_mem_accepts(void *opaque, hwaddr addr,
1072                             unsigned size, bool is_write,
1073                             MemTxAttrs attrs)
1074 {
1075     return (size == 1) || (is_write && size == 4);
1076 }
1077
1078 static bool esp_is_before_version_5(void *opaque, int version_id)
1079 {
1080     ESPState *s = ESP(opaque);
1081
1082     version_id = MIN(version_id, s->mig_version_id);
1083     return version_id < 5;
1084 }
1085
1086 static bool esp_is_version_5(void *opaque, int version_id)
1087 {
1088     ESPState *s = ESP(opaque);
1089
1090     version_id = MIN(version_id, s->mig_version_id);
1091     return version_id == 5;
1092 }
1093
1094 int esp_pre_save(void *opaque)
1095 {
1096     ESPState *s = ESP(object_resolve_path_component(
1097                       OBJECT(opaque), "esp"));
1098
1099     s->mig_version_id = vmstate_esp.version_id;
1100     return 0;
1101 }
1102
1103 static int esp_post_load(void *opaque, int version_id)
1104 {
1105     ESPState *s = ESP(opaque);
1106     int len, i;
1107
1108     version_id = MIN(version_id, s->mig_version_id);
1109
1110     if (version_id < 5) {
1111         esp_set_tc(s, s->mig_dma_left);
1112
1113         /* Migrate ti_buf to fifo */
1114         len = s->mig_ti_wptr - s->mig_ti_rptr;
1115         for (i = 0; i < len; i++) {
1116             fifo8_push(&s->fifo, s->mig_ti_buf[i]);
1117         }
1118
1119         /* Migrate cmdbuf to cmdfifo */
1120         for (i = 0; i < s->mig_cmdlen; i++) {
1121             fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]);
1122         }
1123     }
1124
1125     s->mig_version_id = vmstate_esp.version_id;
1126     return 0;
1127 }
1128
1129 const VMStateDescription vmstate_esp = {
1130     .name = "esp",
1131     .version_id = 5,
1132     .minimum_version_id = 3,
1133     .post_load = esp_post_load,
1134     .fields = (VMStateField[]) {
1135         VMSTATE_BUFFER(rregs, ESPState),
1136         VMSTATE_BUFFER(wregs, ESPState),
1137         VMSTATE_INT32(ti_size, ESPState),
1138         VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5),
1139         VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5),
1140         VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5),
1141         VMSTATE_UINT32(status, ESPState),
1142         VMSTATE_UINT32_TEST(mig_deferred_status, ESPState,
1143                             esp_is_before_version_5),
1144         VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState,
1145                           esp_is_before_version_5),
1146         VMSTATE_UINT32(dma, ESPState),
1147         VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0,
1148                               esp_is_before_version_5, 0, 16),
1149         VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4,
1150                               esp_is_before_version_5, 16,
1151                               sizeof(typeof_field(ESPState, mig_cmdbuf))),
1152         VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5),
1153         VMSTATE_UINT32(do_cmd, ESPState),
1154         VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5),
1155         VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5),
1156         VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5),
1157         VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5),
1158         VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5),
1159         VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5),
1160         VMSTATE_END_OF_LIST()
1161     },
1162 };
1163
1164 static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
1165                                  uint64_t val, unsigned int size)
1166 {
1167     SysBusESPState *sysbus = opaque;
1168     ESPState *s = ESP(&sysbus->esp);
1169     uint32_t saddr;
1170
1171     saddr = addr >> sysbus->it_shift;
1172     esp_reg_write(s, saddr, val);
1173 }
1174
1175 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
1176                                     unsigned int size)
1177 {
1178     SysBusESPState *sysbus = opaque;
1179     ESPState *s = ESP(&sysbus->esp);
1180     uint32_t saddr;
1181
1182     saddr = addr >> sysbus->it_shift;
1183     return esp_reg_read(s, saddr);
1184 }
1185
1186 static const MemoryRegionOps sysbus_esp_mem_ops = {
1187     .read = sysbus_esp_mem_read,
1188     .write = sysbus_esp_mem_write,
1189     .endianness = DEVICE_NATIVE_ENDIAN,
1190     .valid.accepts = esp_mem_accepts,
1191 };
1192
1193 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr,
1194                                   uint64_t val, unsigned int size)
1195 {
1196     SysBusESPState *sysbus = opaque;
1197     ESPState *s = ESP(&sysbus->esp);
1198     uint32_t dmalen;
1199
1200     trace_esp_pdma_write(size);
1201
1202     switch (size) {
1203     case 1:
1204         esp_pdma_write(s, val);
1205         break;
1206     case 2:
1207         esp_pdma_write(s, val >> 8);
1208         esp_pdma_write(s, val);
1209         break;
1210     }
1211     dmalen = esp_get_tc(s);
1212     if (dmalen == 0 || fifo8_num_free(&s->fifo) < 2) {
1213         s->pdma_cb(s);
1214     }
1215 }
1216
1217 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr,
1218                                      unsigned int size)
1219 {
1220     SysBusESPState *sysbus = opaque;
1221     ESPState *s = ESP(&sysbus->esp);
1222     uint64_t val = 0;
1223
1224     trace_esp_pdma_read(size);
1225
1226     switch (size) {
1227     case 1:
1228         val = esp_pdma_read(s);
1229         break;
1230     case 2:
1231         val = esp_pdma_read(s);
1232         val = (val << 8) | esp_pdma_read(s);
1233         break;
1234     }
1235     if (fifo8_num_used(&s->fifo) < 2) {
1236         s->pdma_cb(s);
1237     }
1238     return val;
1239 }
1240
1241 static const MemoryRegionOps sysbus_esp_pdma_ops = {
1242     .read = sysbus_esp_pdma_read,
1243     .write = sysbus_esp_pdma_write,
1244     .endianness = DEVICE_NATIVE_ENDIAN,
1245     .valid.min_access_size = 1,
1246     .valid.max_access_size = 4,
1247     .impl.min_access_size = 1,
1248     .impl.max_access_size = 2,
1249 };
1250
1251 static const struct SCSIBusInfo esp_scsi_info = {
1252     .tcq = false,
1253     .max_target = ESP_MAX_DEVS,
1254     .max_lun = 7,
1255
1256     .transfer_data = esp_transfer_data,
1257     .complete = esp_command_complete,
1258     .cancel = esp_request_cancelled
1259 };
1260
1261 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
1262 {
1263     SysBusESPState *sysbus = SYSBUS_ESP(opaque);
1264     ESPState *s = ESP(&sysbus->esp);
1265
1266     switch (irq) {
1267     case 0:
1268         parent_esp_reset(s, irq, level);
1269         break;
1270     case 1:
1271         esp_dma_enable(opaque, irq, level);
1272         break;
1273     }
1274 }
1275
1276 static void sysbus_esp_realize(DeviceState *dev, Error **errp)
1277 {
1278     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1279     SysBusESPState *sysbus = SYSBUS_ESP(dev);
1280     ESPState *s = ESP(&sysbus->esp);
1281
1282     if (!qdev_realize(DEVICE(s), NULL, errp)) {
1283         return;
1284     }
1285
1286     sysbus_init_irq(sbd, &s->irq);
1287     sysbus_init_irq(sbd, &s->irq_data);
1288     assert(sysbus->it_shift != -1);
1289
1290     s->chip_id = TCHI_FAS100A;
1291     memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
1292                           sysbus, "esp-regs", ESP_REGS << sysbus->it_shift);
1293     sysbus_init_mmio(sbd, &sysbus->iomem);
1294     memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops,
1295                           sysbus, "esp-pdma", 4);
1296     sysbus_init_mmio(sbd, &sysbus->pdma);
1297
1298     qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
1299
1300     scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
1301 }
1302
1303 static void sysbus_esp_hard_reset(DeviceState *dev)
1304 {
1305     SysBusESPState *sysbus = SYSBUS_ESP(dev);
1306     ESPState *s = ESP(&sysbus->esp);
1307
1308     esp_hard_reset(s);
1309 }
1310
1311 static void sysbus_esp_init(Object *obj)
1312 {
1313     SysBusESPState *sysbus = SYSBUS_ESP(obj);
1314
1315     object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP);
1316 }
1317
1318 static const VMStateDescription vmstate_sysbus_esp_scsi = {
1319     .name = "sysbusespscsi",
1320     .version_id = 2,
1321     .minimum_version_id = 1,
1322     .pre_save = esp_pre_save,
1323     .fields = (VMStateField[]) {
1324         VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2),
1325         VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
1326         VMSTATE_END_OF_LIST()
1327     }
1328 };
1329
1330 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
1331 {
1332     DeviceClass *dc = DEVICE_CLASS(klass);
1333
1334     dc->realize = sysbus_esp_realize;
1335     dc->reset = sysbus_esp_hard_reset;
1336     dc->vmsd = &vmstate_sysbus_esp_scsi;
1337     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1338 }
1339
1340 static const TypeInfo sysbus_esp_info = {
1341     .name          = TYPE_SYSBUS_ESP,
1342     .parent        = TYPE_SYS_BUS_DEVICE,
1343     .instance_init = sysbus_esp_init,
1344     .instance_size = sizeof(SysBusESPState),
1345     .class_init    = sysbus_esp_class_init,
1346 };
1347
1348 static void esp_finalize(Object *obj)
1349 {
1350     ESPState *s = ESP(obj);
1351
1352     fifo8_destroy(&s->fifo);
1353     fifo8_destroy(&s->cmdfifo);
1354 }
1355
1356 static void esp_init(Object *obj)
1357 {
1358     ESPState *s = ESP(obj);
1359
1360     fifo8_create(&s->fifo, ESP_FIFO_SZ);
1361     fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ);
1362 }
1363
1364 static void esp_class_init(ObjectClass *klass, void *data)
1365 {
1366     DeviceClass *dc = DEVICE_CLASS(klass);
1367
1368     /* internal device for sysbusesp/pciespscsi, not user-creatable */
1369     dc->user_creatable = false;
1370     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1371 }
1372
1373 static const TypeInfo esp_info = {
1374     .name = TYPE_ESP,
1375     .parent = TYPE_DEVICE,
1376     .instance_init = esp_init,
1377     .instance_finalize = esp_finalize,
1378     .instance_size = sizeof(ESPState),
1379     .class_init = esp_class_init,
1380 };
1381
1382 static void esp_register_types(void)
1383 {
1384     type_register_static(&sysbus_esp_info);
1385     type_register_static(&esp_info);
1386 }
1387
1388 type_init(esp_register_types)