target/moxie/translate.c

   1 /*
   2  *  Moxie emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2009, 2013 Anthony Green
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* For information on the Moxie architecture, see
  21  *    http://moxielogic.org/wiki
  22  */
  23
  24 #include "qemu/osdep.h"
  25
  26 #include "cpu.h"
  27 #include "exec/exec-all.h"
  28 #include "disas/disas.h"
  29 #include "tcg-op.h"
  30 #include "exec/cpu_ldst.h"
  31
  32 #include "exec/helper-proto.h"
  33 #include "exec/helper-gen.h"
  34 #include "exec/log.h"
  35
  36 /* This is the state at translation time.  */
  37 typedef struct DisasContext {
  38     struct TranslationBlock *tb;
  39     target_ulong pc, saved_pc;
  40     uint32_t opcode;
  41     uint32_t fp_status;
  42     /* Routine used to access memory */
  43     int memidx;
  44     int bstate;
  45     target_ulong btarget;
  46     int singlestep_enabled;
  47 } DisasContext;
  48
  49 enum {
  50     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  51                       * exception condition */
  52     BS_STOP     = 1, /* We want to stop translation for any reason */
  53     BS_BRANCH   = 2, /* We reached a branch condition     */
  54     BS_EXCP     = 3, /* We reached an exception condition */
  55 };
  56
  57 static TCGv cpu_pc;
  58 static TCGv cpu_gregs[16];
  59 static TCGv_env cpu_env;
  60 static TCGv cc_a, cc_b;
  61
  62 #include "exec/gen-icount.h"
  63
  64 #define REG(x) (cpu_gregs[x])
  65
  66 /* Extract the signed 10-bit offset from a 16-bit branch
  67    instruction.  */
  68 static int extract_branch_offset(int opcode)
  69 {
  70   return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
  71 }
  72
  73 void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
  74                           int flags)
  75 {
  76     MoxieCPU *cpu = MOXIE_CPU(cs);
  77     CPUMoxieState *env = &cpu->env;
  78     int i;
  79     cpu_fprintf(f, "pc=0x%08x\n", env->pc);
  80     cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
  81                 env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
  82     for (i = 4; i < 16; i += 4) {
  83         cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
  84                     i-2, env->gregs[i], i-1, env->gregs[i + 1],
  85                     i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
  86     }
  87     for (i = 4; i < 16; i += 4) {
  88         cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
  89                     i-2, env->sregs[i], i-1, env->sregs[i + 1],
  90                     i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
  91     }
  92 }
  93
  94 void moxie_translate_init(void)
  95 {
  96     int i;
  97     static const char * const gregnames[16] = {
  98         "$fp", "$sp", "$r0", "$r1",
  99         "$r2", "$r3", "$r4", "$r5",
 100         "$r6", "$r7", "$r8", "$r9",
 101         "$r10", "$r11", "$r12", "$r13"
 102     };
 103
 104     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 105     tcg_ctx.tcg_env = cpu_env;
 106     cpu_pc = tcg_global_mem_new_i32(cpu_env,
 107                                     offsetof(CPUMoxieState, pc), "$pc");
 108     for (i = 0; i < 16; i++)
 109         cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
 110                                               offsetof(CPUMoxieState, gregs[i]),
 111                                               gregnames[i]);
 112
 113     cc_a = tcg_global_mem_new_i32(cpu_env,
 114                                   offsetof(CPUMoxieState, cc_a), "cc_a");
 115     cc_b = tcg_global_mem_new_i32(cpu_env,
 116                                   offsetof(CPUMoxieState, cc_b), "cc_b");
 117 }
 118
 119 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 120 {
 121     if (unlikely(ctx->singlestep_enabled)) {
 122         return false;
 123     }
 124
 125 #ifndef CONFIG_USER_ONLY
 126     return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 127 #else
 128     return true;
 129 #endif
 130 }
 131
 132 static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
 133                                int n, target_ulong dest)
 134 {
 135     if (use_goto_tb(ctx, dest)) {
 136         tcg_gen_goto_tb(n);
 137         tcg_gen_movi_i32(cpu_pc, dest);
 138         tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
 139     } else {
 140         tcg_gen_movi_i32(cpu_pc, dest);
 141         if (ctx->singlestep_enabled) {
 142             gen_helper_debug(cpu_env);
 143         }
 144         tcg_gen_exit_tb(0);
 145     }
 146 }
 147
 148 static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
 149 {
 150     CPUMoxieState *env = &cpu->env;
 151
 152     /* Local cache for the instruction opcode.  */
 153     int opcode;
 154     /* Set the default instruction length.  */
 155     int length = 2;
 156
 157     /* Examine the 16-bit opcode.  */
 158     opcode = ctx->opcode;
 159
 160     /* Decode instruction.  */
 161     if (opcode & (1 << 15)) {
 162         if (opcode & (1 << 14)) {
 163             /* This is a Form 3 instruction.  */
 164             int inst = (opcode >> 10 & 0xf);
 165
 166 #define BRANCH(cond)                                                         \
 167     do {                                                                     \
 168         TCGLabel *l1 = gen_new_label();                                      \
 169         tcg_gen_brcond_i32(cond, cc_a, cc_b, l1);                            \
 170         gen_goto_tb(env, ctx, 1, ctx->pc+2);                                 \
 171         gen_set_label(l1);                                                   \
 172         gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
 173         ctx->bstate = BS_BRANCH;                                             \
 174     } while (0)
 175
 176             switch (inst) {
 177             case 0x00: /* beq */
 178                 BRANCH(TCG_COND_EQ);
 179                 break;
 180             case 0x01: /* bne */
 181                 BRANCH(TCG_COND_NE);
 182                 break;
 183             case 0x02: /* blt */
 184                 BRANCH(TCG_COND_LT);
 185                 break;
 186             case 0x03: /* bgt */
 187                 BRANCH(TCG_COND_GT);
 188                 break;
 189             case 0x04: /* bltu */
 190                 BRANCH(TCG_COND_LTU);
 191                 break;
 192             case 0x05: /* bgtu */
 193                 BRANCH(TCG_COND_GTU);
 194                 break;
 195             case 0x06: /* bge */
 196                 BRANCH(TCG_COND_GE);
 197                 break;
 198             case 0x07: /* ble */
 199                 BRANCH(TCG_COND_LE);
 200                 break;
 201             case 0x08: /* bgeu */
 202                 BRANCH(TCG_COND_GEU);
 203                 break;
 204             case 0x09: /* bleu */
 205                 BRANCH(TCG_COND_LEU);
 206                 break;
 207             default:
 208                 {
 209                     TCGv temp = tcg_temp_new_i32();
 210                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 211                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 212                     gen_helper_raise_exception(cpu_env, temp);
 213                     tcg_temp_free_i32(temp);
 214                 }
 215                 break;
 216             }
 217         } else {
 218             /* This is a Form 2 instruction.  */
 219             int inst = (opcode >> 12 & 0x3);
 220             switch (inst) {
 221             case 0x00: /* inc */
 222                 {
 223                     int a = (opcode >> 8) & 0xf;
 224                     unsigned int v = (opcode & 0xff);
 225                     tcg_gen_addi_i32(REG(a), REG(a), v);
 226                 }
 227                 break;
 228             case 0x01: /* dec */
 229                 {
 230                     int a = (opcode >> 8) & 0xf;
 231                     unsigned int v = (opcode & 0xff);
 232                     tcg_gen_subi_i32(REG(a), REG(a), v);
 233                 }
 234                 break;
 235             case 0x02: /* gsr */
 236                 {
 237                     int a = (opcode >> 8) & 0xf;
 238                     unsigned v = (opcode & 0xff);
 239                     tcg_gen_ld_i32(REG(a), cpu_env,
 240                                    offsetof(CPUMoxieState, sregs[v]));
 241                 }
 242                 break;
 243             case 0x03: /* ssr */
 244                 {
 245                     int a = (opcode >> 8) & 0xf;
 246                     unsigned v = (opcode & 0xff);
 247                     tcg_gen_st_i32(REG(a), cpu_env,
 248                                    offsetof(CPUMoxieState, sregs[v]));
 249                 }
 250                 break;
 251             default:
 252                 {
 253                     TCGv temp = tcg_temp_new_i32();
 254                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 255                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 256                     gen_helper_raise_exception(cpu_env, temp);
 257                     tcg_temp_free_i32(temp);
 258                 }
 259                 break;
 260             }
 261         }
 262     } else {
 263         /* This is a Form 1 instruction.  */
 264         int inst = opcode >> 8;
 265         switch (inst) {
 266         case 0x00: /* nop */
 267             break;
 268         case 0x01: /* ldi.l (immediate) */
 269             {
 270                 int reg = (opcode >> 4) & 0xf;
 271                 int val = cpu_ldl_code(env, ctx->pc+2);
 272                 tcg_gen_movi_i32(REG(reg), val);
 273                 length = 6;
 274             }
 275             break;
 276         case 0x02: /* mov (register-to-register) */
 277             {
 278                 int dest  = (opcode >> 4) & 0xf;
 279                 int src = opcode & 0xf;
 280                 tcg_gen_mov_i32(REG(dest), REG(src));
 281             }
 282             break;
 283         case 0x03: /* jsra */
 284             {
 285                 TCGv t1 = tcg_temp_new_i32();
 286                 TCGv t2 = tcg_temp_new_i32();
 287
 288                 tcg_gen_movi_i32(t1, ctx->pc + 6);
 289
 290                 /* Make space for the static chain and return address.  */
 291                 tcg_gen_subi_i32(t2, REG(1), 8);
 292                 tcg_gen_mov_i32(REG(1), t2);
 293                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 294
 295                 /* Push the current frame pointer.  */
 296                 tcg_gen_subi_i32(t2, REG(1), 4);
 297                 tcg_gen_mov_i32(REG(1), t2);
 298                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 299
 300                 /* Set the pc and $fp.  */
 301                 tcg_gen_mov_i32(REG(0), REG(1));
 302
 303                 gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
 304
 305                 tcg_temp_free_i32(t1);
 306                 tcg_temp_free_i32(t2);
 307
 308                 ctx->bstate = BS_BRANCH;
 309                 length = 6;
 310             }
 311             break;
 312         case 0x04: /* ret */
 313             {
 314                 TCGv t1 = tcg_temp_new_i32();
 315
 316                 /* The new $sp is the old $fp.  */
 317                 tcg_gen_mov_i32(REG(1), REG(0));
 318
 319                 /* Pop the frame pointer.  */
 320                 tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
 321                 tcg_gen_addi_i32(t1, REG(1), 4);
 322                 tcg_gen_mov_i32(REG(1), t1);
 323
 324
 325                 /* Pop the return address and skip over the static chain
 326                    slot.  */
 327                 tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
 328                 tcg_gen_addi_i32(t1, REG(1), 8);
 329                 tcg_gen_mov_i32(REG(1), t1);
 330
 331                 tcg_temp_free_i32(t1);
 332
 333                 /* Jump... */
 334                 tcg_gen_exit_tb(0);
 335
 336                 ctx->bstate = BS_BRANCH;
 337             }
 338             break;
 339         case 0x05: /* add.l */
 340             {
 341                 int a = (opcode >> 4) & 0xf;
 342                 int b = opcode & 0xf;
 343
 344                 tcg_gen_add_i32(REG(a), REG(a), REG(b));
 345             }
 346             break;
 347         case 0x06: /* push */
 348             {
 349                 int a = (opcode >> 4) & 0xf;
 350                 int b = opcode & 0xf;
 351
 352                 TCGv t1 = tcg_temp_new_i32();
 353                 tcg_gen_subi_i32(t1, REG(a), 4);
 354                 tcg_gen_mov_i32(REG(a), t1);
 355                 tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
 356                 tcg_temp_free_i32(t1);
 357             }
 358             break;
 359         case 0x07: /* pop */
 360             {
 361                 int a = (opcode >> 4) & 0xf;
 362                 int b = opcode & 0xf;
 363                 TCGv t1 = tcg_temp_new_i32();
 364
 365                 tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
 366                 tcg_gen_addi_i32(t1, REG(a), 4);
 367                 tcg_gen_mov_i32(REG(a), t1);
 368                 tcg_temp_free_i32(t1);
 369             }
 370             break;
 371         case 0x08: /* lda.l */
 372             {
 373                 int reg = (opcode >> 4) & 0xf;
 374
 375                 TCGv ptr = tcg_temp_new_i32();
 376                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 377                 tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
 378                 tcg_temp_free_i32(ptr);
 379
 380                 length = 6;
 381             }
 382             break;
 383         case 0x09: /* sta.l */
 384             {
 385                 int val = (opcode >> 4) & 0xf;
 386
 387                 TCGv ptr = tcg_temp_new_i32();
 388                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 389                 tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
 390                 tcg_temp_free_i32(ptr);
 391
 392                 length = 6;
 393             }
 394             break;
 395         case 0x0a: /* ld.l (register indirect) */
 396             {
 397                 int src  = opcode & 0xf;
 398                 int dest = (opcode >> 4) & 0xf;
 399
 400                 tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
 401             }
 402             break;
 403         case 0x0b: /* st.l */
 404             {
 405                 int dest = (opcode >> 4) & 0xf;
 406                 int val  = opcode & 0xf;
 407
 408                 tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
 409             }
 410             break;
 411         case 0x0c: /* ldo.l */
 412             {
 413                 int a = (opcode >> 4) & 0xf;
 414                 int b = opcode & 0xf;
 415
 416                 TCGv t1 = tcg_temp_new_i32();
 417                 TCGv t2 = tcg_temp_new_i32();
 418                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 419                 tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
 420                 tcg_gen_mov_i32(REG(a), t2);
 421
 422                 tcg_temp_free_i32(t1);
 423                 tcg_temp_free_i32(t2);
 424
 425                 length = 6;
 426             }
 427             break;
 428         case 0x0d: /* sto.l */
 429             {
 430                 int a = (opcode >> 4) & 0xf;
 431                 int b = opcode & 0xf;
 432
 433                 TCGv t1 = tcg_temp_new_i32();
 434                 TCGv t2 = tcg_temp_new_i32();
 435                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 436                 tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
 437
 438                 tcg_temp_free_i32(t1);
 439                 tcg_temp_free_i32(t2);
 440
 441                 length = 6;
 442             }
 443             break;
 444         case 0x0e: /* cmp */
 445             {
 446                 int a  = (opcode >> 4) & 0xf;
 447                 int b  = opcode & 0xf;
 448
 449                 tcg_gen_mov_i32(cc_a, REG(a));
 450                 tcg_gen_mov_i32(cc_b, REG(b));
 451             }
 452             break;
 453         case 0x19: /* jsr */
 454             {
 455                 int fnreg = (opcode >> 4) & 0xf;
 456
 457                 /* Load the stack pointer into T0.  */
 458                 TCGv t1 = tcg_temp_new_i32();
 459                 TCGv t2 = tcg_temp_new_i32();
 460
 461                 tcg_gen_movi_i32(t1, ctx->pc+2);
 462
 463                 /* Make space for the static chain and return address.  */
 464                 tcg_gen_subi_i32(t2, REG(1), 8);
 465                 tcg_gen_mov_i32(REG(1), t2);
 466                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 467
 468                 /* Push the current frame pointer.  */
 469                 tcg_gen_subi_i32(t2, REG(1), 4);
 470                 tcg_gen_mov_i32(REG(1), t2);
 471                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 472
 473                 /* Set the pc and $fp.  */
 474                 tcg_gen_mov_i32(REG(0), REG(1));
 475                 tcg_gen_mov_i32(cpu_pc, REG(fnreg));
 476                 tcg_temp_free_i32(t1);
 477                 tcg_temp_free_i32(t2);
 478                 tcg_gen_exit_tb(0);
 479                 ctx->bstate = BS_BRANCH;
 480             }
 481             break;
 482         case 0x1a: /* jmpa */
 483             {
 484                 tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
 485                 tcg_gen_exit_tb(0);
 486                 ctx->bstate = BS_BRANCH;
 487                 length = 6;
 488             }
 489             break;
 490         case 0x1b: /* ldi.b (immediate) */
 491             {
 492                 int reg = (opcode >> 4) & 0xf;
 493                 int val = cpu_ldl_code(env, ctx->pc+2);
 494                 tcg_gen_movi_i32(REG(reg), val);
 495                 length = 6;
 496             }
 497             break;
 498         case 0x1c: /* ld.b (register indirect) */
 499             {
 500                 int src  = opcode & 0xf;
 501                 int dest = (opcode >> 4) & 0xf;
 502
 503                 tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
 504             }
 505             break;
 506         case 0x1d: /* lda.b */
 507             {
 508                 int reg = (opcode >> 4) & 0xf;
 509
 510                 TCGv ptr = tcg_temp_new_i32();
 511                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 512                 tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
 513                 tcg_temp_free_i32(ptr);
 514
 515                 length = 6;
 516             }
 517             break;
 518         case 0x1e: /* st.b */
 519             {
 520                 int dest = (opcode >> 4) & 0xf;
 521                 int val  = opcode & 0xf;
 522
 523                 tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
 524             }
 525             break;
 526         case 0x1f: /* sta.b */
 527             {
 528                 int val = (opcode >> 4) & 0xf;
 529
 530                 TCGv ptr = tcg_temp_new_i32();
 531                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 532                 tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
 533                 tcg_temp_free_i32(ptr);
 534
 535                 length = 6;
 536             }
 537             break;
 538         case 0x20: /* ldi.s (immediate) */
 539             {
 540                 int reg = (opcode >> 4) & 0xf;
 541                 int val = cpu_ldl_code(env, ctx->pc+2);
 542                 tcg_gen_movi_i32(REG(reg), val);
 543                 length = 6;
 544             }
 545             break;
 546         case 0x21: /* ld.s (register indirect) */
 547             {
 548                 int src  = opcode & 0xf;
 549                 int dest = (opcode >> 4) & 0xf;
 550
 551                 tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
 552             }
 553             break;
 554         case 0x22: /* lda.s */
 555             {
 556                 int reg = (opcode >> 4) & 0xf;
 557
 558                 TCGv ptr = tcg_temp_new_i32();
 559                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 560                 tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
 561                 tcg_temp_free_i32(ptr);
 562
 563                 length = 6;
 564             }
 565             break;
 566         case 0x23: /* st.s */
 567             {
 568                 int dest = (opcode >> 4) & 0xf;
 569                 int val  = opcode & 0xf;
 570
 571                 tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
 572             }
 573             break;
 574         case 0x24: /* sta.s */
 575             {
 576                 int val = (opcode >> 4) & 0xf;
 577
 578                 TCGv ptr = tcg_temp_new_i32();
 579                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 580                 tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
 581                 tcg_temp_free_i32(ptr);
 582
 583                 length = 6;
 584             }
 585             break;
 586         case 0x25: /* jmp */
 587             {
 588                 int reg = (opcode >> 4) & 0xf;
 589                 tcg_gen_mov_i32(cpu_pc, REG(reg));
 590                 tcg_gen_exit_tb(0);
 591                 ctx->bstate = BS_BRANCH;
 592             }
 593             break;
 594         case 0x26: /* and */
 595             {
 596                 int a = (opcode >> 4) & 0xf;
 597                 int b = opcode & 0xf;
 598
 599                 tcg_gen_and_i32(REG(a), REG(a), REG(b));
 600             }
 601             break;
 602         case 0x27: /* lshr */
 603             {
 604                 int a = (opcode >> 4) & 0xf;
 605                 int b = opcode & 0xf;
 606
 607                 TCGv sv = tcg_temp_new_i32();
 608                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 609                 tcg_gen_shr_i32(REG(a), REG(a), sv);
 610                 tcg_temp_free_i32(sv);
 611             }
 612             break;
 613         case 0x28: /* ashl */
 614             {
 615                 int a = (opcode >> 4) & 0xf;
 616                 int b = opcode & 0xf;
 617
 618                 TCGv sv = tcg_temp_new_i32();
 619                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 620                 tcg_gen_shl_i32(REG(a), REG(a), sv);
 621                 tcg_temp_free_i32(sv);
 622             }
 623             break;
 624         case 0x29: /* sub.l */
 625             {
 626                 int a = (opcode >> 4) & 0xf;
 627                 int b = opcode & 0xf;
 628
 629                 tcg_gen_sub_i32(REG(a), REG(a), REG(b));
 630             }
 631             break;
 632         case 0x2a: /* neg */
 633             {
 634                 int a = (opcode >> 4) & 0xf;
 635                 int b = opcode & 0xf;
 636
 637                 tcg_gen_neg_i32(REG(a), REG(b));
 638             }
 639             break;
 640         case 0x2b: /* or */
 641             {
 642                 int a = (opcode >> 4) & 0xf;
 643                 int b = opcode & 0xf;
 644
 645                 tcg_gen_or_i32(REG(a), REG(a), REG(b));
 646             }
 647             break;
 648         case 0x2c: /* not */
 649             {
 650                 int a = (opcode >> 4) & 0xf;
 651                 int b = opcode & 0xf;
 652
 653                 tcg_gen_not_i32(REG(a), REG(b));
 654             }
 655             break;
 656         case 0x2d: /* ashr */
 657             {
 658                 int a = (opcode >> 4) & 0xf;
 659                 int b = opcode & 0xf;
 660
 661                 TCGv sv = tcg_temp_new_i32();
 662                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 663                 tcg_gen_sar_i32(REG(a), REG(a), sv);
 664                 tcg_temp_free_i32(sv);
 665             }
 666             break;
 667         case 0x2e: /* xor */
 668             {
 669                 int a = (opcode >> 4) & 0xf;
 670                 int b = opcode & 0xf;
 671
 672                 tcg_gen_xor_i32(REG(a), REG(a), REG(b));
 673             }
 674             break;
 675         case 0x2f: /* mul.l */
 676             {
 677                 int a = (opcode >> 4) & 0xf;
 678                 int b = opcode & 0xf;
 679
 680                 tcg_gen_mul_i32(REG(a), REG(a), REG(b));
 681             }
 682             break;
 683         case 0x30: /* swi */
 684             {
 685                 int val = cpu_ldl_code(env, ctx->pc+2);
 686
 687                 TCGv temp = tcg_temp_new_i32();
 688                 tcg_gen_movi_i32(temp, val);
 689                 tcg_gen_st_i32(temp, cpu_env,
 690                                offsetof(CPUMoxieState, sregs[3]));
 691                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 692                 tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
 693                 gen_helper_raise_exception(cpu_env, temp);
 694                 tcg_temp_free_i32(temp);
 695
 696                 length = 6;
 697             }
 698             break;
 699         case 0x31: /* div.l */
 700             {
 701                 int a = (opcode >> 4) & 0xf;
 702                 int b = opcode & 0xf;
 703                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 704                 gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
 705             }
 706             break;
 707         case 0x32: /* udiv.l */
 708             {
 709                 int a = (opcode >> 4) & 0xf;
 710                 int b = opcode & 0xf;
 711                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 712                 gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
 713             }
 714             break;
 715         case 0x33: /* mod.l */
 716             {
 717                 int a = (opcode >> 4) & 0xf;
 718                 int b = opcode & 0xf;
 719                 tcg_gen_rem_i32(REG(a), REG(a), REG(b));
 720             }
 721             break;
 722         case 0x34: /* umod.l */
 723             {
 724                 int a = (opcode >> 4) & 0xf;
 725                 int b = opcode & 0xf;
 726                 tcg_gen_remu_i32(REG(a), REG(a), REG(b));
 727             }
 728             break;
 729         case 0x35: /* brk */
 730             {
 731                 TCGv temp = tcg_temp_new_i32();
 732                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 733                 tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
 734                 gen_helper_raise_exception(cpu_env, temp);
 735                 tcg_temp_free_i32(temp);
 736             }
 737             break;
 738         case 0x36: /* ldo.b */
 739             {
 740                 int a = (opcode >> 4) & 0xf;
 741                 int b = opcode & 0xf;
 742
 743                 TCGv t1 = tcg_temp_new_i32();
 744                 TCGv t2 = tcg_temp_new_i32();
 745                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 746                 tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
 747                 tcg_gen_mov_i32(REG(a), t2);
 748
 749                 tcg_temp_free_i32(t1);
 750                 tcg_temp_free_i32(t2);
 751
 752                 length = 6;
 753             }
 754             break;
 755         case 0x37: /* sto.b */
 756             {
 757                 int a = (opcode >> 4) & 0xf;
 758                 int b = opcode & 0xf;
 759
 760                 TCGv t1 = tcg_temp_new_i32();
 761                 TCGv t2 = tcg_temp_new_i32();
 762                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 763                 tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
 764
 765                 tcg_temp_free_i32(t1);
 766                 tcg_temp_free_i32(t2);
 767
 768                 length = 6;
 769             }
 770             break;
 771         case 0x38: /* ldo.s */
 772             {
 773                 int a = (opcode >> 4) & 0xf;
 774                 int b = opcode & 0xf;
 775
 776                 TCGv t1 = tcg_temp_new_i32();
 777                 TCGv t2 = tcg_temp_new_i32();
 778                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 779                 tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
 780                 tcg_gen_mov_i32(REG(a), t2);
 781
 782                 tcg_temp_free_i32(t1);
 783                 tcg_temp_free_i32(t2);
 784
 785                 length = 6;
 786             }
 787             break;
 788         case 0x39: /* sto.s */
 789             {
 790                 int a = (opcode >> 4) & 0xf;
 791                 int b = opcode & 0xf;
 792
 793                 TCGv t1 = tcg_temp_new_i32();
 794                 TCGv t2 = tcg_temp_new_i32();
 795                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 796                 tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
 797                 tcg_temp_free_i32(t1);
 798                 tcg_temp_free_i32(t2);
 799
 800                 length = 6;
 801             }
 802             break;
 803         default:
 804             {
 805                 TCGv temp = tcg_temp_new_i32();
 806                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 807                 tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 808                 gen_helper_raise_exception(cpu_env, temp);
 809                 tcg_temp_free_i32(temp);
 810              }
 811             break;
 812         }
 813     }
 814
 815     return length;
 816 }
 817
 818 /* generate intermediate code for basic block 'tb'.  */
 819 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
 820 {
 821     CPUMoxieState *env = cs->env_ptr;
 822     MoxieCPU *cpu = moxie_env_get_cpu(env);
 823     DisasContext ctx;
 824     target_ulong pc_start;
 825     int num_insns, max_insns;
 826
 827     pc_start = tb->pc;
 828     ctx.pc = pc_start;
 829     ctx.saved_pc = -1;
 830     ctx.tb = tb;
 831     ctx.memidx = 0;
 832     ctx.singlestep_enabled = 0;
 833     ctx.bstate = BS_NONE;
 834     num_insns = 0;
 835     max_insns = tb->cflags & CF_COUNT_MASK;
 836     if (max_insns == 0) {
 837         max_insns = CF_COUNT_MASK;
 838     }
 839     if (max_insns > TCG_MAX_INSNS) {
 840         max_insns = TCG_MAX_INSNS;
 841     }
 842
 843     gen_tb_start(tb);
 844     do {
 845         tcg_gen_insn_start(ctx.pc);
 846         num_insns++;
 847
 848         if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
 849             tcg_gen_movi_i32(cpu_pc, ctx.pc);
 850             gen_helper_debug(cpu_env);
 851             ctx.bstate = BS_EXCP;
 852             /* The address covered by the breakpoint must be included in
 853                [tb->pc, tb->pc + tb->size) in order to for it to be
 854                properly cleared -- thus we increment the PC here so that
 855                the logic setting tb->size below does the right thing.  */
 856             ctx.pc += 2;
 857             goto done_generating;
 858         }
 859
 860         ctx.opcode = cpu_lduw_code(env, ctx.pc);
 861         ctx.pc += decode_opc(cpu, &ctx);
 862
 863         if (num_insns >= max_insns) {
 864             break;
 865         }
 866         if (cs->singlestep_enabled) {
 867             break;
 868         }
 869         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
 870             break;
 871         }
 872     } while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
 873
 874     if (cs->singlestep_enabled) {
 875         tcg_gen_movi_tl(cpu_pc, ctx.pc);
 876         gen_helper_debug(cpu_env);
 877     } else {
 878         switch (ctx.bstate) {
 879         case BS_STOP:
 880         case BS_NONE:
 881             gen_goto_tb(env, &ctx, 0, ctx.pc);
 882             break;
 883         case BS_EXCP:
 884             tcg_gen_exit_tb(0);
 885             break;
 886         case BS_BRANCH:
 887         default:
 888             break;
 889         }
 890     }
 891  done_generating:
 892     gen_tb_end(tb, num_insns);
 893
 894     tb->size = ctx.pc - pc_start;
 895     tb->icount = num_insns;
 896 }
 897
 898 void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb,
 899                           target_ulong *data)
 900 {
 901     env->pc = data[0];
 902 }