target/alpha/cpu.c

   1 /*
   2  * QEMU Alpha CPU
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "exec/exec-all.h"
  27
  28
  29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     AlphaCPU *cpu = ALPHA_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static bool alpha_cpu_has_work(CPUState *cs)
  37 {
  38     /* Here we are checking to see if the CPU should wake up from HALT.
  39        We will have gotten into this state only for WTINT from PALmode.  */
  40     /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
  41        asleep even if (some) interrupts have been asserted.  For now,
  42        assume that if a CPU really wants to stay asleep, it will mask
  43        interrupts at the chipset level, which will prevent these bits
  44        from being set in the first place.  */
  45     return cs->interrupt_request & (CPU_INTERRUPT_HARD
  46                                     | CPU_INTERRUPT_TIMER
  47                                     | CPU_INTERRUPT_SMP
  48                                     | CPU_INTERRUPT_MCHK);
  49 }
  50
  51 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  52 {
  53     info->mach = bfd_mach_alpha_ev6;
  54     info->print_insn = print_insn_alpha;
  55 }
  56
  57 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
  58 {
  59     CPUState *cs = CPU(dev);
  60     AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
  61     Error *local_err = NULL;
  62
  63     cpu_exec_realizefn(cs, &local_err);
  64     if (local_err != NULL) {
  65         error_propagate(errp, local_err);
  66         return;
  67     }
  68
  69     qemu_init_vcpu(cs);
  70
  71     acc->parent_realize(dev, errp);
  72 }
  73
  74 /* Sort alphabetically by type name. */
  75 static gint alpha_cpu_list_compare(gconstpointer a, gconstpointer b)
  76 {
  77     ObjectClass *class_a = (ObjectClass *)a;
  78     ObjectClass *class_b = (ObjectClass *)b;
  79     const char *name_a, *name_b;
  80
  81     name_a = object_class_get_name(class_a);
  82     name_b = object_class_get_name(class_b);
  83     return strcmp(name_a, name_b);
  84 }
  85
  86 static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
  87 {
  88     ObjectClass *oc = data;
  89     CPUListState *s = user_data;
  90
  91     (*s->cpu_fprintf)(s->file, "  %s\n",
  92                       object_class_get_name(oc));
  93 }
  94
  95 void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf)
  96 {
  97     CPUListState s = {
  98         .file = f,
  99         .cpu_fprintf = cpu_fprintf,
 100     };
 101     GSList *list;
 102
 103     list = object_class_get_list(TYPE_ALPHA_CPU, false);
 104     list = g_slist_sort(list, alpha_cpu_list_compare);
 105     (*cpu_fprintf)(f, "Available CPUs:\n");
 106     g_slist_foreach(list, alpha_cpu_list_entry, &s);
 107     g_slist_free(list);
 108 }
 109
 110 /* Models */
 111
 112 #define TYPE(model) model "-" TYPE_ALPHA_CPU
 113
 114 typedef struct AlphaCPUAlias {
 115     const char *alias;
 116     const char *typename;
 117 } AlphaCPUAlias;
 118
 119 static const AlphaCPUAlias alpha_cpu_aliases[] = {
 120     { "21064",   TYPE("ev4") },
 121     { "21164",   TYPE("ev5") },
 122     { "21164a",  TYPE("ev56") },
 123     { "21164pc", TYPE("pca56") },
 124     { "21264",   TYPE("ev6") },
 125     { "21264a",  TYPE("ev67") },
 126 };
 127
 128 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
 129 {
 130     ObjectClass *oc;
 131     char *typename;
 132     int i;
 133
 134     oc = object_class_by_name(cpu_model);
 135     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
 136         !object_class_is_abstract(oc)) {
 137         return oc;
 138     }
 139
 140     for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
 141         if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
 142             oc = object_class_by_name(alpha_cpu_aliases[i].typename);
 143             assert(oc != NULL && !object_class_is_abstract(oc));
 144             return oc;
 145         }
 146     }
 147
 148     typename = g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model);
 149     oc = object_class_by_name(typename);
 150     g_free(typename);
 151     if (oc != NULL && object_class_is_abstract(oc)) {
 152         oc = NULL;
 153     }
 154
 155     /* TODO: remove match everything nonsense */
 156     /* Default to ev67; no reason not to emulate insns by default. */
 157     if (!oc) {
 158         oc = object_class_by_name(TYPE("ev67"));
 159     }
 160
 161     return oc;
 162 }
 163
 164 static void ev4_cpu_initfn(Object *obj)
 165 {
 166     AlphaCPU *cpu = ALPHA_CPU(obj);
 167     CPUAlphaState *env = &cpu->env;
 168
 169     env->implver = IMPLVER_2106x;
 170 }
 171
 172 static const TypeInfo ev4_cpu_type_info = {
 173     .name = TYPE("ev4"),
 174     .parent = TYPE_ALPHA_CPU,
 175     .instance_init = ev4_cpu_initfn,
 176 };
 177
 178 static void ev5_cpu_initfn(Object *obj)
 179 {
 180     AlphaCPU *cpu = ALPHA_CPU(obj);
 181     CPUAlphaState *env = &cpu->env;
 182
 183     env->implver = IMPLVER_21164;
 184 }
 185
 186 static const TypeInfo ev5_cpu_type_info = {
 187     .name = TYPE("ev5"),
 188     .parent = TYPE_ALPHA_CPU,
 189     .instance_init = ev5_cpu_initfn,
 190 };
 191
 192 static void ev56_cpu_initfn(Object *obj)
 193 {
 194     AlphaCPU *cpu = ALPHA_CPU(obj);
 195     CPUAlphaState *env = &cpu->env;
 196
 197     env->amask |= AMASK_BWX;
 198 }
 199
 200 static const TypeInfo ev56_cpu_type_info = {
 201     .name = TYPE("ev56"),
 202     .parent = TYPE("ev5"),
 203     .instance_init = ev56_cpu_initfn,
 204 };
 205
 206 static void pca56_cpu_initfn(Object *obj)
 207 {
 208     AlphaCPU *cpu = ALPHA_CPU(obj);
 209     CPUAlphaState *env = &cpu->env;
 210
 211     env->amask |= AMASK_MVI;
 212 }
 213
 214 static const TypeInfo pca56_cpu_type_info = {
 215     .name = TYPE("pca56"),
 216     .parent = TYPE("ev56"),
 217     .instance_init = pca56_cpu_initfn,
 218 };
 219
 220 static void ev6_cpu_initfn(Object *obj)
 221 {
 222     AlphaCPU *cpu = ALPHA_CPU(obj);
 223     CPUAlphaState *env = &cpu->env;
 224
 225     env->implver = IMPLVER_21264;
 226     env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
 227 }
 228
 229 static const TypeInfo ev6_cpu_type_info = {
 230     .name = TYPE("ev6"),
 231     .parent = TYPE_ALPHA_CPU,
 232     .instance_init = ev6_cpu_initfn,
 233 };
 234
 235 static void ev67_cpu_initfn(Object *obj)
 236 {
 237     AlphaCPU *cpu = ALPHA_CPU(obj);
 238     CPUAlphaState *env = &cpu->env;
 239
 240     env->amask |= AMASK_CIX | AMASK_PREFETCH;
 241 }
 242
 243 static const TypeInfo ev67_cpu_type_info = {
 244     .name = TYPE("ev67"),
 245     .parent = TYPE("ev6"),
 246     .instance_init = ev67_cpu_initfn,
 247 };
 248
 249 static const TypeInfo ev68_cpu_type_info = {
 250     .name = TYPE("ev68"),
 251     .parent = TYPE("ev67"),
 252 };
 253
 254 static void alpha_cpu_initfn(Object *obj)
 255 {
 256     CPUState *cs = CPU(obj);
 257     AlphaCPU *cpu = ALPHA_CPU(obj);
 258     CPUAlphaState *env = &cpu->env;
 259
 260     cs->env_ptr = env;
 261     tlb_flush(cs);
 262
 263     env->lock_addr = -1;
 264 #if defined(CONFIG_USER_ONLY)
 265     env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
 266     cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
 267                                | FPCR_UNFD | FPCR_INED | FPCR_DNOD
 268                                | FPCR_DYN_NORMAL));
 269 #else
 270     env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;
 271 #endif
 272 }
 273
 274 static void alpha_cpu_class_init(ObjectClass *oc, void *data)
 275 {
 276     DeviceClass *dc = DEVICE_CLASS(oc);
 277     CPUClass *cc = CPU_CLASS(oc);
 278     AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
 279
 280     acc->parent_realize = dc->realize;
 281     dc->realize = alpha_cpu_realizefn;
 282
 283     cc->class_by_name = alpha_cpu_class_by_name;
 284     cc->has_work = alpha_cpu_has_work;
 285     cc->do_interrupt = alpha_cpu_do_interrupt;
 286     cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
 287     cc->dump_state = alpha_cpu_dump_state;
 288     cc->set_pc = alpha_cpu_set_pc;
 289     cc->gdb_read_register = alpha_cpu_gdb_read_register;
 290     cc->gdb_write_register = alpha_cpu_gdb_write_register;
 291 #ifdef CONFIG_USER_ONLY
 292     cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
 293 #else
 294     cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
 295     cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
 296     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
 297     dc->vmsd = &vmstate_alpha_cpu;
 298 #endif
 299     cc->disas_set_info = alpha_cpu_disas_set_info;
 300     cc->tcg_initialize = alpha_translate_init;
 301
 302     cc->gdb_num_core_regs = 67;
 303 }
 304
 305 static const TypeInfo alpha_cpu_type_info = {
 306     .name = TYPE_ALPHA_CPU,
 307     .parent = TYPE_CPU,
 308     .instance_size = sizeof(AlphaCPU),
 309     .instance_init = alpha_cpu_initfn,
 310     .abstract = true,
 311     .class_size = sizeof(AlphaCPUClass),
 312     .class_init = alpha_cpu_class_init,
 313 };
 314
 315 static void alpha_cpu_register_types(void)
 316 {
 317     type_register_static(&alpha_cpu_type_info);
 318     type_register_static(&ev4_cpu_type_info);
 319     type_register_static(&ev5_cpu_type_info);
 320     type_register_static(&ev56_cpu_type_info);
 321     type_register_static(&pca56_cpu_type_info);
 322     type_register_static(&ev6_cpu_type_info);
 323     type_register_static(&ev67_cpu_type_info);
 324     type_register_static(&ev68_cpu_type_info);
 325 }
 326
 327 type_init(alpha_cpu_register_types)