hw/net/xilinx_axienet.c

   1 /*
   2  * QEMU model of Xilinx AXI-Ethernet.
   3  *
   4  * Copyright (c) 2011 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "qemu/log.h"
  27 #include "net/net.h"
  28 #include "net/checksum.h"
  29 #include "qapi/qmp/qerror.h"
  30
  31 #include "hw/stream.h"
  32
  33 #define DPHY(x)
  34
  35 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
  36 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
  37
  38 #define XILINX_AXI_ENET(obj) \
  39      OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
  40
  41 #define XILINX_AXI_ENET_DATA_STREAM(obj) \
  42      OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
  43      TYPE_XILINX_AXI_ENET_DATA_STREAM)
  44
  45 /* Advertisement control register. */
  46 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
  47 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
  48 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
  49 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
  50
  51 struct PHY {
  52     uint32_t regs[32];
  53
  54     int link;
  55
  56     unsigned int (*read)(struct PHY *phy, unsigned int req);
  57     void (*write)(struct PHY *phy, unsigned int req,
  58                   unsigned int data);
  59 };
  60
  61 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
  62 {
  63     int regnum;
  64     unsigned r = 0;
  65
  66     regnum = req & 0x1f;
  67
  68     switch (regnum) {
  69         case 1:
  70             if (!phy->link) {
  71                 break;
  72             }
  73             /* MR1.  */
  74             /* Speeds and modes.  */
  75             r |= (1 << 13) | (1 << 14);
  76             r |= (1 << 11) | (1 << 12);
  77             r |= (1 << 5); /* Autoneg complete.  */
  78             r |= (1 << 3); /* Autoneg able.  */
  79             r |= (1 << 2); /* link.  */
  80             r |= (1 << 1); /* link.  */
  81             break;
  82         case 5:
  83             /* Link partner ability.
  84                We are kind; always agree with whatever best mode
  85                the guest advertises.  */
  86             r = 1 << 14; /* Success.  */
  87             /* Copy advertised modes.  */
  88             r |= phy->regs[4] & (15 << 5);
  89             /* Autoneg support.  */
  90             r |= 1;
  91             break;
  92         case 17:
  93             /* Marvel PHY on many xilinx boards.  */
  94             r = 0x8000; /* 1000Mb  */
  95             break;
  96         case 18:
  97             {
  98                 /* Diagnostics reg.  */
  99                 int duplex = 0;
 100                 int speed_100 = 0;
 101
 102                 if (!phy->link) {
 103                     break;
 104                 }
 105
 106                 /* Are we advertising 100 half or 100 duplex ? */
 107                 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
 108                 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
 109
 110                 /* Are we advertising 10 duplex or 100 duplex ? */
 111                 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
 112                 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
 113                 r = (speed_100 << 10) | (duplex << 11);
 114             }
 115             break;
 116
 117         default:
 118             r = phy->regs[regnum];
 119             break;
 120     }
 121     DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
 122     return r;
 123 }
 124
 125 static void
 126 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
 127 {
 128     int regnum;
 129
 130     regnum = req & 0x1f;
 131     DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
 132     switch (regnum) {
 133         default:
 134             phy->regs[regnum] = data;
 135             break;
 136     }
 137 }
 138
 139 static void
 140 tdk_init(struct PHY *phy)
 141 {
 142     phy->regs[0] = 0x3100;
 143     /* PHY Id.  */
 144     phy->regs[2] = 0x0300;
 145     phy->regs[3] = 0xe400;
 146     /* Autonegotiation advertisement reg.  */
 147     phy->regs[4] = 0x01E1;
 148     phy->link = 1;
 149
 150     phy->read = tdk_read;
 151     phy->write = tdk_write;
 152 }
 153
 154 struct MDIOBus {
 155     /* bus.  */
 156     int mdc;
 157     int mdio;
 158
 159     /* decoder.  */
 160     enum {
 161         PREAMBLE,
 162         SOF,
 163         OPC,
 164         ADDR,
 165         REQ,
 166         TURNAROUND,
 167         DATA
 168     } state;
 169     unsigned int drive;
 170
 171     unsigned int cnt;
 172     unsigned int addr;
 173     unsigned int opc;
 174     unsigned int req;
 175     unsigned int data;
 176
 177     struct PHY *devs[32];
 178 };
 179
 180 static void
 181 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 182 {
 183     bus->devs[addr & 0x1f] = phy;
 184 }
 185
 186 #ifdef USE_THIS_DEAD_CODE
 187 static void
 188 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 189 {
 190     bus->devs[addr & 0x1f] = NULL;
 191 }
 192 #endif
 193
 194 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
 195                   unsigned int reg)
 196 {
 197     struct PHY *phy;
 198     uint16_t data;
 199
 200     phy = bus->devs[addr];
 201     if (phy && phy->read) {
 202         data = phy->read(phy, reg);
 203     } else {
 204         data = 0xffff;
 205     }
 206     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 207     return data;
 208 }
 209
 210 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
 211                unsigned int reg, uint16_t data)
 212 {
 213     struct PHY *phy;
 214
 215     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 216     phy = bus->devs[addr];
 217     if (phy && phy->write) {
 218         phy->write(phy, reg, data);
 219     }
 220 }
 221
 222 #define DENET(x)
 223
 224 #define R_RAF      (0x000 / 4)
 225 enum {
 226     RAF_MCAST_REJ = (1 << 1),
 227     RAF_BCAST_REJ = (1 << 2),
 228     RAF_EMCF_EN = (1 << 12),
 229     RAF_NEWFUNC_EN = (1 << 11)
 230 };
 231
 232 #define R_IS       (0x00C / 4)
 233 enum {
 234     IS_HARD_ACCESS_COMPLETE = 1,
 235     IS_AUTONEG = (1 << 1),
 236     IS_RX_COMPLETE = (1 << 2),
 237     IS_RX_REJECT = (1 << 3),
 238     IS_TX_COMPLETE = (1 << 5),
 239     IS_RX_DCM_LOCK = (1 << 6),
 240     IS_MGM_RDY = (1 << 7),
 241     IS_PHY_RST_DONE = (1 << 8),
 242 };
 243
 244 #define R_IP       (0x010 / 4)
 245 #define R_IE       (0x014 / 4)
 246 #define R_UAWL     (0x020 / 4)
 247 #define R_UAWU     (0x024 / 4)
 248 #define R_PPST     (0x030 / 4)
 249 enum {
 250     PPST_LINKSTATUS = (1 << 0),
 251     PPST_PHY_LINKSTATUS = (1 << 7),
 252 };
 253
 254 #define R_STATS_RX_BYTESL (0x200 / 4)
 255 #define R_STATS_RX_BYTESH (0x204 / 4)
 256 #define R_STATS_TX_BYTESL (0x208 / 4)
 257 #define R_STATS_TX_BYTESH (0x20C / 4)
 258 #define R_STATS_RXL       (0x290 / 4)
 259 #define R_STATS_RXH       (0x294 / 4)
 260 #define R_STATS_RX_BCASTL (0x2a0 / 4)
 261 #define R_STATS_RX_BCASTH (0x2a4 / 4)
 262 #define R_STATS_RX_MCASTL (0x2a8 / 4)
 263 #define R_STATS_RX_MCASTH (0x2ac / 4)
 264
 265 #define R_RCW0     (0x400 / 4)
 266 #define R_RCW1     (0x404 / 4)
 267 enum {
 268     RCW1_VLAN = (1 << 27),
 269     RCW1_RX   = (1 << 28),
 270     RCW1_FCS  = (1 << 29),
 271     RCW1_JUM  = (1 << 30),
 272     RCW1_RST  = (1 << 31),
 273 };
 274
 275 #define R_TC       (0x408 / 4)
 276 enum {
 277     TC_VLAN = (1 << 27),
 278     TC_TX   = (1 << 28),
 279     TC_FCS  = (1 << 29),
 280     TC_JUM  = (1 << 30),
 281     TC_RST  = (1 << 31),
 282 };
 283
 284 #define R_EMMC     (0x410 / 4)
 285 enum {
 286     EMMC_LINKSPEED_10MB = (0 << 30),
 287     EMMC_LINKSPEED_100MB = (1 << 30),
 288     EMMC_LINKSPEED_1000MB = (2 << 30),
 289 };
 290
 291 #define R_PHYC     (0x414 / 4)
 292
 293 #define R_MC       (0x500 / 4)
 294 #define MC_EN      (1 << 6)
 295
 296 #define R_MCR      (0x504 / 4)
 297 #define R_MWD      (0x508 / 4)
 298 #define R_MRD      (0x50c / 4)
 299 #define R_MIS      (0x600 / 4)
 300 #define R_MIP      (0x620 / 4)
 301 #define R_MIE      (0x640 / 4)
 302 #define R_MIC      (0x640 / 4)
 303
 304 #define R_UAW0     (0x700 / 4)
 305 #define R_UAW1     (0x704 / 4)
 306 #define R_FMI      (0x708 / 4)
 307 #define R_AF0      (0x710 / 4)
 308 #define R_AF1      (0x714 / 4)
 309 #define R_MAX      (0x34 / 4)
 310
 311 /* Indirect registers.  */
 312 struct TEMAC  {
 313     struct MDIOBus mdio_bus;
 314     struct PHY phy;
 315
 316     void *parent;
 317 };
 318
 319 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
 320 typedef struct XilinxAXIEnet XilinxAXIEnet;
 321
 322 struct XilinxAXIEnetStreamSlave {
 323     Object parent;
 324
 325     struct XilinxAXIEnet *enet;
 326 } ;
 327
 328 struct XilinxAXIEnet {
 329     SysBusDevice busdev;
 330     MemoryRegion iomem;
 331     qemu_irq irq;
 332     StreamSlave *tx_dev;
 333     XilinxAXIEnetStreamSlave rx_data_dev;
 334     NICState *nic;
 335     NICConf conf;
 336
 337
 338     uint32_t c_rxmem;
 339     uint32_t c_txmem;
 340     uint32_t c_phyaddr;
 341
 342     struct TEMAC TEMAC;
 343
 344     /* MII regs.  */
 345     union {
 346         uint32_t regs[4];
 347         struct {
 348             uint32_t mc;
 349             uint32_t mcr;
 350             uint32_t mwd;
 351             uint32_t mrd;
 352         };
 353     } mii;
 354
 355     struct {
 356         uint64_t rx_bytes;
 357         uint64_t tx_bytes;
 358
 359         uint64_t rx;
 360         uint64_t rx_bcast;
 361         uint64_t rx_mcast;
 362     } stats;
 363
 364     /* Receive configuration words.  */
 365     uint32_t rcw[2];
 366     /* Transmit config.  */
 367     uint32_t tc;
 368     uint32_t emmc;
 369     uint32_t phyc;
 370
 371     /* Unicast Address Word.  */
 372     uint32_t uaw[2];
 373     /* Unicast address filter used with extended mcast.  */
 374     uint32_t ext_uaw[2];
 375     uint32_t fmi;
 376
 377     uint32_t regs[R_MAX];
 378
 379     /* Multicast filter addrs.  */
 380     uint32_t maddr[4][2];
 381     /* 32K x 1 lookup filter.  */
 382     uint32_t ext_mtable[1024];
 383
 384
 385     uint8_t *rxmem;
 386 };
 387
 388 static void axienet_rx_reset(XilinxAXIEnet *s)
 389 {
 390     s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
 391 }
 392
 393 static void axienet_tx_reset(XilinxAXIEnet *s)
 394 {
 395     s->tc = TC_JUM | TC_TX | TC_VLAN;
 396 }
 397
 398 static inline int axienet_rx_resetting(XilinxAXIEnet *s)
 399 {
 400     return s->rcw[1] & RCW1_RST;
 401 }
 402
 403 static inline int axienet_rx_enabled(XilinxAXIEnet *s)
 404 {
 405     return s->rcw[1] & RCW1_RX;
 406 }
 407
 408 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
 409 {
 410     return !!(s->regs[R_RAF] & RAF_EMCF_EN);
 411 }
 412
 413 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
 414 {
 415     return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
 416 }
 417
 418 static void xilinx_axienet_reset(DeviceState *d)
 419 {
 420     XilinxAXIEnet *s = XILINX_AXI_ENET(d);
 421
 422     axienet_rx_reset(s);
 423     axienet_tx_reset(s);
 424
 425     s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
 426     s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
 427
 428     s->emmc = EMMC_LINKSPEED_100MB;
 429 }
 430
 431 static void enet_update_irq(XilinxAXIEnet *s)
 432 {
 433     s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
 434     qemu_set_irq(s->irq, !!s->regs[R_IP]);
 435 }
 436
 437 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
 438 {
 439     XilinxAXIEnet *s = opaque;
 440     uint32_t r = 0;
 441     addr >>= 2;
 442
 443     switch (addr) {
 444         case R_RCW0:
 445         case R_RCW1:
 446             r = s->rcw[addr & 1];
 447             break;
 448
 449         case R_TC:
 450             r = s->tc;
 451             break;
 452
 453         case R_EMMC:
 454             r = s->emmc;
 455             break;
 456
 457         case R_PHYC:
 458             r = s->phyc;
 459             break;
 460
 461         case R_MCR:
 462             r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready.  */
 463             break;
 464
 465         case R_STATS_RX_BYTESL:
 466         case R_STATS_RX_BYTESH:
 467             r = s->stats.rx_bytes >> (32 * (addr & 1));
 468             break;
 469
 470         case R_STATS_TX_BYTESL:
 471         case R_STATS_TX_BYTESH:
 472             r = s->stats.tx_bytes >> (32 * (addr & 1));
 473             break;
 474
 475         case R_STATS_RXL:
 476         case R_STATS_RXH:
 477             r = s->stats.rx >> (32 * (addr & 1));
 478             break;
 479         case R_STATS_RX_BCASTL:
 480         case R_STATS_RX_BCASTH:
 481             r = s->stats.rx_bcast >> (32 * (addr & 1));
 482             break;
 483         case R_STATS_RX_MCASTL:
 484         case R_STATS_RX_MCASTH:
 485             r = s->stats.rx_mcast >> (32 * (addr & 1));
 486             break;
 487
 488         case R_MC:
 489         case R_MWD:
 490         case R_MRD:
 491             r = s->mii.regs[addr & 3];
 492             break;
 493
 494         case R_UAW0:
 495         case R_UAW1:
 496             r = s->uaw[addr & 1];
 497             break;
 498
 499         case R_UAWU:
 500         case R_UAWL:
 501             r = s->ext_uaw[addr & 1];
 502             break;
 503
 504         case R_FMI:
 505             r = s->fmi;
 506             break;
 507
 508         case R_AF0:
 509         case R_AF1:
 510             r = s->maddr[s->fmi & 3][addr & 1];
 511             break;
 512
 513         case 0x8000 ... 0x83ff:
 514             r = s->ext_mtable[addr - 0x8000];
 515             break;
 516
 517         default:
 518             if (addr < ARRAY_SIZE(s->regs)) {
 519                 r = s->regs[addr];
 520             }
 521             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 522                             __func__, addr * 4, r));
 523             break;
 524     }
 525     return r;
 526 }
 527
 528 static void enet_write(void *opaque, hwaddr addr,
 529                        uint64_t value, unsigned size)
 530 {
 531     XilinxAXIEnet *s = opaque;
 532     struct TEMAC *t = &s->TEMAC;
 533
 534     addr >>= 2;
 535     switch (addr) {
 536         case R_RCW0:
 537         case R_RCW1:
 538             s->rcw[addr & 1] = value;
 539             if ((addr & 1) && value & RCW1_RST) {
 540                 axienet_rx_reset(s);
 541             } else {
 542                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 543             }
 544             break;
 545
 546         case R_TC:
 547             s->tc = value;
 548             if (value & TC_RST) {
 549                 axienet_tx_reset(s);
 550             }
 551             break;
 552
 553         case R_EMMC:
 554             s->emmc = value;
 555             break;
 556
 557         case R_PHYC:
 558             s->phyc = value;
 559             break;
 560
 561         case R_MC:
 562              value &= ((1 < 7) - 1);
 563
 564              /* Enable the MII.  */
 565              if (value & MC_EN) {
 566                  unsigned int miiclkdiv = value & ((1 << 6) - 1);
 567                  if (!miiclkdiv) {
 568                      qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
 569                  }
 570              }
 571              s->mii.mc = value;
 572              break;
 573
 574         case R_MCR: {
 575              unsigned int phyaddr = (value >> 24) & 0x1f;
 576              unsigned int regaddr = (value >> 16) & 0x1f;
 577              unsigned int op = (value >> 14) & 3;
 578              unsigned int initiate = (value >> 11) & 1;
 579
 580              if (initiate) {
 581                  if (op == 1) {
 582                      mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
 583                  } else if (op == 2) {
 584                      s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
 585                  } else {
 586                      qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
 587                  }
 588              }
 589              s->mii.mcr = value;
 590              break;
 591         }
 592
 593         case R_MWD:
 594         case R_MRD:
 595              s->mii.regs[addr & 3] = value;
 596              break;
 597
 598
 599         case R_UAW0:
 600         case R_UAW1:
 601             s->uaw[addr & 1] = value;
 602             break;
 603
 604         case R_UAWL:
 605         case R_UAWU:
 606             s->ext_uaw[addr & 1] = value;
 607             break;
 608
 609         case R_FMI:
 610             s->fmi = value;
 611             break;
 612
 613         case R_AF0:
 614         case R_AF1:
 615             s->maddr[s->fmi & 3][addr & 1] = value;
 616             break;
 617
 618         case R_IS:
 619             s->regs[addr] &= ~value;
 620             break;
 621
 622         case 0x8000 ... 0x83ff:
 623             s->ext_mtable[addr - 0x8000] = value;
 624             break;
 625
 626         default:
 627             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 628                            __func__, addr * 4, (unsigned)value));
 629             if (addr < ARRAY_SIZE(s->regs)) {
 630                 s->regs[addr] = value;
 631             }
 632             break;
 633     }
 634     enet_update_irq(s);
 635 }
 636
 637 static const MemoryRegionOps enet_ops = {
 638     .read = enet_read,
 639     .write = enet_write,
 640     .endianness = DEVICE_LITTLE_ENDIAN,
 641 };
 642
 643 static int eth_can_rx(NetClientState *nc)
 644 {
 645     XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
 646
 647     /* RX enabled?  */
 648     return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
 649 }
 650
 651 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
 652 {
 653     int match = 1;
 654
 655     if (memcmp(buf, &f0, 4)) {
 656         match = 0;
 657     }
 658
 659     if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
 660         match = 0;
 661     }
 662
 663     return match;
 664 }
 665
 666 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 667 {
 668     XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
 669     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
 670                                               0xff, 0xff, 0xff};
 671     static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
 672     uint32_t app[6] = {0};
 673     int promisc = s->fmi & (1 << 31);
 674     int unicast, broadcast, multicast, ip_multicast = 0;
 675     uint32_t csum32;
 676     uint16_t csum16;
 677     int i;
 678
 679     DENET(qemu_log("%s: %zd bytes\n", __func__, size));
 680
 681     unicast = ~buf[0] & 0x1;
 682     broadcast = memcmp(buf, sa_bcast, 6) == 0;
 683     multicast = !unicast && !broadcast;
 684     if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
 685         ip_multicast = 1;
 686     }
 687
 688     /* Jumbo or vlan sizes ?  */
 689     if (!(s->rcw[1] & RCW1_JUM)) {
 690         if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
 691             return size;
 692         }
 693     }
 694
 695     /* Basic Address filters.  If you want to use the extended filters
 696        you'll generally have to place the ethernet mac into promiscuous mode
 697        to avoid the basic filtering from dropping most frames.  */
 698     if (!promisc) {
 699         if (unicast) {
 700             if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
 701                 return size;
 702             }
 703         } else {
 704             if (broadcast) {
 705                 /* Broadcast.  */
 706                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 707                     return size;
 708                 }
 709             } else {
 710                 int drop = 1;
 711
 712                 /* Multicast.  */
 713                 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
 714                     return size;
 715                 }
 716
 717                 for (i = 0; i < 4; i++) {
 718                     if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
 719                         drop = 0;
 720                         break;
 721                     }
 722                 }
 723
 724                 if (drop) {
 725                     return size;
 726                 }
 727             }
 728         }
 729     }
 730
 731     /* Extended mcast filtering enabled?  */
 732     if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
 733         if (unicast) {
 734             if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
 735                 return size;
 736             }
 737         } else {
 738             if (broadcast) {
 739                 /* Broadcast. ???  */
 740                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 741                     return size;
 742                 }
 743             } else {
 744                 int idx, bit;
 745
 746                 /* Multicast.  */
 747                 if (!memcmp(buf, sa_ipmcast, 3)) {
 748                     return size;
 749                 }
 750
 751                 idx  = (buf[4] & 0x7f) << 8;
 752                 idx |= buf[5];
 753
 754                 bit = 1 << (idx & 0x1f);
 755                 idx >>= 5;
 756
 757                 if (!(s->ext_mtable[idx] & bit)) {
 758                     return size;
 759                 }
 760             }
 761         }
 762     }
 763
 764     if (size < 12) {
 765         s->regs[R_IS] |= IS_RX_REJECT;
 766         enet_update_irq(s);
 767         return -1;
 768     }
 769
 770     if (size > (s->c_rxmem - 4)) {
 771         size = s->c_rxmem - 4;
 772     }
 773
 774     memcpy(s->rxmem, buf, size);
 775     memset(s->rxmem + size, 0, 4); /* Clear the FCS.  */
 776
 777     if (s->rcw[1] & RCW1_FCS) {
 778         size += 4; /* fcs is inband.  */
 779     }
 780
 781     app[0] = 5 << 28;
 782     csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
 783     /* Fold it once.  */
 784     csum32 = (csum32 & 0xffff) + (csum32 >> 16);
 785     /* And twice to get rid of possible carries.  */
 786     csum16 = (csum32 & 0xffff) + (csum32 >> 16);
 787     app[3] = csum16;
 788     app[4] = size & 0xffff;
 789
 790     s->stats.rx_bytes += size;
 791     s->stats.rx++;
 792     if (multicast) {
 793         s->stats.rx_mcast++;
 794         app[2] |= 1 | (ip_multicast << 1);
 795     } else if (broadcast) {
 796         s->stats.rx_bcast++;
 797         app[2] |= 1 << 3;
 798     }
 799
 800     /* Good frame.  */
 801     app[2] |= 1 << 6;
 802
 803     stream_push(s->tx_dev, (void *)s->rxmem, size, app);
 804
 805     s->regs[R_IS] |= IS_RX_COMPLETE;
 806     enet_update_irq(s);
 807     return size;
 808 }
 809
 810 static void eth_cleanup(NetClientState *nc)
 811 {
 812     /* FIXME.  */
 813     XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
 814     g_free(s->rxmem);
 815     g_free(s);
 816 }
 817
 818 static void
 819 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
 820                                 uint32_t *hdr)
 821 {
 822     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
 823     XilinxAXIEnet *s = ds->enet;
 824
 825     /* TX enable ?  */
 826     if (!(s->tc & TC_TX)) {
 827         return;
 828     }
 829
 830     /* Jumbo or vlan sizes ?  */
 831     if (!(s->tc & TC_JUM)) {
 832         if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
 833             return;
 834         }
 835     }
 836
 837     if (hdr[0] & 1) {
 838         unsigned int start_off = hdr[1] >> 16;
 839         unsigned int write_off = hdr[1] & 0xffff;
 840         uint32_t tmp_csum;
 841         uint16_t csum;
 842
 843         tmp_csum = net_checksum_add(size - start_off,
 844                                     (uint8_t *)buf + start_off);
 845         /* Accumulate the seed.  */
 846         tmp_csum += hdr[2] & 0xffff;
 847
 848         /* Fold the 32bit partial checksum.  */
 849         csum = net_checksum_finish(tmp_csum);
 850
 851         /* Writeback.  */
 852         buf[write_off] = csum >> 8;
 853         buf[write_off + 1] = csum & 0xff;
 854     }
 855
 856     qemu_send_packet(qemu_get_queue(s->nic), buf, size);
 857
 858     s->stats.tx_bytes += size;
 859     s->regs[R_IS] |= IS_TX_COMPLETE;
 860     enet_update_irq(s);
 861 }
 862
 863 static NetClientInfo net_xilinx_enet_info = {
 864     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 865     .size = sizeof(NICState),
 866     .can_receive = eth_can_rx,
 867     .receive = eth_rx,
 868     .cleanup = eth_cleanup,
 869 };
 870
 871 static void xilinx_enet_realize(DeviceState *dev, Error **errp)
 872 {
 873     XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
 874     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
 875     Error *local_errp = NULL;
 876
 877     object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
 878                              (Object **) &ds->enet, &local_errp);
 879     if (local_errp) {
 880         goto xilinx_enet_realize_fail;
 881     }
 882     object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_errp);
 883     if (local_errp) {
 884         goto xilinx_enet_realize_fail;
 885     }
 886
 887     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 888     s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
 889                           object_get_typename(OBJECT(dev)), dev->id, s);
 890     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 891
 892     tdk_init(&s->TEMAC.phy);
 893     mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
 894
 895     s->TEMAC.parent = s;
 896
 897     s->rxmem = g_malloc(s->c_rxmem);
 898     return;
 899
 900 xilinx_enet_realize_fail:
 901     if (!*errp) {
 902         *errp = local_errp;
 903     }
 904 }
 905
 906 static void xilinx_enet_init(Object *obj)
 907 {
 908     XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
 909     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 910     Error *errp = NULL;
 911
 912     object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
 913                              (Object **) &s->tx_dev, &errp);
 914     assert_no_error(errp);
 915
 916     object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM);
 917     object_property_add_child(OBJECT(s), "axistream-connected-target",
 918                               (Object *)&s->rx_data_dev, &errp);
 919     assert_no_error(errp);
 920
 921     sysbus_init_irq(sbd, &s->irq);
 922
 923     memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
 924     sysbus_init_mmio(sbd, &s->iomem);
 925 }
 926
 927 static Property xilinx_enet_properties[] = {
 928     DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
 929     DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
 930     DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
 931     DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
 932     DEFINE_PROP_END_OF_LIST(),
 933 };
 934
 935 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
 936 {
 937     DeviceClass *dc = DEVICE_CLASS(klass);
 938
 939     dc->realize = xilinx_enet_realize;
 940     dc->props = xilinx_enet_properties;
 941     dc->reset = xilinx_axienet_reset;
 942 }
 943
 944 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data)
 945 {
 946     StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
 947
 948     ssc->push = data;
 949 }
 950
 951 static const TypeInfo xilinx_enet_info = {
 952     .name          = TYPE_XILINX_AXI_ENET,
 953     .parent        = TYPE_SYS_BUS_DEVICE,
 954     .instance_size = sizeof(XilinxAXIEnet),
 955     .class_init    = xilinx_enet_class_init,
 956     .instance_init = xilinx_enet_init,
 957 };
 958
 959 static const TypeInfo xilinx_enet_data_stream_info = {
 960     .name          = TYPE_XILINX_AXI_ENET_DATA_STREAM,
 961     .parent        = TYPE_OBJECT,
 962     .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
 963     .class_init    = xilinx_enet_stream_class_init,
 964     .class_data    = xilinx_axienet_data_stream_push,
 965     .interfaces = (InterfaceInfo[]) {
 966             { TYPE_STREAM_SLAVE },
 967             { }
 968     }
 969 };
 970
 971 static void xilinx_enet_register_types(void)
 972 {
 973     type_register_static(&xilinx_enet_info);
 974     type_register_static(&xilinx_enet_data_stream_info);
 975 }
 976
 977 type_init(xilinx_enet_register_types)