4 * Copyright (c) 2009 Red Hat
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
13 #include "exec/memory.h"
14 #include "exec/address-spaces.h"
16 #include "block/block.h"
17 #include "block/accounting.h"
18 #include "sysemu/kvm.h"
20 typedef struct ScatterGatherEntry ScatterGatherEntry
;
23 DMA_DIRECTION_TO_DEVICE
= 0,
24 DMA_DIRECTION_FROM_DEVICE
= 1,
28 ScatterGatherEntry
*sg
;
36 #ifndef CONFIG_USER_ONLY
39 * When an IOMMU is present, bus addresses become distinct from
40 * CPU/memory physical addresses and may be a different size. Because
41 * the IOVA size depends more on the bus than on the platform, we more
42 * or less have to treat these as 64-bit always to cover all (or at
45 typedef uint64_t dma_addr_t
;
47 #define DMA_ADDR_BITS 64
48 #define DMA_ADDR_FMT "%" PRIx64
50 static inline void dma_barrier(AddressSpace
*as
, DMADirection dir
)
53 * This is called before DMA read and write operations
54 * unless the _relaxed form is used and is responsible
55 * for providing some sane ordering of accesses vs
56 * concurrently running VCPUs.
58 * Users of map(), unmap() or lower level st/ld_*
59 * operations are responsible for providing their own
60 * ordering via barriers.
62 * This primitive implementation does a simple smp_mb()
63 * before each operation which provides pretty much full
66 * A smarter implementation can be devised if needed to
67 * use lighter barriers based on the direction of the
68 * transfer, the DMA context, etc...
75 /* Checks that the given range of addresses is valid for DMA. This is
76 * useful for certain cases, but usually you should just use
77 * dma_memory_{read,write}() and check for errors */
78 static inline bool dma_memory_valid(AddressSpace
*as
,
79 dma_addr_t addr
, dma_addr_t len
,
82 return address_space_access_valid(as
, addr
, len
,
83 dir
== DMA_DIRECTION_FROM_DEVICE
);
86 static inline int dma_memory_rw_relaxed(AddressSpace
*as
, dma_addr_t addr
,
87 void *buf
, dma_addr_t len
,
90 return (bool)address_space_rw(as
, addr
, MEMTXATTRS_UNSPECIFIED
,
91 buf
, len
, dir
== DMA_DIRECTION_FROM_DEVICE
);
94 static inline int dma_memory_read_relaxed(AddressSpace
*as
, dma_addr_t addr
,
95 void *buf
, dma_addr_t len
)
97 return dma_memory_rw_relaxed(as
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
100 static inline int dma_memory_write_relaxed(AddressSpace
*as
, dma_addr_t addr
,
101 const void *buf
, dma_addr_t len
)
103 return dma_memory_rw_relaxed(as
, addr
, (void *)buf
, len
,
104 DMA_DIRECTION_FROM_DEVICE
);
107 static inline int dma_memory_rw(AddressSpace
*as
, dma_addr_t addr
,
108 void *buf
, dma_addr_t len
,
111 dma_barrier(as
, dir
);
113 return dma_memory_rw_relaxed(as
, addr
, buf
, len
, dir
);
116 static inline int dma_memory_read(AddressSpace
*as
, dma_addr_t addr
,
117 void *buf
, dma_addr_t len
)
119 return dma_memory_rw(as
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
122 static inline int dma_memory_write(AddressSpace
*as
, dma_addr_t addr
,
123 const void *buf
, dma_addr_t len
)
125 return dma_memory_rw(as
, addr
, (void *)buf
, len
,
126 DMA_DIRECTION_FROM_DEVICE
);
129 int dma_memory_set(AddressSpace
*as
, dma_addr_t addr
, uint8_t c
, dma_addr_t len
);
131 static inline void *dma_memory_map(AddressSpace
*as
,
132 dma_addr_t addr
, dma_addr_t
*len
,
138 p
= address_space_map(as
, addr
, &xlen
, dir
== DMA_DIRECTION_FROM_DEVICE
);
143 static inline void dma_memory_unmap(AddressSpace
*as
,
144 void *buffer
, dma_addr_t len
,
145 DMADirection dir
, dma_addr_t access_len
)
147 address_space_unmap(as
, buffer
, (hwaddr
)len
,
148 dir
== DMA_DIRECTION_FROM_DEVICE
, access_len
);
151 #define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
152 static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \
155 uint##_bits##_t val; \
156 dma_memory_read(as, addr, &val, (_bits) / 8); \
157 return _end##_bits##_to_cpu(val); \
159 static inline void st##_sname##_##_end##_dma(AddressSpace *as, \
161 uint##_bits##_t val) \
163 val = cpu_to_##_end##_bits(val); \
164 dma_memory_write(as, addr, &val, (_bits) / 8); \
167 static inline uint8_t ldub_dma(AddressSpace
*as
, dma_addr_t addr
)
171 dma_memory_read(as
, addr
, &val
, 1);
175 static inline void stb_dma(AddressSpace
*as
, dma_addr_t addr
, uint8_t val
)
177 dma_memory_write(as
, addr
, &val
, 1);
180 DEFINE_LDST_DMA(uw
, w
, 16, le
);
181 DEFINE_LDST_DMA(l
, l
, 32, le
);
182 DEFINE_LDST_DMA(q
, q
, 64, le
);
183 DEFINE_LDST_DMA(uw
, w
, 16, be
);
184 DEFINE_LDST_DMA(l
, l
, 32, be
);
185 DEFINE_LDST_DMA(q
, q
, 64, be
);
187 #undef DEFINE_LDST_DMA
189 struct ScatterGatherEntry
{
194 void qemu_sglist_init(QEMUSGList
*qsg
, DeviceState
*dev
, int alloc_hint
,
196 void qemu_sglist_add(QEMUSGList
*qsg
, dma_addr_t base
, dma_addr_t len
);
197 void qemu_sglist_destroy(QEMUSGList
*qsg
);
200 typedef BlockAIOCB
*DMAIOFunc(BlockBackend
*blk
, int64_t offset
,
201 QEMUIOVector
*iov
, BdrvRequestFlags flags
,
202 BlockCompletionFunc
*cb
, void *opaque
);
204 BlockAIOCB
*dma_blk_io(BlockBackend
*blk
,
205 QEMUSGList
*sg
, uint64_t sector_num
,
206 DMAIOFunc
*io_func
, BlockCompletionFunc
*cb
,
207 void *opaque
, DMADirection dir
);
208 BlockAIOCB
*dma_blk_read(BlockBackend
*blk
,
209 QEMUSGList
*sg
, uint64_t sector
,
210 BlockCompletionFunc
*cb
, void *opaque
);
211 BlockAIOCB
*dma_blk_write(BlockBackend
*blk
,
212 QEMUSGList
*sg
, uint64_t sector
,
213 BlockCompletionFunc
*cb
, void *opaque
);
214 uint64_t dma_buf_read(uint8_t *ptr
, int32_t len
, QEMUSGList
*sg
);
215 uint64_t dma_buf_write(uint8_t *ptr
, int32_t len
, QEMUSGList
*sg
);
217 void dma_acct_start(BlockBackend
*blk
, BlockAcctCookie
*cookie
,
218 QEMUSGList
*sg
, enum BlockAcctType type
);