hw/ide/via.c

   1 /*
   2  * QEMU IDE Emulation: PCI VIA82C686B support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/isa/isa.h"
  30 #include "sysemu/block-backend.h"
  31 #include "sysemu/sysemu.h"
  32 #include "sysemu/dma.h"
  33
  34 #include "hw/ide/pci.h"
  35 #include "trace.h"
  36
  37 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  38                            unsigned size)
  39 {
  40     BMDMAState *bm = opaque;
  41     uint32_t val;
  42
  43     if (size != 1) {
  44         return ((uint64_t)1 << (size * 8)) - 1;
  45     }
  46
  47     switch (addr & 3) {
  48     case 0:
  49         val = bm->cmd;
  50         break;
  51     case 2:
  52         val = bm->status;
  53         break;
  54     default:
  55         val = 0xff;
  56         break;
  57     }
  58
  59     trace_bmdma_read_via(addr, val);
  60     return val;
  61 }
  62
  63 static void bmdma_write(void *opaque, hwaddr addr,
  64                         uint64_t val, unsigned size)
  65 {
  66     BMDMAState *bm = opaque;
  67
  68     if (size != 1) {
  69         return;
  70     }
  71
  72     trace_bmdma_write_via(addr, val);
  73     switch (addr & 3) {
  74     case 0:
  75         bmdma_cmd_writeb(bm, val);
  76         break;
  77     case 2:
  78         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  79         break;
  80     default:;
  81     }
  82 }
  83
  84 static const MemoryRegionOps via_bmdma_ops = {
  85     .read = bmdma_read,
  86     .write = bmdma_write,
  87 };
  88
  89 static void bmdma_setup_bar(PCIIDEState *d)
  90 {
  91     int i;
  92
  93     memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
  94     for(i = 0;i < 2; i++) {
  95         BMDMAState *bm = &d->bmdma[i];
  96
  97         memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
  98                               "via-bmdma", 4);
  99         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 100         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 101                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 102         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 103     }
 104 }
 105
 106 static void via_reset(void *opaque)
 107 {
 108     PCIIDEState *d = opaque;
 109     PCIDevice *pd = PCI_DEVICE(d);
 110     uint8_t *pci_conf = pd->config;
 111     int i;
 112
 113     for (i = 0; i < 2; i++) {
 114         ide_bus_reset(&d->bus[i]);
 115     }
 116
 117     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
 118     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 119                  PCI_STATUS_DEVSEL_MEDIUM);
 120
 121     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
 122     pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
 123     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
 124     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
 125     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
 126     pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
 127
 128     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
 129     pci_set_long(pci_conf + 0x40, 0x0a090600);
 130     /* IDE misc configuration 1/2/3 */
 131     pci_set_long(pci_conf + 0x44, 0x00c00068);
 132     /* IDE Timing control */
 133     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
 134     /* IDE Address Setup Time */
 135     pci_set_long(pci_conf + 0x4c, 0x000000ff);
 136     /* UltraDMA Extended Timing Control*/
 137     pci_set_long(pci_conf + 0x50, 0x07070707);
 138     /* UltraDMA FIFO Control */
 139     pci_set_long(pci_conf + 0x54, 0x00000004);
 140     /* IDE primary sector size */
 141     pci_set_long(pci_conf + 0x60, 0x00000200);
 142     /* IDE secondary sector size */
 143     pci_set_long(pci_conf + 0x68, 0x00000200);
 144     /* PCI PM Block */
 145     pci_set_long(pci_conf + 0xc0, 0x00020001);
 146 }
 147
 148 static void vt82c686b_init_ports(PCIIDEState *d) {
 149     static const struct {
 150         int iobase;
 151         int iobase2;
 152         int isairq;
 153     } port_info[] = {
 154         {0x1f0, 0x3f6, 14},
 155         {0x170, 0x376, 15},
 156     };
 157     int i;
 158
 159     for (i = 0; i < 2; i++) {
 160         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 161         ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
 162                         port_info[i].iobase2);
 163         ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
 164
 165         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 166         d->bmdma[i].bus = &d->bus[i];
 167         ide_register_restart_cb(&d->bus[i]);
 168     }
 169 }
 170
 171 /* via ide func */
 172 static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp)
 173 {
 174     PCIIDEState *d = PCI_IDE(dev);
 175     uint8_t *pci_conf = dev->config;
 176
 177     pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
 178     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 179
 180     qemu_register_reset(via_reset, d);
 181     bmdma_setup_bar(d);
 182     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 183
 184     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 185
 186     vt82c686b_init_ports(d);
 187 }
 188
 189 static void vt82c686b_ide_exitfn(PCIDevice *dev)
 190 {
 191     PCIIDEState *d = PCI_IDE(dev);
 192     unsigned i;
 193
 194     for (i = 0; i < 2; ++i) {
 195         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 196         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 197     }
 198 }
 199
 200 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 201 {
 202     PCIDevice *dev;
 203
 204     dev = pci_create_simple(bus, devfn, "via-ide");
 205     pci_ide_create_devs(dev, hd_table);
 206 }
 207
 208 static void via_ide_class_init(ObjectClass *klass, void *data)
 209 {
 210     DeviceClass *dc = DEVICE_CLASS(klass);
 211     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 212
 213     k->realize = vt82c686b_ide_realize;
 214     k->exit = vt82c686b_ide_exitfn;
 215     k->vendor_id = PCI_VENDOR_ID_VIA;
 216     k->device_id = PCI_DEVICE_ID_VIA_IDE;
 217     k->revision = 0x06;
 218     k->class_id = PCI_CLASS_STORAGE_IDE;
 219     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 220 }
 221
 222 static const TypeInfo via_ide_info = {
 223     .name          = "via-ide",
 224     .parent        = TYPE_PCI_IDE,
 225     .class_init    = via_ide_class_init,
 226 };
 227
 228 static void via_ide_register_types(void)
 229 {
 230     type_register_static(&via_ide_info);
 231 }
 232
 233 type_init(via_ide_register_types)