2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/queue.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
30 #include "qapi/error.h"
36 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
38 #define DPRINTF(...) do {} while (0)
40 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
41 __func__, __LINE__, _msg); abort(); } while (0)
46 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
50 /* Very pessimistic, let's hope it's enough for all cases */
51 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS)
53 #define TRB_LINK_LIMIT 4
54 #define COMMAND_LIMIT 256
55 #define TRANSFER_LIMIT 256
58 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
59 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
60 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
62 #define OFF_OPER LEN_CAP
63 #define OFF_RUNTIME 0x1000
64 #define OFF_DOORBELL 0x2000
65 #define OFF_MSIX_TABLE 0x3000
66 #define OFF_MSIX_PBA 0x3800
67 /* must be power of 2 */
68 #define LEN_REGS 0x4000
70 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
71 #error Increase OFF_RUNTIME
73 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
74 #error Increase OFF_DOORBELL
76 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
77 # error Increase LEN_REGS
81 #define USBCMD_RS (1<<0)
82 #define USBCMD_HCRST (1<<1)
83 #define USBCMD_INTE (1<<2)
84 #define USBCMD_HSEE (1<<3)
85 #define USBCMD_LHCRST (1<<7)
86 #define USBCMD_CSS (1<<8)
87 #define USBCMD_CRS (1<<9)
88 #define USBCMD_EWE (1<<10)
89 #define USBCMD_EU3S (1<<11)
91 #define USBSTS_HCH (1<<0)
92 #define USBSTS_HSE (1<<2)
93 #define USBSTS_EINT (1<<3)
94 #define USBSTS_PCD (1<<4)
95 #define USBSTS_SSS (1<<8)
96 #define USBSTS_RSS (1<<9)
97 #define USBSTS_SRE (1<<10)
98 #define USBSTS_CNR (1<<11)
99 #define USBSTS_HCE (1<<12)
102 #define PORTSC_CCS (1<<0)
103 #define PORTSC_PED (1<<1)
104 #define PORTSC_OCA (1<<3)
105 #define PORTSC_PR (1<<4)
106 #define PORTSC_PLS_SHIFT 5
107 #define PORTSC_PLS_MASK 0xf
108 #define PORTSC_PP (1<<9)
109 #define PORTSC_SPEED_SHIFT 10
110 #define PORTSC_SPEED_MASK 0xf
111 #define PORTSC_SPEED_FULL (1<<10)
112 #define PORTSC_SPEED_LOW (2<<10)
113 #define PORTSC_SPEED_HIGH (3<<10)
114 #define PORTSC_SPEED_SUPER (4<<10)
115 #define PORTSC_PIC_SHIFT 14
116 #define PORTSC_PIC_MASK 0x3
117 #define PORTSC_LWS (1<<16)
118 #define PORTSC_CSC (1<<17)
119 #define PORTSC_PEC (1<<18)
120 #define PORTSC_WRC (1<<19)
121 #define PORTSC_OCC (1<<20)
122 #define PORTSC_PRC (1<<21)
123 #define PORTSC_PLC (1<<22)
124 #define PORTSC_CEC (1<<23)
125 #define PORTSC_CAS (1<<24)
126 #define PORTSC_WCE (1<<25)
127 #define PORTSC_WDE (1<<26)
128 #define PORTSC_WOE (1<<27)
129 #define PORTSC_DR (1<<30)
130 #define PORTSC_WPR (1<<31)
132 #define CRCR_RCS (1<<0)
133 #define CRCR_CS (1<<1)
134 #define CRCR_CA (1<<2)
135 #define CRCR_CRR (1<<3)
137 #define IMAN_IP (1<<0)
138 #define IMAN_IE (1<<1)
140 #define ERDP_EHB (1<<3)
143 typedef struct XHCITRB
{
162 PLS_COMPILANCE_MODE
= 10,
167 typedef enum TRBType
{
180 CR_CONFIGURE_ENDPOINT
,
188 CR_SET_LATENCY_TOLERANCE
,
189 CR_GET_PORT_BANDWIDTH
,
194 ER_PORT_STATUS_CHANGE
,
195 ER_BANDWIDTH_REQUEST
,
198 ER_DEVICE_NOTIFICATION
,
200 /* vendor specific bits */
201 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
202 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
205 #define CR_LINK TR_LINK
207 typedef enum TRBCCode
{
210 CC_DATA_BUFFER_ERROR
,
212 CC_USB_TRANSACTION_ERROR
,
218 CC_INVALID_STREAM_TYPE_ERROR
,
219 CC_SLOT_NOT_ENABLED_ERROR
,
220 CC_EP_NOT_ENABLED_ERROR
,
226 CC_BANDWIDTH_OVERRUN
,
227 CC_CONTEXT_STATE_ERROR
,
228 CC_NO_PING_RESPONSE_ERROR
,
229 CC_EVENT_RING_FULL_ERROR
,
230 CC_INCOMPATIBLE_DEVICE_ERROR
,
231 CC_MISSED_SERVICE_ERROR
,
232 CC_COMMAND_RING_STOPPED
,
235 CC_STOPPED_LENGTH_INVALID
,
236 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
237 CC_ISOCH_BUFFER_OVERRUN
= 31,
240 CC_INVALID_STREAM_ID_ERROR
,
241 CC_SECONDARY_BANDWIDTH_ERROR
,
242 CC_SPLIT_TRANSACTION_ERROR
246 #define TRB_TYPE_SHIFT 10
247 #define TRB_TYPE_MASK 0x3f
248 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
250 #define TRB_EV_ED (1<<2)
252 #define TRB_TR_ENT (1<<1)
253 #define TRB_TR_ISP (1<<2)
254 #define TRB_TR_NS (1<<3)
255 #define TRB_TR_CH (1<<4)
256 #define TRB_TR_IOC (1<<5)
257 #define TRB_TR_IDT (1<<6)
258 #define TRB_TR_TBC_SHIFT 7
259 #define TRB_TR_TBC_MASK 0x3
260 #define TRB_TR_BEI (1<<9)
261 #define TRB_TR_TLBPC_SHIFT 16
262 #define TRB_TR_TLBPC_MASK 0xf
263 #define TRB_TR_FRAMEID_SHIFT 20
264 #define TRB_TR_FRAMEID_MASK 0x7ff
265 #define TRB_TR_SIA (1<<31)
267 #define TRB_TR_DIR (1<<16)
269 #define TRB_CR_SLOTID_SHIFT 24
270 #define TRB_CR_SLOTID_MASK 0xff
271 #define TRB_CR_EPID_SHIFT 16
272 #define TRB_CR_EPID_MASK 0x1f
274 #define TRB_CR_BSR (1<<9)
275 #define TRB_CR_DC (1<<9)
277 #define TRB_LK_TC (1<<1)
279 #define TRB_INTR_SHIFT 22
280 #define TRB_INTR_MASK 0x3ff
281 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
283 #define EP_TYPE_MASK 0x7
284 #define EP_TYPE_SHIFT 3
286 #define EP_STATE_MASK 0x7
287 #define EP_DISABLED (0<<0)
288 #define EP_RUNNING (1<<0)
289 #define EP_HALTED (2<<0)
290 #define EP_STOPPED (3<<0)
291 #define EP_ERROR (4<<0)
293 #define SLOT_STATE_MASK 0x1f
294 #define SLOT_STATE_SHIFT 27
295 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
296 #define SLOT_ENABLED 0
297 #define SLOT_DEFAULT 1
298 #define SLOT_ADDRESSED 2
299 #define SLOT_CONFIGURED 3
301 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
302 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
304 typedef struct XHCIState XHCIState
;
305 typedef struct XHCIStreamContext XHCIStreamContext
;
306 typedef struct XHCIEPContext XHCIEPContext
;
308 #define get_field(data, field) \
309 (((data) >> field##_SHIFT) & field##_MASK)
311 #define set_field(data, newval, field) do { \
312 uint32_t val = *data; \
313 val &= ~(field##_MASK << field##_SHIFT); \
314 val |= ((newval) & field##_MASK) << field##_SHIFT; \
318 typedef enum EPType
{
329 typedef struct XHCIRing
{
334 typedef struct XHCIPort
{
344 typedef struct XHCITransfer
{
345 XHCIEPContext
*epctx
;
352 unsigned int iso_pkts
;
353 unsigned int streamid
;
358 unsigned int trb_count
;
364 unsigned int pktsize
;
365 unsigned int cur_pkt
;
367 uint64_t mfindex_kick
;
369 QTAILQ_ENTRY(XHCITransfer
) next
;
372 struct XHCIStreamContext
{
378 struct XHCIEPContext
{
385 QTAILQ_HEAD(, XHCITransfer
) transfers
;
389 unsigned int max_psize
;
391 uint32_t kick_active
;
394 unsigned int max_pstreams
;
396 unsigned int nr_pstreams
;
397 XHCIStreamContext
*pstreams
;
399 /* iso xfer scheduling */
400 unsigned int interval
;
401 int64_t mfindex_last
;
402 QEMUTimer
*kick_timer
;
405 typedef struct XHCISlot
{
410 XHCIEPContext
* eps
[31];
413 typedef struct XHCIEvent
{
423 typedef struct XHCIInterrupter
{
428 uint32_t erstba_high
;
432 bool msix_used
, er_pcs
;
436 unsigned int er_ep_idx
;
438 /* kept for live migration compat only */
440 XHCIEvent ev_buffer
[EV_QUEUE
];
441 unsigned int ev_buffer_put
;
442 unsigned int ev_buffer_get
;
448 PCIDevice parent_obj
;
453 MemoryRegion mem_cap
;
454 MemoryRegion mem_oper
;
455 MemoryRegion mem_runtime
;
456 MemoryRegion mem_doorbell
;
464 uint32_t max_pstreams_mask
;
468 /* Operational Registers */
475 uint32_t dcbaap_high
;
478 USBPort uports
[MAX(MAXPORTS_2
, MAXPORTS_3
)];
479 XHCIPort ports
[MAXPORTS
];
480 XHCISlot slots
[MAXSLOTS
];
483 /* Runtime Registers */
484 int64_t mfindex_start
;
485 QEMUTimer
*mfwrap_timer
;
486 XHCIInterrupter intr
[MAXINTRS
];
493 #define TYPE_XHCI "base-xhci"
494 #define TYPE_NEC_XHCI "nec-usb-xhci"
495 #define TYPE_QEMU_XHCI "qemu-xhci"
498 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
500 typedef struct XHCIEvRingSeg
{
508 XHCI_FLAG_SS_FIRST
= 1,
509 XHCI_FLAG_FORCE_PCIE_ENDCAP
,
510 XHCI_FLAG_ENABLE_STREAMS
,
513 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
514 unsigned int epid
, unsigned int streamid
);
515 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
);
516 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
518 static void xhci_xfer_report(XHCITransfer
*xfer
);
519 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
520 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
521 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
);
523 static const char *TRBType_names
[] = {
524 [TRB_RESERVED
] = "TRB_RESERVED",
525 [TR_NORMAL
] = "TR_NORMAL",
526 [TR_SETUP
] = "TR_SETUP",
527 [TR_DATA
] = "TR_DATA",
528 [TR_STATUS
] = "TR_STATUS",
529 [TR_ISOCH
] = "TR_ISOCH",
530 [TR_LINK
] = "TR_LINK",
531 [TR_EVDATA
] = "TR_EVDATA",
532 [TR_NOOP
] = "TR_NOOP",
533 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
534 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
535 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
536 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
537 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
538 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
539 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
540 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
541 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
542 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
543 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
544 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
545 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
546 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
547 [CR_NOOP
] = "CR_NOOP",
548 [ER_TRANSFER
] = "ER_TRANSFER",
549 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
550 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
551 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
552 [ER_DOORBELL
] = "ER_DOORBELL",
553 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
554 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
555 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
556 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
557 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
560 static const char *TRBCCode_names
[] = {
561 [CC_INVALID
] = "CC_INVALID",
562 [CC_SUCCESS
] = "CC_SUCCESS",
563 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
564 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
565 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
566 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
567 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
568 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
569 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
570 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
571 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
572 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
573 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
574 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
575 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
576 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
577 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
578 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
579 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
580 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
581 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
582 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
583 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
584 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
585 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
586 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
587 [CC_STOPPED
] = "CC_STOPPED",
588 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
589 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
590 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
591 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
592 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
593 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
594 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
595 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
596 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
599 static const char *ep_state_names
[] = {
600 [EP_DISABLED
] = "disabled",
601 [EP_RUNNING
] = "running",
602 [EP_HALTED
] = "halted",
603 [EP_STOPPED
] = "stopped",
604 [EP_ERROR
] = "error",
607 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
609 if (index
>= llen
|| list
[index
] == NULL
) {
615 static const char *trb_name(XHCITRB
*trb
)
617 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
618 ARRAY_SIZE(TRBType_names
));
621 static const char *event_name(XHCIEvent
*event
)
623 return lookup_name(event
->ccode
, TRBCCode_names
,
624 ARRAY_SIZE(TRBCCode_names
));
627 static const char *ep_state_name(uint32_t state
)
629 return lookup_name(state
, ep_state_names
,
630 ARRAY_SIZE(ep_state_names
));
633 static bool xhci_get_flag(XHCIState
*xhci
, enum xhci_flags bit
)
635 return xhci
->flags
& (1 << bit
);
638 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
640 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
641 return (now
- xhci
->mfindex_start
) / 125000;
644 static void xhci_mfwrap_update(XHCIState
*xhci
)
646 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
647 uint32_t mfindex
, left
;
650 if ((xhci
->usbcmd
& bits
) == bits
) {
651 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
652 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
653 left
= 0x4000 - mfindex
;
654 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
656 timer_del(xhci
->mfwrap_timer
);
660 static void xhci_mfwrap_timer(void *opaque
)
662 XHCIState
*xhci
= opaque
;
663 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
665 xhci_event(xhci
, &wrap
, 0);
666 xhci_mfwrap_update(xhci
);
669 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
671 if (sizeof(dma_addr_t
) == 4) {
674 return low
| (((dma_addr_t
)high
<< 16) << 16);
678 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
680 if (sizeof(dma_addr_t
) == 4) {
681 return addr
& 0xffffffff;
687 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
688 uint32_t *buf
, size_t len
)
692 assert((len
% sizeof(uint32_t)) == 0);
694 pci_dma_read(PCI_DEVICE(xhci
), addr
, buf
, len
);
696 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
697 buf
[i
] = le32_to_cpu(buf
[i
]);
701 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
702 uint32_t *buf
, size_t len
)
706 uint32_t n
= len
/ sizeof(uint32_t);
708 assert((len
% sizeof(uint32_t)) == 0);
709 assert(n
<= ARRAY_SIZE(tmp
));
711 for (i
= 0; i
< n
; i
++) {
712 tmp
[i
] = cpu_to_le32(buf
[i
]);
714 pci_dma_write(PCI_DEVICE(xhci
), addr
, tmp
, len
);
717 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
724 switch (uport
->dev
->speed
) {
728 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
729 index
= uport
->index
+ xhci
->numports_3
;
731 index
= uport
->index
;
734 case USB_SPEED_SUPER
:
735 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
736 index
= uport
->index
;
738 index
= uport
->index
+ xhci
->numports_2
;
744 return &xhci
->ports
[index
];
747 static void xhci_intx_update(XHCIState
*xhci
)
749 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
752 if (msix_enabled(pci_dev
) ||
753 msi_enabled(pci_dev
)) {
757 if (xhci
->intr
[0].iman
& IMAN_IP
&&
758 xhci
->intr
[0].iman
& IMAN_IE
&&
759 xhci
->usbcmd
& USBCMD_INTE
) {
763 trace_usb_xhci_irq_intx(level
);
764 pci_set_irq(pci_dev
, level
);
767 static void xhci_msix_update(XHCIState
*xhci
, int v
)
769 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
772 if (!msix_enabled(pci_dev
)) {
776 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
777 if (enabled
== xhci
->intr
[v
].msix_used
) {
782 trace_usb_xhci_irq_msix_use(v
);
783 msix_vector_use(pci_dev
, v
);
784 xhci
->intr
[v
].msix_used
= true;
786 trace_usb_xhci_irq_msix_unuse(v
);
787 msix_vector_unuse(pci_dev
, v
);
788 xhci
->intr
[v
].msix_used
= false;
792 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
794 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
795 bool pending
= (xhci
->intr
[v
].erdp_low
& ERDP_EHB
);
797 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
798 xhci
->intr
[v
].iman
|= IMAN_IP
;
799 xhci
->usbsts
|= USBSTS_EINT
;
804 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
808 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
812 if (msix_enabled(pci_dev
)) {
813 trace_usb_xhci_irq_msix(v
);
814 msix_notify(pci_dev
, v
);
818 if (msi_enabled(pci_dev
)) {
819 trace_usb_xhci_irq_msi(v
);
820 msi_notify(pci_dev
, v
);
825 trace_usb_xhci_irq_intx(1);
826 pci_irq_assert(pci_dev
);
830 static inline int xhci_running(XHCIState
*xhci
)
832 return !(xhci
->usbsts
& USBSTS_HCH
);
835 static void xhci_die(XHCIState
*xhci
)
837 xhci
->usbsts
|= USBSTS_HCE
;
838 DPRINTF("xhci: asserted controller error\n");
841 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
843 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
844 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
848 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
849 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
850 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
851 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
853 ev_trb
.control
|= TRB_C
;
855 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
857 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
858 event_name(event
), ev_trb
.parameter
,
859 ev_trb
.status
, ev_trb
.control
);
861 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
862 pci_dma_write(pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
865 if (intr
->er_ep_idx
>= intr
->er_size
) {
867 intr
->er_pcs
= !intr
->er_pcs
;
871 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
873 XHCIInterrupter
*intr
;
877 if (v
>= xhci
->numintrs
) {
878 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
881 intr
= &xhci
->intr
[v
];
883 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
884 if (erdp
< intr
->er_start
||
885 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
886 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
887 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
888 v
, intr
->er_start
, intr
->er_size
);
893 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
894 assert(dp_idx
< intr
->er_size
);
896 if ((intr
->er_ep_idx
+ 2) % intr
->er_size
== dp_idx
) {
897 DPRINTF("xhci: ER %d full, send ring full error\n", v
);
898 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
899 xhci_write_event(xhci
, &full
, v
);
900 } else if ((intr
->er_ep_idx
+ 1) % intr
->er_size
== dp_idx
) {
901 DPRINTF("xhci: ER %d full, drop event\n", v
);
903 xhci_write_event(xhci
, event
, v
);
906 xhci_intr_raise(xhci
, v
);
909 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
912 ring
->dequeue
= base
;
916 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
919 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
920 uint32_t link_cnt
= 0;
924 pci_dma_read(pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
925 trb
->addr
= ring
->dequeue
;
926 trb
->ccs
= ring
->ccs
;
927 le64_to_cpus(&trb
->parameter
);
928 le32_to_cpus(&trb
->status
);
929 le32_to_cpus(&trb
->control
);
931 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
932 trb
->parameter
, trb
->status
, trb
->control
);
934 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
938 type
= TRB_TYPE(*trb
);
940 if (type
!= TR_LINK
) {
942 *addr
= ring
->dequeue
;
944 ring
->dequeue
+= TRB_SIZE
;
947 if (++link_cnt
> TRB_LINK_LIMIT
) {
948 trace_usb_xhci_enforced_limit("trb-link");
951 ring
->dequeue
= xhci_mask64(trb
->parameter
);
952 if (trb
->control
& TRB_LK_TC
) {
953 ring
->ccs
= !ring
->ccs
;
959 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
961 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
964 dma_addr_t dequeue
= ring
->dequeue
;
965 bool ccs
= ring
->ccs
;
966 /* hack to bundle together the two/three TDs that make a setup transfer */
967 bool control_td_set
= 0;
968 uint32_t link_cnt
= 0;
972 pci_dma_read(pci_dev
, dequeue
, &trb
, TRB_SIZE
);
973 le64_to_cpus(&trb
.parameter
);
974 le32_to_cpus(&trb
.status
);
975 le32_to_cpus(&trb
.control
);
977 if ((trb
.control
& TRB_C
) != ccs
) {
981 type
= TRB_TYPE(trb
);
983 if (type
== TR_LINK
) {
984 if (++link_cnt
> TRB_LINK_LIMIT
) {
987 dequeue
= xhci_mask64(trb
.parameter
);
988 if (trb
.control
& TRB_LK_TC
) {
997 if (type
== TR_SETUP
) {
999 } else if (type
== TR_STATUS
) {
1003 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
1009 static void xhci_er_reset(XHCIState
*xhci
, int v
)
1011 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
1014 if (intr
->erstsz
== 0) {
1020 /* cache the (sole) event ring segment location */
1021 if (intr
->erstsz
!= 1) {
1022 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
1026 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
1027 pci_dma_read(PCI_DEVICE(xhci
), erstba
, &seg
, sizeof(seg
));
1028 le32_to_cpus(&seg
.addr_low
);
1029 le32_to_cpus(&seg
.addr_high
);
1030 le32_to_cpus(&seg
.size
);
1031 if (seg
.size
< 16 || seg
.size
> 4096) {
1032 DPRINTF("xhci: invalid value for segment size: %d\n", seg
.size
);
1036 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
1037 intr
->er_size
= seg
.size
;
1039 intr
->er_ep_idx
= 0;
1042 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
1043 v
, intr
->er_start
, intr
->er_size
);
1046 static void xhci_run(XHCIState
*xhci
)
1048 trace_usb_xhci_run();
1049 xhci
->usbsts
&= ~USBSTS_HCH
;
1050 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1053 static void xhci_stop(XHCIState
*xhci
)
1055 trace_usb_xhci_stop();
1056 xhci
->usbsts
|= USBSTS_HCH
;
1057 xhci
->crcr_low
&= ~CRCR_CRR
;
1060 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
1063 XHCIStreamContext
*stctx
;
1066 stctx
= g_new0(XHCIStreamContext
, count
);
1067 for (i
= 0; i
< count
; i
++) {
1068 stctx
[i
].pctx
= base
+ i
* 16;
1074 static void xhci_reset_streams(XHCIEPContext
*epctx
)
1078 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
1079 epctx
->pstreams
[i
].sct
= -1;
1083 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
1085 assert(epctx
->pstreams
== NULL
);
1086 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
1087 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
1090 static void xhci_free_streams(XHCIEPContext
*epctx
)
1092 assert(epctx
->pstreams
!= NULL
);
1094 g_free(epctx
->pstreams
);
1095 epctx
->pstreams
= NULL
;
1096 epctx
->nr_pstreams
= 0;
1099 static int xhci_epmask_to_eps_with_streams(XHCIState
*xhci
,
1100 unsigned int slotid
,
1102 XHCIEPContext
**epctxs
,
1106 XHCIEPContext
*epctx
;
1110 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1112 slot
= &xhci
->slots
[slotid
- 1];
1114 for (i
= 2, j
= 0; i
<= 31; i
++) {
1115 if (!(epmask
& (1u << i
))) {
1119 epctx
= slot
->eps
[i
- 1];
1120 ep
= xhci_epid_to_usbep(epctx
);
1121 if (!epctx
|| !epctx
->nr_pstreams
|| !ep
) {
1133 static void xhci_free_device_streams(XHCIState
*xhci
, unsigned int slotid
,
1136 USBEndpoint
*eps
[30];
1139 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, NULL
, eps
);
1141 usb_device_free_streams(eps
[0]->dev
, eps
, nr_eps
);
1145 static TRBCCode
xhci_alloc_device_streams(XHCIState
*xhci
, unsigned int slotid
,
1148 XHCIEPContext
*epctxs
[30];
1149 USBEndpoint
*eps
[30];
1150 int i
, r
, nr_eps
, req_nr_streams
, dev_max_streams
;
1152 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, epctxs
,
1158 req_nr_streams
= epctxs
[0]->nr_pstreams
;
1159 dev_max_streams
= eps
[0]->max_streams
;
1161 for (i
= 1; i
< nr_eps
; i
++) {
1163 * HdG: I don't expect these to ever trigger, but if they do we need
1164 * to come up with another solution, ie group identical endpoints
1165 * together and make an usb_device_alloc_streams call per group.
1167 if (epctxs
[i
]->nr_pstreams
!= req_nr_streams
) {
1168 FIXME("guest streams config not identical for all eps");
1169 return CC_RESOURCE_ERROR
;
1171 if (eps
[i
]->max_streams
!= dev_max_streams
) {
1172 FIXME("device streams config not identical for all eps");
1173 return CC_RESOURCE_ERROR
;
1178 * max-streams in both the device descriptor and in the controller is a
1179 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1180 * streams the guest will ask for 5 rounded up to the next power of 2 which
1181 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1183 * For redirected devices however this is an issue, as there we must ask
1184 * the real xhci controller to alloc streams, and the host driver for the
1185 * real xhci controller will likely disallow allocating more streams then
1186 * the device can handle.
1188 * So we limit the requested nr_streams to the maximum number the device
1191 if (req_nr_streams
> dev_max_streams
) {
1192 req_nr_streams
= dev_max_streams
;
1195 r
= usb_device_alloc_streams(eps
[0]->dev
, eps
, nr_eps
, req_nr_streams
);
1197 DPRINTF("xhci: alloc streams failed\n");
1198 return CC_RESOURCE_ERROR
;
1204 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
1205 unsigned int streamid
,
1208 XHCIStreamContext
*sctx
;
1210 uint32_t ctx
[2], sct
;
1212 assert(streamid
!= 0);
1214 if (streamid
>= epctx
->nr_pstreams
) {
1215 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
1218 sctx
= epctx
->pstreams
+ streamid
;
1220 FIXME("secondary streams not implemented yet");
1223 if (sctx
->sct
== -1) {
1224 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
1225 sct
= (ctx
[0] >> 1) & 0x07;
1226 if (epctx
->lsa
&& sct
!= 1) {
1227 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
1231 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
1232 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
1237 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1238 XHCIStreamContext
*sctx
, uint32_t state
)
1240 XHCIRing
*ring
= NULL
;
1244 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1245 ctx
[0] &= ~EP_STATE_MASK
;
1248 /* update ring dequeue ptr */
1249 if (epctx
->nr_pstreams
) {
1252 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1254 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1255 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1256 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1259 ring
= &epctx
->ring
;
1262 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1263 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1265 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1266 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1269 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1270 if (epctx
->state
!= state
) {
1271 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1272 ep_state_name(epctx
->state
),
1273 ep_state_name(state
));
1275 epctx
->state
= state
;
1278 static void xhci_ep_kick_timer(void *opaque
)
1280 XHCIEPContext
*epctx
= opaque
;
1281 xhci_kick_epctx(epctx
, 0);
1284 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1285 unsigned int slotid
,
1288 XHCIEPContext
*epctx
;
1290 epctx
= g_new0(XHCIEPContext
, 1);
1292 epctx
->slotid
= slotid
;
1295 QTAILQ_INIT(&epctx
->transfers
);
1296 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1301 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1302 dma_addr_t pctx
, uint32_t *ctx
)
1306 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1308 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1310 epctx
->max_psize
= ctx
[1]>>16;
1311 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1312 epctx
->max_pstreams
= (ctx
[0] >> 10) & epctx
->xhci
->max_pstreams_mask
;
1313 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1314 if (epctx
->max_pstreams
) {
1315 xhci_alloc_streams(epctx
, dequeue
);
1317 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1318 epctx
->ring
.ccs
= ctx
[2] & 1;
1321 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1324 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1325 unsigned int epid
, dma_addr_t pctx
,
1329 XHCIEPContext
*epctx
;
1331 trace_usb_xhci_ep_enable(slotid
, epid
);
1332 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1333 assert(epid
>= 1 && epid
<= 31);
1335 slot
= &xhci
->slots
[slotid
-1];
1336 if (slot
->eps
[epid
-1]) {
1337 xhci_disable_ep(xhci
, slotid
, epid
);
1340 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1341 slot
->eps
[epid
-1] = epctx
;
1342 xhci_init_epctx(epctx
, pctx
, ctx
);
1344 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1345 "size is %d\n", epid
/2, epid
%2, epctx
->type
, epctx
->max_psize
);
1347 epctx
->mfindex_last
= 0;
1349 epctx
->state
= EP_RUNNING
;
1350 ctx
[0] &= ~EP_STATE_MASK
;
1351 ctx
[0] |= EP_RUNNING
;
1356 static XHCITransfer
*xhci_ep_alloc_xfer(XHCIEPContext
*epctx
,
1359 uint32_t limit
= epctx
->nr_pstreams
+ 16;
1362 if (epctx
->xfer_count
>= limit
) {
1366 xfer
= g_new0(XHCITransfer
, 1);
1367 xfer
->epctx
= epctx
;
1368 xfer
->trbs
= g_new(XHCITRB
, length
);
1369 xfer
->trb_count
= length
;
1370 usb_packet_init(&xfer
->packet
);
1372 QTAILQ_INSERT_TAIL(&epctx
->transfers
, xfer
, next
);
1373 epctx
->xfer_count
++;
1378 static void xhci_ep_free_xfer(XHCITransfer
*xfer
)
1380 QTAILQ_REMOVE(&xfer
->epctx
->transfers
, xfer
, next
);
1381 xfer
->epctx
->xfer_count
--;
1383 usb_packet_cleanup(&xfer
->packet
);
1388 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1392 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1394 xhci_xfer_report(t
);
1397 if (t
->running_async
) {
1398 usb_cancel_packet(&t
->packet
);
1399 t
->running_async
= 0;
1402 if (t
->running_retry
) {
1404 t
->epctx
->retry
= NULL
;
1405 timer_del(t
->epctx
->kick_timer
);
1407 t
->running_retry
= 0;
1418 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1419 unsigned int epid
, TRBCCode report
)
1422 XHCIEPContext
*epctx
;
1425 USBEndpoint
*ep
= NULL
;
1426 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1427 assert(epid
>= 1 && epid
<= 31);
1429 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1431 slot
= &xhci
->slots
[slotid
-1];
1433 if (!slot
->eps
[epid
-1]) {
1437 epctx
= slot
->eps
[epid
-1];
1440 xfer
= QTAILQ_FIRST(&epctx
->transfers
);
1444 killed
+= xhci_ep_nuke_one_xfer(xfer
, report
);
1446 report
= 0; /* Only report once */
1448 xhci_ep_free_xfer(xfer
);
1451 ep
= xhci_epid_to_usbep(epctx
);
1453 usb_device_ep_stopped(ep
->dev
, ep
);
1458 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1462 XHCIEPContext
*epctx
;
1464 trace_usb_xhci_ep_disable(slotid
, epid
);
1465 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1466 assert(epid
>= 1 && epid
<= 31);
1468 slot
= &xhci
->slots
[slotid
-1];
1470 if (!slot
->eps
[epid
-1]) {
1471 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1475 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1477 epctx
= slot
->eps
[epid
-1];
1479 if (epctx
->nr_pstreams
) {
1480 xhci_free_streams(epctx
);
1483 /* only touch guest RAM if we're not resetting the HC */
1484 if (xhci
->dcbaap_low
|| xhci
->dcbaap_high
) {
1485 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1488 timer_free(epctx
->kick_timer
);
1490 slot
->eps
[epid
-1] = NULL
;
1495 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1499 XHCIEPContext
*epctx
;
1501 trace_usb_xhci_ep_stop(slotid
, epid
);
1502 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1504 if (epid
< 1 || epid
> 31) {
1505 DPRINTF("xhci: bad ep %d\n", epid
);
1506 return CC_TRB_ERROR
;
1509 slot
= &xhci
->slots
[slotid
-1];
1511 if (!slot
->eps
[epid
-1]) {
1512 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1513 return CC_EP_NOT_ENABLED_ERROR
;
1516 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1517 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1518 "data might be lost\n");
1521 epctx
= slot
->eps
[epid
-1];
1523 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1525 if (epctx
->nr_pstreams
) {
1526 xhci_reset_streams(epctx
);
1532 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1536 XHCIEPContext
*epctx
;
1538 trace_usb_xhci_ep_reset(slotid
, epid
);
1539 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1541 if (epid
< 1 || epid
> 31) {
1542 DPRINTF("xhci: bad ep %d\n", epid
);
1543 return CC_TRB_ERROR
;
1546 slot
= &xhci
->slots
[slotid
-1];
1548 if (!slot
->eps
[epid
-1]) {
1549 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1550 return CC_EP_NOT_ENABLED_ERROR
;
1553 epctx
= slot
->eps
[epid
-1];
1555 if (epctx
->state
!= EP_HALTED
) {
1556 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1557 epid
, epctx
->state
);
1558 return CC_CONTEXT_STATE_ERROR
;
1561 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1562 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1563 "data might be lost\n");
1566 if (!xhci
->slots
[slotid
-1].uport
||
1567 !xhci
->slots
[slotid
-1].uport
->dev
||
1568 !xhci
->slots
[slotid
-1].uport
->dev
->attached
) {
1569 return CC_USB_TRANSACTION_ERROR
;
1572 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1574 if (epctx
->nr_pstreams
) {
1575 xhci_reset_streams(epctx
);
1581 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1582 unsigned int epid
, unsigned int streamid
,
1586 XHCIEPContext
*epctx
;
1587 XHCIStreamContext
*sctx
;
1590 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1592 if (epid
< 1 || epid
> 31) {
1593 DPRINTF("xhci: bad ep %d\n", epid
);
1594 return CC_TRB_ERROR
;
1597 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1598 dequeue
= xhci_mask64(pdequeue
);
1600 slot
= &xhci
->slots
[slotid
-1];
1602 if (!slot
->eps
[epid
-1]) {
1603 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1604 return CC_EP_NOT_ENABLED_ERROR
;
1607 epctx
= slot
->eps
[epid
-1];
1609 if (epctx
->state
!= EP_STOPPED
) {
1610 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1611 return CC_CONTEXT_STATE_ERROR
;
1614 if (epctx
->nr_pstreams
) {
1616 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1620 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1621 sctx
->ring
.ccs
= dequeue
& 1;
1624 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1625 epctx
->ring
.ccs
= dequeue
& 1;
1628 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1633 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1635 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1638 xfer
->int_req
= false;
1639 pci_dma_sglist_init(&xfer
->sgl
, PCI_DEVICE(xhci
), xfer
->trb_count
);
1640 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1641 XHCITRB
*trb
= &xfer
->trbs
[i
];
1643 unsigned int chunk
= 0;
1645 if (trb
->control
& TRB_TR_IOC
) {
1646 xfer
->int_req
= true;
1649 switch (TRB_TYPE(*trb
)) {
1651 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1652 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1658 addr
= xhci_mask64(trb
->parameter
);
1659 chunk
= trb
->status
& 0x1ffff;
1660 if (trb
->control
& TRB_TR_IDT
) {
1661 if (chunk
> 8 || in_xfer
) {
1662 DPRINTF("xhci: invalid immediate data TRB\n");
1665 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1667 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1676 qemu_sglist_destroy(&xfer
->sgl
);
1681 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1683 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1684 qemu_sglist_destroy(&xfer
->sgl
);
1687 static void xhci_xfer_report(XHCITransfer
*xfer
)
1693 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1694 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1697 left
= xfer
->packet
.actual_length
;
1699 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1700 XHCITRB
*trb
= &xfer
->trbs
[i
];
1701 unsigned int chunk
= 0;
1703 switch (TRB_TYPE(*trb
)) {
1705 chunk
= trb
->status
& 0x1ffff;
1713 chunk
= trb
->status
& 0x1ffff;
1716 if (xfer
->status
== CC_SUCCESS
) {
1729 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1730 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1731 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1732 event
.slotid
= xfer
->epctx
->slotid
;
1733 event
.epid
= xfer
->epctx
->epid
;
1734 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1736 event
.ptr
= trb
->addr
;
1737 if (xfer
->status
== CC_SUCCESS
) {
1738 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1740 event
.ccode
= xfer
->status
;
1742 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1743 event
.ptr
= trb
->parameter
;
1744 event
.flags
|= TRB_EV_ED
;
1745 event
.length
= edtla
& 0xffffff;
1746 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1749 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1751 if (xfer
->status
!= CC_SUCCESS
) {
1756 switch (TRB_TYPE(*trb
)) {
1766 static void xhci_stall_ep(XHCITransfer
*xfer
)
1768 XHCIEPContext
*epctx
= xfer
->epctx
;
1769 XHCIState
*xhci
= epctx
->xhci
;
1771 XHCIStreamContext
*sctx
;
1773 if (epctx
->nr_pstreams
) {
1774 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1778 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1779 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1780 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1782 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1783 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1784 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1788 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1789 XHCIEPContext
*epctx
);
1791 static int xhci_setup_packet(XHCITransfer
*xfer
)
1796 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1798 if (xfer
->packet
.ep
) {
1799 ep
= xfer
->packet
.ep
;
1801 ep
= xhci_epid_to_usbep(xfer
->epctx
);
1803 DPRINTF("xhci: slot %d has no device\n",
1809 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1810 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1811 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1812 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1813 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1814 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1818 static int xhci_try_complete_packet(XHCITransfer
*xfer
)
1820 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1821 trace_usb_xhci_xfer_async(xfer
);
1822 xfer
->running_async
= 1;
1823 xfer
->running_retry
= 0;
1826 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1827 trace_usb_xhci_xfer_nak(xfer
);
1828 xfer
->running_async
= 0;
1829 xfer
->running_retry
= 1;
1833 xfer
->running_async
= 0;
1834 xfer
->running_retry
= 0;
1836 xhci_xfer_unmap(xfer
);
1839 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1840 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1841 xfer
->status
= CC_SUCCESS
;
1842 xhci_xfer_report(xfer
);
1847 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1848 switch (xfer
->packet
.status
) {
1850 case USB_RET_IOERROR
:
1851 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1852 xhci_xfer_report(xfer
);
1853 xhci_stall_ep(xfer
);
1856 xfer
->status
= CC_STALL_ERROR
;
1857 xhci_xfer_report(xfer
);
1858 xhci_stall_ep(xfer
);
1860 case USB_RET_BABBLE
:
1861 xfer
->status
= CC_BABBLE_DETECTED
;
1862 xhci_xfer_report(xfer
);
1863 xhci_stall_ep(xfer
);
1866 DPRINTF("%s: FIXME: status = %d\n", __func__
,
1867 xfer
->packet
.status
);
1868 FIXME("unhandled USB_RET_*");
1873 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1875 XHCITRB
*trb_setup
, *trb_status
;
1876 uint8_t bmRequestType
;
1878 trb_setup
= &xfer
->trbs
[0];
1879 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1881 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1882 xfer
->epctx
->epid
, xfer
->streamid
);
1884 /* at most one Event Data TRB allowed after STATUS */
1885 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1889 /* do some sanity checks */
1890 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1891 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1892 TRB_TYPE(*trb_setup
));
1895 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1896 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1897 TRB_TYPE(*trb_status
));
1900 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1901 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1904 if ((trb_setup
->status
& 0x1ffff) != 8) {
1905 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1906 (trb_setup
->status
& 0x1ffff));
1910 bmRequestType
= trb_setup
->parameter
;
1912 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1913 xfer
->iso_xfer
= false;
1914 xfer
->timed_xfer
= false;
1916 if (xhci_setup_packet(xfer
) < 0) {
1919 xfer
->packet
.parameter
= trb_setup
->parameter
;
1921 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1922 xhci_try_complete_packet(xfer
);
1926 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1927 XHCIEPContext
*epctx
, uint64_t mfindex
)
1929 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1930 ~(epctx
->interval
-1));
1931 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1933 assert(epctx
->interval
!= 0);
1934 xfer
->mfindex_kick
= MAX(asap
, kick
);
1937 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1938 XHCIEPContext
*epctx
, uint64_t mfindex
)
1940 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1941 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1942 ~(epctx
->interval
-1));
1943 if (asap
>= epctx
->mfindex_last
&&
1944 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1945 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1947 xfer
->mfindex_kick
= asap
;
1950 xfer
->mfindex_kick
= ((xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1951 & TRB_TR_FRAMEID_MASK
) << 3;
1952 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1953 if (xfer
->mfindex_kick
+ 0x100 < mfindex
) {
1954 xfer
->mfindex_kick
+= 0x4000;
1959 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1960 XHCIEPContext
*epctx
, uint64_t mfindex
)
1962 if (xfer
->mfindex_kick
> mfindex
) {
1963 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1964 (xfer
->mfindex_kick
- mfindex
) * 125000);
1965 xfer
->running_retry
= 1;
1967 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1968 timer_del(epctx
->kick_timer
);
1969 xfer
->running_retry
= 0;
1974 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1978 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1980 xfer
->in_xfer
= epctx
->type
>>2;
1982 switch(epctx
->type
) {
1986 xfer
->iso_xfer
= false;
1987 xfer
->timed_xfer
= true;
1988 mfindex
= xhci_mfindex_get(xhci
);
1989 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
1990 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1991 if (xfer
->running_retry
) {
1998 xfer
->iso_xfer
= false;
1999 xfer
->timed_xfer
= false;
2004 xfer
->iso_xfer
= true;
2005 xfer
->timed_xfer
= true;
2006 mfindex
= xhci_mfindex_get(xhci
);
2007 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2008 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2009 if (xfer
->running_retry
) {
2014 trace_usb_xhci_unimplemented("endpoint type", epctx
->type
);
2018 if (xhci_setup_packet(xfer
) < 0) {
2021 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2022 xhci_try_complete_packet(xfer
);
2026 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
2028 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
2029 xfer
->epctx
->epid
, xfer
->streamid
);
2030 return xhci_submit(xhci
, xfer
, epctx
);
2033 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
2034 unsigned int epid
, unsigned int streamid
)
2036 XHCIEPContext
*epctx
;
2038 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2039 assert(epid
>= 1 && epid
<= 31);
2041 if (!xhci
->slots
[slotid
-1].enabled
) {
2042 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
2045 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
2047 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2052 if (epctx
->kick_active
) {
2055 xhci_kick_epctx(epctx
, streamid
);
2058 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
)
2060 XHCIState
*xhci
= epctx
->xhci
;
2061 XHCIStreamContext
*stctx
;
2064 USBEndpoint
*ep
= NULL
;
2066 unsigned int count
= 0;
2070 trace_usb_xhci_ep_kick(epctx
->slotid
, epctx
->epid
, streamid
);
2071 assert(!epctx
->kick_active
);
2073 /* If the device has been detached, but the guest has not noticed this
2074 yet the 2 above checks will succeed, but we must NOT continue */
2075 if (!xhci
->slots
[epctx
->slotid
- 1].uport
||
2076 !xhci
->slots
[epctx
->slotid
- 1].uport
->dev
||
2077 !xhci
->slots
[epctx
->slotid
- 1].uport
->dev
->attached
) {
2082 XHCITransfer
*xfer
= epctx
->retry
;
2084 trace_usb_xhci_xfer_retry(xfer
);
2085 assert(xfer
->running_retry
);
2086 if (xfer
->timed_xfer
) {
2087 /* time to kick the transfer? */
2088 mfindex
= xhci_mfindex_get(xhci
);
2089 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
2090 if (xfer
->running_retry
) {
2093 xfer
->timed_xfer
= 0;
2094 xfer
->running_retry
= 1;
2096 if (xfer
->iso_xfer
) {
2097 /* retry iso transfer */
2098 if (xhci_setup_packet(xfer
) < 0) {
2101 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2102 assert(xfer
->packet
.status
!= USB_RET_NAK
);
2103 xhci_try_complete_packet(xfer
);
2105 /* retry nak'ed transfer */
2106 if (xhci_setup_packet(xfer
) < 0) {
2109 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2110 if (xfer
->packet
.status
== USB_RET_NAK
) {
2113 xhci_try_complete_packet(xfer
);
2115 assert(!xfer
->running_retry
);
2116 if (xfer
->complete
) {
2117 xhci_ep_free_xfer(epctx
->retry
);
2119 epctx
->retry
= NULL
;
2122 if (epctx
->state
== EP_HALTED
) {
2123 DPRINTF("xhci: ep halted, not running schedule\n");
2128 if (epctx
->nr_pstreams
) {
2130 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
2131 if (stctx
== NULL
) {
2134 ring
= &stctx
->ring
;
2135 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
2137 ring
= &epctx
->ring
;
2139 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
2141 assert(ring
->dequeue
!= 0);
2143 epctx
->kick_active
++;
2145 length
= xhci_ring_chain_length(xhci
, ring
);
2149 xfer
= xhci_ep_alloc_xfer(epctx
, length
);
2154 for (i
= 0; i
< length
; i
++) {
2156 type
= xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
);
2159 xfer
->streamid
= streamid
;
2161 if (epctx
->epid
== 1) {
2162 xhci_fire_ctl_transfer(xhci
, xfer
);
2164 xhci_fire_transfer(xhci
, xfer
, epctx
);
2166 if (xfer
->complete
) {
2167 xhci_ep_free_xfer(xfer
);
2171 if (epctx
->state
== EP_HALTED
) {
2174 if (xfer
!= NULL
&& xfer
->running_retry
) {
2175 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2176 epctx
->retry
= xfer
;
2179 if (count
++ > TRANSFER_LIMIT
) {
2180 trace_usb_xhci_enforced_limit("transfers");
2184 epctx
->kick_active
--;
2186 ep
= xhci_epid_to_usbep(epctx
);
2188 usb_device_flush_ep_queue(ep
->dev
, ep
);
2192 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
2194 trace_usb_xhci_slot_enable(slotid
);
2195 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2196 xhci
->slots
[slotid
-1].enabled
= 1;
2197 xhci
->slots
[slotid
-1].uport
= NULL
;
2198 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2203 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2207 trace_usb_xhci_slot_disable(slotid
);
2208 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2210 for (i
= 1; i
<= 31; i
++) {
2211 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2212 xhci_disable_ep(xhci
, slotid
, i
);
2216 xhci
->slots
[slotid
-1].enabled
= 0;
2217 xhci
->slots
[slotid
-1].addressed
= 0;
2218 xhci
->slots
[slotid
-1].uport
= NULL
;
2222 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2228 port
= (slot_ctx
[1]>>16) & 0xFF;
2229 if (port
< 1 || port
> xhci
->numports
) {
2232 port
= xhci
->ports
[port
-1].uport
->index
+1;
2233 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2234 for (i
= 0; i
< 5; i
++) {
2235 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2239 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2242 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2243 if (strcmp(uport
->path
, path
) == 0) {
2250 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2251 uint64_t pictx
, bool bsr
)
2256 dma_addr_t ictx
, octx
, dcbaap
;
2258 uint32_t ictl_ctx
[2];
2259 uint32_t slot_ctx
[4];
2260 uint32_t ep0_ctx
[5];
2264 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2266 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2267 poctx
= ldq_le_pci_dma(PCI_DEVICE(xhci
), dcbaap
+ 8 * slotid
);
2268 ictx
= xhci_mask64(pictx
);
2269 octx
= xhci_mask64(poctx
);
2271 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2272 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2274 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2276 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2277 DPRINTF("xhci: invalid input context control %08x %08x\n",
2278 ictl_ctx
[0], ictl_ctx
[1]);
2279 return CC_TRB_ERROR
;
2282 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2283 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2285 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2286 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2288 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2289 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2291 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2292 if (uport
== NULL
) {
2293 DPRINTF("xhci: port not found\n");
2294 return CC_TRB_ERROR
;
2296 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2299 if (!dev
|| !dev
->attached
) {
2300 DPRINTF("xhci: port %s not connected\n", uport
->path
);
2301 return CC_USB_TRANSACTION_ERROR
;
2304 for (i
= 0; i
< xhci
->numslots
; i
++) {
2305 if (i
== slotid
-1) {
2308 if (xhci
->slots
[i
].uport
== uport
) {
2309 DPRINTF("xhci: port %s already assigned to slot %d\n",
2311 return CC_TRB_ERROR
;
2315 slot
= &xhci
->slots
[slotid
-1];
2316 slot
->uport
= uport
;
2319 /* Make sure device is in USB_STATE_DEFAULT state */
2320 usb_device_reset(dev
);
2322 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2327 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2328 memset(&p
, 0, sizeof(p
));
2329 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2330 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2331 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2333 usb_device_handle_control(dev
, &p
,
2334 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2335 slotid
, 0, 0, NULL
);
2336 assert(p
.status
!= USB_RET_ASYNC
);
2339 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2341 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2342 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2343 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2344 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2346 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2347 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2349 xhci
->slots
[slotid
-1].addressed
= 1;
2354 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2355 uint64_t pictx
, bool dc
)
2357 dma_addr_t ictx
, octx
;
2358 uint32_t ictl_ctx
[2];
2359 uint32_t slot_ctx
[4];
2360 uint32_t islot_ctx
[4];
2365 trace_usb_xhci_slot_configure(slotid
);
2366 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2368 ictx
= xhci_mask64(pictx
);
2369 octx
= xhci
->slots
[slotid
-1].ctx
;
2371 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2372 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2375 for (i
= 2; i
<= 31; i
++) {
2376 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2377 xhci_disable_ep(xhci
, slotid
, i
);
2381 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2382 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2383 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2384 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2385 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2386 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2391 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2393 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2394 DPRINTF("xhci: invalid input context control %08x %08x\n",
2395 ictl_ctx
[0], ictl_ctx
[1]);
2396 return CC_TRB_ERROR
;
2399 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2400 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2402 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2403 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx
[3]);
2404 return CC_CONTEXT_STATE_ERROR
;
2407 xhci_free_device_streams(xhci
, slotid
, ictl_ctx
[0] | ictl_ctx
[1]);
2409 for (i
= 2; i
<= 31; i
++) {
2410 if (ictl_ctx
[0] & (1<<i
)) {
2411 xhci_disable_ep(xhci
, slotid
, i
);
2413 if (ictl_ctx
[1] & (1<<i
)) {
2414 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2415 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2416 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2417 ep_ctx
[3], ep_ctx
[4]);
2418 xhci_disable_ep(xhci
, slotid
, i
);
2419 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2420 if (res
!= CC_SUCCESS
) {
2423 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2424 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2425 ep_ctx
[3], ep_ctx
[4]);
2426 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2430 res
= xhci_alloc_device_streams(xhci
, slotid
, ictl_ctx
[1]);
2431 if (res
!= CC_SUCCESS
) {
2432 for (i
= 2; i
<= 31; i
++) {
2433 if (ictl_ctx
[1] & (1u << i
)) {
2434 xhci_disable_ep(xhci
, slotid
, i
);
2440 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2441 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2442 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2443 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2444 SLOT_CONTEXT_ENTRIES_SHIFT
);
2445 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2446 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2448 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2454 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2457 dma_addr_t ictx
, octx
;
2458 uint32_t ictl_ctx
[2];
2459 uint32_t iep0_ctx
[5];
2460 uint32_t ep0_ctx
[5];
2461 uint32_t islot_ctx
[4];
2462 uint32_t slot_ctx
[4];
2464 trace_usb_xhci_slot_evaluate(slotid
);
2465 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2467 ictx
= xhci_mask64(pictx
);
2468 octx
= xhci
->slots
[slotid
-1].ctx
;
2470 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2471 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2473 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2475 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2476 DPRINTF("xhci: invalid input context control %08x %08x\n",
2477 ictl_ctx
[0], ictl_ctx
[1]);
2478 return CC_TRB_ERROR
;
2481 if (ictl_ctx
[1] & 0x1) {
2482 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2484 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2485 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2487 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2489 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2490 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2491 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2492 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2494 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2495 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2497 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2500 if (ictl_ctx
[1] & 0x2) {
2501 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2503 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2504 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2505 iep0_ctx
[3], iep0_ctx
[4]);
2507 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2509 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2510 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2512 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2513 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2515 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2521 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2523 uint32_t slot_ctx
[4];
2527 trace_usb_xhci_slot_reset(slotid
);
2528 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2530 octx
= xhci
->slots
[slotid
-1].ctx
;
2532 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2534 for (i
= 2; i
<= 31; i
++) {
2535 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2536 xhci_disable_ep(xhci
, slotid
, i
);
2540 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2541 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2542 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2543 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2544 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2545 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2550 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2552 unsigned int slotid
;
2553 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2554 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2555 DPRINTF("xhci: bad slot id %d\n", slotid
);
2556 event
->ccode
= CC_TRB_ERROR
;
2558 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2559 DPRINTF("xhci: slot id %d not enabled\n", slotid
);
2560 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2566 /* cleanup slot state on usb device detach */
2567 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2571 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2572 if (xhci
->slots
[slot
].uport
== uport
) {
2576 if (slot
== xhci
->numslots
) {
2580 for (ep
= 0; ep
< 31; ep
++) {
2581 if (xhci
->slots
[slot
].eps
[ep
]) {
2582 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2585 xhci
->slots
[slot
].uport
= NULL
;
2588 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2591 uint8_t bw_ctx
[xhci
->numports
+1];
2593 DPRINTF("xhci_get_port_bandwidth()\n");
2595 ctx
= xhci_mask64(pctx
);
2597 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2599 /* TODO: actually implement real values here */
2601 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2602 pci_dma_write(PCI_DEVICE(xhci
), ctx
, bw_ctx
, sizeof(bw_ctx
));
2607 static uint32_t rotl(uint32_t v
, unsigned count
)
2610 return (v
<< count
) | (v
>> (32 - count
));
2614 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2617 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2618 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2619 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2623 static void xhci_process_commands(XHCIState
*xhci
)
2627 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2629 unsigned int i
, slotid
= 0, count
= 0;
2631 DPRINTF("xhci_process_commands()\n");
2632 if (!xhci_running(xhci
)) {
2633 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2637 xhci
->crcr_low
|= CRCR_CRR
;
2639 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2642 case CR_ENABLE_SLOT
:
2643 for (i
= 0; i
< xhci
->numslots
; i
++) {
2644 if (!xhci
->slots
[i
].enabled
) {
2648 if (i
>= xhci
->numslots
) {
2649 DPRINTF("xhci: no device slots available\n");
2650 event
.ccode
= CC_NO_SLOTS_ERROR
;
2653 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2656 case CR_DISABLE_SLOT
:
2657 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2659 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2662 case CR_ADDRESS_DEVICE
:
2663 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2665 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2666 trb
.control
& TRB_CR_BSR
);
2669 case CR_CONFIGURE_ENDPOINT
:
2670 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2672 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2673 trb
.control
& TRB_CR_DC
);
2676 case CR_EVALUATE_CONTEXT
:
2677 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2679 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2682 case CR_STOP_ENDPOINT
:
2683 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2685 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2687 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2690 case CR_RESET_ENDPOINT
:
2691 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2693 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2695 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2698 case CR_SET_TR_DEQUEUE
:
2699 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2701 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2703 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2704 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2709 case CR_RESET_DEVICE
:
2710 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2712 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2715 case CR_GET_PORT_BANDWIDTH
:
2716 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2718 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2719 if (xhci
->nec_quirks
) {
2720 event
.type
= 48; /* NEC reply */
2721 event
.length
= 0x3025;
2723 event
.ccode
= CC_TRB_ERROR
;
2726 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2727 if (xhci
->nec_quirks
) {
2728 uint32_t chi
= trb
.parameter
>> 32;
2729 uint32_t clo
= trb
.parameter
;
2730 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2731 event
.length
= val
& 0xFFFF;
2732 event
.epid
= val
>> 16;
2734 event
.type
= 48; /* NEC reply */
2736 event
.ccode
= CC_TRB_ERROR
;
2740 trace_usb_xhci_unimplemented("command", type
);
2741 event
.ccode
= CC_TRB_ERROR
;
2744 event
.slotid
= slotid
;
2745 xhci_event(xhci
, &event
, 0);
2747 if (count
++ > COMMAND_LIMIT
) {
2748 trace_usb_xhci_enforced_limit("commands");
2754 static bool xhci_port_have_device(XHCIPort
*port
)
2756 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2757 return false; /* no device present */
2759 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2760 return false; /* speed mismatch */
2765 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2767 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2768 port
->portnr
<< 24 };
2770 if ((port
->portsc
& bits
) == bits
) {
2773 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2774 port
->portsc
|= bits
;
2775 if (!xhci_running(port
->xhci
)) {
2778 xhci_event(port
->xhci
, &ev
, 0);
2781 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2783 uint32_t pls
= PLS_RX_DETECT
;
2785 port
->portsc
= PORTSC_PP
;
2786 if (!is_detach
&& xhci_port_have_device(port
)) {
2787 port
->portsc
|= PORTSC_CCS
;
2788 switch (port
->uport
->dev
->speed
) {
2790 port
->portsc
|= PORTSC_SPEED_LOW
;
2793 case USB_SPEED_FULL
:
2794 port
->portsc
|= PORTSC_SPEED_FULL
;
2797 case USB_SPEED_HIGH
:
2798 port
->portsc
|= PORTSC_SPEED_HIGH
;
2801 case USB_SPEED_SUPER
:
2802 port
->portsc
|= PORTSC_SPEED_SUPER
;
2803 port
->portsc
|= PORTSC_PED
;
2808 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2809 trace_usb_xhci_port_link(port
->portnr
, pls
);
2810 xhci_port_notify(port
, PORTSC_CSC
);
2813 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2815 trace_usb_xhci_port_reset(port
->portnr
, warm_reset
);
2817 if (!xhci_port_have_device(port
)) {
2821 usb_device_reset(port
->uport
->dev
);
2823 switch (port
->uport
->dev
->speed
) {
2824 case USB_SPEED_SUPER
:
2826 port
->portsc
|= PORTSC_WRC
;
2830 case USB_SPEED_FULL
:
2831 case USB_SPEED_HIGH
:
2832 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2833 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2834 port
->portsc
|= PORTSC_PED
;
2838 port
->portsc
&= ~PORTSC_PR
;
2839 xhci_port_notify(port
, PORTSC_PRC
);
2842 static void xhci_reset(DeviceState
*dev
)
2844 XHCIState
*xhci
= XHCI(dev
);
2847 trace_usb_xhci_reset();
2848 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2849 DPRINTF("xhci: reset while running!\n");
2853 xhci
->usbsts
= USBSTS_HCH
;
2856 xhci
->crcr_high
= 0;
2857 xhci
->dcbaap_low
= 0;
2858 xhci
->dcbaap_high
= 0;
2861 for (i
= 0; i
< xhci
->numslots
; i
++) {
2862 xhci_disable_slot(xhci
, i
+1);
2865 for (i
= 0; i
< xhci
->numports
; i
++) {
2866 xhci_port_update(xhci
->ports
+ i
, 0);
2869 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2870 xhci
->intr
[i
].iman
= 0;
2871 xhci
->intr
[i
].imod
= 0;
2872 xhci
->intr
[i
].erstsz
= 0;
2873 xhci
->intr
[i
].erstba_low
= 0;
2874 xhci
->intr
[i
].erstba_high
= 0;
2875 xhci
->intr
[i
].erdp_low
= 0;
2876 xhci
->intr
[i
].erdp_high
= 0;
2877 xhci
->intr
[i
].msix_used
= 0;
2879 xhci
->intr
[i
].er_ep_idx
= 0;
2880 xhci
->intr
[i
].er_pcs
= 1;
2881 xhci
->intr
[i
].ev_buffer_put
= 0;
2882 xhci
->intr
[i
].ev_buffer_get
= 0;
2885 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2886 xhci_mfwrap_update(xhci
);
2889 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2891 XHCIState
*xhci
= ptr
;
2895 case 0x00: /* HCIVERSION, CAPLENGTH */
2896 ret
= 0x01000000 | LEN_CAP
;
2898 case 0x04: /* HCSPARAMS 1 */
2899 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2900 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2902 case 0x08: /* HCSPARAMS 2 */
2905 case 0x0c: /* HCSPARAMS 3 */
2908 case 0x10: /* HCCPARAMS */
2909 if (sizeof(dma_addr_t
) == 4) {
2910 ret
= 0x00080000 | (xhci
->max_pstreams_mask
<< 12);
2912 ret
= 0x00080001 | (xhci
->max_pstreams_mask
<< 12);
2915 case 0x14: /* DBOFF */
2918 case 0x18: /* RTSOFF */
2922 /* extended capabilities */
2923 case 0x20: /* Supported Protocol:00 */
2924 ret
= 0x02000402; /* USB 2.0 */
2926 case 0x24: /* Supported Protocol:04 */
2927 ret
= 0x20425355; /* "USB " */
2929 case 0x28: /* Supported Protocol:08 */
2930 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2931 ret
= (xhci
->numports_2
<<8) | (xhci
->numports_3
+1);
2933 ret
= (xhci
->numports_2
<<8) | 1;
2936 case 0x2c: /* Supported Protocol:0c */
2937 ret
= 0x00000000; /* reserved */
2939 case 0x30: /* Supported Protocol:00 */
2940 ret
= 0x03000002; /* USB 3.0 */
2942 case 0x34: /* Supported Protocol:04 */
2943 ret
= 0x20425355; /* "USB " */
2945 case 0x38: /* Supported Protocol:08 */
2946 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2947 ret
= (xhci
->numports_3
<<8) | 1;
2949 ret
= (xhci
->numports_3
<<8) | (xhci
->numports_2
+1);
2952 case 0x3c: /* Supported Protocol:0c */
2953 ret
= 0x00000000; /* reserved */
2956 trace_usb_xhci_unimplemented("cap read", reg
);
2960 trace_usb_xhci_cap_read(reg
, ret
);
2964 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2966 XHCIPort
*port
= ptr
;
2970 case 0x00: /* PORTSC */
2973 case 0x04: /* PORTPMSC */
2974 case 0x08: /* PORTLI */
2977 case 0x0c: /* reserved */
2979 trace_usb_xhci_unimplemented("port read", reg
);
2983 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2987 static void xhci_port_write(void *ptr
, hwaddr reg
,
2988 uint64_t val
, unsigned size
)
2990 XHCIPort
*port
= ptr
;
2991 uint32_t portsc
, notify
;
2993 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2996 case 0x00: /* PORTSC */
2997 /* write-1-to-start bits */
2998 if (val
& PORTSC_WPR
) {
2999 xhci_port_reset(port
, true);
3002 if (val
& PORTSC_PR
) {
3003 xhci_port_reset(port
, false);
3007 portsc
= port
->portsc
;
3009 /* write-1-to-clear bits*/
3010 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
3011 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
3012 if (val
& PORTSC_LWS
) {
3013 /* overwrite PLS only when LWS=1 */
3014 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
3015 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
3018 if (old_pls
!= PLS_U0
) {
3019 set_field(&portsc
, new_pls
, PORTSC_PLS
);
3020 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
3021 notify
= PORTSC_PLC
;
3025 if (old_pls
< PLS_U3
) {
3026 set_field(&portsc
, new_pls
, PORTSC_PLS
);
3027 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
3031 /* windows does this for some reason, don't spam stderr */
3034 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3035 __func__
, old_pls
, new_pls
);
3039 /* read/write bits */
3040 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
3041 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
3042 port
->portsc
= portsc
;
3044 xhci_port_notify(port
, notify
);
3047 case 0x04: /* PORTPMSC */
3048 case 0x08: /* PORTLI */
3050 trace_usb_xhci_unimplemented("port write", reg
);
3054 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
3056 XHCIState
*xhci
= ptr
;
3060 case 0x00: /* USBCMD */
3063 case 0x04: /* USBSTS */
3066 case 0x08: /* PAGESIZE */
3069 case 0x14: /* DNCTRL */
3072 case 0x18: /* CRCR low */
3073 ret
= xhci
->crcr_low
& ~0xe;
3075 case 0x1c: /* CRCR high */
3076 ret
= xhci
->crcr_high
;
3078 case 0x30: /* DCBAAP low */
3079 ret
= xhci
->dcbaap_low
;
3081 case 0x34: /* DCBAAP high */
3082 ret
= xhci
->dcbaap_high
;
3084 case 0x38: /* CONFIG */
3088 trace_usb_xhci_unimplemented("oper read", reg
);
3092 trace_usb_xhci_oper_read(reg
, ret
);
3096 static void xhci_oper_write(void *ptr
, hwaddr reg
,
3097 uint64_t val
, unsigned size
)
3099 XHCIState
*xhci
= ptr
;
3100 DeviceState
*d
= DEVICE(ptr
);
3102 trace_usb_xhci_oper_write(reg
, val
);
3105 case 0x00: /* USBCMD */
3106 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
3108 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
3111 if (val
& USBCMD_CSS
) {
3113 xhci
->usbsts
&= ~USBSTS_SRE
;
3115 if (val
& USBCMD_CRS
) {
3117 xhci
->usbsts
|= USBSTS_SRE
;
3119 xhci
->usbcmd
= val
& 0xc0f;
3120 xhci_mfwrap_update(xhci
);
3121 if (val
& USBCMD_HCRST
) {
3124 xhci_intx_update(xhci
);
3127 case 0x04: /* USBSTS */
3128 /* these bits are write-1-to-clear */
3129 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
3130 xhci_intx_update(xhci
);
3133 case 0x14: /* DNCTRL */
3134 xhci
->dnctrl
= val
& 0xffff;
3136 case 0x18: /* CRCR low */
3137 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
3139 case 0x1c: /* CRCR high */
3140 xhci
->crcr_high
= val
;
3141 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
3142 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
3143 xhci
->crcr_low
&= ~CRCR_CRR
;
3144 xhci_event(xhci
, &event
, 0);
3145 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
3147 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
3148 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
3150 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
3152 case 0x30: /* DCBAAP low */
3153 xhci
->dcbaap_low
= val
& 0xffffffc0;
3155 case 0x34: /* DCBAAP high */
3156 xhci
->dcbaap_high
= val
;
3158 case 0x38: /* CONFIG */
3159 xhci
->config
= val
& 0xff;
3162 trace_usb_xhci_unimplemented("oper write", reg
);
3166 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
3169 XHCIState
*xhci
= ptr
;
3174 case 0x00: /* MFINDEX */
3175 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
3178 trace_usb_xhci_unimplemented("runtime read", reg
);
3182 int v
= (reg
- 0x20) / 0x20;
3183 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3184 switch (reg
& 0x1f) {
3185 case 0x00: /* IMAN */
3188 case 0x04: /* IMOD */
3191 case 0x08: /* ERSTSZ */
3194 case 0x10: /* ERSTBA low */
3195 ret
= intr
->erstba_low
;
3197 case 0x14: /* ERSTBA high */
3198 ret
= intr
->erstba_high
;
3200 case 0x18: /* ERDP low */
3201 ret
= intr
->erdp_low
;
3203 case 0x1c: /* ERDP high */
3204 ret
= intr
->erdp_high
;
3209 trace_usb_xhci_runtime_read(reg
, ret
);
3213 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3214 uint64_t val
, unsigned size
)
3216 XHCIState
*xhci
= ptr
;
3217 int v
= (reg
- 0x20) / 0x20;
3218 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3219 trace_usb_xhci_runtime_write(reg
, val
);
3222 trace_usb_xhci_unimplemented("runtime write", reg
);
3226 switch (reg
& 0x1f) {
3227 case 0x00: /* IMAN */
3228 if (val
& IMAN_IP
) {
3229 intr
->iman
&= ~IMAN_IP
;
3231 intr
->iman
&= ~IMAN_IE
;
3232 intr
->iman
|= val
& IMAN_IE
;
3234 xhci_intx_update(xhci
);
3236 xhci_msix_update(xhci
, v
);
3238 case 0x04: /* IMOD */
3241 case 0x08: /* ERSTSZ */
3242 intr
->erstsz
= val
& 0xffff;
3244 case 0x10: /* ERSTBA low */
3245 if (xhci
->nec_quirks
) {
3246 /* NEC driver bug: it doesn't align this to 64 bytes */
3247 intr
->erstba_low
= val
& 0xfffffff0;
3249 intr
->erstba_low
= val
& 0xffffffc0;
3252 case 0x14: /* ERSTBA high */
3253 intr
->erstba_high
= val
;
3254 xhci_er_reset(xhci
, v
);
3256 case 0x18: /* ERDP low */
3257 if (val
& ERDP_EHB
) {
3258 intr
->erdp_low
&= ~ERDP_EHB
;
3260 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3261 if (val
& ERDP_EHB
) {
3262 dma_addr_t erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
3263 unsigned int dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
3264 if (erdp
>= intr
->er_start
&&
3265 erdp
< (intr
->er_start
+ TRB_SIZE
* intr
->er_size
) &&
3266 dp_idx
!= intr
->er_ep_idx
) {
3267 xhci_intr_raise(xhci
, v
);
3271 case 0x1c: /* ERDP high */
3272 intr
->erdp_high
= val
;
3275 trace_usb_xhci_unimplemented("oper write", reg
);
3279 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3282 /* doorbells always read as 0 */
3283 trace_usb_xhci_doorbell_read(reg
, 0);
3287 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3288 uint64_t val
, unsigned size
)
3290 XHCIState
*xhci
= ptr
;
3291 unsigned int epid
, streamid
;
3293 trace_usb_xhci_doorbell_write(reg
, val
);
3295 if (!xhci_running(xhci
)) {
3296 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3304 xhci_process_commands(xhci
);
3306 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3311 streamid
= (val
>> 16) & 0xffff;
3312 if (reg
> xhci
->numslots
) {
3313 DPRINTF("xhci: bad doorbell %d\n", (int)reg
);
3314 } else if (epid
> 31) {
3315 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3316 (int)reg
, (uint32_t)val
);
3318 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3323 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3329 static const MemoryRegionOps xhci_cap_ops
= {
3330 .read
= xhci_cap_read
,
3331 .write
= xhci_cap_write
,
3332 .valid
.min_access_size
= 1,
3333 .valid
.max_access_size
= 4,
3334 .impl
.min_access_size
= 4,
3335 .impl
.max_access_size
= 4,
3336 .endianness
= DEVICE_LITTLE_ENDIAN
,
3339 static const MemoryRegionOps xhci_oper_ops
= {
3340 .read
= xhci_oper_read
,
3341 .write
= xhci_oper_write
,
3342 .valid
.min_access_size
= 4,
3343 .valid
.max_access_size
= 4,
3344 .endianness
= DEVICE_LITTLE_ENDIAN
,
3347 static const MemoryRegionOps xhci_port_ops
= {
3348 .read
= xhci_port_read
,
3349 .write
= xhci_port_write
,
3350 .valid
.min_access_size
= 4,
3351 .valid
.max_access_size
= 4,
3352 .endianness
= DEVICE_LITTLE_ENDIAN
,
3355 static const MemoryRegionOps xhci_runtime_ops
= {
3356 .read
= xhci_runtime_read
,
3357 .write
= xhci_runtime_write
,
3358 .valid
.min_access_size
= 4,
3359 .valid
.max_access_size
= 4,
3360 .endianness
= DEVICE_LITTLE_ENDIAN
,
3363 static const MemoryRegionOps xhci_doorbell_ops
= {
3364 .read
= xhci_doorbell_read
,
3365 .write
= xhci_doorbell_write
,
3366 .valid
.min_access_size
= 4,
3367 .valid
.max_access_size
= 4,
3368 .endianness
= DEVICE_LITTLE_ENDIAN
,
3371 static void xhci_attach(USBPort
*usbport
)
3373 XHCIState
*xhci
= usbport
->opaque
;
3374 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3376 xhci_port_update(port
, 0);
3379 static void xhci_detach(USBPort
*usbport
)
3381 XHCIState
*xhci
= usbport
->opaque
;
3382 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3384 xhci_detach_slot(xhci
, usbport
);
3385 xhci_port_update(port
, 1);
3388 static void xhci_wakeup(USBPort
*usbport
)
3390 XHCIState
*xhci
= usbport
->opaque
;
3391 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3393 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3396 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3397 xhci_port_notify(port
, PORTSC_PLC
);
3400 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3402 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3404 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3405 xhci_ep_nuke_one_xfer(xfer
, 0);
3408 xhci_try_complete_packet(xfer
);
3409 xhci_kick_epctx(xfer
->epctx
, xfer
->streamid
);
3410 if (xfer
->complete
) {
3411 xhci_ep_free_xfer(xfer
);
3415 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3417 USBBus
*bus
= usb_bus_from_device(child
);
3418 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3420 xhci_detach_slot(xhci
, child
->port
);
3423 static USBPortOps xhci_uport_ops
= {
3424 .attach
= xhci_attach
,
3425 .detach
= xhci_detach
,
3426 .wakeup
= xhci_wakeup
,
3427 .complete
= xhci_complete
,
3428 .child_detach
= xhci_child_detach
,
3431 static int xhci_find_epid(USBEndpoint
*ep
)
3436 if (ep
->pid
== USB_TOKEN_IN
) {
3437 return ep
->nr
* 2 + 1;
3443 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
)
3451 uport
= epctx
->xhci
->slots
[epctx
->slotid
- 1].uport
;
3452 token
= (epctx
->epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
;
3456 return usb_ep_get(uport
->dev
, token
, epctx
->epid
>> 1);
3459 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3460 unsigned int stream
)
3462 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3465 DPRINTF("%s\n", __func__
);
3466 slotid
= ep
->dev
->addr
;
3467 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3468 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3471 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3474 static USBBusOps xhci_bus_ops
= {
3475 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3478 static void usb_xhci_init(XHCIState
*xhci
)
3480 DeviceState
*dev
= DEVICE(xhci
);
3482 int i
, usbports
, speedmask
;
3484 xhci
->usbsts
= USBSTS_HCH
;
3486 if (xhci
->numports_2
> MAXPORTS_2
) {
3487 xhci
->numports_2
= MAXPORTS_2
;
3489 if (xhci
->numports_3
> MAXPORTS_3
) {
3490 xhci
->numports_3
= MAXPORTS_3
;
3492 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3493 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3495 usb_bus_new(&xhci
->bus
, sizeof(xhci
->bus
), &xhci_bus_ops
, dev
);
3497 for (i
= 0; i
< usbports
; i
++) {
3499 if (i
< xhci
->numports_2
) {
3500 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3501 port
= &xhci
->ports
[i
+ xhci
->numports_3
];
3502 port
->portnr
= i
+ 1 + xhci
->numports_3
;
3504 port
= &xhci
->ports
[i
];
3505 port
->portnr
= i
+ 1;
3507 port
->uport
= &xhci
->uports
[i
];
3509 USB_SPEED_MASK_LOW
|
3510 USB_SPEED_MASK_FULL
|
3511 USB_SPEED_MASK_HIGH
;
3512 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3513 speedmask
|= port
->speedmask
;
3515 if (i
< xhci
->numports_3
) {
3516 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3517 port
= &xhci
->ports
[i
];
3518 port
->portnr
= i
+ 1;
3520 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3521 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3523 port
->uport
= &xhci
->uports
[i
];
3524 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3525 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3526 speedmask
|= port
->speedmask
;
3528 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3529 &xhci_uport_ops
, speedmask
);
3533 static void usb_xhci_realize(struct PCIDevice
*dev
, Error
**errp
)
3538 XHCIState
*xhci
= XHCI(dev
);
3540 dev
->config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3541 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3542 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3543 dev
->config
[0x60] = 0x30; /* release number */
3545 if (strcmp(object_get_typename(OBJECT(dev
)), TYPE_NEC_XHCI
) == 0) {
3546 xhci
->nec_quirks
= true;
3548 if (xhci
->numintrs
> MAXINTRS
) {
3549 xhci
->numintrs
= MAXINTRS
;
3551 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3554 if (xhci
->numintrs
< 1) {
3557 if (xhci
->numslots
> MAXSLOTS
) {
3558 xhci
->numslots
= MAXSLOTS
;
3560 if (xhci
->numslots
< 1) {
3563 if (xhci_get_flag(xhci
, XHCI_FLAG_ENABLE_STREAMS
)) {
3564 xhci
->max_pstreams_mask
= 7; /* == 256 primary streams */
3566 xhci
->max_pstreams_mask
= 0;
3569 if (xhci
->msi
!= ON_OFF_AUTO_OFF
) {
3570 ret
= msi_init(dev
, 0x70, xhci
->numintrs
, true, false, &err
);
3571 /* Any error other than -ENOTSUP(board's MSI support is broken)
3572 * is a programming error */
3573 assert(!ret
|| ret
== -ENOTSUP
);
3574 if (ret
&& xhci
->msi
== ON_OFF_AUTO_ON
) {
3575 /* Can't satisfy user's explicit msi=on request, fail */
3576 error_append_hint(&err
, "You have to use msi=auto (default) or "
3577 "msi=off with this machine type.\n");
3578 error_propagate(errp
, err
);
3581 assert(!err
|| xhci
->msi
== ON_OFF_AUTO_AUTO
);
3582 /* With msi=auto, we fall back to MSI off silently */
3586 usb_xhci_init(xhci
);
3587 xhci
->mfwrap_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_mfwrap_timer
, xhci
);
3589 memory_region_init(&xhci
->mem
, OBJECT(xhci
), "xhci", LEN_REGS
);
3590 memory_region_init_io(&xhci
->mem_cap
, OBJECT(xhci
), &xhci_cap_ops
, xhci
,
3591 "capabilities", LEN_CAP
);
3592 memory_region_init_io(&xhci
->mem_oper
, OBJECT(xhci
), &xhci_oper_ops
, xhci
,
3593 "operational", 0x400);
3594 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(xhci
), &xhci_runtime_ops
, xhci
,
3595 "runtime", LEN_RUNTIME
);
3596 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(xhci
), &xhci_doorbell_ops
, xhci
,
3597 "doorbell", LEN_DOORBELL
);
3599 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3600 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3601 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3602 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3604 for (i
= 0; i
< xhci
->numports
; i
++) {
3605 XHCIPort
*port
= &xhci
->ports
[i
];
3606 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3608 memory_region_init_io(&port
->mem
, OBJECT(xhci
), &xhci_port_ops
, port
,
3610 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3613 pci_register_bar(dev
, 0,
3614 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3617 if (pci_bus_is_express(dev
->bus
) ||
3618 xhci_get_flag(xhci
, XHCI_FLAG_FORCE_PCIE_ENDCAP
)) {
3619 ret
= pcie_endpoint_cap_init(dev
, 0xa0);
3623 if (xhci
->msix
!= ON_OFF_AUTO_OFF
) {
3624 /* TODO check for errors, and should fail when msix=on */
3625 msix_init(dev
, xhci
->numintrs
,
3626 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3627 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3632 static void usb_xhci_exit(PCIDevice
*dev
)
3635 XHCIState
*xhci
= XHCI(dev
);
3637 trace_usb_xhci_exit();
3639 for (i
= 0; i
< xhci
->numslots
; i
++) {
3640 xhci_disable_slot(xhci
, i
+ 1);
3643 if (xhci
->mfwrap_timer
) {
3644 timer_del(xhci
->mfwrap_timer
);
3645 timer_free(xhci
->mfwrap_timer
);
3646 xhci
->mfwrap_timer
= NULL
;
3649 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_cap
);
3650 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_oper
);
3651 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_runtime
);
3652 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_doorbell
);
3654 for (i
= 0; i
< xhci
->numports
; i
++) {
3655 XHCIPort
*port
= &xhci
->ports
[i
];
3656 memory_region_del_subregion(&xhci
->mem
, &port
->mem
);
3659 /* destroy msix memory region */
3660 if (dev
->msix_table
&& dev
->msix_pba
3661 && dev
->msix_entry_used
) {
3662 msix_uninit(dev
, &xhci
->mem
, &xhci
->mem
);
3665 usb_bus_release(&xhci
->bus
);
3668 static int usb_xhci_post_load(void *opaque
, int version_id
)
3670 XHCIState
*xhci
= opaque
;
3671 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
3673 XHCIEPContext
*epctx
;
3674 dma_addr_t dcbaap
, pctx
;
3675 uint32_t slot_ctx
[4];
3677 int slotid
, epid
, state
, intr
;
3679 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3681 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3682 slot
= &xhci
->slots
[slotid
-1];
3683 if (!slot
->addressed
) {
3687 xhci_mask64(ldq_le_pci_dma(pci_dev
, dcbaap
+ 8 * slotid
));
3688 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3689 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3691 /* should not happen, but may trigger on guest bugs */
3693 slot
->addressed
= 0;
3696 assert(slot
->uport
&& slot
->uport
->dev
);
3698 for (epid
= 1; epid
<= 31; epid
++) {
3699 pctx
= slot
->ctx
+ 32 * epid
;
3700 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3701 state
= ep_ctx
[0] & EP_STATE_MASK
;
3702 if (state
== EP_DISABLED
) {
3705 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3706 slot
->eps
[epid
-1] = epctx
;
3707 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3708 epctx
->state
= state
;
3709 if (state
== EP_RUNNING
) {
3710 /* kick endpoint after vmload is finished */
3711 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
3716 for (intr
= 0; intr
< xhci
->numintrs
; intr
++) {
3717 if (xhci
->intr
[intr
].msix_used
) {
3718 msix_vector_use(pci_dev
, intr
);
3720 msix_vector_unuse(pci_dev
, intr
);
3727 static const VMStateDescription vmstate_xhci_ring
= {
3728 .name
= "xhci-ring",
3730 .fields
= (VMStateField
[]) {
3731 VMSTATE_UINT64(dequeue
, XHCIRing
),
3732 VMSTATE_BOOL(ccs
, XHCIRing
),
3733 VMSTATE_END_OF_LIST()
3737 static const VMStateDescription vmstate_xhci_port
= {
3738 .name
= "xhci-port",
3740 .fields
= (VMStateField
[]) {
3741 VMSTATE_UINT32(portsc
, XHCIPort
),
3742 VMSTATE_END_OF_LIST()
3746 static const VMStateDescription vmstate_xhci_slot
= {
3747 .name
= "xhci-slot",
3749 .fields
= (VMStateField
[]) {
3750 VMSTATE_BOOL(enabled
, XHCISlot
),
3751 VMSTATE_BOOL(addressed
, XHCISlot
),
3752 VMSTATE_END_OF_LIST()
3756 static const VMStateDescription vmstate_xhci_event
= {
3757 .name
= "xhci-event",
3759 .fields
= (VMStateField
[]) {
3760 VMSTATE_UINT32(type
, XHCIEvent
),
3761 VMSTATE_UINT32(ccode
, XHCIEvent
),
3762 VMSTATE_UINT64(ptr
, XHCIEvent
),
3763 VMSTATE_UINT32(length
, XHCIEvent
),
3764 VMSTATE_UINT32(flags
, XHCIEvent
),
3765 VMSTATE_UINT8(slotid
, XHCIEvent
),
3766 VMSTATE_UINT8(epid
, XHCIEvent
),
3767 VMSTATE_END_OF_LIST()
3771 static bool xhci_er_full(void *opaque
, int version_id
)
3776 static const VMStateDescription vmstate_xhci_intr
= {
3777 .name
= "xhci-intr",
3779 .fields
= (VMStateField
[]) {
3781 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3782 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3783 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3784 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3785 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3786 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3787 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3790 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3791 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3792 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3793 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3794 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3796 /* event queue (used if ring is full) */
3797 VMSTATE_BOOL(er_full_unused
, XHCIInterrupter
),
3798 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3799 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3800 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3802 vmstate_xhci_event
, XHCIEvent
),
3804 VMSTATE_END_OF_LIST()
3808 static const VMStateDescription vmstate_xhci
= {
3811 .post_load
= usb_xhci_post_load
,
3812 .fields
= (VMStateField
[]) {
3813 VMSTATE_PCI_DEVICE(parent_obj
, XHCIState
),
3814 VMSTATE_MSIX(parent_obj
, XHCIState
),
3816 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3817 vmstate_xhci_port
, XHCIPort
),
3818 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3819 vmstate_xhci_slot
, XHCISlot
),
3820 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3821 vmstate_xhci_intr
, XHCIInterrupter
),
3823 /* Operational Registers */
3824 VMSTATE_UINT32(usbcmd
, XHCIState
),
3825 VMSTATE_UINT32(usbsts
, XHCIState
),
3826 VMSTATE_UINT32(dnctrl
, XHCIState
),
3827 VMSTATE_UINT32(crcr_low
, XHCIState
),
3828 VMSTATE_UINT32(crcr_high
, XHCIState
),
3829 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3830 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3831 VMSTATE_UINT32(config
, XHCIState
),
3833 /* Runtime Registers & state */
3834 VMSTATE_INT64(mfindex_start
, XHCIState
),
3835 VMSTATE_TIMER_PTR(mfwrap_timer
, XHCIState
),
3836 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3838 VMSTATE_END_OF_LIST()
3842 static Property xhci_properties
[] = {
3843 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState
, msi
, ON_OFF_AUTO_AUTO
),
3844 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState
, msix
, ON_OFF_AUTO_AUTO
),
3845 DEFINE_PROP_BIT("superspeed-ports-first",
3846 XHCIState
, flags
, XHCI_FLAG_SS_FIRST
, true),
3847 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState
, flags
,
3848 XHCI_FLAG_FORCE_PCIE_ENDCAP
, false),
3849 DEFINE_PROP_BIT("streams", XHCIState
, flags
,
3850 XHCI_FLAG_ENABLE_STREAMS
, true),
3851 DEFINE_PROP_UINT32("intrs", XHCIState
, numintrs
, MAXINTRS
),
3852 DEFINE_PROP_UINT32("slots", XHCIState
, numslots
, MAXSLOTS
),
3853 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3854 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3855 DEFINE_PROP_END_OF_LIST(),
3858 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3860 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3861 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3863 dc
->vmsd
= &vmstate_xhci
;
3864 dc
->props
= xhci_properties
;
3865 dc
->reset
= xhci_reset
;
3866 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
3867 k
->realize
= usb_xhci_realize
;
3868 k
->exit
= usb_xhci_exit
;
3869 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3873 static const TypeInfo xhci_info
= {
3875 .parent
= TYPE_PCI_DEVICE
,
3876 .instance_size
= sizeof(XHCIState
),
3877 .class_init
= xhci_class_init
,
3881 static void nec_xhci_class_init(ObjectClass
*klass
, void *data
)
3883 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3885 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
3886 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
3890 static const TypeInfo nec_xhci_info
= {
3891 .name
= TYPE_NEC_XHCI
,
3892 .parent
= TYPE_XHCI
,
3893 .class_init
= nec_xhci_class_init
,
3896 static void qemu_xhci_class_init(ObjectClass
*klass
, void *data
)
3898 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3900 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
3901 k
->device_id
= PCI_DEVICE_ID_REDHAT_XHCI
;
3905 static const TypeInfo qemu_xhci_info
= {
3906 .name
= TYPE_QEMU_XHCI
,
3907 .parent
= TYPE_XHCI
,
3908 .class_init
= qemu_xhci_class_init
,
3911 static void xhci_register_types(void)
3913 type_register_static(&xhci_info
);
3914 type_register_static(&nec_xhci_info
);
3915 type_register_static(&qemu_xhci_info
);
3918 type_init(xhci_register_types
)