hw/riscv/spike.c

   1 /*
   2  * QEMU RISC-V Spike Board
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This provides a RISC-V Board with the following devices:
   8  *
   9  * 0) HTIF Console and Poweroff
  10  * 1) CLINT (Timer and IPI)
  11  * 2) PLIC (Platform Level Interrupt Controller)
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms and conditions of the GNU General Public License,
  15  * version 2 or later, as published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope it will be useful, but WITHOUT
  18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20  * more details.
  21  *
  22  * You should have received a copy of the GNU General Public License along with
  23  * this program.  If not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/log.h"
  28 #include "qemu/error-report.h"
  29 #include "qapi/error.h"
  30 #include "hw/boards.h"
  31 #include "hw/loader.h"
  32 #include "hw/sysbus.h"
  33 #include "target/riscv/cpu.h"
  34 #include "hw/riscv/riscv_htif.h"
  35 #include "hw/riscv/riscv_hart.h"
  36 #include "hw/riscv/sifive_clint.h"
  37 #include "hw/riscv/spike.h"
  38 #include "hw/riscv/boot.h"
  39 #include "chardev/char.h"
  40 #include "sysemu/arch_init.h"
  41 #include "sysemu/device_tree.h"
  42 #include "sysemu/qtest.h"
  43 #include "sysemu/sysemu.h"
  44 #include "exec/address-spaces.h"
  45
  46 #include <libfdt.h>
  47
  48 #if defined(TARGET_RISCV32)
  49 # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
  50 #else
  51 # define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
  52 #endif
  53
  54 static const struct MemmapEntry {
  55     hwaddr base;
  56     hwaddr size;
  57 } spike_memmap[] = {
  58     [SPIKE_MROM] =     {     0x1000,    0x11000 },
  59     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
  60     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
  61 };
  62
  63 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
  64     uint64_t mem_size, const char *cmdline)
  65 {
  66     void *fdt;
  67     int cpu;
  68     uint32_t *cells;
  69     char *nodename;
  70
  71     fdt = s->fdt = create_device_tree(&s->fdt_size);
  72     if (!fdt) {
  73         error_report("create_device_tree() failed");
  74         exit(1);
  75     }
  76
  77     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
  78     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
  79     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  80     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
  81
  82     qemu_fdt_add_subnode(fdt, "/htif");
  83     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
  84
  85     qemu_fdt_add_subnode(fdt, "/soc");
  86     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
  87     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
  88     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
  89     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
  90
  91     nodename = g_strdup_printf("/memory@%lx",
  92         (long)memmap[SPIKE_DRAM].base);
  93     qemu_fdt_add_subnode(fdt, nodename);
  94     qemu_fdt_setprop_cells(fdt, nodename, "reg",
  95         memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
  96         mem_size >> 32, mem_size);
  97     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
  98     g_free(nodename);
  99
 100     qemu_fdt_add_subnode(fdt, "/cpus");
 101     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 102         SIFIVE_CLINT_TIMEBASE_FREQ);
 103     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 104     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 105
 106     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 107         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 108         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 109         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 110         qemu_fdt_add_subnode(fdt, nodename);
 111 #if defined(TARGET_RISCV32)
 112         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 113 #else
 114         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 115 #endif
 116         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 117         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 118         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 119         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 120         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 121         qemu_fdt_add_subnode(fdt, intc);
 122         qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 123         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 124         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 125         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 126         g_free(isa);
 127         g_free(intc);
 128         g_free(nodename);
 129     }
 130
 131     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 132     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 133         nodename =
 134             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 135         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 136         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 137         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 138         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 139         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 140         g_free(nodename);
 141     }
 142     nodename = g_strdup_printf("/soc/clint@%lx",
 143         (long)memmap[SPIKE_CLINT].base);
 144     qemu_fdt_add_subnode(fdt, nodename);
 145     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 146     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 147         0x0, memmap[SPIKE_CLINT].base,
 148         0x0, memmap[SPIKE_CLINT].size);
 149     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 150         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 151     g_free(cells);
 152     g_free(nodename);
 153
 154     if (cmdline) {
 155         qemu_fdt_add_subnode(fdt, "/chosen");
 156         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 157     }
 158 }
 159
 160 static void spike_board_init(MachineState *machine)
 161 {
 162     const struct MemmapEntry *memmap = spike_memmap;
 163
 164     SpikeState *s = g_new0(SpikeState, 1);
 165     MemoryRegion *system_memory = get_system_memory();
 166     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 167     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 168     int i;
 169     unsigned int smp_cpus = machine->smp.cpus;
 170
 171     /* Initialize SOC */
 172     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 173                             TYPE_RISCV_HART_ARRAY);
 174     object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
 175                             &error_abort);
 176     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 177                             &error_abort);
 178     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
 179
 180     /* register system main memory (actual RAM) */
 181     memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
 182                            machine->ram_size, &error_fatal);
 183     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
 184         main_mem);
 185
 186     /* create device tree */
 187     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 188
 189     /* boot rom */
 190     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
 191                            memmap[SPIKE_MROM].size, &error_fatal);
 192     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
 193                                 mask_rom);
 194
 195     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 196                                  memmap[SPIKE_DRAM].base,
 197                                  htif_symbol_callback);
 198
 199     if (machine->kernel_filename) {
 200         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
 201                                                   htif_symbol_callback);
 202
 203         if (machine->initrd_filename) {
 204             hwaddr start;
 205             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 206                                            machine->ram_size, kernel_entry,
 207                                            &start);
 208             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 209                                   "linux,initrd-start", start);
 210             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 211                                   end);
 212         }
 213     }
 214
 215     /* reset vector */
 216     uint32_t reset_vec[8] = {
 217         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 218         0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 219         0xf1402573,                  /*     csrr   a0, mhartid  */
 220 #if defined(TARGET_RISCV32)
 221         0x0182a283,                  /*     lw     t0, 24(t0) */
 222 #elif defined(TARGET_RISCV64)
 223         0x0182b283,                  /*     ld     t0, 24(t0) */
 224 #endif
 225         0x00028067,                  /*     jr     t0 */
 226         0x00000000,
 227         memmap[SPIKE_DRAM].base,     /* start: .dword DRAM_BASE */
 228         0x00000000,
 229                                      /* dtb: */
 230     };
 231
 232     /* copy in the reset vector in little_endian byte order */
 233     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 234         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 235     }
 236     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 237                           memmap[SPIKE_MROM].base, &address_space_memory);
 238
 239     /* copy in the device tree */
 240     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 241             memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
 242         error_report("not enough space to store device-tree");
 243         exit(1);
 244     }
 245     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 246     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 247                           memmap[SPIKE_MROM].base + sizeof(reset_vec),
 248                           &address_space_memory);
 249
 250     /* initialize HTIF using symbols found in load_kernel */
 251     htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
 252
 253     /* Core Local Interruptor (timer and IPI) */
 254     sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
 255         smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 256         false);
 257 }
 258
 259 static void spike_machine_init(MachineClass *mc)
 260 {
 261     mc->desc = "RISC-V Spike Board";
 262     mc->init = spike_board_init;
 263     mc->max_cpus = 8;
 264     mc->is_default = true;
 265     mc->default_cpu_type = SPIKE_V1_10_0_CPU;
 266 }
 267
 268 DEFINE_MACHINE("spike", spike_machine_init)