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qom: Crash more nicely on object_property_get_link() failure
[qemu/ar7.git] / hw / arm / fsl-imx6.c
blob417ca6889cbbf6df3afc9e6185a31838fb443bac
1 /*
2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/usb/imx-usb-phy.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29 #include "chardev/char.h"
30 #include "qemu/error-report.h"
31 #include "qemu/module.h"
32
33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
34
35 #define NAME_SIZE 20
36
37 static void fsl_imx6_init(Object *obj)
38 {
39 MachineState *ms = MACHINE(qdev_get_machine());
40 FslIMX6State *s = FSL_IMX6(obj);
41 char name[NAME_SIZE];
42 int i;
43
44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
45 snprintf(name, NAME_SIZE, "cpu%d", i);
46 object_initialize_child(obj, name, &s->cpu[i],
47 ARM_CPU_TYPE_NAME("cortex-a9"));
48 }
49
50 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
51
52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
53
54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
55
56 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
57 snprintf(name, NAME_SIZE, "uart%d", i + 1);
58 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
59 }
60
61 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
62
63 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
64 snprintf(name, NAME_SIZE, "epit%d", i + 1);
65 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
66 }
67
68 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
69 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
70 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
71 }
72
73 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
74 snprintf(name, NAME_SIZE, "gpio%d", i + 1);
75 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
76 }
77
78 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
79 snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
80 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
81 }
82
83 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
84 snprintf(name, NAME_SIZE, "usbphy%d", i);
85 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
86 }
87 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
88 snprintf(name, NAME_SIZE, "usb%d", i);
89 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
90 }
91
92 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
93 snprintf(name, NAME_SIZE, "spi%d", i + 1);
94 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
95 }
96 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
97 snprintf(name, NAME_SIZE, "wdt%d", i);
98 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
99 }
100
101
102 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
103 }
104
105 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
106 {
107 MachineState *ms = MACHINE(qdev_get_machine());
108 FslIMX6State *s = FSL_IMX6(dev);
109 uint16_t i;
110 Error *err = NULL;
111 unsigned int smp_cpus = ms->smp.cpus;
112
113 if (smp_cpus > FSL_IMX6_NUM_CPUS) {
114 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
115 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
116 return;
117 }
118
119 for (i = 0; i < smp_cpus; i++) {
120
121 /* On uniprocessor, the CBAR is set to 0 */
122 if (smp_cpus > 1) {
123 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
124 "reset-cbar", &error_abort);
125 }
126
127 /* All CPU but CPU 0 start in power off mode */
128 if (i) {
129 object_property_set_bool(OBJECT(&s->cpu[i]), true,
130 "start-powered-off", &error_abort);
131 }
132
133 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, &err)) {
134 error_propagate(errp, err);
135 return;
136 }
137 }
138
139 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
140 &error_abort);
141
142 object_property_set_int(OBJECT(&s->a9mpcore),
143 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
144 &error_abort);
145
146 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err)) {
147 error_propagate(errp, err);
148 return;
149 }
150 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
151
152 for (i = 0; i < smp_cpus; i++) {
153 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
154 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
156 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
157 }
158
159 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err)) {
160 error_propagate(errp, err);
161 return;
162 }
163 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
164
165 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), &err)) {
166 error_propagate(errp, err);
167 return;
168 }
169 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
170
171 /* Initialize all UARTs */
172 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
173 static const struct {
174 hwaddr addr;
175 unsigned int irq;
176 } serial_table[FSL_IMX6_NUM_UARTS] = {
177 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
178 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
179 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
180 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
181 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
182 };
183
184 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
185
186 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err)) {
187 error_propagate(errp, err);
188 return;
189 }
190
191 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
192 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
193 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
194 serial_table[i].irq));
195 }
196
197 s->gpt.ccm = IMX_CCM(&s->ccm);
198
199 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err)) {
200 error_propagate(errp, err);
201 return;
202 }
203
204 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
205 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
206 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
207 FSL_IMX6_GPT_IRQ));
208
209 /* Initialize all EPIT timers */
210 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
211 static const struct {
212 hwaddr addr;
213 unsigned int irq;
214 } epit_table[FSL_IMX6_NUM_EPITS] = {
215 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
216 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
217 };
218
219 s->epit[i].ccm = IMX_CCM(&s->ccm);
220
221 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err)) {
222 error_propagate(errp, err);
223 return;
224 }
225
226 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
227 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
228 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
229 epit_table[i].irq));
230 }
231
232 /* Initialize all I2C */
233 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
234 static const struct {
235 hwaddr addr;
236 unsigned int irq;
237 } i2c_table[FSL_IMX6_NUM_I2CS] = {
238 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
239 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
240 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
241 };
242
243 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err)) {
244 error_propagate(errp, err);
245 return;
246 }
247
248 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
249 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
250 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
251 i2c_table[i].irq));
252 }
253
254 /* Initialize all GPIOs */
255 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
256 static const struct {
257 hwaddr addr;
258 unsigned int irq_low;
259 unsigned int irq_high;
260 } gpio_table[FSL_IMX6_NUM_GPIOS] = {
261 {
262 FSL_IMX6_GPIO1_ADDR,
263 FSL_IMX6_GPIO1_LOW_IRQ,
264 FSL_IMX6_GPIO1_HIGH_IRQ
265 },
266 {
267 FSL_IMX6_GPIO2_ADDR,
268 FSL_IMX6_GPIO2_LOW_IRQ,
269 FSL_IMX6_GPIO2_HIGH_IRQ
270 },
271 {
272 FSL_IMX6_GPIO3_ADDR,
273 FSL_IMX6_GPIO3_LOW_IRQ,
274 FSL_IMX6_GPIO3_HIGH_IRQ
275 },
276 {
277 FSL_IMX6_GPIO4_ADDR,
278 FSL_IMX6_GPIO4_LOW_IRQ,
279 FSL_IMX6_GPIO4_HIGH_IRQ
280 },
281 {
282 FSL_IMX6_GPIO5_ADDR,
283 FSL_IMX6_GPIO5_LOW_IRQ,
284 FSL_IMX6_GPIO5_HIGH_IRQ
285 },
286 {
287 FSL_IMX6_GPIO6_ADDR,
288 FSL_IMX6_GPIO6_LOW_IRQ,
289 FSL_IMX6_GPIO6_HIGH_IRQ
290 },
291 {
292 FSL_IMX6_GPIO7_ADDR,
293 FSL_IMX6_GPIO7_LOW_IRQ,
294 FSL_IMX6_GPIO7_HIGH_IRQ
295 },
296 };
297
298 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
299 &error_abort);
300 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
301 &error_abort);
302 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err)) {
303 error_propagate(errp, err);
304 return;
305 }
306
307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
309 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
310 gpio_table[i].irq_low));
311 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
312 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
313 gpio_table[i].irq_high));
314 }
315
316 /* Initialize all SDHC */
317 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
318 static const struct {
319 hwaddr addr;
320 unsigned int irq;
321 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
322 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
323 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
324 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
325 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
326 };
327
328 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
329 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
330 &error_abort);
331 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
332 "capareg",
333 &error_abort);
334 object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX,
335 "vendor",
336 &error_abort);
337 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err)) {
338 error_propagate(errp, err);
339 return;
340 }
341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
343 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
344 esdhc_table[i].irq));
345 }
346
347 /* USB */
348 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
349 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
351 FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
352 }
353 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
354 static const int FSL_IMX6_USBn_IRQ[] = {
355 FSL_IMX6_USB_OTG_IRQ,
356 FSL_IMX6_USB_HOST1_IRQ,
357 FSL_IMX6_USB_HOST2_IRQ,
358 FSL_IMX6_USB_HOST3_IRQ,
359 };
360
361 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
362 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
363 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
365 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
366 FSL_IMX6_USBn_IRQ[i]));
367 }
368
369 /* Initialize all ECSPI */
370 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
371 static const struct {
372 hwaddr addr;
373 unsigned int irq;
374 } spi_table[FSL_IMX6_NUM_ECSPIS] = {
375 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
376 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
377 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
378 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
379 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
380 };
381
382 /* Initialize the SPI */
383 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) {
384 error_propagate(errp, err);
385 return;
386 }
387
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
390 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
391 spi_table[i].irq));
392 }
393
394 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), &err)) {
396 error_propagate(errp, err);
397 return;
398 }
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
401 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
402 FSL_IMX6_ENET_MAC_IRQ));
403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
404 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
405 FSL_IMX6_ENET_MAC_1588_IRQ));
406
407 /*
408 * Watchdog
409 */
410 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
411 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
412 FSL_IMX6_WDOG1_ADDR,
413 FSL_IMX6_WDOG2_ADDR,
414 };
415 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
416 FSL_IMX6_WDOG1_IRQ,
417 FSL_IMX6_WDOG2_IRQ,
418 };
419
420 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
421 &error_abort);
422 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
423
424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
426 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
427 FSL_IMX6_WDOGn_IRQ[i]));
428 }
429
430 /* ROM memory */
431 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
432 FSL_IMX6_ROM_SIZE, &err);
433 if (err) {
434 error_propagate(errp, err);
435 return;
436 }
437 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
438 &s->rom);
439
440 /* CAAM memory */
441 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
442 FSL_IMX6_CAAM_MEM_SIZE, &err);
443 if (err) {
444 error_propagate(errp, err);
445 return;
446 }
447 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
448 &s->caam);
449
450 /* OCRAM memory */
451 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
452 &err);
453 if (err) {
454 error_propagate(errp, err);
455 return;
456 }
457 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
458 &s->ocram);
459
460 /* internal OCRAM (256 KB) is aliased over 1 MB */
461 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
462 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
463 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
464 &s->ocram_alias);
465 }
466
467 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
468 {
469 DeviceClass *dc = DEVICE_CLASS(oc);
470
471 dc->realize = fsl_imx6_realize;
472 dc->desc = "i.MX6 SOC";
473 /* Reason: Uses serial_hd() in the realize() function */
474 dc->user_creatable = false;
475 }
476
477 static const TypeInfo fsl_imx6_type_info = {
478 .name = TYPE_FSL_IMX6,
479 .parent = TYPE_DEVICE,
480 .instance_size = sizeof(FslIMX6State),
481 .instance_init = fsl_imx6_init,
482 .class_init = fsl_imx6_class_init,
483 };
484
485 static void fsl_imx6_register_types(void)
486 {
487 type_register_static(&fsl_imx6_type_info);
488 }
489
490 type_init(fsl_imx6_register_types)
AR7 emulation for QEMU