2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
18 #include "qemu/osdep.h"
20 #include "hw/pci/pci.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu-common.h"
26 #include "qemu/bswap.h"
27 #include "hw/pci/msix.h"
28 #include "hw/pci/msi.h"
31 #include "vmxnet_debug.h"
32 #include "vmware_utils.h"
33 #include "net_tx_pkt.h"
34 #include "net_rx_pkt.h"
36 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
37 #define VMXNET3_MSIX_BAR_SIZE 0x2000
38 #define MIN_BUF_SIZE 60
40 /* Compatibility flags for migration */
41 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
43 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
44 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
46 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
48 #define VMXNET3_EXP_EP_OFFSET (0x48)
49 #define VMXNET3_MSI_OFFSET(s) \
50 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
51 #define VMXNET3_MSIX_OFFSET(s) \
52 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
53 #define VMXNET3_DSN_OFFSET (0x100)
55 #define VMXNET3_BAR0_IDX (0)
56 #define VMXNET3_BAR1_IDX (1)
57 #define VMXNET3_MSIX_BAR_IDX (2)
59 #define VMXNET3_OFF_MSIX_TABLE (0x000)
60 #define VMXNET3_OFF_MSIX_PBA(s) \
61 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
63 /* Link speed in Mbps should be shifted by 16 */
64 #define VMXNET3_LINK_SPEED (1000 << 16)
66 /* Link status: 1 - up, 0 - down. */
67 #define VMXNET3_LINK_STATUS_UP 0x1
69 /* Least significant bit should be set for revision and version */
70 #define VMXNET3_UPT_REVISION 0x1
71 #define VMXNET3_DEVICE_REVISION 0x1
73 /* Number of interrupt vectors for non-MSIx modes */
74 #define VMXNET3_MAX_NMSIX_INTRS (1)
76 /* Macros for rings descriptors access */
77 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
78 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
80 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
81 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
83 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
84 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
86 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
87 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
89 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
90 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
92 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
93 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
95 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
96 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
98 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
99 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
101 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
102 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
104 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
105 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
107 /* Macros for guest driver shared area access */
108 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
109 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
111 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
112 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
114 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
115 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
117 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
118 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
120 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
121 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
123 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
124 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
126 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
128 typedef struct VMXNET3Class
{
129 PCIDeviceClass parent_class
;
130 DeviceRealize parent_dc_realize
;
133 #define TYPE_VMXNET3 "vmxnet3"
134 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
136 #define VMXNET3_DEVICE_CLASS(klass) \
137 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
138 #define VMXNET3_DEVICE_GET_CLASS(obj) \
139 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
141 /* Cyclic ring abstraction */
150 static inline void vmxnet3_ring_init(PCIDevice
*d
,
159 ring
->cell_size
= cell_size
;
160 ring
->gen
= VMXNET3_INIT_GEN
;
164 vmw_shmem_set(d
, pa
, 0, size
* cell_size
);
168 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
169 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
170 (ring_name), (ridx), \
171 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
173 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
175 if (++ring
->next
>= ring
->size
) {
181 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
183 if (ring
->next
-- == 0) {
184 ring
->next
= ring
->size
- 1;
189 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
191 return ring
->pa
+ ring
->next
* ring
->cell_size
;
194 static inline void vmxnet3_ring_read_curr_cell(PCIDevice
*d
, Vmxnet3Ring
*ring
,
197 vmw_shmem_read(d
, vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
200 static inline void vmxnet3_ring_write_curr_cell(PCIDevice
*d
, Vmxnet3Ring
*ring
,
203 vmw_shmem_write(d
, vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
206 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
211 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
216 /* Debug trace-related functions */
218 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
220 VMW_PKPRN("TX DESCR: "
221 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
222 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
223 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
224 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
, descr
->rsvd
,
225 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
226 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
230 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
232 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
233 "csum_start: %d, csum_offset: %d",
234 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
235 vhdr
->csum_start
, vhdr
->csum_offset
);
239 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
241 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
242 "dtype: %d, ext1: %d, btype: %d",
243 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
,
244 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
247 /* Device state and helper functions */
248 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
252 Vmxnet3Ring comp_ring
;
256 struct UPT1_TxStats txq_stats
;
260 Vmxnet3Ring rx_ring
[VMXNET3_RX_RINGS_PER_QUEUE
];
261 Vmxnet3Ring comp_ring
;
264 struct UPT1_RxStats rxq_stats
;
274 PCIDevice parent_obj
;
279 MemoryRegion msix_bar
;
281 Vmxnet3RxqDescr rxq_descr
[VMXNET3_DEVICE_MAX_RX_QUEUES
];
282 Vmxnet3TxqDescr txq_descr
[VMXNET3_DEVICE_MAX_TX_QUEUES
];
284 /* Whether MSI-X support was installed successfully */
287 hwaddr temp_shared_guest_driver_memory
;
291 /* This boolean tells whether RX packet being indicated has to */
292 /* be split into head and body chunks from different RX rings */
293 bool rx_packets_compound
;
295 bool rx_vlan_stripping
;
303 /* Maximum number of fragments for indicated TX packets */
304 uint32_t max_tx_frags
;
306 /* Maximum number of fragments for indicated RX packets */
307 uint16_t max_rx_frags
;
309 /* Index for events interrupt */
310 uint8_t event_int_idx
;
312 /* Whether automatic interrupts masking enabled */
313 bool auto_int_masking
;
317 /* TX packets to QEMU interface */
318 struct NetTxPkt
*tx_pkt
;
319 uint32_t offload_mode
;
320 uint32_t cso_or_gso_size
;
324 struct NetRxPkt
*rx_pkt
;
327 bool skip_current_tx_pkt
;
329 uint32_t device_active
;
330 uint32_t last_command
;
332 uint32_t link_status_and_speed
;
334 Vmxnet3IntState interrupt_states
[VMXNET3_MAX_INTRS
];
336 uint32_t temp_mac
; /* To store the low part first */
339 uint32_t vlan_table
[VMXNET3_VFT_SIZE
];
342 uint32_t mcast_list_len
;
343 uint32_t mcast_list_buff_size
; /* needed for live migration. */
345 /* Compatibility flags for migration */
346 uint32_t compat_flags
;
349 /* Interrupt management */
352 * This function returns sign whether interrupt line is in asserted state
353 * This depends on the type of interrupt used. For INTX interrupt line will
354 * be asserted until explicit deassertion, for MSI(X) interrupt line will
355 * be deasserted automatically due to notification semantics of the MSI(X)
358 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
360 PCIDevice
*d
= PCI_DEVICE(s
);
362 if (s
->msix_used
&& msix_enabled(d
)) {
363 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
364 msix_notify(d
, int_idx
);
367 if (msi_enabled(d
)) {
368 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
369 msi_notify(d
, int_idx
);
373 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
378 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
380 PCIDevice
*d
= PCI_DEVICE(s
);
383 * This function should never be called for MSI(X) interrupts
384 * because deassertion never required for message interrupts
386 assert(!s
->msix_used
|| !msix_enabled(d
));
388 * This function should never be called for MSI(X) interrupts
389 * because deassertion never required for message interrupts
391 assert(!msi_enabled(d
));
393 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
397 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
399 if (!s
->interrupt_states
[lidx
].is_pending
&&
400 s
->interrupt_states
[lidx
].is_asserted
) {
401 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
402 _vmxnet3_deassert_interrupt_line(s
, lidx
);
403 s
->interrupt_states
[lidx
].is_asserted
= false;
407 if (s
->interrupt_states
[lidx
].is_pending
&&
408 !s
->interrupt_states
[lidx
].is_masked
&&
409 !s
->interrupt_states
[lidx
].is_asserted
) {
410 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
411 s
->interrupt_states
[lidx
].is_asserted
=
412 _vmxnet3_assert_interrupt_line(s
, lidx
);
413 s
->interrupt_states
[lidx
].is_pending
= false;
418 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
420 PCIDevice
*d
= PCI_DEVICE(s
);
421 s
->interrupt_states
[lidx
].is_pending
= true;
422 vmxnet3_update_interrupt_line_state(s
, lidx
);
424 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
428 if (msi_enabled(d
) && s
->auto_int_masking
) {
435 s
->interrupt_states
[lidx
].is_masked
= true;
436 vmxnet3_update_interrupt_line_state(s
, lidx
);
439 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
441 return s
->interrupt_states
[lidx
].is_asserted
;
444 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
446 s
->interrupt_states
[int_idx
].is_pending
= false;
447 if (s
->auto_int_masking
) {
448 s
->interrupt_states
[int_idx
].is_masked
= true;
450 vmxnet3_update_interrupt_line_state(s
, int_idx
);
454 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
456 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
457 vmxnet3_update_interrupt_line_state(s
, lidx
);
460 static bool vmxnet3_verify_driver_magic(PCIDevice
*d
, hwaddr dshmem
)
462 return (VMXNET3_READ_DRV_SHARED32(d
, dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
465 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
466 #define VMXNET3_MAKE_BYTE(byte_num, val) \
467 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
469 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
471 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
472 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
473 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
474 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
475 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
476 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
478 VMW_CFPRN("Variable MAC: " MAC_FMT
, MAC_ARG(s
->conf
.macaddr
.a
));
480 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
483 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
485 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
486 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
487 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
488 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
491 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
493 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
494 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
498 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
500 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
504 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
506 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
510 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
512 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
516 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
518 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
522 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
524 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
527 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32_t tx_ridx
)
529 struct Vmxnet3_TxCompDesc txcq_descr
;
530 PCIDevice
*d
= PCI_DEVICE(s
);
532 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
534 memset(&txcq_descr
, 0, sizeof(txcq_descr
));
535 txcq_descr
.txdIdx
= tx_ridx
;
536 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
538 vmxnet3_ring_write_curr_cell(d
, &s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
540 /* Flush changes in TX descriptor before changing the counter value */
543 vmxnet3_inc_tx_completion_counter(s
, qidx
);
544 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
548 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
550 switch (s
->offload_mode
) {
551 case VMXNET3_OM_NONE
:
552 net_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
555 case VMXNET3_OM_CSUM
:
556 net_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
557 VMW_PKPRN("L4 CSO requested\n");
561 net_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
563 net_tx_pkt_update_ip_checksums(s
->tx_pkt
);
564 VMW_PKPRN("GSO offload requested.");
568 g_assert_not_reached();
576 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
577 const struct Vmxnet3_TxDesc
*txd
)
579 s
->offload_mode
= txd
->om
;
580 s
->cso_or_gso_size
= txd
->msscof
;
582 s
->needs_vlan
= txd
->ti
;
586 VMXNET3_PKT_STATUS_OK
,
587 VMXNET3_PKT_STATUS_ERROR
,
588 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
589 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
593 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
594 Vmxnet3PktStatus status
)
596 size_t tot_len
= net_tx_pkt_get_total_len(s
->tx_pkt
);
597 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
600 case VMXNET3_PKT_STATUS_OK
:
601 switch (net_tx_pkt_get_packet_type(s
->tx_pkt
)) {
603 stats
->bcastPktsTxOK
++;
604 stats
->bcastBytesTxOK
+= tot_len
;
607 stats
->mcastPktsTxOK
++;
608 stats
->mcastBytesTxOK
+= tot_len
;
611 stats
->ucastPktsTxOK
++;
612 stats
->ucastBytesTxOK
+= tot_len
;
615 g_assert_not_reached();
618 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
620 * According to VMWARE headers this statistic is a number
621 * of packets after segmentation but since we don't have
622 * this information in QEMU model, the best we can do is to
623 * provide number of non-segmented packets
625 stats
->TSOPktsTxOK
++;
626 stats
->TSOBytesTxOK
+= tot_len
;
630 case VMXNET3_PKT_STATUS_DISCARD
:
631 stats
->pktsTxDiscard
++;
634 case VMXNET3_PKT_STATUS_ERROR
:
635 stats
->pktsTxError
++;
639 g_assert_not_reached();
644 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
646 Vmxnet3PktStatus status
)
648 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
649 size_t tot_len
= net_rx_pkt_get_total_len(s
->rx_pkt
);
652 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
653 stats
->pktsRxOutOfBuf
++;
656 case VMXNET3_PKT_STATUS_ERROR
:
657 stats
->pktsRxError
++;
659 case VMXNET3_PKT_STATUS_OK
:
660 switch (net_rx_pkt_get_packet_type(s
->rx_pkt
)) {
662 stats
->bcastPktsRxOK
++;
663 stats
->bcastBytesRxOK
+= tot_len
;
666 stats
->mcastPktsRxOK
++;
667 stats
->mcastBytesRxOK
+= tot_len
;
670 stats
->ucastPktsRxOK
++;
671 stats
->ucastBytesRxOK
+= tot_len
;
674 g_assert_not_reached();
677 if (tot_len
> s
->mtu
) {
678 stats
->LROPktsRxOK
++;
679 stats
->LROBytesRxOK
+= tot_len
;
683 g_assert_not_reached();
688 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
690 struct Vmxnet3_TxDesc
*txd
,
693 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
694 PCIDevice
*d
= PCI_DEVICE(s
);
696 vmxnet3_ring_read_curr_cell(d
, ring
, txd
);
697 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
698 /* Only read after generation field verification */
700 /* Re-read to be sure we got the latest version */
701 vmxnet3_ring_read_curr_cell(d
, ring
, txd
);
702 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
703 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
704 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
712 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
714 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
716 if (!vmxnet3_setup_tx_offloads(s
)) {
717 status
= VMXNET3_PKT_STATUS_ERROR
;
722 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s
->tx_pkt
));
723 net_tx_pkt_dump(s
->tx_pkt
);
725 if (!net_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
726 status
= VMXNET3_PKT_STATUS_DISCARD
;
731 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
732 return (status
== VMXNET3_PKT_STATUS_OK
);
735 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
737 struct Vmxnet3_TxDesc txd
;
743 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
747 vmxnet3_dump_tx_descr(&txd
);
749 if (!s
->skip_current_tx_pkt
) {
750 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
751 data_pa
= le64_to_cpu(txd
.addr
);
753 if (!net_tx_pkt_add_raw_fragment(s
->tx_pkt
,
756 s
->skip_current_tx_pkt
= true;
761 vmxnet3_tx_retrieve_metadata(s
, &txd
);
766 if (!s
->skip_current_tx_pkt
&& net_tx_pkt_parse(s
->tx_pkt
)) {
768 net_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
771 vmxnet3_send_packet(s
, qidx
);
773 vmxnet3_on_tx_done_update_stats(s
, qidx
,
774 VMXNET3_PKT_STATUS_ERROR
);
777 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
779 s
->skip_current_tx_pkt
= false;
780 net_tx_pkt_reset(s
->tx_pkt
);
786 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
787 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
789 PCIDevice
*d
= PCI_DEVICE(s
);
791 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
792 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
793 vmxnet3_ring_read_curr_cell(d
, ring
, dbuf
);
796 static inline uint8_t
797 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
799 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
803 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
806 struct Vmxnet3_RxCompDesc rxcd
;
809 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
811 pci_dma_read(PCI_DEVICE(s
),
812 daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
813 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
815 if (rxcd
.gen
!= ring_gen
) {
816 *descr_gen
= ring_gen
;
817 vmxnet3_inc_rx_completion_counter(s
, qidx
);
825 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
827 vmxnet3_dec_rx_completion_counter(s
, qidx
);
831 #define RX_HEAD_BODY_RING (0)
832 #define RX_BODY_ONLY_RING (1)
835 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
836 struct Vmxnet3_RxDesc
*descr_buf
,
842 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
843 descr_buf
, descr_idx
);
845 /* If no more free descriptors - return */
846 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
847 if (descr_buf
->gen
!= ring_gen
) {
851 /* Only read after generation field verification */
853 /* Re-read to be sure we got the latest version */
854 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
855 descr_buf
, descr_idx
);
857 /* Mark current descriptor as used/skipped */
858 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
860 /* If this is what we are looking for - return */
861 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
862 *ridx
= RX_HEAD_BODY_RING
;
869 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
870 struct Vmxnet3_RxDesc
*d
,
874 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
876 /* Try to find corresponding descriptor in head/body ring */
877 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
878 /* Only read after generation field verification */
880 /* Re-read to be sure we got the latest version */
881 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
882 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
883 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
884 *ridx
= RX_HEAD_BODY_RING
;
890 * If there is no free descriptors on head/body ring or next free
891 * descriptor is a head descriptor switch to body only ring
893 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
895 /* If no more free descriptors - return */
896 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
897 /* Only read after generation field verification */
899 /* Re-read to be sure we got the latest version */
900 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
901 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
902 *ridx
= RX_BODY_ONLY_RING
;
903 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
911 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
912 struct Vmxnet3_RxDesc
*descr_buf
,
916 if (is_head
|| !s
->rx_packets_compound
) {
917 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
919 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
923 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
924 * the implementation always passes an RxCompDesc with a "Checksum
925 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
926 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
928 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
929 * and place a fully computed checksum into the tcp/udp header.
930 * Otherwise, the OS driver will receive a checksum-correct indication
931 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
932 * having just the pseudo header csum value.
934 * While this is not a problem if packet is destined for local delivery,
935 * in the case the host OS performs forwarding, it will forward an
936 * incorrectly checksummed packet.
938 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt
*pkt
,
939 const void *pkt_data
,
942 struct virtio_net_hdr
*vhdr
;
943 bool isip4
, isip6
, istcp
, isudp
;
947 if (!net_rx_pkt_has_virt_hdr(pkt
)) {
951 vhdr
= net_rx_pkt_get_vhdr(pkt
);
952 if (!VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
956 net_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
957 if (!(isip4
|| isip6
) || !(istcp
|| isudp
)) {
961 vmxnet3_dump_virt_hdr(vhdr
);
963 /* Validate packet len: csum_start + scum_offset + length of csum field */
964 if (pkt_len
< (vhdr
->csum_start
+ vhdr
->csum_offset
+ 2)) {
965 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
966 "cannot calculate checksum",
967 pkt_len
, vhdr
->csum_start
, vhdr
->csum_offset
);
971 data
= (uint8_t *)pkt_data
+ vhdr
->csum_start
;
972 len
= pkt_len
- vhdr
->csum_start
;
973 /* Put the checksum obtained into the packet */
974 stw_be_p(data
+ vhdr
->csum_offset
, net_raw_checksum(data
, len
));
976 vhdr
->flags
&= ~VIRTIO_NET_HDR_F_NEEDS_CSUM
;
977 vhdr
->flags
|= VIRTIO_NET_HDR_F_DATA_VALID
;
980 static void vmxnet3_rx_update_descr(struct NetRxPkt
*pkt
,
981 struct Vmxnet3_RxCompDesc
*rxcd
)
984 bool isip4
, isip6
, istcp
, isudp
;
985 struct virtio_net_hdr
*vhdr
;
986 uint8_t offload_type
;
988 if (net_rx_pkt_is_vlan_stripped(pkt
)) {
990 rxcd
->tci
= net_rx_pkt_get_vlan_tag(pkt
);
993 if (!net_rx_pkt_has_virt_hdr(pkt
)) {
997 vhdr
= net_rx_pkt_get_vhdr(pkt
);
999 * Checksum is valid when lower level tell so or when lower level
1000 * requires checksum offload telling that packet produced/bridged
1001 * locally and did travel over network after last checksum calculation
1004 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
1005 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
1007 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
1008 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
1010 if (!csum_ok
&& !is_gso
) {
1014 net_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
1015 if ((!istcp
&& !isudp
) || (!isip4
&& !isip6
)) {
1020 rxcd
->v4
= isip4
? 1 : 0;
1021 rxcd
->v6
= isip6
? 1 : 0;
1022 rxcd
->tcp
= istcp
? 1 : 0;
1023 rxcd
->udp
= isudp
? 1 : 0;
1024 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
1033 vmxnet3_pci_dma_writev(PCIDevice
*pci_dev
,
1034 const struct iovec
*iov
,
1035 size_t start_iov_off
,
1037 size_t bytes_to_copy
)
1039 size_t curr_off
= 0;
1042 while (bytes_to_copy
) {
1043 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
1045 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
1047 pci_dma_write(pci_dev
, target_addr
+ copied
,
1048 iov
->iov_base
+ start_iov_off
- curr_off
,
1051 copied
+= chunk_len
;
1052 start_iov_off
+= chunk_len
;
1053 curr_off
= start_iov_off
;
1054 bytes_to_copy
-= chunk_len
;
1056 curr_off
+= iov
->iov_len
;
1063 vmxnet3_indicate_packet(VMXNET3State
*s
)
1065 struct Vmxnet3_RxDesc rxd
;
1066 PCIDevice
*d
= PCI_DEVICE(s
);
1067 bool is_head
= true;
1069 uint32_t rx_ridx
= 0;
1071 struct Vmxnet3_RxCompDesc rxcd
;
1072 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
1073 hwaddr new_rxcd_pa
= 0;
1074 hwaddr ready_rxcd_pa
= 0;
1075 struct iovec
*data
= net_rx_pkt_get_iovec(s
->rx_pkt
);
1076 size_t bytes_copied
= 0;
1077 size_t bytes_left
= net_rx_pkt_get_total_len(s
->rx_pkt
);
1078 uint16_t num_frags
= 0;
1081 net_rx_pkt_dump(s
->rx_pkt
);
1083 while (bytes_left
> 0) {
1085 /* cannot add more frags to packet */
1086 if (num_frags
== s
->max_rx_frags
) {
1090 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
1095 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1099 chunk_size
= MIN(bytes_left
, rxd
.len
);
1100 vmxnet3_pci_dma_writev(d
, data
, bytes_copied
,
1101 le64_to_cpu(rxd
.addr
), chunk_size
);
1102 bytes_copied
+= chunk_size
;
1103 bytes_left
-= chunk_size
;
1105 vmxnet3_dump_rx_descr(&rxd
);
1107 if (ready_rxcd_pa
!= 0) {
1108 pci_dma_write(d
, ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1111 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1112 rxcd
.rxdIdx
= rxd_idx
;
1113 rxcd
.len
= chunk_size
;
1115 rxcd
.gen
= new_rxcd_gen
;
1116 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1118 if (bytes_left
== 0) {
1119 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1122 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1123 "sop %d csum_correct %lu",
1124 (unsigned long) rx_ridx
,
1125 (unsigned long) rxcd
.rxdIdx
,
1126 (unsigned long) rxcd
.len
,
1128 (unsigned long) rxcd
.tuc
);
1131 ready_rxcd_pa
= new_rxcd_pa
;
1136 if (ready_rxcd_pa
!= 0) {
1138 rxcd
.err
= (bytes_left
!= 0);
1140 pci_dma_write(d
, ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1142 /* Flush RX descriptor changes */
1146 if (new_rxcd_pa
!= 0) {
1147 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1150 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1152 if (bytes_left
== 0) {
1153 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1155 } else if (num_frags
== s
->max_rx_frags
) {
1156 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1159 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1160 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1166 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1167 uint64_t val
, unsigned size
)
1169 VMXNET3State
*s
= opaque
;
1171 if (!s
->device_active
) {
1175 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1176 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1178 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1180 assert(tx_queue_idx
<= s
->txq_num
);
1181 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1185 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1186 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1187 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1190 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1192 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1196 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1197 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1198 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1199 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1203 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1204 (uint64_t) addr
, val
, size
);
1208 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1210 VMXNET3State
*s
= opaque
;
1212 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1213 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1214 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1216 return s
->interrupt_states
[l
].is_masked
;
1219 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1223 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1226 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1227 s
->interrupt_states
[i
].is_asserted
= false;
1228 s
->interrupt_states
[i
].is_pending
= false;
1229 s
->interrupt_states
[i
].is_masked
= true;
1233 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1235 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1236 VMW_CFPRN("MAC address set to: " MAC_FMT
, MAC_ARG(s
->conf
.macaddr
.a
));
1239 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1241 if (s
->device_active
) {
1242 VMW_CBPRN("Deactivating vmxnet3...");
1243 net_tx_pkt_reset(s
->tx_pkt
);
1244 net_tx_pkt_uninit(s
->tx_pkt
);
1245 net_rx_pkt_uninit(s
->rx_pkt
);
1246 s
->device_active
= false;
1250 static void vmxnet3_reset(VMXNET3State
*s
)
1252 VMW_CBPRN("Resetting vmxnet3...");
1254 vmxnet3_deactivate_device(s
);
1255 vmxnet3_reset_interrupt_states(s
);
1258 s
->skip_current_tx_pkt
= false;
1261 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1263 PCIDevice
*d
= PCI_DEVICE(s
);
1265 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
,
1266 devRead
.rxFilterConf
.rxMode
);
1267 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1270 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1273 PCIDevice
*d
= PCI_DEVICE(s
);
1275 /* Copy configuration from shared memory */
1276 VMXNET3_READ_DRV_SHARED(d
, s
->drv_shmem
,
1277 devRead
.rxFilterConf
.vfTable
,
1279 sizeof(s
->vlan_table
));
1281 /* Invert byte order when needed */
1282 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1283 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1286 /* Dump configuration for debugging purposes */
1287 VMW_CFPRN("Configured VLANs:");
1288 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1289 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1290 VMW_CFPRN("\tVLAN %d is present", i
);
1295 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1297 PCIDevice
*d
= PCI_DEVICE(s
);
1299 uint16_t list_bytes
=
1300 VMXNET3_READ_DRV_SHARED16(d
, s
->drv_shmem
,
1301 devRead
.rxFilterConf
.mfTableLen
);
1303 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1305 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1306 if (!s
->mcast_list
) {
1307 if (s
->mcast_list_len
== 0) {
1308 VMW_CFPRN("Current multicast list is empty");
1310 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1313 s
->mcast_list_len
= 0;
1316 hwaddr mcast_list_pa
=
1317 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
,
1318 devRead
.rxFilterConf
.mfTablePA
);
1320 pci_dma_read(d
, mcast_list_pa
, s
->mcast_list
, list_bytes
);
1322 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1323 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1324 VMW_CFPRN("\t" MAC_FMT
, MAC_ARG(s
->mcast_list
[i
].a
));
1329 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1331 vmxnet3_update_rx_mode(s
);
1332 vmxnet3_update_vlan_filters(s
);
1333 vmxnet3_update_mcast_filters(s
);
1336 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1338 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1339 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1340 return interrupt_mode
;
1343 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1346 PCIDevice
*d
= PCI_DEVICE(s
);
1348 if (!s
->device_active
)
1351 for (i
= 0; i
< s
->txq_num
; i
++) {
1353 s
->txq_descr
[i
].tx_stats_pa
,
1354 &s
->txq_descr
[i
].txq_stats
,
1355 sizeof(s
->txq_descr
[i
].txq_stats
));
1358 for (i
= 0; i
< s
->rxq_num
; i
++) {
1360 s
->rxq_descr
[i
].rx_stats_pa
,
1361 &s
->rxq_descr
[i
].rxq_stats
,
1362 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1366 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1368 struct Vmxnet3_GOSInfo gos
;
1369 PCIDevice
*d
= PCI_DEVICE(s
);
1371 VMXNET3_READ_DRV_SHARED(d
, s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1373 s
->rx_packets_compound
=
1374 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1376 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1380 vmxnet3_dump_conf_descr(const char *name
,
1381 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1383 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1384 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1388 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1390 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1391 PCIDevice
*d
= PCI_DEVICE(s
);
1394 VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1396 VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1398 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1400 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1403 static void vmxnet3_update_features(VMXNET3State
*s
)
1405 uint32_t guest_features
;
1406 int rxcso_supported
;
1407 PCIDevice
*d
= PCI_DEVICE(s
);
1409 guest_features
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
,
1410 devRead
.misc
.uptFeatures
);
1412 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1413 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1414 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1416 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1417 s
->lro_supported
, rxcso_supported
,
1418 s
->rx_vlan_stripping
);
1419 if (s
->peer_has_vhdr
) {
1420 qemu_set_offload(qemu_get_queue(s
->nic
)->peer
,
1429 static bool vmxnet3_verify_intx(VMXNET3State
*s
, int intx
)
1431 return s
->msix_used
|| msi_enabled(PCI_DEVICE(s
))
1432 || intx
== pci_get_byte(s
->parent_obj
.config
+ PCI_INTERRUPT_PIN
) - 1;
1435 static void vmxnet3_validate_interrupt_idx(bool is_msix
, int idx
)
1437 int max_ints
= is_msix
? VMXNET3_MAX_INTRS
: VMXNET3_MAX_NMSIX_INTRS
;
1438 if (idx
>= max_ints
) {
1439 hw_error("Bad interrupt index: %d\n", idx
);
1443 static void vmxnet3_validate_interrupts(VMXNET3State
*s
)
1447 VMW_CFPRN("Verifying event interrupt index (%d)", s
->event_int_idx
);
1448 vmxnet3_validate_interrupt_idx(s
->msix_used
, s
->event_int_idx
);
1450 for (i
= 0; i
< s
->txq_num
; i
++) {
1451 int idx
= s
->txq_descr
[i
].intr_idx
;
1452 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i
, idx
);
1453 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1456 for (i
= 0; i
< s
->rxq_num
; i
++) {
1457 int idx
= s
->rxq_descr
[i
].intr_idx
;
1458 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i
, idx
);
1459 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1463 static void vmxnet3_validate_queues(VMXNET3State
*s
)
1466 * txq_num and rxq_num are total number of queues
1467 * configured by guest. These numbers must not
1468 * exceed corresponding maximal values.
1471 if (s
->txq_num
> VMXNET3_DEVICE_MAX_TX_QUEUES
) {
1472 hw_error("Bad TX queues number: %d\n", s
->txq_num
);
1475 if (s
->rxq_num
> VMXNET3_DEVICE_MAX_RX_QUEUES
) {
1476 hw_error("Bad RX queues number: %d\n", s
->rxq_num
);
1480 static void vmxnet3_activate_device(VMXNET3State
*s
)
1483 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1484 PCIDevice
*d
= PCI_DEVICE(s
);
1485 hwaddr qdescr_table_pa
;
1489 /* Verify configuration consistency */
1490 if (!vmxnet3_verify_driver_magic(d
, s
->drv_shmem
)) {
1491 VMW_ERPRN("Device configuration received from driver is invalid");
1495 /* Verify if device is active */
1496 if (s
->device_active
) {
1497 VMW_CFPRN("Vmxnet3 device is active");
1501 vmxnet3_adjust_by_guest_type(s
);
1502 vmxnet3_update_features(s
);
1503 vmxnet3_update_pm_state(s
);
1504 vmxnet3_setup_rx_filtering(s
);
1505 /* Cache fields from shared memory */
1506 s
->mtu
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.misc
.mtu
);
1507 VMW_CFPRN("MTU is %u", s
->mtu
);
1510 VMXNET3_READ_DRV_SHARED16(d
, s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1512 if (s
->max_rx_frags
== 0) {
1513 s
->max_rx_frags
= 1;
1516 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1519 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1520 assert(vmxnet3_verify_intx(s
, s
->event_int_idx
));
1521 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1523 s
->auto_int_masking
=
1524 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1525 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1528 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1530 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1532 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1533 vmxnet3_validate_queues(s
);
1536 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1537 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1540 * Worst-case scenario is a packet that holds all TX rings space so
1541 * we calculate total size of all TX rings for max TX fragments number
1543 s
->max_tx_frags
= 0;
1546 for (i
= 0; i
< s
->txq_num
; i
++) {
1548 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1550 /* Read interrupt number for this TX queue */
1551 s
->txq_descr
[i
].intr_idx
=
1552 VMXNET3_READ_TX_QUEUE_DESCR8(d
, qdescr_pa
, conf
.intrIdx
);
1553 assert(vmxnet3_verify_intx(s
, s
->txq_descr
[i
].intr_idx
));
1555 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1557 /* Read rings memory locations for TX queues */
1558 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(d
, qdescr_pa
, conf
.txRingBasePA
);
1559 size
= VMXNET3_READ_TX_QUEUE_DESCR32(d
, qdescr_pa
, conf
.txRingSize
);
1561 vmxnet3_ring_init(d
, &s
->txq_descr
[i
].tx_ring
, pa
, size
,
1562 sizeof(struct Vmxnet3_TxDesc
), false);
1563 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1565 s
->max_tx_frags
+= size
;
1568 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(d
, qdescr_pa
, conf
.compRingBasePA
);
1569 size
= VMXNET3_READ_TX_QUEUE_DESCR32(d
, qdescr_pa
, conf
.compRingSize
);
1570 vmxnet3_ring_init(d
, &s
->txq_descr
[i
].comp_ring
, pa
, size
,
1571 sizeof(struct Vmxnet3_TxCompDesc
), true);
1572 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1574 s
->txq_descr
[i
].tx_stats_pa
=
1575 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1577 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1578 sizeof(s
->txq_descr
[i
].txq_stats
));
1580 /* Fill device-managed parameters for queues */
1581 VMXNET3_WRITE_TX_QUEUE_DESCR32(d
, qdescr_pa
,
1583 VMXNET3_DEF_TX_THRESHOLD
);
1586 /* Preallocate TX packet wrapper */
1587 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1588 net_tx_pkt_init(&s
->tx_pkt
, PCI_DEVICE(s
),
1589 s
->max_tx_frags
, s
->peer_has_vhdr
);
1590 net_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
1592 /* Read rings memory locations for RX queues */
1593 for (i
= 0; i
< s
->rxq_num
; i
++) {
1596 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1597 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1599 /* Read interrupt number for this RX queue */
1600 s
->rxq_descr
[i
].intr_idx
=
1601 VMXNET3_READ_TX_QUEUE_DESCR8(d
, qd_pa
, conf
.intrIdx
);
1602 assert(vmxnet3_verify_intx(s
, s
->rxq_descr
[i
].intr_idx
));
1604 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1606 /* Read rings memory locations */
1607 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1609 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(d
, qd_pa
, conf
.rxRingBasePA
[j
]);
1610 size
= VMXNET3_READ_RX_QUEUE_DESCR32(d
, qd_pa
, conf
.rxRingSize
[j
]);
1611 vmxnet3_ring_init(d
, &s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1612 sizeof(struct Vmxnet3_RxDesc
), false);
1613 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1618 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(d
, qd_pa
, conf
.compRingBasePA
);
1619 size
= VMXNET3_READ_RX_QUEUE_DESCR32(d
, qd_pa
, conf
.compRingSize
);
1620 vmxnet3_ring_init(d
, &s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1621 sizeof(struct Vmxnet3_RxCompDesc
), true);
1622 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1624 s
->rxq_descr
[i
].rx_stats_pa
=
1625 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1626 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1627 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1630 vmxnet3_validate_interrupts(s
);
1632 /* Make sure everything is in place before device activation */
1635 vmxnet3_reset_mac(s
);
1637 s
->device_active
= true;
1640 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1642 s
->last_command
= cmd
;
1645 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1646 VMW_CBPRN("Set: Get upper part of permanent MAC");
1649 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1650 VMW_CBPRN("Set: Get lower part of permanent MAC");
1653 case VMXNET3_CMD_GET_STATS
:
1654 VMW_CBPRN("Set: Get device statistics");
1655 vmxnet3_fill_stats(s
);
1658 case VMXNET3_CMD_ACTIVATE_DEV
:
1659 VMW_CBPRN("Set: Activating vmxnet3 device");
1660 vmxnet3_activate_device(s
);
1663 case VMXNET3_CMD_UPDATE_RX_MODE
:
1664 VMW_CBPRN("Set: Update rx mode");
1665 vmxnet3_update_rx_mode(s
);
1668 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1669 VMW_CBPRN("Set: Update VLAN filters");
1670 vmxnet3_update_vlan_filters(s
);
1673 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1674 VMW_CBPRN("Set: Update MAC filters");
1675 vmxnet3_update_mcast_filters(s
);
1678 case VMXNET3_CMD_UPDATE_FEATURE
:
1679 VMW_CBPRN("Set: Update features");
1680 vmxnet3_update_features(s
);
1683 case VMXNET3_CMD_UPDATE_PMCFG
:
1684 VMW_CBPRN("Set: Update power management config");
1685 vmxnet3_update_pm_state(s
);
1688 case VMXNET3_CMD_GET_LINK
:
1689 VMW_CBPRN("Set: Get link");
1692 case VMXNET3_CMD_RESET_DEV
:
1693 VMW_CBPRN("Set: Reset device");
1697 case VMXNET3_CMD_QUIESCE_DEV
:
1698 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1699 vmxnet3_deactivate_device(s
);
1702 case VMXNET3_CMD_GET_CONF_INTR
:
1703 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1706 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1707 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1708 "adaptive ring info flags");
1711 case VMXNET3_CMD_GET_DID_LO
:
1712 VMW_CBPRN("Set: Get lower part of device ID");
1715 case VMXNET3_CMD_GET_DID_HI
:
1716 VMW_CBPRN("Set: Get upper part of device ID");
1719 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1720 VMW_CBPRN("Set: Get device extra info");
1724 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1729 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1733 switch (s
->last_command
) {
1734 case VMXNET3_CMD_ACTIVATE_DEV
:
1735 ret
= (s
->device_active
) ? 0 : 1;
1736 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1739 case VMXNET3_CMD_RESET_DEV
:
1740 case VMXNET3_CMD_QUIESCE_DEV
:
1741 case VMXNET3_CMD_GET_QUEUE_STATUS
:
1742 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1746 case VMXNET3_CMD_GET_LINK
:
1747 ret
= s
->link_status_and_speed
;
1748 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1751 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1752 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1755 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1756 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1759 case VMXNET3_CMD_GET_CONF_INTR
:
1760 ret
= vmxnet3_get_interrupt_config(s
);
1763 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1764 ret
= VMXNET3_DISABLE_ADAPTIVE_RING
;
1767 case VMXNET3_CMD_GET_DID_LO
:
1768 ret
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
1771 case VMXNET3_CMD_GET_DID_HI
:
1772 ret
= VMXNET3_DEVICE_REVISION
;
1776 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1784 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1787 PCIDevice
*d
= PCI_DEVICE(s
);
1789 VMW_CBPRN("Setting events: 0x%x", val
);
1790 events
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, ecr
) | val
;
1791 VMXNET3_WRITE_DRV_SHARED32(d
, s
->drv_shmem
, ecr
, events
);
1794 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1796 PCIDevice
*d
= PCI_DEVICE(s
);
1799 VMW_CBPRN("Clearing events: 0x%x", val
);
1800 events
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, ecr
) & ~val
;
1801 VMXNET3_WRITE_DRV_SHARED32(d
, s
->drv_shmem
, ecr
, events
);
1805 vmxnet3_io_bar1_write(void *opaque
,
1810 VMXNET3State
*s
= opaque
;
1813 /* Vmxnet3 Revision Report Selection */
1814 case VMXNET3_REG_VRRS
:
1815 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1819 /* UPT Version Report Selection */
1820 case VMXNET3_REG_UVRS
:
1821 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1825 /* Driver Shared Address Low */
1826 case VMXNET3_REG_DSAL
:
1827 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1830 * Guest driver will first write the low part of the shared
1831 * memory address. We save it to temp variable and set the
1832 * shared address only after we get the high part
1835 vmxnet3_deactivate_device(s
);
1837 s
->temp_shared_guest_driver_memory
= val
;
1841 /* Driver Shared Address High */
1842 case VMXNET3_REG_DSAH
:
1843 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1846 * Set the shared memory between guest driver and device.
1847 * We already should have low address part.
1849 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1853 case VMXNET3_REG_CMD
:
1854 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1856 vmxnet3_handle_command(s
, val
);
1859 /* MAC Address Low */
1860 case VMXNET3_REG_MACL
:
1861 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1866 /* MAC Address High */
1867 case VMXNET3_REG_MACH
:
1868 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1870 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1873 /* Interrupt Cause Register */
1874 case VMXNET3_REG_ICR
:
1875 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1877 g_assert_not_reached();
1880 /* Event Cause Register */
1881 case VMXNET3_REG_ECR
:
1882 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1884 vmxnet3_ack_events(s
, val
);
1888 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1895 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1897 VMXNET3State
*s
= opaque
;
1901 /* Vmxnet3 Revision Report Selection */
1902 case VMXNET3_REG_VRRS
:
1903 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1904 ret
= VMXNET3_DEVICE_REVISION
;
1907 /* UPT Version Report Selection */
1908 case VMXNET3_REG_UVRS
:
1909 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1910 ret
= VMXNET3_UPT_REVISION
;
1914 case VMXNET3_REG_CMD
:
1915 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1916 ret
= vmxnet3_get_command_status(s
);
1919 /* MAC Address Low */
1920 case VMXNET3_REG_MACL
:
1921 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1922 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1925 /* MAC Address High */
1926 case VMXNET3_REG_MACH
:
1927 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1928 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1932 * Interrupt Cause Register
1933 * Used for legacy interrupts only so interrupt index always 0
1935 case VMXNET3_REG_ICR
:
1936 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1937 if (vmxnet3_interrupt_asserted(s
, 0)) {
1938 vmxnet3_clear_interrupt(s
, 0);
1946 VMW_CBPRN("Unknow read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1954 vmxnet3_can_receive(NetClientState
*nc
)
1956 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1957 return s
->device_active
&&
1958 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1962 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1964 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1965 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1969 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1973 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1976 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1977 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1985 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1988 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1990 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1994 if (!vmxnet3_is_registered_vlan(s
, data
)) {
1998 switch (net_rx_pkt_get_packet_type(s
->rx_pkt
)) {
2000 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
2003 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
2009 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
2015 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
2018 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
2021 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
2027 g_assert_not_reached();
2034 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
2036 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2037 size_t bytes_indicated
;
2038 uint8_t min_buf
[MIN_BUF_SIZE
];
2040 if (!vmxnet3_can_receive(nc
)) {
2041 VMW_PKPRN("Cannot receive now");
2045 if (s
->peer_has_vhdr
) {
2046 net_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
2047 buf
+= sizeof(struct virtio_net_hdr
);
2048 size
-= sizeof(struct virtio_net_hdr
);
2051 /* Pad to minimum Ethernet frame length */
2052 if (size
< sizeof(min_buf
)) {
2053 memcpy(min_buf
, buf
, size
);
2054 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
2056 size
= sizeof(min_buf
);
2059 net_rx_pkt_set_packet_type(s
->rx_pkt
,
2060 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
2062 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
2063 net_rx_pkt_set_protocols(s
->rx_pkt
, buf
, size
);
2064 vmxnet3_rx_need_csum_calculate(s
->rx_pkt
, buf
, size
);
2065 net_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
2066 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
2067 if (bytes_indicated
< size
) {
2068 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated
, size
);
2071 VMW_PKPRN("Packet dropped by RX filter");
2072 bytes_indicated
= size
;
2076 assert(bytes_indicated
!= 0);
2077 return bytes_indicated
;
2080 static void vmxnet3_set_link_status(NetClientState
*nc
)
2082 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2084 if (nc
->link_down
) {
2085 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
2087 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
2090 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
2091 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
2094 static NetClientInfo net_vmxnet3_info
= {
2095 .type
= NET_CLIENT_DRIVER_NIC
,
2096 .size
= sizeof(NICState
),
2097 .receive
= vmxnet3_receive
,
2098 .link_status_changed
= vmxnet3_set_link_status
,
2101 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
2103 NetClientState
*nc
= qemu_get_queue(s
->nic
);
2105 if (qemu_has_vnet_hdr(nc
->peer
)) {
2112 static void vmxnet3_net_uninit(VMXNET3State
*s
)
2114 g_free(s
->mcast_list
);
2115 vmxnet3_deactivate_device(s
);
2116 qemu_del_nic(s
->nic
);
2119 static void vmxnet3_net_init(VMXNET3State
*s
)
2121 DeviceState
*d
= DEVICE(s
);
2123 VMW_CBPRN("vmxnet3_net_init called...");
2125 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
2127 /* Windows guest will query the address that was set on init */
2128 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
2130 s
->mcast_list
= NULL
;
2131 s
->mcast_list_len
= 0;
2133 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
2135 VMW_CFPRN("Permanent MAC: " MAC_FMT
, MAC_ARG(s
->perm_mac
.a
));
2137 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
2138 object_get_typename(OBJECT(s
)),
2141 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
2143 s
->skip_current_tx_pkt
= false;
2146 s
->rx_vlan_stripping
= false;
2147 s
->lro_supported
= false;
2149 if (s
->peer_has_vhdr
) {
2150 qemu_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
2151 sizeof(struct virtio_net_hdr
));
2153 qemu_using_vnet_hdr(qemu_get_queue(s
->nic
)->peer
, 1);
2156 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
2160 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2162 PCIDevice
*d
= PCI_DEVICE(s
);
2164 for (i
= 0; i
< num_vectors
; i
++) {
2165 msix_vector_unuse(d
, i
);
2170 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2172 PCIDevice
*d
= PCI_DEVICE(s
);
2174 for (i
= 0; i
< num_vectors
; i
++) {
2175 int res
= msix_vector_use(d
, i
);
2177 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i
, res
);
2178 vmxnet3_unuse_msix_vectors(s
, i
);
2186 vmxnet3_init_msix(VMXNET3State
*s
)
2188 PCIDevice
*d
= PCI_DEVICE(s
);
2189 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
2191 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
2193 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA(s
),
2194 VMXNET3_MSIX_OFFSET(s
), NULL
);
2197 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
2198 s
->msix_used
= false;
2200 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2201 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res
);
2202 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2203 s
->msix_used
= false;
2205 s
->msix_used
= true;
2208 return s
->msix_used
;
2212 vmxnet3_cleanup_msix(VMXNET3State
*s
)
2214 PCIDevice
*d
= PCI_DEVICE(s
);
2217 vmxnet3_unuse_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2218 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2223 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2225 PCIDevice
*d
= PCI_DEVICE(s
);
2231 vmxnet3_msix_save(QEMUFile
*f
, void *opaque
)
2233 PCIDevice
*d
= PCI_DEVICE(opaque
);
2238 vmxnet3_msix_load(QEMUFile
*f
, void *opaque
, int version_id
)
2240 PCIDevice
*d
= PCI_DEVICE(opaque
);
2245 static const MemoryRegionOps b0_ops
= {
2246 .read
= vmxnet3_io_bar0_read
,
2247 .write
= vmxnet3_io_bar0_write
,
2248 .endianness
= DEVICE_LITTLE_ENDIAN
,
2250 .min_access_size
= 4,
2251 .max_access_size
= 4,
2255 static const MemoryRegionOps b1_ops
= {
2256 .read
= vmxnet3_io_bar1_read
,
2257 .write
= vmxnet3_io_bar1_write
,
2258 .endianness
= DEVICE_LITTLE_ENDIAN
,
2260 .min_access_size
= 4,
2261 .max_access_size
= 4,
2265 static uint64_t vmxnet3_device_serial_num(VMXNET3State
*s
)
2267 uint64_t dsn_payload
;
2268 uint8_t *dsnp
= (uint8_t *)&dsn_payload
;
2271 dsnp
[1] = s
->conf
.macaddr
.a
[3];
2272 dsnp
[2] = s
->conf
.macaddr
.a
[4];
2273 dsnp
[3] = s
->conf
.macaddr
.a
[5];
2274 dsnp
[4] = s
->conf
.macaddr
.a
[0];
2275 dsnp
[5] = s
->conf
.macaddr
.a
[1];
2276 dsnp
[6] = s
->conf
.macaddr
.a
[2];
2282 #define VMXNET3_USE_64BIT (true)
2283 #define VMXNET3_PER_VECTOR_MASK (false)
2285 static void vmxnet3_pci_realize(PCIDevice
*pci_dev
, Error
**errp
)
2287 DeviceState
*dev
= DEVICE(pci_dev
);
2288 VMXNET3State
*s
= VMXNET3(pci_dev
);
2291 VMW_CBPRN("Starting init...");
2293 memory_region_init_io(&s
->bar0
, OBJECT(s
), &b0_ops
, s
,
2294 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2295 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2296 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2298 memory_region_init_io(&s
->bar1
, OBJECT(s
), &b1_ops
, s
,
2299 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2300 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2301 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2303 memory_region_init(&s
->msix_bar
, OBJECT(s
), "vmxnet3-msix-bar",
2304 VMXNET3_MSIX_BAR_SIZE
);
2305 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2306 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2308 vmxnet3_reset_interrupt_states(s
);
2310 /* Interrupt pin A */
2311 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2313 ret
= msi_init(pci_dev
, VMXNET3_MSI_OFFSET(s
), VMXNET3_MAX_NMSIX_INTRS
,
2314 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
, NULL
);
2315 /* Any error other than -ENOTSUP(board's MSI support is broken)
2316 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2317 assert(!ret
|| ret
== -ENOTSUP
);
2319 if (!vmxnet3_init_msix(s
)) {
2320 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2323 vmxnet3_net_init(s
);
2325 if (pci_is_express(pci_dev
)) {
2326 if (pci_bus_is_express(pci_dev
->bus
)) {
2327 pcie_endpoint_cap_init(pci_dev
, VMXNET3_EXP_EP_OFFSET
);
2330 pcie_dev_ser_num_init(pci_dev
, VMXNET3_DSN_OFFSET
,
2331 vmxnet3_device_serial_num(s
));
2334 register_savevm(dev
, "vmxnet3-msix", -1, 1,
2335 vmxnet3_msix_save
, vmxnet3_msix_load
, s
);
2338 static void vmxnet3_instance_init(Object
*obj
)
2340 VMXNET3State
*s
= VMXNET3(obj
);
2341 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
2342 "bootindex", "/ethernet-phy@0",
2346 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2348 DeviceState
*dev
= DEVICE(pci_dev
);
2349 VMXNET3State
*s
= VMXNET3(pci_dev
);
2351 VMW_CBPRN("Starting uninit...");
2353 unregister_savevm(dev
, "vmxnet3-msix", s
);
2355 vmxnet3_net_uninit(s
);
2357 vmxnet3_cleanup_msix(s
);
2359 vmxnet3_cleanup_msi(s
);
2362 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2364 PCIDevice
*d
= PCI_DEVICE(dev
);
2365 VMXNET3State
*s
= VMXNET3(d
);
2367 VMW_CBPRN("Starting QDEV reset...");
2371 static bool vmxnet3_mc_list_needed(void *opaque
)
2376 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2378 VMXNET3State
*s
= opaque
;
2380 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2386 static void vmxnet3_pre_save(void *opaque
)
2388 VMXNET3State
*s
= opaque
;
2390 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2393 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2394 .name
= "vmxnet3/mcast_list",
2396 .minimum_version_id
= 1,
2397 .pre_load
= vmxnet3_mcast_list_pre_load
,
2398 .needed
= vmxnet3_mc_list_needed
,
2399 .fields
= (VMStateField
[]) {
2400 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
,
2401 mcast_list_buff_size
),
2402 VMSTATE_END_OF_LIST()
2406 static void vmxnet3_get_ring_from_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2408 r
->pa
= qemu_get_be64(f
);
2409 r
->size
= qemu_get_be32(f
);
2410 r
->cell_size
= qemu_get_be32(f
);
2411 r
->next
= qemu_get_be32(f
);
2412 r
->gen
= qemu_get_byte(f
);
2415 static void vmxnet3_put_ring_to_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2417 qemu_put_be64(f
, r
->pa
);
2418 qemu_put_be32(f
, r
->size
);
2419 qemu_put_be32(f
, r
->cell_size
);
2420 qemu_put_be32(f
, r
->next
);
2421 qemu_put_byte(f
, r
->gen
);
2424 static void vmxnet3_get_tx_stats_from_file(QEMUFile
*f
,
2425 struct UPT1_TxStats
*tx_stat
)
2427 tx_stat
->TSOPktsTxOK
= qemu_get_be64(f
);
2428 tx_stat
->TSOBytesTxOK
= qemu_get_be64(f
);
2429 tx_stat
->ucastPktsTxOK
= qemu_get_be64(f
);
2430 tx_stat
->ucastBytesTxOK
= qemu_get_be64(f
);
2431 tx_stat
->mcastPktsTxOK
= qemu_get_be64(f
);
2432 tx_stat
->mcastBytesTxOK
= qemu_get_be64(f
);
2433 tx_stat
->bcastPktsTxOK
= qemu_get_be64(f
);
2434 tx_stat
->bcastBytesTxOK
= qemu_get_be64(f
);
2435 tx_stat
->pktsTxError
= qemu_get_be64(f
);
2436 tx_stat
->pktsTxDiscard
= qemu_get_be64(f
);
2439 static void vmxnet3_put_tx_stats_to_file(QEMUFile
*f
,
2440 struct UPT1_TxStats
*tx_stat
)
2442 qemu_put_be64(f
, tx_stat
->TSOPktsTxOK
);
2443 qemu_put_be64(f
, tx_stat
->TSOBytesTxOK
);
2444 qemu_put_be64(f
, tx_stat
->ucastPktsTxOK
);
2445 qemu_put_be64(f
, tx_stat
->ucastBytesTxOK
);
2446 qemu_put_be64(f
, tx_stat
->mcastPktsTxOK
);
2447 qemu_put_be64(f
, tx_stat
->mcastBytesTxOK
);
2448 qemu_put_be64(f
, tx_stat
->bcastPktsTxOK
);
2449 qemu_put_be64(f
, tx_stat
->bcastBytesTxOK
);
2450 qemu_put_be64(f
, tx_stat
->pktsTxError
);
2451 qemu_put_be64(f
, tx_stat
->pktsTxDiscard
);
2454 static int vmxnet3_get_txq_descr(QEMUFile
*f
, void *pv
, size_t size
,
2455 VMStateField
*field
)
2457 Vmxnet3TxqDescr
*r
= pv
;
2459 vmxnet3_get_ring_from_file(f
, &r
->tx_ring
);
2460 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2461 r
->intr_idx
= qemu_get_byte(f
);
2462 r
->tx_stats_pa
= qemu_get_be64(f
);
2464 vmxnet3_get_tx_stats_from_file(f
, &r
->txq_stats
);
2469 static int vmxnet3_put_txq_descr(QEMUFile
*f
, void *pv
, size_t size
,
2470 VMStateField
*field
, QJSON
*vmdesc
)
2472 Vmxnet3TxqDescr
*r
= pv
;
2474 vmxnet3_put_ring_to_file(f
, &r
->tx_ring
);
2475 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2476 qemu_put_byte(f
, r
->intr_idx
);
2477 qemu_put_be64(f
, r
->tx_stats_pa
);
2478 vmxnet3_put_tx_stats_to_file(f
, &r
->txq_stats
);
2483 static const VMStateInfo txq_descr_info
= {
2484 .name
= "txq_descr",
2485 .get
= vmxnet3_get_txq_descr
,
2486 .put
= vmxnet3_put_txq_descr
2489 static void vmxnet3_get_rx_stats_from_file(QEMUFile
*f
,
2490 struct UPT1_RxStats
*rx_stat
)
2492 rx_stat
->LROPktsRxOK
= qemu_get_be64(f
);
2493 rx_stat
->LROBytesRxOK
= qemu_get_be64(f
);
2494 rx_stat
->ucastPktsRxOK
= qemu_get_be64(f
);
2495 rx_stat
->ucastBytesRxOK
= qemu_get_be64(f
);
2496 rx_stat
->mcastPktsRxOK
= qemu_get_be64(f
);
2497 rx_stat
->mcastBytesRxOK
= qemu_get_be64(f
);
2498 rx_stat
->bcastPktsRxOK
= qemu_get_be64(f
);
2499 rx_stat
->bcastBytesRxOK
= qemu_get_be64(f
);
2500 rx_stat
->pktsRxOutOfBuf
= qemu_get_be64(f
);
2501 rx_stat
->pktsRxError
= qemu_get_be64(f
);
2504 static void vmxnet3_put_rx_stats_to_file(QEMUFile
*f
,
2505 struct UPT1_RxStats
*rx_stat
)
2507 qemu_put_be64(f
, rx_stat
->LROPktsRxOK
);
2508 qemu_put_be64(f
, rx_stat
->LROBytesRxOK
);
2509 qemu_put_be64(f
, rx_stat
->ucastPktsRxOK
);
2510 qemu_put_be64(f
, rx_stat
->ucastBytesRxOK
);
2511 qemu_put_be64(f
, rx_stat
->mcastPktsRxOK
);
2512 qemu_put_be64(f
, rx_stat
->mcastBytesRxOK
);
2513 qemu_put_be64(f
, rx_stat
->bcastPktsRxOK
);
2514 qemu_put_be64(f
, rx_stat
->bcastBytesRxOK
);
2515 qemu_put_be64(f
, rx_stat
->pktsRxOutOfBuf
);
2516 qemu_put_be64(f
, rx_stat
->pktsRxError
);
2519 static int vmxnet3_get_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
,
2520 VMStateField
*field
)
2522 Vmxnet3RxqDescr
*r
= pv
;
2525 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2526 vmxnet3_get_ring_from_file(f
, &r
->rx_ring
[i
]);
2529 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2530 r
->intr_idx
= qemu_get_byte(f
);
2531 r
->rx_stats_pa
= qemu_get_be64(f
);
2533 vmxnet3_get_rx_stats_from_file(f
, &r
->rxq_stats
);
2538 static int vmxnet3_put_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
,
2539 VMStateField
*field
, QJSON
*vmdesc
)
2541 Vmxnet3RxqDescr
*r
= pv
;
2544 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2545 vmxnet3_put_ring_to_file(f
, &r
->rx_ring
[i
]);
2548 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2549 qemu_put_byte(f
, r
->intr_idx
);
2550 qemu_put_be64(f
, r
->rx_stats_pa
);
2551 vmxnet3_put_rx_stats_to_file(f
, &r
->rxq_stats
);
2556 static int vmxnet3_post_load(void *opaque
, int version_id
)
2558 VMXNET3State
*s
= opaque
;
2559 PCIDevice
*d
= PCI_DEVICE(s
);
2561 net_tx_pkt_init(&s
->tx_pkt
, PCI_DEVICE(s
),
2562 s
->max_tx_frags
, s
->peer_has_vhdr
);
2563 net_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
2566 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2567 VMW_WRPRN("Failed to re-use MSI-X vectors");
2568 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2569 s
->msix_used
= false;
2574 vmxnet3_validate_queues(s
);
2575 vmxnet3_validate_interrupts(s
);
2580 static const VMStateInfo rxq_descr_info
= {
2581 .name
= "rxq_descr",
2582 .get
= vmxnet3_get_rxq_descr
,
2583 .put
= vmxnet3_put_rxq_descr
2586 static int vmxnet3_get_int_state(QEMUFile
*f
, void *pv
, size_t size
,
2587 VMStateField
*field
)
2589 Vmxnet3IntState
*r
= pv
;
2591 r
->is_masked
= qemu_get_byte(f
);
2592 r
->is_pending
= qemu_get_byte(f
);
2593 r
->is_asserted
= qemu_get_byte(f
);
2598 static int vmxnet3_put_int_state(QEMUFile
*f
, void *pv
, size_t size
,
2599 VMStateField
*field
, QJSON
*vmdesc
)
2601 Vmxnet3IntState
*r
= pv
;
2603 qemu_put_byte(f
, r
->is_masked
);
2604 qemu_put_byte(f
, r
->is_pending
);
2605 qemu_put_byte(f
, r
->is_asserted
);
2610 static const VMStateInfo int_state_info
= {
2611 .name
= "int_state",
2612 .get
= vmxnet3_get_int_state
,
2613 .put
= vmxnet3_put_int_state
2616 static bool vmxnet3_vmstate_need_pcie_device(void *opaque
)
2618 VMXNET3State
*s
= VMXNET3(opaque
);
2620 return !(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
);
2623 static bool vmxnet3_vmstate_test_pci_device(void *opaque
, int version_id
)
2625 return !vmxnet3_vmstate_need_pcie_device(opaque
);
2628 static const VMStateDescription vmstate_vmxnet3_pcie_device
= {
2629 .name
= "vmxnet3/pcie",
2631 .minimum_version_id
= 1,
2632 .needed
= vmxnet3_vmstate_need_pcie_device
,
2633 .fields
= (VMStateField
[]) {
2634 VMSTATE_PCI_DEVICE(parent_obj
, VMXNET3State
),
2635 VMSTATE_END_OF_LIST()
2639 static const VMStateDescription vmstate_vmxnet3
= {
2642 .minimum_version_id
= 1,
2643 .pre_save
= vmxnet3_pre_save
,
2644 .post_load
= vmxnet3_post_load
,
2645 .fields
= (VMStateField
[]) {
2646 VMSTATE_STRUCT_TEST(parent_obj
, VMXNET3State
,
2647 vmxnet3_vmstate_test_pci_device
, 0,
2648 vmstate_pci_device
, PCIDevice
),
2649 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2650 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2651 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2652 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2653 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2654 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2655 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2656 VMSTATE_UINT32(mtu
, VMXNET3State
),
2657 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2658 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2659 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2660 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2661 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2662 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2663 VMSTATE_UINT32(device_active
, VMXNET3State
),
2664 VMSTATE_UINT32(last_command
, VMXNET3State
),
2665 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2666 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2667 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2668 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2670 VMSTATE_ARRAY(txq_descr
, VMXNET3State
,
2671 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, txq_descr_info
,
2673 VMSTATE_ARRAY(rxq_descr
, VMXNET3State
,
2674 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, rxq_descr_info
,
2676 VMSTATE_ARRAY(interrupt_states
, VMXNET3State
, VMXNET3_MAX_INTRS
,
2677 0, int_state_info
, Vmxnet3IntState
),
2679 VMSTATE_END_OF_LIST()
2681 .subsections
= (const VMStateDescription
*[]) {
2682 &vmxstate_vmxnet3_mcast_list
,
2683 &vmstate_vmxnet3_pcie_device
,
2688 static Property vmxnet3_properties
[] = {
2689 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2690 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State
, compat_flags
,
2691 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT
, false),
2692 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State
, compat_flags
,
2693 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT
, false),
2694 DEFINE_PROP_END_OF_LIST(),
2697 static void vmxnet3_realize(DeviceState
*qdev
, Error
**errp
)
2699 VMXNET3Class
*vc
= VMXNET3_DEVICE_GET_CLASS(qdev
);
2700 PCIDevice
*pci_dev
= PCI_DEVICE(qdev
);
2701 VMXNET3State
*s
= VMXNET3(qdev
);
2703 if (!(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
)) {
2704 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2707 vc
->parent_dc_realize(qdev
, errp
);
2710 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2712 DeviceClass
*dc
= DEVICE_CLASS(class);
2713 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2714 VMXNET3Class
*vc
= VMXNET3_DEVICE_CLASS(class);
2716 c
->realize
= vmxnet3_pci_realize
;
2717 c
->exit
= vmxnet3_pci_uninit
;
2718 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2719 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2720 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2721 c
->romfile
= "efi-vmxnet3.rom";
2722 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2723 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2724 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2725 vc
->parent_dc_realize
= dc
->realize
;
2726 dc
->realize
= vmxnet3_realize
;
2727 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2728 dc
->reset
= vmxnet3_qdev_reset
;
2729 dc
->vmsd
= &vmstate_vmxnet3
;
2730 dc
->props
= vmxnet3_properties
;
2731 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2734 static const TypeInfo vmxnet3_info
= {
2735 .name
= TYPE_VMXNET3
,
2736 .parent
= TYPE_PCI_DEVICE
,
2737 .class_size
= sizeof(VMXNET3Class
),
2738 .instance_size
= sizeof(VMXNET3State
),
2739 .class_init
= vmxnet3_class_init
,
2740 .instance_init
= vmxnet3_instance_init
,
2743 static void vmxnet3_register_types(void)
2745 VMW_CBPRN("vmxnet3_register_types called...");
2746 type_register_static(&vmxnet3_info
);
2749 type_init(vmxnet3_register_types
)