hw/char/grlib_apbuart.c

   1 /*
   2  * QEMU GRLIB APB UART Emulator
   3  *
   4  * Copyright (c) 2010-2011 AdaCore
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/char.h"
  27
  28 #include "trace.h"
  29
  30 #define UART_REG_SIZE 20     /* Size of memory mapped registers */
  31
  32 /* UART status register fields */
  33 #define UART_DATA_READY           (1 <<  0)
  34 #define UART_TRANSMIT_SHIFT_EMPTY (1 <<  1)
  35 #define UART_TRANSMIT_FIFO_EMPTY  (1 <<  2)
  36 #define UART_BREAK_RECEIVED       (1 <<  3)
  37 #define UART_OVERRUN              (1 <<  4)
  38 #define UART_PARITY_ERROR         (1 <<  5)
  39 #define UART_FRAMING_ERROR        (1 <<  6)
  40 #define UART_TRANSMIT_FIFO_HALF   (1 <<  7)
  41 #define UART_RECEIVE_FIFO_HALF    (1 <<  8)
  42 #define UART_TRANSMIT_FIFO_FULL   (1 <<  9)
  43 #define UART_RECEIVE_FIFO_FULL    (1 << 10)
  44
  45 /* UART control register fields */
  46 #define UART_RECEIVE_ENABLE          (1 <<  0)
  47 #define UART_TRANSMIT_ENABLE         (1 <<  1)
  48 #define UART_RECEIVE_INTERRUPT       (1 <<  2)
  49 #define UART_TRANSMIT_INTERRUPT      (1 <<  3)
  50 #define UART_PARITY_SELECT           (1 <<  4)
  51 #define UART_PARITY_ENABLE           (1 <<  5)
  52 #define UART_FLOW_CONTROL            (1 <<  6)
  53 #define UART_LOOPBACK                (1 <<  7)
  54 #define UART_EXTERNAL_CLOCK          (1 <<  8)
  55 #define UART_RECEIVE_FIFO_INTERRUPT  (1 <<  9)
  56 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
  57 #define UART_FIFO_DEBUG_MODE         (1 << 11)
  58 #define UART_OUTPUT_ENABLE           (1 << 12)
  59 #define UART_FIFO_AVAILABLE          (1 << 31)
  60
  61 /* Memory mapped register offsets */
  62 #define DATA_OFFSET       0x00
  63 #define STATUS_OFFSET     0x04
  64 #define CONTROL_OFFSET    0x08
  65 #define SCALER_OFFSET     0x0C  /* not supported */
  66 #define FIFO_DEBUG_OFFSET 0x10  /* not supported */
  67
  68 #define FIFO_LENGTH 1024
  69
  70 #define TYPE_GRLIB_APB_UART "grlib,apbuart"
  71 #define GRLIB_APB_UART(obj) \
  72     OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
  73
  74 typedef struct UART {
  75     SysBusDevice parent_obj;
  76
  77     MemoryRegion iomem;
  78     qemu_irq irq;
  79
  80     CharDriverState *chr;
  81
  82     /* registers */
  83     uint32_t status;
  84     uint32_t control;
  85
  86     /* FIFO */
  87     char buffer[FIFO_LENGTH];
  88     int  len;
  89     int  current;
  90 } UART;
  91
  92 static int uart_data_to_read(UART *uart)
  93 {
  94     return uart->current < uart->len;
  95 }
  96
  97 static char uart_pop(UART *uart)
  98 {
  99     char ret;
 100
 101     if (uart->len == 0) {
 102         uart->status &= ~UART_DATA_READY;
 103         return 0;
 104     }
 105
 106     ret = uart->buffer[uart->current++];
 107
 108     if (uart->current >= uart->len) {
 109         /* Flush */
 110         uart->len     = 0;
 111         uart->current = 0;
 112     }
 113
 114     if (!uart_data_to_read(uart)) {
 115         uart->status &= ~UART_DATA_READY;
 116     }
 117
 118     return ret;
 119 }
 120
 121 static void uart_add_to_fifo(UART          *uart,
 122                              const uint8_t *buffer,
 123                              int            length)
 124 {
 125     if (uart->len + length > FIFO_LENGTH) {
 126         abort();
 127     }
 128     memcpy(uart->buffer + uart->len, buffer, length);
 129     uart->len += length;
 130 }
 131
 132 static int grlib_apbuart_can_receive(void *opaque)
 133 {
 134     UART *uart = opaque;
 135
 136     return FIFO_LENGTH - uart->len;
 137 }
 138
 139 static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
 140 {
 141     UART *uart = opaque;
 142
 143     if (uart->control & UART_RECEIVE_ENABLE) {
 144         uart_add_to_fifo(uart, buf, size);
 145
 146         uart->status |= UART_DATA_READY;
 147
 148         if (uart->control & UART_RECEIVE_INTERRUPT) {
 149             qemu_irq_pulse(uart->irq);
 150         }
 151     }
 152 }
 153
 154 static void grlib_apbuart_event(void *opaque, int event)
 155 {
 156     trace_grlib_apbuart_event(event);
 157 }
 158
 159
 160 static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
 161                                    unsigned size)
 162 {
 163     UART     *uart = opaque;
 164
 165     addr &= 0xff;
 166
 167     /* Unit registers */
 168     switch (addr) {
 169     case DATA_OFFSET:
 170     case DATA_OFFSET + 3:       /* when only one byte read */
 171         return uart_pop(uart);
 172
 173     case STATUS_OFFSET:
 174         /* Read Only */
 175         return uart->status;
 176
 177     case CONTROL_OFFSET:
 178         return uart->control;
 179
 180     case SCALER_OFFSET:
 181         /* Not supported */
 182         return 0;
 183
 184     default:
 185         trace_grlib_apbuart_readl_unknown(addr);
 186         return 0;
 187     }
 188 }
 189
 190 static void grlib_apbuart_write(void *opaque, hwaddr addr,
 191                                 uint64_t value, unsigned size)
 192 {
 193     UART          *uart = opaque;
 194     unsigned char  c    = 0;
 195
 196     addr &= 0xff;
 197
 198     /* Unit registers */
 199     switch (addr) {
 200     case DATA_OFFSET:
 201     case DATA_OFFSET + 3:       /* When only one byte write */
 202         /* Transmit when character device available and transmitter enabled */
 203         if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {
 204             c = value & 0xFF;
 205             qemu_chr_fe_write(uart->chr, &c, 1);
 206             /* Generate interrupt */
 207             if (uart->control & UART_TRANSMIT_INTERRUPT) {
 208                 qemu_irq_pulse(uart->irq);
 209             }
 210         }
 211         return;
 212
 213     case STATUS_OFFSET:
 214         /* Read Only */
 215         return;
 216
 217     case CONTROL_OFFSET:
 218         uart->control = value;
 219         return;
 220
 221     case SCALER_OFFSET:
 222         /* Not supported */
 223         return;
 224
 225     default:
 226         break;
 227     }
 228
 229     trace_grlib_apbuart_writel_unknown(addr, value);
 230 }
 231
 232 static const MemoryRegionOps grlib_apbuart_ops = {
 233     .write      = grlib_apbuart_write,
 234     .read       = grlib_apbuart_read,
 235     .endianness = DEVICE_NATIVE_ENDIAN,
 236 };
 237
 238 static int grlib_apbuart_init(SysBusDevice *dev)
 239 {
 240     UART *uart = GRLIB_APB_UART(dev);
 241
 242     qemu_chr_add_handlers(uart->chr,
 243                           grlib_apbuart_can_receive,
 244                           grlib_apbuart_receive,
 245                           grlib_apbuart_event,
 246                           uart);
 247
 248     sysbus_init_irq(dev, &uart->irq);
 249
 250     memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
 251                           "uart", UART_REG_SIZE);
 252
 253     sysbus_init_mmio(dev, &uart->iomem);
 254
 255     return 0;
 256 }
 257
 258 static void grlib_apbuart_reset(DeviceState *d)
 259 {
 260     UART *uart = GRLIB_APB_UART(d);
 261
 262     /* Transmitter FIFO and shift registers are always empty in QEMU */
 263     uart->status =  UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;
 264     /* Everything is off */
 265     uart->control = 0;
 266     /* Flush receive FIFO */
 267     uart->len = 0;
 268     uart->current = 0;
 269 }
 270
 271 static Property grlib_apbuart_properties[] = {
 272     DEFINE_PROP_CHR("chrdev", UART, chr),
 273     DEFINE_PROP_END_OF_LIST(),
 274 };
 275
 276 static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
 277 {
 278     DeviceClass *dc = DEVICE_CLASS(klass);
 279     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 280
 281     k->init = grlib_apbuart_init;
 282     dc->reset = grlib_apbuart_reset;
 283     dc->props = grlib_apbuart_properties;
 284 }
 285
 286 static const TypeInfo grlib_apbuart_info = {
 287     .name          = TYPE_GRLIB_APB_UART,
 288     .parent        = TYPE_SYS_BUS_DEVICE,
 289     .instance_size = sizeof(UART),
 290     .class_init    = grlib_apbuart_class_init,
 291 };
 292
 293 static void grlib_apbuart_register_types(void)
 294 {
 295     type_register_static(&grlib_apbuart_info);
 296 }
 297
 298 type_init(grlib_apbuart_register_types)