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fuzz: Add support for custom fuzzing library
[qemu/ar7.git] / hw / scsi / megasas.c
blob390c2f2edb6135e4ce9ec354f40a02c986146a18
1 /*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "hw/pci/pci.h"
24 #include "hw/qdev-properties.h"
25 #include "sysemu/dma.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "qemu/iov.h"
30 #include "qemu/module.h"
31 #include "hw/scsi/scsi.h"
32 #include "scsi/constants.h"
33 #include "trace.h"
34 #include "qapi/error.h"
35 #include "mfi.h"
36 #include "migration/vmstate.h"
37
38 #define MEGASAS_VERSION_GEN1 "1.70"
39 #define MEGASAS_VERSION_GEN2 "1.80"
40 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
41 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
42 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
43 #define MEGASAS_MAX_SGE 128 /* Firmware limit */
44 #define MEGASAS_DEFAULT_SGE 80
45 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
46 #define MEGASAS_MAX_ARRAYS 128
47
48 #define MEGASAS_HBA_SERIAL "QEMU123456"
49 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
50 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
51
52 #define MEGASAS_FLAG_USE_JBOD 0
53 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
54 #define MEGASAS_FLAG_USE_QUEUE64 1
55 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
56
57 typedef struct MegasasCmd {
58 uint32_t index;
59 uint16_t flags;
60 uint16_t count;
61 uint64_t context;
62
63 hwaddr pa;
64 hwaddr pa_size;
65 uint32_t dcmd_opcode;
66 union mfi_frame *frame;
67 SCSIRequest *req;
68 QEMUSGList qsg;
69 void *iov_buf;
70 size_t iov_size;
71 size_t iov_offset;
72 struct MegasasState *state;
73 } MegasasCmd;
74
75 typedef struct MegasasState {
76 /*< private >*/
77 PCIDevice parent_obj;
78 /*< public >*/
79
80 MemoryRegion mmio_io;
81 MemoryRegion port_io;
82 MemoryRegion queue_io;
83 uint32_t frame_hi;
84
85 uint32_t fw_state;
86 uint32_t fw_sge;
87 uint32_t fw_cmds;
88 uint32_t flags;
89 uint32_t fw_luns;
90 uint32_t intr_mask;
91 uint32_t doorbell;
92 uint32_t busy;
93 uint32_t diag;
94 uint32_t adp_reset;
95 OnOffAuto msi;
96 OnOffAuto msix;
97
98 MegasasCmd *event_cmd;
99 uint16_t event_locale;
100 int event_class;
101 uint32_t event_count;
102 uint32_t shutdown_event;
103 uint32_t boot_event;
104
105 uint64_t sas_addr;
106 char *hba_serial;
107
108 uint64_t reply_queue_pa;
109 void *reply_queue;
110 uint16_t reply_queue_len;
111 uint16_t reply_queue_head;
112 uint16_t reply_queue_tail;
113 uint64_t consumer_pa;
114 uint64_t producer_pa;
115
116 MegasasCmd frames[MEGASAS_MAX_FRAMES];
117 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
118 SCSIBus bus;
119 } MegasasState;
120
121 typedef struct MegasasBaseClass {
122 PCIDeviceClass parent_class;
123 const char *product_name;
124 const char *product_version;
125 int mmio_bar;
126 int ioport_bar;
127 int osts;
128 } MegasasBaseClass;
129
130 #define TYPE_MEGASAS_BASE "megasas-base"
131 #define TYPE_MEGASAS_GEN1 "megasas"
132 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
133
134 #define MEGASAS(obj) \
135 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
136
137 #define MEGASAS_CLASS(oc) \
138 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
139 #define MEGASAS_GET_CLASS(oc) \
140 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
141
142 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
143
144 static bool megasas_intr_enabled(MegasasState *s)
145 {
146 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
147 MEGASAS_INTR_DISABLED_MASK) {
148 return true;
149 }
150 return false;
151 }
152
153 static bool megasas_use_queue64(MegasasState *s)
154 {
155 return s->flags & MEGASAS_MASK_USE_QUEUE64;
156 }
157
158 static bool megasas_use_msix(MegasasState *s)
159 {
160 return s->msix != ON_OFF_AUTO_OFF;
161 }
162
163 static bool megasas_is_jbod(MegasasState *s)
164 {
165 return s->flags & MEGASAS_MASK_USE_JBOD;
166 }
167
168 static void megasas_frame_set_cmd_status(MegasasState *s,
169 unsigned long frame, uint8_t v)
170 {
171 PCIDevice *pci = &s->parent_obj;
172 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
173 }
174
175 static void megasas_frame_set_scsi_status(MegasasState *s,
176 unsigned long frame, uint8_t v)
177 {
178 PCIDevice *pci = &s->parent_obj;
179 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
180 }
181
182 static inline const char *mfi_frame_desc(unsigned int cmd)
183 {
184 static const char *mfi_frame_descs[] = {
185 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
186 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"
187 };
188
189 if (cmd < ARRAY_SIZE(mfi_frame_descs)) {
190 return mfi_frame_descs[cmd];
191 }
192
193 return "Unknown";
194 }
195
196 /*
197 * Context is considered opaque, but the HBA firmware is running
198 * in little endian mode. So convert it to little endian, too.
199 */
200 static uint64_t megasas_frame_get_context(MegasasState *s,
201 unsigned long frame)
202 {
203 PCIDevice *pci = &s->parent_obj;
204 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
205 }
206
207 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
208 {
209 return cmd->flags & MFI_FRAME_IEEE_SGL;
210 }
211
212 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
213 {
214 return cmd->flags & MFI_FRAME_SGL64;
215 }
216
217 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
218 {
219 return cmd->flags & MFI_FRAME_SENSE64;
220 }
221
222 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
223 union mfi_sgl *sgl)
224 {
225 uint64_t addr;
226
227 if (megasas_frame_is_ieee_sgl(cmd)) {
228 addr = le64_to_cpu(sgl->sg_skinny->addr);
229 } else if (megasas_frame_is_sgl64(cmd)) {
230 addr = le64_to_cpu(sgl->sg64->addr);
231 } else {
232 addr = le32_to_cpu(sgl->sg32->addr);
233 }
234 return addr;
235 }
236
237 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
238 union mfi_sgl *sgl)
239 {
240 uint32_t len;
241
242 if (megasas_frame_is_ieee_sgl(cmd)) {
243 len = le32_to_cpu(sgl->sg_skinny->len);
244 } else if (megasas_frame_is_sgl64(cmd)) {
245 len = le32_to_cpu(sgl->sg64->len);
246 } else {
247 len = le32_to_cpu(sgl->sg32->len);
248 }
249 return len;
250 }
251
252 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
253 union mfi_sgl *sgl)
254 {
255 uint8_t *next = (uint8_t *)sgl;
256
257 if (megasas_frame_is_ieee_sgl(cmd)) {
258 next += sizeof(struct mfi_sg_skinny);
259 } else if (megasas_frame_is_sgl64(cmd)) {
260 next += sizeof(struct mfi_sg64);
261 } else {
262 next += sizeof(struct mfi_sg32);
263 }
264
265 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
266 return NULL;
267 }
268 return (union mfi_sgl *)next;
269 }
270
271 static void megasas_soft_reset(MegasasState *s);
272
273 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
274 {
275 int i;
276 int iov_count = 0;
277 size_t iov_size = 0;
278
279 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
280 iov_count = cmd->frame->header.sge_count;
281 if (iov_count > MEGASAS_MAX_SGE) {
282 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
283 MEGASAS_MAX_SGE);
284 return iov_count;
285 }
286 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
287 for (i = 0; i < iov_count; i++) {
288 dma_addr_t iov_pa, iov_size_p;
289
290 if (!sgl) {
291 trace_megasas_iovec_sgl_underflow(cmd->index, i);
292 goto unmap;
293 }
294 iov_pa = megasas_sgl_get_addr(cmd, sgl);
295 iov_size_p = megasas_sgl_get_len(cmd, sgl);
296 if (!iov_pa || !iov_size_p) {
297 trace_megasas_iovec_sgl_invalid(cmd->index, i,
298 iov_pa, iov_size_p);
299 goto unmap;
300 }
301 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
302 sgl = megasas_sgl_next(cmd, sgl);
303 iov_size += (size_t)iov_size_p;
304 }
305 if (cmd->iov_size > iov_size) {
306 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
307 } else if (cmd->iov_size < iov_size) {
308 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
309 }
310 cmd->iov_offset = 0;
311 return 0;
312 unmap:
313 qemu_sglist_destroy(&cmd->qsg);
314 return iov_count - i;
315 }
316
317 /*
318 * passthrough sense and io sense are at the same offset
319 */
320 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
321 uint8_t sense_len)
322 {
323 PCIDevice *pcid = PCI_DEVICE(cmd->state);
324 uint32_t pa_hi = 0, pa_lo;
325 hwaddr pa;
326 int frame_sense_len;
327
328 frame_sense_len = cmd->frame->header.sense_len;
329 if (sense_len > frame_sense_len) {
330 sense_len = frame_sense_len;
331 }
332 if (sense_len) {
333 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
334 if (megasas_frame_is_sense64(cmd)) {
335 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
336 }
337 pa = ((uint64_t) pa_hi << 32) | pa_lo;
338 pci_dma_write(pcid, pa, sense_ptr, sense_len);
339 cmd->frame->header.sense_len = sense_len;
340 }
341 return sense_len;
342 }
343
344 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
345 {
346 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
347 uint8_t sense_len = 18;
348
349 memset(sense_buf, 0, sense_len);
350 sense_buf[0] = 0xf0;
351 sense_buf[2] = sense.key;
352 sense_buf[7] = 10;
353 sense_buf[12] = sense.asc;
354 sense_buf[13] = sense.ascq;
355 megasas_build_sense(cmd, sense_buf, sense_len);
356 }
357
358 static void megasas_copy_sense(MegasasCmd *cmd)
359 {
360 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
361 uint8_t sense_len;
362
363 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
364 SCSI_SENSE_BUF_SIZE);
365 megasas_build_sense(cmd, sense_buf, sense_len);
366 }
367
368 /*
369 * Format an INQUIRY CDB
370 */
371 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
372 {
373 memset(cdb, 0, 6);
374 cdb[0] = INQUIRY;
375 if (pg > 0) {
376 cdb[1] = 0x1;
377 cdb[2] = pg;
378 }
379 cdb[3] = (len >> 8) & 0xff;
380 cdb[4] = (len & 0xff);
381 return len;
382 }
383
384 /*
385 * Encode lba and len into a READ_16/WRITE_16 CDB
386 */
387 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
388 uint32_t len, bool is_write)
389 {
390 memset(cdb, 0x0, 16);
391 if (is_write) {
392 cdb[0] = WRITE_16;
393 } else {
394 cdb[0] = READ_16;
395 }
396 cdb[2] = (lba >> 56) & 0xff;
397 cdb[3] = (lba >> 48) & 0xff;
398 cdb[4] = (lba >> 40) & 0xff;
399 cdb[5] = (lba >> 32) & 0xff;
400 cdb[6] = (lba >> 24) & 0xff;
401 cdb[7] = (lba >> 16) & 0xff;
402 cdb[8] = (lba >> 8) & 0xff;
403 cdb[9] = (lba) & 0xff;
404 cdb[10] = (len >> 24) & 0xff;
405 cdb[11] = (len >> 16) & 0xff;
406 cdb[12] = (len >> 8) & 0xff;
407 cdb[13] = (len) & 0xff;
408 }
409
410 /*
411 * Utility functions
412 */
413 static uint64_t megasas_fw_time(void)
414 {
415 struct tm curtime;
416
417 qemu_get_timedate(&curtime, 0);
418 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
419 ((uint64_t)curtime.tm_min & 0xff) << 40 |
420 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
421 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
422 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
423 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
424 }
425
426 /*
427 * Default disk sata address
428 * 0x1221 is the magic number as
429 * present in real hardware,
430 * so use it here, too.
431 */
432 static uint64_t megasas_get_sata_addr(uint16_t id)
433 {
434 uint64_t addr = (0x1221ULL << 48);
435 return addr | ((uint64_t)id << 24);
436 }
437
438 /*
439 * Frame handling
440 */
441 static int megasas_next_index(MegasasState *s, int index, int limit)
442 {
443 index++;
444 if (index == limit) {
445 index = 0;
446 }
447 return index;
448 }
449
450 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
451 hwaddr frame)
452 {
453 MegasasCmd *cmd = NULL;
454 int num = 0, index;
455
456 index = s->reply_queue_head;
457
458 while (num < s->fw_cmds && index < MEGASAS_MAX_FRAMES) {
459 if (s->frames[index].pa && s->frames[index].pa == frame) {
460 cmd = &s->frames[index];
461 break;
462 }
463 index = megasas_next_index(s, index, s->fw_cmds);
464 num++;
465 }
466
467 return cmd;
468 }
469
470 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
471 {
472 PCIDevice *p = PCI_DEVICE(s);
473
474 if (cmd->pa_size) {
475 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
476 }
477 cmd->frame = NULL;
478 cmd->pa = 0;
479 cmd->pa_size = 0;
480 qemu_sglist_destroy(&cmd->qsg);
481 clear_bit(cmd->index, s->frame_map);
482 }
483
484 /*
485 * This absolutely needs to be locked if
486 * qemu ever goes multithreaded.
487 */
488 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
489 hwaddr frame, uint64_t context, int count)
490 {
491 PCIDevice *pcid = PCI_DEVICE(s);
492 MegasasCmd *cmd = NULL;
493 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
494 hwaddr frame_size_p = frame_size;
495 unsigned long index;
496
497 index = 0;
498 while (index < s->fw_cmds) {
499 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
500 if (!s->frames[index].pa)
501 break;
502 /* Busy frame found */
503 trace_megasas_qf_mapped(index);
504 }
505 if (index >= s->fw_cmds) {
506 /* All frames busy */
507 trace_megasas_qf_busy(frame);
508 return NULL;
509 }
510 cmd = &s->frames[index];
511 set_bit(index, s->frame_map);
512 trace_megasas_qf_new(index, frame);
513
514 cmd->pa = frame;
515 /* Map all possible frames */
516 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
517 if (!cmd->frame || frame_size_p != frame_size) {
518 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
519 if (cmd->frame) {
520 megasas_unmap_frame(s, cmd);
521 }
522 s->event_count++;
523 return NULL;
524 }
525 cmd->pa_size = frame_size_p;
526 cmd->context = context;
527 if (!megasas_use_queue64(s)) {
528 cmd->context &= (uint64_t)0xFFFFFFFF;
529 }
530 cmd->count = count;
531 cmd->dcmd_opcode = -1;
532 s->busy++;
533
534 if (s->consumer_pa) {
535 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
536 }
537 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
538 s->reply_queue_head, s->reply_queue_tail, s->busy);
539
540 return cmd;
541 }
542
543 static void megasas_complete_frame(MegasasState *s, uint64_t context)
544 {
545 PCIDevice *pci_dev = PCI_DEVICE(s);
546 int tail, queue_offset;
547
548 /* Decrement busy count */
549 s->busy--;
550 if (s->reply_queue_pa) {
551 /*
552 * Put command on the reply queue.
553 * Context is opaque, but emulation is running in
554 * little endian. So convert it.
555 */
556 if (megasas_use_queue64(s)) {
557 queue_offset = s->reply_queue_head * sizeof(uint64_t);
558 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
559 } else {
560 queue_offset = s->reply_queue_head * sizeof(uint32_t);
561 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
562 }
563 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
564 trace_megasas_qf_complete(context, s->reply_queue_head,
565 s->reply_queue_tail, s->busy);
566 }
567
568 if (megasas_intr_enabled(s)) {
569 /* Update reply queue pointer */
570 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
571 tail = s->reply_queue_head;
572 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
573 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
574 s->busy);
575 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
576 /* Notify HBA */
577 if (msix_enabled(pci_dev)) {
578 trace_megasas_msix_raise(0);
579 msix_notify(pci_dev, 0);
580 } else if (msi_enabled(pci_dev)) {
581 trace_megasas_msi_raise(0);
582 msi_notify(pci_dev, 0);
583 } else {
584 s->doorbell++;
585 if (s->doorbell == 1) {
586 trace_megasas_irq_raise();
587 pci_irq_assert(pci_dev);
588 }
589 }
590 } else {
591 trace_megasas_qf_complete_noirq(context);
592 }
593 }
594
595 static void megasas_complete_command(MegasasCmd *cmd)
596 {
597 cmd->iov_size = 0;
598 cmd->iov_offset = 0;
599
600 cmd->req->hba_private = NULL;
601 scsi_req_unref(cmd->req);
602 cmd->req = NULL;
603
604 megasas_unmap_frame(cmd->state, cmd);
605 megasas_complete_frame(cmd->state, cmd->context);
606 }
607
608 static void megasas_reset_frames(MegasasState *s)
609 {
610 int i;
611 MegasasCmd *cmd;
612
613 for (i = 0; i < s->fw_cmds; i++) {
614 cmd = &s->frames[i];
615 if (cmd->pa) {
616 megasas_unmap_frame(s, cmd);
617 }
618 }
619 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
620 }
621
622 static void megasas_abort_command(MegasasCmd *cmd)
623 {
624 /* Never abort internal commands. */
625 if (cmd->dcmd_opcode != -1) {
626 return;
627 }
628 if (cmd->req != NULL) {
629 scsi_req_cancel(cmd->req);
630 }
631 }
632
633 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
634 {
635 PCIDevice *pcid = PCI_DEVICE(s);
636 uint32_t pa_hi, pa_lo;
637 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
638 struct mfi_init_qinfo *initq = NULL;
639 uint32_t flags;
640 int ret = MFI_STAT_OK;
641
642 if (s->reply_queue_pa) {
643 trace_megasas_initq_mapped(s->reply_queue_pa);
644 goto out;
645 }
646 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
647 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
648 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
649 trace_megasas_init_firmware((uint64_t)iq_pa);
650 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
651 if (!initq || initq_size != sizeof(*initq)) {
652 trace_megasas_initq_map_failed(cmd->index);
653 s->event_count++;
654 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
655 goto out;
656 }
657 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
658 if (s->reply_queue_len > s->fw_cmds) {
659 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
660 s->event_count++;
661 ret = MFI_STAT_INVALID_PARAMETER;
662 goto out;
663 }
664 pa_lo = le32_to_cpu(initq->rq_addr_lo);
665 pa_hi = le32_to_cpu(initq->rq_addr_hi);
666 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
667 pa_lo = le32_to_cpu(initq->ci_addr_lo);
668 pa_hi = le32_to_cpu(initq->ci_addr_hi);
669 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
670 pa_lo = le32_to_cpu(initq->pi_addr_lo);
671 pa_hi = le32_to_cpu(initq->pi_addr_hi);
672 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
673 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
674 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
675 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
676 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
677 flags = le32_to_cpu(initq->flags);
678 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
679 s->flags |= MEGASAS_MASK_USE_QUEUE64;
680 }
681 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
682 s->reply_queue_len, s->reply_queue_head,
683 s->reply_queue_tail, flags);
684 megasas_reset_frames(s);
685 s->fw_state = MFI_FWSTATE_OPERATIONAL;
686 out:
687 if (initq) {
688 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
689 }
690 return ret;
691 }
692
693 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
694 {
695 dma_addr_t iov_pa, iov_size;
696 int iov_count;
697
698 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
699 iov_count = cmd->frame->header.sge_count;
700 if (!iov_count) {
701 trace_megasas_dcmd_zero_sge(cmd->index);
702 cmd->iov_size = 0;
703 return 0;
704 } else if (iov_count > 1) {
705 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
706 cmd->iov_size = 0;
707 return -EINVAL;
708 }
709 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
710 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
711 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
712 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
713 cmd->iov_size = iov_size;
714 return 0;
715 }
716
717 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
718 {
719 trace_megasas_finish_dcmd(cmd->index, iov_size);
720
721 if (iov_size > cmd->iov_size) {
722 if (megasas_frame_is_ieee_sgl(cmd)) {
723 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
724 } else if (megasas_frame_is_sgl64(cmd)) {
725 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
726 } else {
727 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
728 }
729 }
730 }
731
732 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
733 {
734 PCIDevice *pci_dev = PCI_DEVICE(s);
735 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
736 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
737 struct mfi_ctrl_info info;
738 size_t dcmd_size = sizeof(info);
739 BusChild *kid;
740 int num_pd_disks = 0;
741
742 memset(&info, 0x0, dcmd_size);
743 if (cmd->iov_size < dcmd_size) {
744 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
745 dcmd_size);
746 return MFI_STAT_INVALID_PARAMETER;
747 }
748
749 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
750 info.pci.device = cpu_to_le16(pci_class->device_id);
751 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
752 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
753
754 /*
755 * For some reason the firmware supports
756 * only up to 8 device ports.
757 * Despite supporting a far larger number
758 * of devices for the physical devices.
759 * So just display the first 8 devices
760 * in the device port list, independent
761 * of how many logical devices are actually
762 * present.
763 */
764 info.host.type = MFI_INFO_HOST_PCIE;
765 info.device.type = MFI_INFO_DEV_SAS3G;
766 info.device.port_count = 8;
767 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
768 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
769 uint16_t pd_id;
770
771 if (num_pd_disks < 8) {
772 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
773 info.device.port_addr[num_pd_disks] =
774 cpu_to_le64(megasas_get_sata_addr(pd_id));
775 }
776 num_pd_disks++;
777 }
778
779 memcpy(info.product_name, base_class->product_name, 24);
780 snprintf(info.serial_number, 32, "%s", s->hba_serial);
781 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
782 memcpy(info.image_component[0].name, "APP", 3);
783 snprintf(info.image_component[0].version, 10, "%s-QEMU",
784 base_class->product_version);
785 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
786 memcpy(info.image_component[0].build_time, "12:34:56", 8);
787 info.image_component_count = 1;
788 if (pci_dev->has_rom) {
789 uint8_t biosver[32];
790 uint8_t *ptr;
791
792 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
793 memcpy(biosver, ptr + 0x41, 31);
794 biosver[31] = 0;
795 memcpy(info.image_component[1].name, "BIOS", 4);
796 memcpy(info.image_component[1].version, biosver,
797 strlen((const char *)biosver));
798 info.image_component_count++;
799 }
800 info.current_fw_time = cpu_to_le32(megasas_fw_time());
801 info.max_arms = 32;
802 info.max_spans = 8;
803 info.max_arrays = MEGASAS_MAX_ARRAYS;
804 info.max_lds = MFI_MAX_LD;
805 info.max_cmds = cpu_to_le16(s->fw_cmds);
806 info.max_sg_elements = cpu_to_le16(s->fw_sge);
807 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
808 if (!megasas_is_jbod(s))
809 info.lds_present = cpu_to_le16(num_pd_disks);
810 info.pd_present = cpu_to_le16(num_pd_disks);
811 info.pd_disks_present = cpu_to_le16(num_pd_disks);
812 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
813 MFI_INFO_HW_MEM |
814 MFI_INFO_HW_FLASH);
815 info.memory_size = cpu_to_le16(512);
816 info.nvram_size = cpu_to_le16(32);
817 info.flash_size = cpu_to_le16(16);
818 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
819 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
820 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
821 MFI_INFO_AOPS_MIXED_ARRAY);
822 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
823 MFI_INFO_LDOPS_ACCESS_POLICY |
824 MFI_INFO_LDOPS_IO_POLICY |
825 MFI_INFO_LDOPS_WRITE_POLICY |
826 MFI_INFO_LDOPS_READ_POLICY);
827 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
828 info.stripe_sz_ops.min = 3;
829 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
830 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
831 info.properties.intr_throttle_cnt = cpu_to_le16(16);
832 info.properties.intr_throttle_timeout = cpu_to_le16(50);
833 info.properties.rebuild_rate = 30;
834 info.properties.patrol_read_rate = 30;
835 info.properties.bgi_rate = 30;
836 info.properties.cc_rate = 30;
837 info.properties.recon_rate = 30;
838 info.properties.cache_flush_interval = 4;
839 info.properties.spinup_drv_cnt = 2;
840 info.properties.spinup_delay = 6;
841 info.properties.ecc_bucket_size = 15;
842 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
843 info.properties.expose_encl_devices = 1;
844 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
845 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
846 MFI_INFO_PDOPS_FORCE_OFFLINE);
847 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
848 MFI_INFO_PDMIX_SATA |
849 MFI_INFO_PDMIX_LD);
850
851 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
852 return MFI_STAT_OK;
853 }
854
855 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
856 {
857 struct mfi_defaults info;
858 size_t dcmd_size = sizeof(struct mfi_defaults);
859
860 memset(&info, 0x0, dcmd_size);
861 if (cmd->iov_size < dcmd_size) {
862 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
863 dcmd_size);
864 return MFI_STAT_INVALID_PARAMETER;
865 }
866
867 info.sas_addr = cpu_to_le64(s->sas_addr);
868 info.stripe_size = 3;
869 info.flush_time = 4;
870 info.background_rate = 30;
871 info.allow_mix_in_enclosure = 1;
872 info.allow_mix_in_ld = 1;
873 info.direct_pd_mapping = 1;
874 /* Enable for BIOS support */
875 info.bios_enumerate_lds = 1;
876 info.disable_ctrl_r = 1;
877 info.expose_enclosure_devices = 1;
878 info.disable_preboot_cli = 1;
879 info.cluster_disable = 1;
880
881 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
882 return MFI_STAT_OK;
883 }
884
885 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
886 {
887 struct mfi_bios_data info;
888 size_t dcmd_size = sizeof(info);
889
890 memset(&info, 0x0, dcmd_size);
891 if (cmd->iov_size < dcmd_size) {
892 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
893 dcmd_size);
894 return MFI_STAT_INVALID_PARAMETER;
895 }
896 info.continue_on_error = 1;
897 info.verbose = 1;
898 if (megasas_is_jbod(s)) {
899 info.expose_all_drives = 1;
900 }
901
902 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
903 return MFI_STAT_OK;
904 }
905
906 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
907 {
908 uint64_t fw_time;
909 size_t dcmd_size = sizeof(fw_time);
910
911 fw_time = cpu_to_le64(megasas_fw_time());
912
913 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
914 return MFI_STAT_OK;
915 }
916
917 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
918 {
919 uint64_t fw_time;
920
921 /* This is a dummy; setting of firmware time is not allowed */
922 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
923
924 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
925 fw_time = cpu_to_le64(megasas_fw_time());
926 return MFI_STAT_OK;
927 }
928
929 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
930 {
931 struct mfi_evt_log_state info;
932 size_t dcmd_size = sizeof(info);
933
934 memset(&info, 0, dcmd_size);
935
936 info.newest_seq_num = cpu_to_le32(s->event_count);
937 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
938 info.boot_seq_num = cpu_to_le32(s->boot_event);
939
940 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
941 return MFI_STAT_OK;
942 }
943
944 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
945 {
946 union mfi_evt event;
947
948 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
949 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
950 sizeof(struct mfi_evt_detail));
951 return MFI_STAT_INVALID_PARAMETER;
952 }
953 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
954 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
955 s->event_locale = event.members.locale;
956 s->event_class = event.members.class;
957 s->event_cmd = cmd;
958 /* Decrease busy count; event frame doesn't count here */
959 s->busy--;
960 cmd->iov_size = sizeof(struct mfi_evt_detail);
961 return MFI_STAT_INVALID_STATUS;
962 }
963
964 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
965 {
966 struct mfi_pd_list info;
967 size_t dcmd_size = sizeof(info);
968 BusChild *kid;
969 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
970
971 memset(&info, 0, dcmd_size);
972 offset = 8;
973 dcmd_limit = offset + sizeof(struct mfi_pd_address);
974 if (cmd->iov_size < dcmd_limit) {
975 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
976 dcmd_limit);
977 return MFI_STAT_INVALID_PARAMETER;
978 }
979
980 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
981 if (max_pd_disks > MFI_MAX_SYS_PDS) {
982 max_pd_disks = MFI_MAX_SYS_PDS;
983 }
984 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
985 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
986 uint16_t pd_id;
987
988 if (num_pd_disks >= max_pd_disks)
989 break;
990
991 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
992 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
993 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
994 info.addr[num_pd_disks].encl_index = 0;
995 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
996 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
997 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
998 info.addr[num_pd_disks].sas_addr[0] =
999 cpu_to_le64(megasas_get_sata_addr(pd_id));
1000 num_pd_disks++;
1001 offset += sizeof(struct mfi_pd_address);
1002 }
1003 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
1004 max_pd_disks, offset);
1005
1006 info.size = cpu_to_le32(offset);
1007 info.count = cpu_to_le32(num_pd_disks);
1008
1009 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
1010 return MFI_STAT_OK;
1011 }
1012
1013 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1014 {
1015 uint16_t flags;
1016
1017 /* mbox0 contains flags */
1018 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1019 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1020 if (flags == MR_PD_QUERY_TYPE_ALL ||
1021 megasas_is_jbod(s)) {
1022 return megasas_dcmd_pd_get_list(s, cmd);
1023 }
1024
1025 return MFI_STAT_OK;
1026 }
1027
1028 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1029 MegasasCmd *cmd)
1030 {
1031 struct mfi_pd_info *info = cmd->iov_buf;
1032 size_t dcmd_size = sizeof(struct mfi_pd_info);
1033 uint64_t pd_size;
1034 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1035 uint8_t cmdbuf[6];
1036 size_t len, resid;
1037
1038 if (!cmd->iov_buf) {
1039 cmd->iov_buf = g_malloc0(dcmd_size);
1040 info = cmd->iov_buf;
1041 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1042 info->vpd_page83[0] = 0x7f;
1043 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1044 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1045 if (!cmd->req) {
1046 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1047 "PD get info std inquiry");
1048 g_free(cmd->iov_buf);
1049 cmd->iov_buf = NULL;
1050 return MFI_STAT_FLASH_ALLOC_FAIL;
1051 }
1052 trace_megasas_dcmd_internal_submit(cmd->index,
1053 "PD get info std inquiry", lun);
1054 len = scsi_req_enqueue(cmd->req);
1055 if (len > 0) {
1056 cmd->iov_size = len;
1057 scsi_req_continue(cmd->req);
1058 }
1059 return MFI_STAT_INVALID_STATUS;
1060 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1061 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1062 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1063 if (!cmd->req) {
1064 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1065 "PD get info vpd inquiry");
1066 return MFI_STAT_FLASH_ALLOC_FAIL;
1067 }
1068 trace_megasas_dcmd_internal_submit(cmd->index,
1069 "PD get info vpd inquiry", lun);
1070 len = scsi_req_enqueue(cmd->req);
1071 if (len > 0) {
1072 cmd->iov_size = len;
1073 scsi_req_continue(cmd->req);
1074 }
1075 return MFI_STAT_INVALID_STATUS;
1076 }
1077 /* Finished, set FW state */
1078 if ((info->inquiry_data[0] >> 5) == 0) {
1079 if (megasas_is_jbod(cmd->state)) {
1080 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1081 } else {
1082 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1083 }
1084 } else {
1085 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1086 }
1087
1088 info->ref.v.device_id = cpu_to_le16(pd_id);
1089 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1090 MFI_PD_DDF_TYPE_INTF_SAS);
1091 blk_get_geometry(sdev->conf.blk, &pd_size);
1092 info->raw_size = cpu_to_le64(pd_size);
1093 info->non_coerced_size = cpu_to_le64(pd_size);
1094 info->coerced_size = cpu_to_le64(pd_size);
1095 info->encl_device_id = 0xFFFF;
1096 info->slot_number = (sdev->id & 0xFF);
1097 info->path_info.count = 1;
1098 info->path_info.sas_addr[0] =
1099 cpu_to_le64(megasas_get_sata_addr(pd_id));
1100 info->connected_port_bitmap = 0x1;
1101 info->device_speed = 1;
1102 info->link_speed = 1;
1103 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1104 g_free(cmd->iov_buf);
1105 cmd->iov_size = dcmd_size - resid;
1106 cmd->iov_buf = NULL;
1107 return MFI_STAT_OK;
1108 }
1109
1110 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1111 {
1112 size_t dcmd_size = sizeof(struct mfi_pd_info);
1113 uint16_t pd_id;
1114 uint8_t target_id, lun_id;
1115 SCSIDevice *sdev = NULL;
1116 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1117
1118 if (cmd->iov_size < dcmd_size) {
1119 return MFI_STAT_INVALID_PARAMETER;
1120 }
1121
1122 /* mbox0 has the ID */
1123 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1124 target_id = (pd_id >> 8) & 0xFF;
1125 lun_id = pd_id & 0xFF;
1126 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1127 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1128
1129 if (sdev) {
1130 /* Submit inquiry */
1131 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1132 }
1133
1134 return retval;
1135 }
1136
1137 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1138 {
1139 struct mfi_ld_list info;
1140 size_t dcmd_size = sizeof(info), resid;
1141 uint32_t num_ld_disks = 0, max_ld_disks;
1142 uint64_t ld_size;
1143 BusChild *kid;
1144
1145 memset(&info, 0, dcmd_size);
1146 if (cmd->iov_size > dcmd_size) {
1147 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1148 dcmd_size);
1149 return MFI_STAT_INVALID_PARAMETER;
1150 }
1151
1152 max_ld_disks = (cmd->iov_size - 8) / 16;
1153 if (megasas_is_jbod(s)) {
1154 max_ld_disks = 0;
1155 }
1156 if (max_ld_disks > MFI_MAX_LD) {
1157 max_ld_disks = MFI_MAX_LD;
1158 }
1159 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1160 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1161
1162 if (num_ld_disks >= max_ld_disks) {
1163 break;
1164 }
1165 /* Logical device size is in blocks */
1166 blk_get_geometry(sdev->conf.blk, &ld_size);
1167 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1168 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1169 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1170 num_ld_disks++;
1171 }
1172 info.ld_count = cpu_to_le32(num_ld_disks);
1173 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1174
1175 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1176 cmd->iov_size = dcmd_size - resid;
1177 return MFI_STAT_OK;
1178 }
1179
1180 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1181 {
1182 uint16_t flags;
1183 struct mfi_ld_targetid_list info;
1184 size_t dcmd_size = sizeof(info), resid;
1185 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1186 BusChild *kid;
1187
1188 /* mbox0 contains flags */
1189 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1190 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1191 if (flags != MR_LD_QUERY_TYPE_ALL &&
1192 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1193 max_ld_disks = 0;
1194 }
1195
1196 memset(&info, 0, dcmd_size);
1197 if (cmd->iov_size < 12) {
1198 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1199 dcmd_size);
1200 return MFI_STAT_INVALID_PARAMETER;
1201 }
1202 dcmd_size = sizeof(uint32_t) * 2 + 3;
1203 max_ld_disks = cmd->iov_size - dcmd_size;
1204 if (megasas_is_jbod(s)) {
1205 max_ld_disks = 0;
1206 }
1207 if (max_ld_disks > MFI_MAX_LD) {
1208 max_ld_disks = MFI_MAX_LD;
1209 }
1210 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1211 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1212
1213 if (num_ld_disks >= max_ld_disks) {
1214 break;
1215 }
1216 info.targetid[num_ld_disks] = sdev->lun;
1217 num_ld_disks++;
1218 dcmd_size++;
1219 }
1220 info.ld_count = cpu_to_le32(num_ld_disks);
1221 info.size = dcmd_size;
1222 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1223
1224 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1225 cmd->iov_size = dcmd_size - resid;
1226 return MFI_STAT_OK;
1227 }
1228
1229 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1230 MegasasCmd *cmd)
1231 {
1232 struct mfi_ld_info *info = cmd->iov_buf;
1233 size_t dcmd_size = sizeof(struct mfi_ld_info);
1234 uint8_t cdb[6];
1235 ssize_t len, resid;
1236 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1237 uint64_t ld_size;
1238
1239 if (!cmd->iov_buf) {
1240 cmd->iov_buf = g_malloc0(dcmd_size);
1241 info = cmd->iov_buf;
1242 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1243 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1244 if (!cmd->req) {
1245 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1246 "LD get info vpd inquiry");
1247 g_free(cmd->iov_buf);
1248 cmd->iov_buf = NULL;
1249 return MFI_STAT_FLASH_ALLOC_FAIL;
1250 }
1251 trace_megasas_dcmd_internal_submit(cmd->index,
1252 "LD get info vpd inquiry", lun);
1253 len = scsi_req_enqueue(cmd->req);
1254 if (len > 0) {
1255 cmd->iov_size = len;
1256 scsi_req_continue(cmd->req);
1257 }
1258 return MFI_STAT_INVALID_STATUS;
1259 }
1260
1261 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1262 info->ld_config.properties.ld.v.target_id = lun;
1263 info->ld_config.params.stripe_size = 3;
1264 info->ld_config.params.num_drives = 1;
1265 info->ld_config.params.is_consistent = 1;
1266 /* Logical device size is in blocks */
1267 blk_get_geometry(sdev->conf.blk, &ld_size);
1268 info->size = cpu_to_le64(ld_size);
1269 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1270 info->ld_config.span[0].start_block = 0;
1271 info->ld_config.span[0].num_blocks = info->size;
1272 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1273
1274 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1275 g_free(cmd->iov_buf);
1276 cmd->iov_size = dcmd_size - resid;
1277 cmd->iov_buf = NULL;
1278 return MFI_STAT_OK;
1279 }
1280
1281 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1282 {
1283 struct mfi_ld_info info;
1284 size_t dcmd_size = sizeof(info);
1285 uint16_t ld_id;
1286 uint32_t max_ld_disks = s->fw_luns;
1287 SCSIDevice *sdev = NULL;
1288 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1289
1290 if (cmd->iov_size < dcmd_size) {
1291 return MFI_STAT_INVALID_PARAMETER;
1292 }
1293
1294 /* mbox0 has the ID */
1295 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1296 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1297
1298 if (megasas_is_jbod(s)) {
1299 return MFI_STAT_DEVICE_NOT_FOUND;
1300 }
1301
1302 if (ld_id < max_ld_disks) {
1303 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1304 }
1305
1306 if (sdev) {
1307 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1308 }
1309
1310 return retval;
1311 }
1312
1313 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1314 {
1315 uint8_t data[4096] = { 0 };
1316 struct mfi_config_data *info;
1317 int num_pd_disks = 0, array_offset, ld_offset;
1318 BusChild *kid;
1319
1320 if (cmd->iov_size > 4096) {
1321 return MFI_STAT_INVALID_PARAMETER;
1322 }
1323
1324 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1325 num_pd_disks++;
1326 }
1327 info = (struct mfi_config_data *)&data;
1328 /*
1329 * Array mapping:
1330 * - One array per SCSI device
1331 * - One logical drive per SCSI device
1332 * spanning the entire device
1333 */
1334 info->array_count = num_pd_disks;
1335 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1336 info->log_drv_count = num_pd_disks;
1337 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1338 info->spares_count = 0;
1339 info->spares_size = sizeof(struct mfi_spare);
1340 info->size = sizeof(struct mfi_config_data) + info->array_size +
1341 info->log_drv_size;
1342 if (info->size > 4096) {
1343 return MFI_STAT_INVALID_PARAMETER;
1344 }
1345
1346 array_offset = sizeof(struct mfi_config_data);
1347 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1348
1349 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1350 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1351 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1352 struct mfi_array *array;
1353 struct mfi_ld_config *ld;
1354 uint64_t pd_size;
1355 int i;
1356
1357 array = (struct mfi_array *)(data + array_offset);
1358 blk_get_geometry(sdev->conf.blk, &pd_size);
1359 array->size = cpu_to_le64(pd_size);
1360 array->num_drives = 1;
1361 array->array_ref = cpu_to_le16(sdev_id);
1362 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1363 array->pd[0].ref.v.seq_num = 0;
1364 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1365 array->pd[0].encl.pd = 0xFF;
1366 array->pd[0].encl.slot = (sdev->id & 0xFF);
1367 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1368 array->pd[i].ref.v.device_id = 0xFFFF;
1369 array->pd[i].ref.v.seq_num = 0;
1370 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1371 array->pd[i].encl.pd = 0xFF;
1372 array->pd[i].encl.slot = 0xFF;
1373 }
1374 array_offset += sizeof(struct mfi_array);
1375 ld = (struct mfi_ld_config *)(data + ld_offset);
1376 memset(ld, 0, sizeof(struct mfi_ld_config));
1377 ld->properties.ld.v.target_id = sdev->id;
1378 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1379 MR_LD_CACHE_READ_ADAPTIVE;
1380 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1381 MR_LD_CACHE_READ_ADAPTIVE;
1382 ld->params.state = MFI_LD_STATE_OPTIMAL;
1383 ld->params.stripe_size = 3;
1384 ld->params.num_drives = 1;
1385 ld->params.span_depth = 1;
1386 ld->params.is_consistent = 1;
1387 ld->span[0].start_block = 0;
1388 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1389 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1390 ld_offset += sizeof(struct mfi_ld_config);
1391 }
1392
1393 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1394 return MFI_STAT_OK;
1395 }
1396
1397 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1398 {
1399 struct mfi_ctrl_props info;
1400 size_t dcmd_size = sizeof(info);
1401
1402 memset(&info, 0x0, dcmd_size);
1403 if (cmd->iov_size < dcmd_size) {
1404 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1405 dcmd_size);
1406 return MFI_STAT_INVALID_PARAMETER;
1407 }
1408 info.pred_fail_poll_interval = cpu_to_le16(300);
1409 info.intr_throttle_cnt = cpu_to_le16(16);
1410 info.intr_throttle_timeout = cpu_to_le16(50);
1411 info.rebuild_rate = 30;
1412 info.patrol_read_rate = 30;
1413 info.bgi_rate = 30;
1414 info.cc_rate = 30;
1415 info.recon_rate = 30;
1416 info.cache_flush_interval = 4;
1417 info.spinup_drv_cnt = 2;
1418 info.spinup_delay = 6;
1419 info.ecc_bucket_size = 15;
1420 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1421 info.expose_encl_devices = 1;
1422
1423 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1424 return MFI_STAT_OK;
1425 }
1426
1427 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1428 {
1429 blk_drain_all();
1430 return MFI_STAT_OK;
1431 }
1432
1433 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1434 {
1435 s->fw_state = MFI_FWSTATE_READY;
1436 return MFI_STAT_OK;
1437 }
1438
1439 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
1440 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1441 {
1442 uint16_t target_id;
1443 int i;
1444
1445 /* mbox0 contains the device index */
1446 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1447 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1448 for (i = 0; i < s->fw_cmds; i++) {
1449 MegasasCmd *tmp_cmd = &s->frames[i];
1450 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1451 SCSIDevice *d = tmp_cmd->req->dev;
1452 qdev_reset_all(&d->qdev);
1453 }
1454 }
1455 return MFI_STAT_OK;
1456 }
1457
1458 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1459 {
1460 struct mfi_ctrl_props info;
1461 size_t dcmd_size = sizeof(info);
1462
1463 if (cmd->iov_size < dcmd_size) {
1464 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1465 dcmd_size);
1466 return MFI_STAT_INVALID_PARAMETER;
1467 }
1468 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1469 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1470 return MFI_STAT_OK;
1471 }
1472
1473 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1474 {
1475 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1476 return MFI_STAT_OK;
1477 }
1478
1479 static const struct dcmd_cmd_tbl_t {
1480 int opcode;
1481 const char *desc;
1482 int (*func)(MegasasState *s, MegasasCmd *cmd);
1483 } dcmd_cmd_tbl[] = {
1484 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1485 megasas_dcmd_dummy },
1486 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1487 megasas_ctrl_get_info },
1488 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1489 megasas_dcmd_get_properties },
1490 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1491 megasas_dcmd_set_properties },
1492 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1493 megasas_dcmd_dummy },
1494 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1495 megasas_dcmd_dummy },
1496 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1497 megasas_dcmd_dummy },
1498 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1499 megasas_dcmd_dummy },
1500 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1501 megasas_dcmd_dummy },
1502 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1503 megasas_event_info },
1504 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1505 megasas_dcmd_dummy },
1506 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1507 megasas_event_wait },
1508 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1509 megasas_ctrl_shutdown },
1510 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1511 megasas_dcmd_dummy },
1512 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1513 megasas_dcmd_get_fw_time },
1514 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1515 megasas_dcmd_set_fw_time },
1516 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1517 megasas_dcmd_get_bios_info },
1518 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1519 megasas_dcmd_dummy },
1520 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1521 megasas_mfc_get_defaults },
1522 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1523 megasas_dcmd_dummy },
1524 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1525 megasas_cache_flush },
1526 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1527 megasas_dcmd_pd_get_list },
1528 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1529 megasas_dcmd_pd_list_query },
1530 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1531 megasas_dcmd_pd_get_info },
1532 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1533 megasas_dcmd_dummy },
1534 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1535 megasas_dcmd_dummy },
1536 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1537 megasas_dcmd_dummy },
1538 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1539 megasas_dcmd_dummy },
1540 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1541 megasas_dcmd_ld_get_list},
1542 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1543 megasas_dcmd_ld_list_query },
1544 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1545 megasas_dcmd_ld_get_info },
1546 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_CFG_READ, "CFG_READ",
1553 megasas_dcmd_cfg_read },
1554 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1555 megasas_dcmd_dummy },
1556 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1557 megasas_dcmd_dummy },
1558 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1559 megasas_dcmd_dummy },
1560 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1561 megasas_dcmd_dummy },
1562 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1563 megasas_dcmd_dummy },
1564 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1565 megasas_dcmd_dummy },
1566 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1567 megasas_dcmd_dummy },
1568 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1569 megasas_dcmd_dummy },
1570 { MFI_DCMD_CLUSTER, "CLUSTER",
1571 megasas_dcmd_dummy },
1572 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1573 megasas_dcmd_dummy },
1574 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1575 megasas_cluster_reset_ld },
1576 { -1, NULL, NULL }
1577 };
1578
1579 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1580 {
1581 int retval = 0;
1582 size_t len;
1583 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1584
1585 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1586 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
1587 if (megasas_map_dcmd(s, cmd) < 0) {
1588 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1589 }
1590 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
1591 cmdptr++;
1592 }
1593 len = cmd->iov_size;
1594 if (cmdptr->opcode == -1) {
1595 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
1596 retval = megasas_dcmd_dummy(s, cmd);
1597 } else {
1598 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1599 retval = cmdptr->func(s, cmd);
1600 }
1601 if (retval != MFI_STAT_INVALID_STATUS) {
1602 megasas_finish_dcmd(cmd, len);
1603 }
1604 return retval;
1605 }
1606
1607 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1608 SCSIRequest *req, size_t resid)
1609 {
1610 int retval = MFI_STAT_OK;
1611 int lun = req->lun;
1612
1613 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
1614 cmd->iov_size -= resid;
1615 switch (cmd->dcmd_opcode) {
1616 case MFI_DCMD_PD_GET_INFO:
1617 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1618 break;
1619 case MFI_DCMD_LD_GET_INFO:
1620 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1621 break;
1622 default:
1623 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
1624 retval = MFI_STAT_INVALID_DCMD;
1625 break;
1626 }
1627 if (retval != MFI_STAT_INVALID_STATUS) {
1628 megasas_finish_dcmd(cmd, cmd->iov_size);
1629 }
1630 return retval;
1631 }
1632
1633 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1634 {
1635 int len;
1636
1637 len = scsi_req_enqueue(cmd->req);
1638 if (len < 0) {
1639 len = -len;
1640 }
1641 if (len > 0) {
1642 if (len > cmd->iov_size) {
1643 if (is_write) {
1644 trace_megasas_iov_write_overflow(cmd->index, len,
1645 cmd->iov_size);
1646 } else {
1647 trace_megasas_iov_read_overflow(cmd->index, len,
1648 cmd->iov_size);
1649 }
1650 }
1651 if (len < cmd->iov_size) {
1652 if (is_write) {
1653 trace_megasas_iov_write_underflow(cmd->index, len,
1654 cmd->iov_size);
1655 } else {
1656 trace_megasas_iov_read_underflow(cmd->index, len,
1657 cmd->iov_size);
1658 }
1659 cmd->iov_size = len;
1660 }
1661 scsi_req_continue(cmd->req);
1662 }
1663 return len;
1664 }
1665
1666 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1667 int frame_cmd)
1668 {
1669 uint8_t *cdb;
1670 int target_id, lun_id, cdb_len;
1671 bool is_write;
1672 struct SCSIDevice *sdev = NULL;
1673 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
1674
1675 cdb = cmd->frame->pass.cdb;
1676 target_id = cmd->frame->header.target_id;
1677 lun_id = cmd->frame->header.lun_id;
1678 cdb_len = cmd->frame->header.cdb_len;
1679
1680 if (is_logical) {
1681 if (target_id >= MFI_MAX_LD || lun_id != 0) {
1682 trace_megasas_scsi_target_not_present(
1683 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
1684 return MFI_STAT_DEVICE_NOT_FOUND;
1685 }
1686 }
1687 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1688
1689 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1690 trace_megasas_handle_scsi(mfi_frame_desc(frame_cmd), is_logical,
1691 target_id, lun_id, sdev, cmd->iov_size);
1692
1693 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1694 trace_megasas_scsi_target_not_present(
1695 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
1696 return MFI_STAT_DEVICE_NOT_FOUND;
1697 }
1698
1699 if (cdb_len > 16) {
1700 trace_megasas_scsi_invalid_cdb_len(
1701 mfi_frame_desc(frame_cmd), is_logical,
1702 target_id, lun_id, cdb_len);
1703 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1704 cmd->frame->header.scsi_status = CHECK_CONDITION;
1705 s->event_count++;
1706 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1707 }
1708
1709 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1710 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1711 cmd->frame->header.scsi_status = CHECK_CONDITION;
1712 s->event_count++;
1713 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1714 }
1715
1716 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cmd);
1717 if (!cmd->req) {
1718 trace_megasas_scsi_req_alloc_failed(
1719 mfi_frame_desc(frame_cmd), target_id, lun_id);
1720 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1721 cmd->frame->header.scsi_status = BUSY;
1722 s->event_count++;
1723 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1724 }
1725
1726 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1727 if (cmd->iov_size) {
1728 if (is_write) {
1729 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1730 } else {
1731 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1732 }
1733 } else {
1734 trace_megasas_scsi_nodata(cmd->index);
1735 }
1736 megasas_enqueue_req(cmd, is_write);
1737 return MFI_STAT_INVALID_STATUS;
1738 }
1739
1740 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
1741 {
1742 uint32_t lba_count, lba_start_hi, lba_start_lo;
1743 uint64_t lba_start;
1744 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
1745 uint8_t cdb[16];
1746 int len;
1747 struct SCSIDevice *sdev = NULL;
1748 int target_id, lun_id, cdb_len;
1749
1750 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1751 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1752 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1753 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1754
1755 target_id = cmd->frame->header.target_id;
1756 lun_id = cmd->frame->header.lun_id;
1757 cdb_len = cmd->frame->header.cdb_len;
1758
1759 if (target_id < MFI_MAX_LD && lun_id == 0) {
1760 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1761 }
1762
1763 trace_megasas_handle_io(cmd->index,
1764 mfi_frame_desc(frame_cmd), target_id, lun_id,
1765 (unsigned long)lba_start, (unsigned long)lba_count);
1766 if (!sdev) {
1767 trace_megasas_io_target_not_present(cmd->index,
1768 mfi_frame_desc(frame_cmd), target_id, lun_id);
1769 return MFI_STAT_DEVICE_NOT_FOUND;
1770 }
1771
1772 if (cdb_len > 16) {
1773 trace_megasas_scsi_invalid_cdb_len(
1774 mfi_frame_desc(frame_cmd), 1, target_id, lun_id, cdb_len);
1775 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1776 cmd->frame->header.scsi_status = CHECK_CONDITION;
1777 s->event_count++;
1778 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1779 }
1780
1781 cmd->iov_size = lba_count * sdev->blocksize;
1782 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1783 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1784 cmd->frame->header.scsi_status = CHECK_CONDITION;
1785 s->event_count++;
1786 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1787 }
1788
1789 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1790 cmd->req = scsi_req_new(sdev, cmd->index,
1791 lun_id, cdb, cmd);
1792 if (!cmd->req) {
1793 trace_megasas_scsi_req_alloc_failed(
1794 mfi_frame_desc(frame_cmd), target_id, lun_id);
1795 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1796 cmd->frame->header.scsi_status = BUSY;
1797 s->event_count++;
1798 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1799 }
1800 len = megasas_enqueue_req(cmd, is_write);
1801 if (len > 0) {
1802 if (is_write) {
1803 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1804 } else {
1805 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1806 }
1807 }
1808 return MFI_STAT_INVALID_STATUS;
1809 }
1810
1811 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1812 {
1813 MegasasCmd *cmd = req->hba_private;
1814
1815 if (cmd->dcmd_opcode != -1) {
1816 return NULL;
1817 } else {
1818 return &cmd->qsg;
1819 }
1820 }
1821
1822 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1823 {
1824 MegasasCmd *cmd = req->hba_private;
1825 uint8_t *buf;
1826
1827 trace_megasas_io_complete(cmd->index, len);
1828
1829 if (cmd->dcmd_opcode != -1) {
1830 scsi_req_continue(req);
1831 return;
1832 }
1833
1834 buf = scsi_req_get_buf(req);
1835 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1836 struct mfi_pd_info *info = cmd->iov_buf;
1837
1838 if (info->inquiry_data[0] == 0x7f) {
1839 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1840 memcpy(info->inquiry_data, buf, len);
1841 } else if (info->vpd_page83[0] == 0x7f) {
1842 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1843 memcpy(info->vpd_page83, buf, len);
1844 }
1845 scsi_req_continue(req);
1846 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
1847 struct mfi_ld_info *info = cmd->iov_buf;
1848
1849 if (cmd->iov_buf) {
1850 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1851 scsi_req_continue(req);
1852 }
1853 }
1854 }
1855
1856 static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1857 size_t resid)
1858 {
1859 MegasasCmd *cmd = req->hba_private;
1860 uint8_t cmd_status = MFI_STAT_OK;
1861
1862 trace_megasas_command_complete(cmd->index, status, resid);
1863
1864 if (req->io_canceled) {
1865 return;
1866 }
1867
1868 if (cmd->dcmd_opcode != -1) {
1869 /*
1870 * Internal command complete
1871 */
1872 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
1873 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1874 return;
1875 }
1876 } else {
1877 req->status = status;
1878 trace_megasas_scsi_complete(cmd->index, req->status,
1879 cmd->iov_size, req->cmd.xfer);
1880 if (req->status != GOOD) {
1881 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1882 }
1883 if (req->status == CHECK_CONDITION) {
1884 megasas_copy_sense(cmd);
1885 }
1886
1887 cmd->frame->header.scsi_status = req->status;
1888 }
1889 cmd->frame->header.cmd_status = cmd_status;
1890 megasas_complete_command(cmd);
1891 }
1892
1893 static void megasas_command_cancelled(SCSIRequest *req)
1894 {
1895 MegasasCmd *cmd = req->hba_private;
1896
1897 if (!cmd) {
1898 return;
1899 }
1900 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1901 megasas_complete_command(cmd);
1902 }
1903
1904 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1905 {
1906 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1907 hwaddr abort_addr, addr_hi, addr_lo;
1908 MegasasCmd *abort_cmd;
1909
1910 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1911 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1912 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1913
1914 abort_cmd = megasas_lookup_frame(s, abort_addr);
1915 if (!abort_cmd) {
1916 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1917 s->event_count++;
1918 return MFI_STAT_OK;
1919 }
1920 if (!megasas_use_queue64(s)) {
1921 abort_ctx &= (uint64_t)0xFFFFFFFF;
1922 }
1923 if (abort_cmd->context != abort_ctx) {
1924 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1925 abort_cmd->index);
1926 s->event_count++;
1927 return MFI_STAT_ABORT_NOT_POSSIBLE;
1928 }
1929 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1930 megasas_abort_command(abort_cmd);
1931 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1932 s->event_cmd = NULL;
1933 }
1934 s->event_count++;
1935 return MFI_STAT_OK;
1936 }
1937
1938 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1939 uint32_t frame_count)
1940 {
1941 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1942 uint64_t frame_context;
1943 int frame_cmd;
1944 MegasasCmd *cmd;
1945
1946 /*
1947 * Always read 64bit context, top bits will be
1948 * masked out if required in megasas_enqueue_frame()
1949 */
1950 frame_context = megasas_frame_get_context(s, frame_addr);
1951
1952 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1953 if (!cmd) {
1954 /* reply queue full */
1955 trace_megasas_frame_busy(frame_addr);
1956 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1957 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1958 megasas_complete_frame(s, frame_context);
1959 s->event_count++;
1960 return;
1961 }
1962 frame_cmd = cmd->frame->header.frame_cmd;
1963 switch (frame_cmd) {
1964 case MFI_CMD_INIT:
1965 frame_status = megasas_init_firmware(s, cmd);
1966 break;
1967 case MFI_CMD_DCMD:
1968 frame_status = megasas_handle_dcmd(s, cmd);
1969 break;
1970 case MFI_CMD_ABORT:
1971 frame_status = megasas_handle_abort(s, cmd);
1972 break;
1973 case MFI_CMD_PD_SCSI_IO:
1974 case MFI_CMD_LD_SCSI_IO:
1975 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
1976 break;
1977 case MFI_CMD_LD_READ:
1978 case MFI_CMD_LD_WRITE:
1979 frame_status = megasas_handle_io(s, cmd, frame_cmd);
1980 break;
1981 default:
1982 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
1983 s->event_count++;
1984 break;
1985 }
1986 if (frame_status != MFI_STAT_INVALID_STATUS) {
1987 if (cmd->frame) {
1988 cmd->frame->header.cmd_status = frame_status;
1989 } else {
1990 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1991 }
1992 megasas_unmap_frame(s, cmd);
1993 megasas_complete_frame(s, cmd->context);
1994 }
1995 }
1996
1997 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
1998 unsigned size)
1999 {
2000 MegasasState *s = opaque;
2001 PCIDevice *pci_dev = PCI_DEVICE(s);
2002 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
2003 uint32_t retval = 0;
2004
2005 switch (addr) {
2006 case MFI_IDB:
2007 retval = 0;
2008 trace_megasas_mmio_readl("MFI_IDB", retval);
2009 break;
2010 case MFI_OMSG0:
2011 case MFI_OSP0:
2012 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2013 (s->fw_state & MFI_FWSTATE_MASK) |
2014 ((s->fw_sge & 0xff) << 16) |
2015 (s->fw_cmds & 0xFFFF);
2016 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2017 retval);
2018 break;
2019 case MFI_OSTS:
2020 if (megasas_intr_enabled(s) && s->doorbell) {
2021 retval = base_class->osts;
2022 }
2023 trace_megasas_mmio_readl("MFI_OSTS", retval);
2024 break;
2025 case MFI_OMSK:
2026 retval = s->intr_mask;
2027 trace_megasas_mmio_readl("MFI_OMSK", retval);
2028 break;
2029 case MFI_ODCR0:
2030 retval = s->doorbell ? 1 : 0;
2031 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2032 break;
2033 case MFI_DIAG:
2034 retval = s->diag;
2035 trace_megasas_mmio_readl("MFI_DIAG", retval);
2036 break;
2037 case MFI_OSP1:
2038 retval = 15;
2039 trace_megasas_mmio_readl("MFI_OSP1", retval);
2040 break;
2041 default:
2042 trace_megasas_mmio_invalid_readl(addr);
2043 break;
2044 }
2045 return retval;
2046 }
2047
2048 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2049
2050 static void megasas_mmio_write(void *opaque, hwaddr addr,
2051 uint64_t val, unsigned size)
2052 {
2053 MegasasState *s = opaque;
2054 PCIDevice *pci_dev = PCI_DEVICE(s);
2055 uint64_t frame_addr;
2056 uint32_t frame_count;
2057 int i;
2058
2059 switch (addr) {
2060 case MFI_IDB:
2061 trace_megasas_mmio_writel("MFI_IDB", val);
2062 if (val & MFI_FWINIT_ABORT) {
2063 /* Abort all pending cmds */
2064 for (i = 0; i < s->fw_cmds; i++) {
2065 megasas_abort_command(&s->frames[i]);
2066 }
2067 }
2068 if (val & MFI_FWINIT_READY) {
2069 /* move to FW READY */
2070 megasas_soft_reset(s);
2071 }
2072 if (val & MFI_FWINIT_MFIMODE) {
2073 /* discard MFIs */
2074 }
2075 if (val & MFI_FWINIT_STOP_ADP) {
2076 /* Terminal error, stop processing */
2077 s->fw_state = MFI_FWSTATE_FAULT;
2078 }
2079 break;
2080 case MFI_OMSK:
2081 trace_megasas_mmio_writel("MFI_OMSK", val);
2082 s->intr_mask = val;
2083 if (!megasas_intr_enabled(s) &&
2084 !msi_enabled(pci_dev) &&
2085 !msix_enabled(pci_dev)) {
2086 trace_megasas_irq_lower();
2087 pci_irq_deassert(pci_dev);
2088 }
2089 if (megasas_intr_enabled(s)) {
2090 if (msix_enabled(pci_dev)) {
2091 trace_megasas_msix_enabled(0);
2092 } else if (msi_enabled(pci_dev)) {
2093 trace_megasas_msi_enabled(0);
2094 } else {
2095 trace_megasas_intr_enabled();
2096 }
2097 } else {
2098 trace_megasas_intr_disabled();
2099 megasas_soft_reset(s);
2100 }
2101 break;
2102 case MFI_ODCR0:
2103 trace_megasas_mmio_writel("MFI_ODCR0", val);
2104 s->doorbell = 0;
2105 if (megasas_intr_enabled(s)) {
2106 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2107 trace_megasas_irq_lower();
2108 pci_irq_deassert(pci_dev);
2109 }
2110 }
2111 break;
2112 case MFI_IQPH:
2113 trace_megasas_mmio_writel("MFI_IQPH", val);
2114 /* Received high 32 bits of a 64 bit MFI frame address */
2115 s->frame_hi = val;
2116 break;
2117 case MFI_IQPL:
2118 trace_megasas_mmio_writel("MFI_IQPL", val);
2119 /* Received low 32 bits of a 64 bit MFI frame address */
2120 /* Fallthrough */
2121 case MFI_IQP:
2122 if (addr == MFI_IQP) {
2123 trace_megasas_mmio_writel("MFI_IQP", val);
2124 /* Received 64 bit MFI frame address */
2125 s->frame_hi = 0;
2126 }
2127 frame_addr = (val & ~0x1F);
2128 /* Add possible 64 bit offset */
2129 frame_addr |= ((uint64_t)s->frame_hi << 32);
2130 s->frame_hi = 0;
2131 frame_count = (val >> 1) & 0xF;
2132 megasas_handle_frame(s, frame_addr, frame_count);
2133 break;
2134 case MFI_SEQ:
2135 trace_megasas_mmio_writel("MFI_SEQ", val);
2136 /* Magic sequence to start ADP reset */
2137 if (adp_reset_seq[s->adp_reset++] == val) {
2138 if (s->adp_reset == 6) {
2139 s->adp_reset = 0;
2140 s->diag = MFI_DIAG_WRITE_ENABLE;
2141 }
2142 } else {
2143 s->adp_reset = 0;
2144 s->diag = 0;
2145 }
2146 break;
2147 case MFI_DIAG:
2148 trace_megasas_mmio_writel("MFI_DIAG", val);
2149 /* ADP reset */
2150 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2151 (val & MFI_DIAG_RESET_ADP)) {
2152 s->diag |= MFI_DIAG_RESET_ADP;
2153 megasas_soft_reset(s);
2154 s->adp_reset = 0;
2155 s->diag = 0;
2156 }
2157 break;
2158 default:
2159 trace_megasas_mmio_invalid_writel(addr, val);
2160 break;
2161 }
2162 }
2163
2164 static const MemoryRegionOps megasas_mmio_ops = {
2165 .read = megasas_mmio_read,
2166 .write = megasas_mmio_write,
2167 .endianness = DEVICE_LITTLE_ENDIAN,
2168 .impl = {
2169 .min_access_size = 8,
2170 .max_access_size = 8,
2171 }
2172 };
2173
2174 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2175 unsigned size)
2176 {
2177 return megasas_mmio_read(opaque, addr & 0xff, size);
2178 }
2179
2180 static void megasas_port_write(void *opaque, hwaddr addr,
2181 uint64_t val, unsigned size)
2182 {
2183 megasas_mmio_write(opaque, addr & 0xff, val, size);
2184 }
2185
2186 static const MemoryRegionOps megasas_port_ops = {
2187 .read = megasas_port_read,
2188 .write = megasas_port_write,
2189 .endianness = DEVICE_LITTLE_ENDIAN,
2190 .impl = {
2191 .min_access_size = 4,
2192 .max_access_size = 4,
2193 }
2194 };
2195
2196 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2197 unsigned size)
2198 {
2199 return 0;
2200 }
2201
2202 static void megasas_queue_write(void *opaque, hwaddr addr,
2203 uint64_t val, unsigned size)
2204 {
2205 return;
2206 }
2207
2208 static const MemoryRegionOps megasas_queue_ops = {
2209 .read = megasas_queue_read,
2210 .write = megasas_queue_write,
2211 .endianness = DEVICE_LITTLE_ENDIAN,
2212 .impl = {
2213 .min_access_size = 8,
2214 .max_access_size = 8,
2215 }
2216 };
2217
2218 static void megasas_soft_reset(MegasasState *s)
2219 {
2220 int i;
2221 MegasasCmd *cmd;
2222
2223 trace_megasas_reset(s->fw_state);
2224 for (i = 0; i < s->fw_cmds; i++) {
2225 cmd = &s->frames[i];
2226 megasas_abort_command(cmd);
2227 }
2228 if (s->fw_state == MFI_FWSTATE_READY) {
2229 BusChild *kid;
2230
2231 /*
2232 * The EFI firmware doesn't handle UA,
2233 * so we need to clear the Power On/Reset UA
2234 * after the initial reset.
2235 */
2236 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2237 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2238
2239 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2240 scsi_device_unit_attention_reported(sdev);
2241 }
2242 }
2243 megasas_reset_frames(s);
2244 s->reply_queue_len = s->fw_cmds;
2245 s->reply_queue_pa = 0;
2246 s->consumer_pa = 0;
2247 s->producer_pa = 0;
2248 s->fw_state = MFI_FWSTATE_READY;
2249 s->doorbell = 0;
2250 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2251 s->frame_hi = 0;
2252 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2253 s->event_count++;
2254 s->boot_event = s->event_count;
2255 }
2256
2257 static void megasas_scsi_reset(DeviceState *dev)
2258 {
2259 MegasasState *s = MEGASAS(dev);
2260
2261 megasas_soft_reset(s);
2262 }
2263
2264 static const VMStateDescription vmstate_megasas_gen1 = {
2265 .name = "megasas",
2266 .version_id = 0,
2267 .minimum_version_id = 0,
2268 .fields = (VMStateField[]) {
2269 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2270 VMSTATE_MSIX(parent_obj, MegasasState),
2271
2272 VMSTATE_UINT32(fw_state, MegasasState),
2273 VMSTATE_UINT32(intr_mask, MegasasState),
2274 VMSTATE_UINT32(doorbell, MegasasState),
2275 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2276 VMSTATE_UINT64(consumer_pa, MegasasState),
2277 VMSTATE_UINT64(producer_pa, MegasasState),
2278 VMSTATE_END_OF_LIST()
2279 }
2280 };
2281
2282 static const VMStateDescription vmstate_megasas_gen2 = {
2283 .name = "megasas-gen2",
2284 .version_id = 0,
2285 .minimum_version_id = 0,
2286 .minimum_version_id_old = 0,
2287 .fields = (VMStateField[]) {
2288 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2289 VMSTATE_MSIX(parent_obj, MegasasState),
2290
2291 VMSTATE_UINT32(fw_state, MegasasState),
2292 VMSTATE_UINT32(intr_mask, MegasasState),
2293 VMSTATE_UINT32(doorbell, MegasasState),
2294 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2295 VMSTATE_UINT64(consumer_pa, MegasasState),
2296 VMSTATE_UINT64(producer_pa, MegasasState),
2297 VMSTATE_END_OF_LIST()
2298 }
2299 };
2300
2301 static void megasas_scsi_uninit(PCIDevice *d)
2302 {
2303 MegasasState *s = MEGASAS(d);
2304
2305 if (megasas_use_msix(s)) {
2306 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2307 }
2308 msi_uninit(d);
2309 }
2310
2311 static const struct SCSIBusInfo megasas_scsi_info = {
2312 .tcq = true,
2313 .max_target = MFI_MAX_LD,
2314 .max_lun = 255,
2315
2316 .transfer_data = megasas_xfer_complete,
2317 .get_sg_list = megasas_get_sg_list,
2318 .complete = megasas_command_complete,
2319 .cancel = megasas_command_cancelled,
2320 };
2321
2322 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2323 {
2324 MegasasState *s = MEGASAS(dev);
2325 MegasasBaseClass *b = MEGASAS_GET_CLASS(s);
2326 uint8_t *pci_conf;
2327 int i, bar_type;
2328 Error *err = NULL;
2329 int ret;
2330
2331 pci_conf = dev->config;
2332
2333 /* PCI latency timer = 0 */
2334 pci_conf[PCI_LATENCY_TIMER] = 0;
2335 /* Interrupt pin 1 */
2336 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2337
2338 if (s->msi != ON_OFF_AUTO_OFF) {
2339 ret = msi_init(dev, 0x50, 1, true, false, &err);
2340 /* Any error other than -ENOTSUP(board's MSI support is broken)
2341 * is a programming error */
2342 assert(!ret || ret == -ENOTSUP);
2343 if (ret && s->msi == ON_OFF_AUTO_ON) {
2344 /* Can't satisfy user's explicit msi=on request, fail */
2345 error_append_hint(&err, "You have to use msi=auto (default) or "
2346 "msi=off with this machine type.\n");
2347 error_propagate(errp, err);
2348 return;
2349 } else if (ret) {
2350 /* With msi=auto, we fall back to MSI off silently */
2351 s->msi = ON_OFF_AUTO_OFF;
2352 error_free(err);
2353 }
2354 }
2355
2356 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2357 "megasas-mmio", 0x4000);
2358 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2359 "megasas-io", 256);
2360 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2361 "megasas-queue", 0x40000);
2362
2363 if (megasas_use_msix(s) &&
2364 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2365 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2366 /* TODO: check msix_init's error, and should fail on msix=on */
2367 s->msix = ON_OFF_AUTO_OFF;
2368 }
2369
2370 if (pci_is_express(dev)) {
2371 pcie_endpoint_cap_init(dev, 0xa0);
2372 }
2373
2374 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2375 pci_register_bar(dev, b->ioport_bar,
2376 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2377 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2378 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2379
2380 if (megasas_use_msix(s)) {
2381 msix_vector_use(dev, 0);
2382 }
2383
2384 s->fw_state = MFI_FWSTATE_READY;
2385 if (!s->sas_addr) {
2386 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2387 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2388 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
2389 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2390 s->sas_addr |= PCI_FUNC(dev->devfn);
2391 }
2392 if (!s->hba_serial) {
2393 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2394 }
2395 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2396 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2397 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2398 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2399 } else {
2400 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2401 }
2402 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2403 s->fw_cmds = MEGASAS_MAX_FRAMES;
2404 }
2405 trace_megasas_init(s->fw_sge, s->fw_cmds,
2406 megasas_is_jbod(s) ? "jbod" : "raid");
2407
2408 if (megasas_is_jbod(s)) {
2409 s->fw_luns = MFI_MAX_SYS_PDS;
2410 } else {
2411 s->fw_luns = MFI_MAX_LD;
2412 }
2413 s->producer_pa = 0;
2414 s->consumer_pa = 0;
2415 for (i = 0; i < s->fw_cmds; i++) {
2416 s->frames[i].index = i;
2417 s->frames[i].context = -1;
2418 s->frames[i].pa = 0;
2419 s->frames[i].state = s;
2420 }
2421
2422 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2423 &megasas_scsi_info, NULL);
2424 }
2425
2426 static Property megasas_properties_gen1[] = {
2427 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2428 MEGASAS_DEFAULT_SGE),
2429 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2430 MEGASAS_DEFAULT_FRAMES),
2431 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2432 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2433 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2434 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2435 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2436 MEGASAS_FLAG_USE_JBOD, false),
2437 DEFINE_PROP_END_OF_LIST(),
2438 };
2439
2440 static Property megasas_properties_gen2[] = {
2441 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2442 MEGASAS_DEFAULT_SGE),
2443 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2444 MEGASAS_GEN2_DEFAULT_FRAMES),
2445 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2446 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2447 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2448 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2449 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2450 MEGASAS_FLAG_USE_JBOD, false),
2451 DEFINE_PROP_END_OF_LIST(),
2452 };
2453
2454 typedef struct MegasasInfo {
2455 const char *name;
2456 const char *desc;
2457 const char *product_name;
2458 const char *product_version;
2459 uint16_t device_id;
2460 uint16_t subsystem_id;
2461 int ioport_bar;
2462 int mmio_bar;
2463 int osts;
2464 const VMStateDescription *vmsd;
2465 Property *props;
2466 InterfaceInfo *interfaces;
2467 } MegasasInfo;
2468
2469 static struct MegasasInfo megasas_devices[] = {
2470 {
2471 .name = TYPE_MEGASAS_GEN1,
2472 .desc = "LSI MegaRAID SAS 1078",
2473 .product_name = "LSI MegaRAID SAS 8708EM2",
2474 .product_version = MEGASAS_VERSION_GEN1,
2475 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2476 .subsystem_id = 0x1013,
2477 .ioport_bar = 2,
2478 .mmio_bar = 0,
2479 .osts = MFI_1078_RM | 1,
2480 .vmsd = &vmstate_megasas_gen1,
2481 .props = megasas_properties_gen1,
2482 .interfaces = (InterfaceInfo[]) {
2483 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2484 { },
2485 },
2486 },{
2487 .name = TYPE_MEGASAS_GEN2,
2488 .desc = "LSI MegaRAID SAS 2108",
2489 .product_name = "LSI MegaRAID SAS 9260-8i",
2490 .product_version = MEGASAS_VERSION_GEN2,
2491 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2492 .subsystem_id = 0x9261,
2493 .ioport_bar = 0,
2494 .mmio_bar = 1,
2495 .osts = MFI_GEN2_RM,
2496 .vmsd = &vmstate_megasas_gen2,
2497 .props = megasas_properties_gen2,
2498 .interfaces = (InterfaceInfo[]) {
2499 { INTERFACE_PCIE_DEVICE },
2500 { }
2501 },
2502 }
2503 };
2504
2505 static void megasas_class_init(ObjectClass *oc, void *data)
2506 {
2507 DeviceClass *dc = DEVICE_CLASS(oc);
2508 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2509 MegasasBaseClass *e = MEGASAS_CLASS(oc);
2510 const MegasasInfo *info = data;
2511
2512 pc->realize = megasas_scsi_realize;
2513 pc->exit = megasas_scsi_uninit;
2514 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2515 pc->device_id = info->device_id;
2516 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2517 pc->subsystem_id = info->subsystem_id;
2518 pc->class_id = PCI_CLASS_STORAGE_RAID;
2519 e->mmio_bar = info->mmio_bar;
2520 e->ioport_bar = info->ioport_bar;
2521 e->osts = info->osts;
2522 e->product_name = info->product_name;
2523 e->product_version = info->product_version;
2524 device_class_set_props(dc, info->props);
2525 dc->reset = megasas_scsi_reset;
2526 dc->vmsd = info->vmsd;
2527 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2528 dc->desc = info->desc;
2529 }
2530
2531 static const TypeInfo megasas_info = {
2532 .name = TYPE_MEGASAS_BASE,
2533 .parent = TYPE_PCI_DEVICE,
2534 .instance_size = sizeof(MegasasState),
2535 .class_size = sizeof(MegasasBaseClass),
2536 .abstract = true,
2537 };
2538
2539 static void megasas_register_types(void)
2540 {
2541 int i;
2542
2543 type_register_static(&megasas_info);
2544 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2545 const MegasasInfo *info = &megasas_devices[i];
2546 TypeInfo type_info = {};
2547
2548 type_info.name = info->name;
2549 type_info.parent = TYPE_MEGASAS_BASE;
2550 type_info.class_data = (void *)info;
2551 type_info.class_init = megasas_class_init;
2552 type_info.interfaces = info->interfaces;
2553
2554 type_register(&type_info);
2555 }
2556 }
2557
2558 type_init(megasas_register_types)
AR7 emulation for QEMU