2 * QEMU RISC-V VirtIO Board
4 * Copyright (c) 2017 SiFive, Inc.
6 * RISC-V machine with 16550a UART and VirtIO MMIO
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/riscv/riscv_hart.h"
33 #include "hw/riscv/sifive_plic.h"
34 #include "hw/riscv/sifive_clint.h"
35 #include "hw/riscv/sifive_test.h"
36 #include "hw/riscv/virt.h"
37 #include "hw/riscv/boot.h"
38 #include "hw/riscv/numa.h"
39 #include "chardev/char.h"
40 #include "sysemu/arch_init.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/sysemu.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci-host/gpex.h"
46 #if defined(TARGET_RISCV32)
47 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
49 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
52 static const struct MemmapEntry
{
56 [VIRT_DEBUG
] = { 0x0, 0x100 },
57 [VIRT_MROM
] = { 0x1000, 0xf000 },
58 [VIRT_TEST
] = { 0x100000, 0x1000 },
59 [VIRT_RTC
] = { 0x101000, 0x1000 },
60 [VIRT_CLINT
] = { 0x2000000, 0x10000 },
61 [VIRT_PCIE_PIO
] = { 0x3000000, 0x10000 },
62 [VIRT_PLIC
] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX
* 2) },
63 [VIRT_UART0
] = { 0x10000000, 0x100 },
64 [VIRT_VIRTIO
] = { 0x10001000, 0x1000 },
65 [VIRT_FLASH
] = { 0x20000000, 0x4000000 },
66 [VIRT_PCIE_ECAM
] = { 0x30000000, 0x10000000 },
67 [VIRT_PCIE_MMIO
] = { 0x40000000, 0x40000000 },
68 [VIRT_DRAM
] = { 0x80000000, 0x0 },
71 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
73 static PFlashCFI01
*virt_flash_create1(RISCVVirtState
*s
,
75 const char *alias_prop_name
)
78 * Create a single flash device. We use the same parameters as
79 * the flash devices on the ARM virt board.
81 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
83 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
84 qdev_prop_set_uint8(dev
, "width", 4);
85 qdev_prop_set_uint8(dev
, "device-width", 2);
86 qdev_prop_set_bit(dev
, "big-endian", false);
87 qdev_prop_set_uint16(dev
, "id0", 0x89);
88 qdev_prop_set_uint16(dev
, "id1", 0x18);
89 qdev_prop_set_uint16(dev
, "id2", 0x00);
90 qdev_prop_set_uint16(dev
, "id3", 0x00);
91 qdev_prop_set_string(dev
, "name", name
);
93 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
));
94 object_property_add_alias(OBJECT(s
), alias_prop_name
,
95 OBJECT(dev
), "drive");
97 return PFLASH_CFI01(dev
);
100 static void virt_flash_create(RISCVVirtState
*s
)
102 s
->flash
[0] = virt_flash_create1(s
, "virt.flash0", "pflash0");
103 s
->flash
[1] = virt_flash_create1(s
, "virt.flash1", "pflash1");
106 static void virt_flash_map1(PFlashCFI01
*flash
,
107 hwaddr base
, hwaddr size
,
108 MemoryRegion
*sysmem
)
110 DeviceState
*dev
= DEVICE(flash
);
112 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
113 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
114 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
115 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
117 memory_region_add_subregion(sysmem
, base
,
118 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
122 static void virt_flash_map(RISCVVirtState
*s
,
123 MemoryRegion
*sysmem
)
125 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
126 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
128 virt_flash_map1(s
->flash
[0], flashbase
, flashsize
,
130 virt_flash_map1(s
->flash
[1], flashbase
+ flashsize
, flashsize
,
134 static void create_pcie_irq_map(void *fdt
, char *nodename
,
135 uint32_t plic_phandle
)
139 full_irq_map
[GPEX_NUM_IRQS
* GPEX_NUM_IRQS
* FDT_INT_MAP_WIDTH
] = {};
140 uint32_t *irq_map
= full_irq_map
;
142 /* This code creates a standard swizzle of interrupts such that
143 * each device's first interrupt is based on it's PCI_SLOT number.
144 * (See pci_swizzle_map_irq_fn())
146 * We only need one entry per interrupt in the table (not one per
147 * possible slot) seeing the interrupt-map-mask will allow the table
148 * to wrap to any number of devices.
150 for (dev
= 0; dev
< GPEX_NUM_IRQS
; dev
++) {
151 int devfn
= dev
* 0x8;
153 for (pin
= 0; pin
< GPEX_NUM_IRQS
; pin
++) {
154 int irq_nr
= PCIE_IRQ
+ ((pin
+ PCI_SLOT(devfn
)) % GPEX_NUM_IRQS
);
157 irq_map
[i
] = cpu_to_be32(devfn
<< 8);
159 i
+= FDT_PCI_ADDR_CELLS
;
160 irq_map
[i
] = cpu_to_be32(pin
+ 1);
162 i
+= FDT_PCI_INT_CELLS
;
163 irq_map
[i
++] = cpu_to_be32(plic_phandle
);
165 i
+= FDT_PLIC_ADDR_CELLS
;
166 irq_map
[i
] = cpu_to_be32(irq_nr
);
168 irq_map
+= FDT_INT_MAP_WIDTH
;
172 qemu_fdt_setprop(fdt
, nodename
, "interrupt-map",
173 full_irq_map
, sizeof(full_irq_map
));
175 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-map-mask",
179 static void create_fdt(RISCVVirtState
*s
, const struct MemmapEntry
*memmap
,
180 uint64_t mem_size
, const char *cmdline
)
184 MachineState
*mc
= MACHINE(s
);
186 uint32_t *clint_cells
, *plic_cells
;
187 unsigned long clint_addr
, plic_addr
;
188 uint32_t plic_phandle
[MAX_NODES
];
189 uint32_t cpu_phandle
, intc_phandle
, test_phandle
;
190 uint32_t phandle
= 1, plic_mmio_phandle
= 1;
191 uint32_t plic_pcie_phandle
= 1, plic_virtio_phandle
= 1;
192 char *mem_name
, *cpu_name
, *core_name
, *intc_name
;
193 char *name
, *clint_name
, *plic_name
, *clust_name
;
194 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
195 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
197 fdt
= s
->fdt
= create_device_tree(&s
->fdt_size
);
199 error_report("create_device_tree() failed");
203 qemu_fdt_setprop_string(fdt
, "/", "model", "riscv-virtio,qemu");
204 qemu_fdt_setprop_string(fdt
, "/", "compatible", "riscv-virtio");
205 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
206 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
208 qemu_fdt_add_subnode(fdt
, "/soc");
209 qemu_fdt_setprop(fdt
, "/soc", "ranges", NULL
, 0);
210 qemu_fdt_setprop_string(fdt
, "/soc", "compatible", "simple-bus");
211 qemu_fdt_setprop_cell(fdt
, "/soc", "#size-cells", 0x2);
212 qemu_fdt_setprop_cell(fdt
, "/soc", "#address-cells", 0x2);
214 qemu_fdt_add_subnode(fdt
, "/cpus");
215 qemu_fdt_setprop_cell(fdt
, "/cpus", "timebase-frequency",
216 SIFIVE_CLINT_TIMEBASE_FREQ
);
217 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0x0);
218 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 0x1);
219 qemu_fdt_add_subnode(fdt
, "/cpus/cpu-map");
221 for (socket
= (riscv_socket_count(mc
) - 1); socket
>= 0; socket
--) {
222 clust_name
= g_strdup_printf("/cpus/cpu-map/cluster%d", socket
);
223 qemu_fdt_add_subnode(fdt
, clust_name
);
225 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
226 clint_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
228 for (cpu
= s
->soc
[socket
].num_harts
- 1; cpu
>= 0; cpu
--) {
229 cpu_phandle
= phandle
++;
231 cpu_name
= g_strdup_printf("/cpus/cpu@%d",
232 s
->soc
[socket
].hartid_base
+ cpu
);
233 qemu_fdt_add_subnode(fdt
, cpu_name
);
234 #if defined(TARGET_RISCV32)
235 qemu_fdt_setprop_string(fdt
, cpu_name
, "mmu-type", "riscv,sv32");
237 qemu_fdt_setprop_string(fdt
, cpu_name
, "mmu-type", "riscv,sv48");
239 name
= riscv_isa_string(&s
->soc
[socket
].harts
[cpu
]);
240 qemu_fdt_setprop_string(fdt
, cpu_name
, "riscv,isa", name
);
242 qemu_fdt_setprop_string(fdt
, cpu_name
, "compatible", "riscv");
243 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "okay");
244 qemu_fdt_setprop_cell(fdt
, cpu_name
, "reg",
245 s
->soc
[socket
].hartid_base
+ cpu
);
246 qemu_fdt_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
247 riscv_socket_fdt_write_id(mc
, fdt
, cpu_name
, socket
);
248 qemu_fdt_setprop_cell(fdt
, cpu_name
, "phandle", cpu_phandle
);
250 intc_name
= g_strdup_printf("%s/interrupt-controller", cpu_name
);
251 qemu_fdt_add_subnode(fdt
, intc_name
);
252 intc_phandle
= phandle
++;
253 qemu_fdt_setprop_cell(fdt
, intc_name
, "phandle", intc_phandle
);
254 qemu_fdt_setprop_string(fdt
, intc_name
, "compatible",
256 qemu_fdt_setprop(fdt
, intc_name
, "interrupt-controller", NULL
, 0);
257 qemu_fdt_setprop_cell(fdt
, intc_name
, "#interrupt-cells", 1);
259 clint_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
260 clint_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
261 clint_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
262 clint_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
264 plic_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
265 plic_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_EXT
);
266 plic_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
267 plic_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_S_EXT
);
269 core_name
= g_strdup_printf("%s/core%d", clust_name
, cpu
);
270 qemu_fdt_add_subnode(fdt
, core_name
);
271 qemu_fdt_setprop_cell(fdt
, core_name
, "cpu", cpu_phandle
);
278 addr
= memmap
[VIRT_DRAM
].base
+ riscv_socket_mem_offset(mc
, socket
);
279 size
= riscv_socket_mem_size(mc
, socket
);
280 mem_name
= g_strdup_printf("/memory@%lx", (long)addr
);
281 qemu_fdt_add_subnode(fdt
, mem_name
);
282 qemu_fdt_setprop_cells(fdt
, mem_name
, "reg",
283 addr
>> 32, addr
, size
>> 32, size
);
284 qemu_fdt_setprop_string(fdt
, mem_name
, "device_type", "memory");
285 riscv_socket_fdt_write_id(mc
, fdt
, mem_name
, socket
);
288 clint_addr
= memmap
[VIRT_CLINT
].base
+
289 (memmap
[VIRT_CLINT
].size
* socket
);
290 clint_name
= g_strdup_printf("/soc/clint@%lx", clint_addr
);
291 qemu_fdt_add_subnode(fdt
, clint_name
);
292 qemu_fdt_setprop_string(fdt
, clint_name
, "compatible", "riscv,clint0");
293 qemu_fdt_setprop_cells(fdt
, clint_name
, "reg",
294 0x0, clint_addr
, 0x0, memmap
[VIRT_CLINT
].size
);
295 qemu_fdt_setprop(fdt
, clint_name
, "interrupts-extended",
296 clint_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
297 riscv_socket_fdt_write_id(mc
, fdt
, clint_name
, socket
);
300 plic_phandle
[socket
] = phandle
++;
301 plic_addr
= memmap
[VIRT_PLIC
].base
+ (memmap
[VIRT_PLIC
].size
* socket
);
302 plic_name
= g_strdup_printf("/soc/plic@%lx", plic_addr
);
303 qemu_fdt_add_subnode(fdt
, plic_name
);
304 qemu_fdt_setprop_cell(fdt
, plic_name
,
305 "#address-cells", FDT_PLIC_ADDR_CELLS
);
306 qemu_fdt_setprop_cell(fdt
, plic_name
,
307 "#interrupt-cells", FDT_PLIC_INT_CELLS
);
308 qemu_fdt_setprop_string(fdt
, plic_name
, "compatible", "riscv,plic0");
309 qemu_fdt_setprop(fdt
, plic_name
, "interrupt-controller", NULL
, 0);
310 qemu_fdt_setprop(fdt
, plic_name
, "interrupts-extended",
311 plic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
312 qemu_fdt_setprop_cells(fdt
, plic_name
, "reg",
313 0x0, plic_addr
, 0x0, memmap
[VIRT_PLIC
].size
);
314 qemu_fdt_setprop_cell(fdt
, plic_name
, "riscv,ndev", VIRTIO_NDEV
);
315 riscv_socket_fdt_write_id(mc
, fdt
, plic_name
, socket
);
316 qemu_fdt_setprop_cell(fdt
, plic_name
, "phandle", plic_phandle
[socket
]);
324 for (socket
= 0; socket
< riscv_socket_count(mc
); socket
++) {
326 plic_mmio_phandle
= plic_phandle
[socket
];
327 plic_virtio_phandle
= plic_phandle
[socket
];
328 plic_pcie_phandle
= plic_phandle
[socket
];
331 plic_virtio_phandle
= plic_phandle
[socket
];
332 plic_pcie_phandle
= plic_phandle
[socket
];
335 plic_pcie_phandle
= plic_phandle
[socket
];
339 riscv_socket_fdt_write_distance_matrix(mc
, fdt
);
341 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
342 name
= g_strdup_printf("/soc/virtio_mmio@%lx",
343 (long)(memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
));
344 qemu_fdt_add_subnode(fdt
, name
);
345 qemu_fdt_setprop_string(fdt
, name
, "compatible", "virtio,mmio");
346 qemu_fdt_setprop_cells(fdt
, name
, "reg",
347 0x0, memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
348 0x0, memmap
[VIRT_VIRTIO
].size
);
349 qemu_fdt_setprop_cell(fdt
, name
, "interrupt-parent",
350 plic_virtio_phandle
);
351 qemu_fdt_setprop_cell(fdt
, name
, "interrupts", VIRTIO_IRQ
+ i
);
355 name
= g_strdup_printf("/soc/pci@%lx",
356 (long) memmap
[VIRT_PCIE_ECAM
].base
);
357 qemu_fdt_add_subnode(fdt
, name
);
358 qemu_fdt_setprop_cell(fdt
, name
, "#address-cells", FDT_PCI_ADDR_CELLS
);
359 qemu_fdt_setprop_cell(fdt
, name
, "#interrupt-cells", FDT_PCI_INT_CELLS
);
360 qemu_fdt_setprop_cell(fdt
, name
, "#size-cells", 0x2);
361 qemu_fdt_setprop_string(fdt
, name
, "compatible", "pci-host-ecam-generic");
362 qemu_fdt_setprop_string(fdt
, name
, "device_type", "pci");
363 qemu_fdt_setprop_cell(fdt
, name
, "linux,pci-domain", 0);
364 qemu_fdt_setprop_cells(fdt
, name
, "bus-range", 0,
365 memmap
[VIRT_PCIE_ECAM
].size
/ PCIE_MMCFG_SIZE_MIN
- 1);
366 qemu_fdt_setprop(fdt
, name
, "dma-coherent", NULL
, 0);
367 qemu_fdt_setprop_cells(fdt
, name
, "reg", 0,
368 memmap
[VIRT_PCIE_ECAM
].base
, 0, memmap
[VIRT_PCIE_ECAM
].size
);
369 qemu_fdt_setprop_sized_cells(fdt
, name
, "ranges",
370 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
371 2, memmap
[VIRT_PCIE_PIO
].base
, 2, memmap
[VIRT_PCIE_PIO
].size
,
372 1, FDT_PCI_RANGE_MMIO
,
373 2, memmap
[VIRT_PCIE_MMIO
].base
,
374 2, memmap
[VIRT_PCIE_MMIO
].base
, 2, memmap
[VIRT_PCIE_MMIO
].size
);
375 create_pcie_irq_map(fdt
, name
, plic_pcie_phandle
);
378 test_phandle
= phandle
++;
379 name
= g_strdup_printf("/soc/test@%lx",
380 (long)memmap
[VIRT_TEST
].base
);
381 qemu_fdt_add_subnode(fdt
, name
);
383 const char compat
[] = "sifive,test1\0sifive,test0\0syscon";
384 qemu_fdt_setprop(fdt
, name
, "compatible", compat
, sizeof(compat
));
386 qemu_fdt_setprop_cells(fdt
, name
, "reg",
387 0x0, memmap
[VIRT_TEST
].base
,
388 0x0, memmap
[VIRT_TEST
].size
);
389 qemu_fdt_setprop_cell(fdt
, name
, "phandle", test_phandle
);
390 test_phandle
= qemu_fdt_get_phandle(fdt
, name
);
393 name
= g_strdup_printf("/soc/reboot");
394 qemu_fdt_add_subnode(fdt
, name
);
395 qemu_fdt_setprop_string(fdt
, name
, "compatible", "syscon-reboot");
396 qemu_fdt_setprop_cell(fdt
, name
, "regmap", test_phandle
);
397 qemu_fdt_setprop_cell(fdt
, name
, "offset", 0x0);
398 qemu_fdt_setprop_cell(fdt
, name
, "value", FINISHER_RESET
);
401 name
= g_strdup_printf("/soc/poweroff");
402 qemu_fdt_add_subnode(fdt
, name
);
403 qemu_fdt_setprop_string(fdt
, name
, "compatible", "syscon-poweroff");
404 qemu_fdt_setprop_cell(fdt
, name
, "regmap", test_phandle
);
405 qemu_fdt_setprop_cell(fdt
, name
, "offset", 0x0);
406 qemu_fdt_setprop_cell(fdt
, name
, "value", FINISHER_PASS
);
409 name
= g_strdup_printf("/soc/uart@%lx", (long)memmap
[VIRT_UART0
].base
);
410 qemu_fdt_add_subnode(fdt
, name
);
411 qemu_fdt_setprop_string(fdt
, name
, "compatible", "ns16550a");
412 qemu_fdt_setprop_cells(fdt
, name
, "reg",
413 0x0, memmap
[VIRT_UART0
].base
,
414 0x0, memmap
[VIRT_UART0
].size
);
415 qemu_fdt_setprop_cell(fdt
, name
, "clock-frequency", 3686400);
416 qemu_fdt_setprop_cell(fdt
, name
, "interrupt-parent", plic_mmio_phandle
);
417 qemu_fdt_setprop_cell(fdt
, name
, "interrupts", UART0_IRQ
);
419 qemu_fdt_add_subnode(fdt
, "/chosen");
420 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", name
);
422 qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs", cmdline
);
426 name
= g_strdup_printf("/soc/rtc@%lx", (long)memmap
[VIRT_RTC
].base
);
427 qemu_fdt_add_subnode(fdt
, name
);
428 qemu_fdt_setprop_string(fdt
, name
, "compatible", "google,goldfish-rtc");
429 qemu_fdt_setprop_cells(fdt
, name
, "reg",
430 0x0, memmap
[VIRT_RTC
].base
,
431 0x0, memmap
[VIRT_RTC
].size
);
432 qemu_fdt_setprop_cell(fdt
, name
, "interrupt-parent", plic_mmio_phandle
);
433 qemu_fdt_setprop_cell(fdt
, name
, "interrupts", RTC_IRQ
);
436 name
= g_strdup_printf("/soc/flash@%" PRIx64
, flashbase
);
437 qemu_fdt_add_subnode(s
->fdt
, name
);
438 qemu_fdt_setprop_string(s
->fdt
, name
, "compatible", "cfi-flash");
439 qemu_fdt_setprop_sized_cells(s
->fdt
, name
, "reg",
440 2, flashbase
, 2, flashsize
,
441 2, flashbase
+ flashsize
, 2, flashsize
);
442 qemu_fdt_setprop_cell(s
->fdt
, name
, "bank-width", 4);
446 static inline DeviceState
*gpex_pcie_init(MemoryRegion
*sys_mem
,
447 hwaddr ecam_base
, hwaddr ecam_size
,
448 hwaddr mmio_base
, hwaddr mmio_size
,
450 DeviceState
*plic
, bool link_up
)
453 MemoryRegion
*ecam_alias
, *ecam_reg
;
454 MemoryRegion
*mmio_alias
, *mmio_reg
;
458 dev
= qdev_new(TYPE_GPEX_HOST
);
460 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
462 ecam_alias
= g_new0(MemoryRegion
, 1);
463 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
464 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
465 ecam_reg
, 0, ecam_size
);
466 memory_region_add_subregion(get_system_memory(), ecam_base
, ecam_alias
);
468 mmio_alias
= g_new0(MemoryRegion
, 1);
469 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
470 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
471 mmio_reg
, mmio_base
, mmio_size
);
472 memory_region_add_subregion(get_system_memory(), mmio_base
, mmio_alias
);
474 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, pio_base
);
476 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
477 irq
= qdev_get_gpio_in(plic
, PCIE_IRQ
+ i
);
479 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, irq
);
480 gpex_set_irq_num(GPEX_HOST(dev
), i
, PCIE_IRQ
+ i
);
486 static void virt_machine_init(MachineState
*machine
)
488 const struct MemmapEntry
*memmap
= virt_memmap
;
489 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(machine
);
490 MemoryRegion
*system_memory
= get_system_memory();
491 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
492 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
493 char *plic_hart_config
, *soc_name
;
494 size_t plic_hart_config_len
;
495 target_ulong start_addr
= memmap
[VIRT_DRAM
].base
;
496 uint32_t fdt_load_addr
;
497 uint64_t kernel_entry
;
498 DeviceState
*mmio_plic
, *virtio_plic
, *pcie_plic
;
499 int i
, j
, base_hartid
, hart_count
;
501 /* Check socket count limit */
502 if (VIRT_SOCKETS_MAX
< riscv_socket_count(machine
)) {
503 error_report("number of sockets/nodes should be less than %d",
508 /* Initialize sockets */
509 mmio_plic
= virtio_plic
= pcie_plic
= NULL
;
510 for (i
= 0; i
< riscv_socket_count(machine
); i
++) {
511 if (!riscv_socket_check_hartids(machine
, i
)) {
512 error_report("discontinuous hartids in socket%d", i
);
516 base_hartid
= riscv_socket_first_hartid(machine
, i
);
517 if (base_hartid
< 0) {
518 error_report("can't find hartid base for socket%d", i
);
522 hart_count
= riscv_socket_hart_count(machine
, i
);
523 if (hart_count
< 0) {
524 error_report("can't find hart count for socket%d", i
);
528 soc_name
= g_strdup_printf("soc%d", i
);
529 object_initialize_child(OBJECT(machine
), soc_name
, &s
->soc
[i
],
530 TYPE_RISCV_HART_ARRAY
);
532 object_property_set_str(OBJECT(&s
->soc
[i
]), "cpu-type",
533 machine
->cpu_type
, &error_abort
);
534 object_property_set_int(OBJECT(&s
->soc
[i
]), "hartid-base",
535 base_hartid
, &error_abort
);
536 object_property_set_int(OBJECT(&s
->soc
[i
]), "num-harts",
537 hart_count
, &error_abort
);
538 sysbus_realize(SYS_BUS_DEVICE(&s
->soc
[i
]), &error_abort
);
540 /* Per-socket CLINT */
542 memmap
[VIRT_CLINT
].base
+ i
* memmap
[VIRT_CLINT
].size
,
543 memmap
[VIRT_CLINT
].size
, base_hartid
, hart_count
,
544 SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
, true);
546 /* Per-socket PLIC hart topology configuration string */
547 plic_hart_config_len
=
548 (strlen(VIRT_PLIC_HART_CONFIG
) + 1) * hart_count
;
549 plic_hart_config
= g_malloc0(plic_hart_config_len
);
550 for (j
= 0; j
< hart_count
; j
++) {
552 strncat(plic_hart_config
, ",", plic_hart_config_len
);
554 strncat(plic_hart_config
, VIRT_PLIC_HART_CONFIG
,
555 plic_hart_config_len
);
556 plic_hart_config_len
-= (strlen(VIRT_PLIC_HART_CONFIG
) + 1);
559 /* Per-socket PLIC */
560 s
->plic
[i
] = sifive_plic_create(
561 memmap
[VIRT_PLIC
].base
+ i
* memmap
[VIRT_PLIC
].size
,
562 plic_hart_config
, base_hartid
,
563 VIRT_PLIC_NUM_SOURCES
,
564 VIRT_PLIC_NUM_PRIORITIES
,
565 VIRT_PLIC_PRIORITY_BASE
,
566 VIRT_PLIC_PENDING_BASE
,
567 VIRT_PLIC_ENABLE_BASE
,
568 VIRT_PLIC_ENABLE_STRIDE
,
569 VIRT_PLIC_CONTEXT_BASE
,
570 VIRT_PLIC_CONTEXT_STRIDE
,
571 memmap
[VIRT_PLIC
].size
);
572 g_free(plic_hart_config
);
574 /* Try to use different PLIC instance based device type */
576 mmio_plic
= s
->plic
[i
];
577 virtio_plic
= s
->plic
[i
];
578 pcie_plic
= s
->plic
[i
];
581 virtio_plic
= s
->plic
[i
];
582 pcie_plic
= s
->plic
[i
];
585 pcie_plic
= s
->plic
[i
];
589 /* register system main memory (actual RAM) */
590 memory_region_init_ram(main_mem
, NULL
, "riscv_virt_board.ram",
591 machine
->ram_size
, &error_fatal
);
592 memory_region_add_subregion(system_memory
, memmap
[VIRT_DRAM
].base
,
595 /* create device tree */
596 create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
);
599 memory_region_init_rom(mask_rom
, NULL
, "riscv_virt_board.mrom",
600 memmap
[VIRT_MROM
].size
, &error_fatal
);
601 memory_region_add_subregion(system_memory
, memmap
[VIRT_MROM
].base
,
604 riscv_find_and_load_firmware(machine
, BIOS_FILENAME
,
605 memmap
[VIRT_DRAM
].base
, NULL
);
607 if (machine
->kernel_filename
) {
608 kernel_entry
= riscv_load_kernel(machine
->kernel_filename
, NULL
);
610 if (machine
->initrd_filename
) {
612 hwaddr end
= riscv_load_initrd(machine
->initrd_filename
,
613 machine
->ram_size
, kernel_entry
,
615 qemu_fdt_setprop_cell(s
->fdt
, "/chosen",
616 "linux,initrd-start", start
);
617 qemu_fdt_setprop_cell(s
->fdt
, "/chosen", "linux,initrd-end",
622 * If dynamic firmware is used, it doesn't know where is the next mode
623 * if kernel argument is not set.
628 if (drive_get(IF_PFLASH
, 0, 0)) {
630 * Pflash was supplied, let's overwrite the address we jump to after
631 * reset to the base of the flash.
633 start_addr
= virt_memmap
[VIRT_FLASH
].base
;
636 /* Compute the fdt load address in dram */
637 fdt_load_addr
= riscv_load_fdt(memmap
[VIRT_DRAM
].base
,
638 machine
->ram_size
, s
->fdt
);
639 /* load the reset vector */
640 riscv_setup_rom_reset_vec(start_addr
, virt_memmap
[VIRT_MROM
].base
,
641 virt_memmap
[VIRT_MROM
].size
, kernel_entry
,
642 fdt_load_addr
, s
->fdt
);
644 /* SiFive Test MMIO device */
645 sifive_test_create(memmap
[VIRT_TEST
].base
);
647 /* VirtIO MMIO devices */
648 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
649 sysbus_create_simple("virtio-mmio",
650 memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
651 qdev_get_gpio_in(DEVICE(virtio_plic
), VIRTIO_IRQ
+ i
));
654 gpex_pcie_init(system_memory
,
655 memmap
[VIRT_PCIE_ECAM
].base
,
656 memmap
[VIRT_PCIE_ECAM
].size
,
657 memmap
[VIRT_PCIE_MMIO
].base
,
658 memmap
[VIRT_PCIE_MMIO
].size
,
659 memmap
[VIRT_PCIE_PIO
].base
,
660 DEVICE(pcie_plic
), true);
662 serial_mm_init(system_memory
, memmap
[VIRT_UART0
].base
,
663 0, qdev_get_gpio_in(DEVICE(mmio_plic
), UART0_IRQ
), 399193,
664 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
666 sysbus_create_simple("goldfish_rtc", memmap
[VIRT_RTC
].base
,
667 qdev_get_gpio_in(DEVICE(mmio_plic
), RTC_IRQ
));
669 virt_flash_create(s
);
671 for (i
= 0; i
< ARRAY_SIZE(s
->flash
); i
++) {
672 /* Map legacy -drive if=pflash to machine properties */
673 pflash_cfi01_legacy_drive(s
->flash
[i
],
674 drive_get(IF_PFLASH
, 0, i
));
676 virt_flash_map(s
, system_memory
);
679 static void virt_machine_instance_init(Object
*obj
)
683 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
685 MachineClass
*mc
= MACHINE_CLASS(oc
);
687 mc
->desc
= "RISC-V VirtIO board";
688 mc
->init
= virt_machine_init
;
689 mc
->max_cpus
= VIRT_CPUS_MAX
;
690 mc
->default_cpu_type
= VIRT_CPU
;
691 mc
->pci_allow_0_address
= true;
692 mc
->possible_cpu_arch_ids
= riscv_numa_possible_cpu_arch_ids
;
693 mc
->cpu_index_to_instance_props
= riscv_numa_cpu_index_to_props
;
694 mc
->get_default_cpu_node_id
= riscv_numa_get_default_cpu_node_id
;
695 mc
->numa_mem_supported
= true;
698 static const TypeInfo virt_machine_typeinfo
= {
699 .name
= MACHINE_TYPE_NAME("virt"),
700 .parent
= TYPE_MACHINE
,
701 .class_init
= virt_machine_class_init
,
702 .instance_init
= virt_machine_instance_init
,
703 .instance_size
= sizeof(RISCVVirtState
),
706 static void virt_machine_init_register_types(void)
708 type_register_static(&virt_machine_typeinfo
);
711 type_init(virt_machine_init_register_types
)