?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/loongarch/virt: Fix memory leak
[qemu/ar7.git] / hw / loongarch / virt.c
blob69924a87347cacdc4e3aec32a5f8dab1d955799a
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * QEMU loongson 3a5000 develop board emulation
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
6 */
7 #include "qemu/osdep.h"
8 #include "qemu/units.h"
9 #include "qemu/datadir.h"
10 #include "qapi/error.h"
11 #include "hw/boards.h"
12 #include "hw/char/serial.h"
13 #include "sysemu/sysemu.h"
14 #include "sysemu/qtest.h"
15 #include "sysemu/runstate.h"
16 #include "sysemu/reset.h"
17 #include "sysemu/rtc.h"
18 #include "hw/loongarch/virt.h"
19 #include "exec/address-spaces.h"
20 #include "hw/irq.h"
21 #include "net/net.h"
22 #include "hw/loader.h"
23 #include "elf.h"
24 #include "hw/intc/loongarch_ipi.h"
25 #include "hw/intc/loongarch_extioi.h"
26 #include "hw/intc/loongarch_pch_pic.h"
27 #include "hw/intc/loongarch_pch_msi.h"
28 #include "hw/pci-host/ls7a.h"
29 #include "hw/pci-host/gpex.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/loongarch/fw_cfg.h"
32 #include "target/loongarch/cpu.h"
33 #include "hw/firmware/smbios.h"
34 #include "hw/acpi/aml-build.h"
35 #include "qapi/qapi-visit-common.h"
36 #include "hw/acpi/generic_event_device.h"
37 #include "hw/mem/nvdimm.h"
38 #include "sysemu/device_tree.h"
39 #include <libfdt.h>
40 #include "hw/core/sysbus-fdt.h"
41 #include "hw/platform-bus.h"
42 #include "hw/display/ramfb.h"
43 #include "hw/mem/pc-dimm.h"
44 #include "sysemu/tpm.h"
45 #include "sysemu/block-backend.h"
46 #include "hw/block/flash.h"
47 #include "qemu/error-report.h"
48
49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams,
50 const char *name,
51 const char *alias_prop_name)
52 {
53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
54
55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
56 qdev_prop_set_uint8(dev, "width", 4);
57 qdev_prop_set_uint8(dev, "device-width", 2);
58 qdev_prop_set_bit(dev, "big-endian", false);
59 qdev_prop_set_uint16(dev, "id0", 0x89);
60 qdev_prop_set_uint16(dev, "id1", 0x18);
61 qdev_prop_set_uint16(dev, "id2", 0x00);
62 qdev_prop_set_uint16(dev, "id3", 0x00);
63 qdev_prop_set_string(dev, "name", name);
64 object_property_add_child(OBJECT(lams), name, OBJECT(dev));
65 object_property_add_alias(OBJECT(lams), alias_prop_name,
66 OBJECT(dev), "drive");
67 return PFLASH_CFI01(dev);
68 }
69
70 static void virt_flash_create(LoongArchMachineState *lams)
71 {
72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0");
73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1");
74 }
75
76 static void virt_flash_map1(PFlashCFI01 *flash,
77 hwaddr base, hwaddr size,
78 MemoryRegion *sysmem)
79 {
80 DeviceState *dev = DEVICE(flash);
81 BlockBackend *blk;
82 hwaddr real_size = size;
83
84 blk = pflash_cfi01_get_blk(flash);
85 if (blk) {
86 real_size = blk_getlength(blk);
87 assert(real_size && real_size <= size);
88 }
89
90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE));
91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
92
93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE);
94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
95 memory_region_add_subregion(sysmem, base,
96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
97 }
98
99 static void virt_flash_map(LoongArchMachineState *lams,
100 MemoryRegion *sysmem)
101 {
102 PFlashCFI01 *flash0 = lams->flash[0];
103 PFlashCFI01 *flash1 = lams->flash[1];
104
105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem);
106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem);
107 }
108
109 static void fdt_add_cpuic_node(LoongArchMachineState *lams,
110 uint32_t *cpuintc_phandle)
111 {
112 MachineState *ms = MACHINE(lams);
113 char *nodename;
114
115 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
116 nodename = g_strdup_printf("/cpuic");
117 qemu_fdt_add_subnode(ms->fdt, nodename);
118 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle);
119 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
120 "loongson,cpu-interrupt-controller");
121 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
122 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
123 g_free(nodename);
124 }
125
126 static void fdt_add_eiointc_node(LoongArchMachineState *lams,
127 uint32_t *cpuintc_phandle,
128 uint32_t *eiointc_phandle)
129 {
130 MachineState *ms = MACHINE(lams);
131 char *nodename;
132 hwaddr extioi_base = APIC_BASE;
133 hwaddr extioi_size = EXTIOI_SIZE;
134
135 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
136 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base);
137 qemu_fdt_add_subnode(ms->fdt, nodename);
138 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle);
139 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
140 "loongson,ls2k2000-eiointc");
141 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
142 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
143 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
144 *cpuintc_phandle);
145 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3);
146 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0,
147 extioi_base, 0x0, extioi_size);
148 g_free(nodename);
149 }
150
151 static void fdt_add_pch_pic_node(LoongArchMachineState *lams,
152 uint32_t *eiointc_phandle,
153 uint32_t *pch_pic_phandle)
154 {
155 MachineState *ms = MACHINE(lams);
156 char *nodename;
157 hwaddr pch_pic_base = VIRT_PCH_REG_BASE;
158 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE;
159
160 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
161 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base);
162 qemu_fdt_add_subnode(ms->fdt, nodename);
163 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle);
164 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
165 "loongson,pch-pic-1.0");
166 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0,
167 pch_pic_base, 0, pch_pic_size);
168 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
169 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2);
170 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
171 *eiointc_phandle);
172 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0);
173 g_free(nodename);
174 }
175
176 static void fdt_add_pch_msi_node(LoongArchMachineState *lams,
177 uint32_t *eiointc_phandle,
178 uint32_t *pch_msi_phandle)
179 {
180 MachineState *ms = MACHINE(lams);
181 char *nodename;
182 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW;
183 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE;
184
185 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
186 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base);
187 qemu_fdt_add_subnode(ms->fdt, nodename);
188 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle);
189 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
190 "loongson,pch-msi-1.0");
191 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg",
192 0, pch_msi_base,
193 0, pch_msi_size);
194 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
195 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
196 *eiointc_phandle);
197 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec",
198 VIRT_PCH_PIC_IRQ_NUM);
199 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs",
200 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM);
201 g_free(nodename);
202 }
203
204 static void fdt_add_flash_node(LoongArchMachineState *lams)
205 {
206 MachineState *ms = MACHINE(lams);
207 char *nodename;
208 MemoryRegion *flash_mem;
209
210 hwaddr flash0_base;
211 hwaddr flash0_size;
212
213 hwaddr flash1_base;
214 hwaddr flash1_size;
215
216 flash_mem = pflash_cfi01_get_memory(lams->flash[0]);
217 flash0_base = flash_mem->addr;
218 flash0_size = memory_region_size(flash_mem);
219
220 flash_mem = pflash_cfi01_get_memory(lams->flash[1]);
221 flash1_base = flash_mem->addr;
222 flash1_size = memory_region_size(flash_mem);
223
224 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base);
225 qemu_fdt_add_subnode(ms->fdt, nodename);
226 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
227 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
228 2, flash0_base, 2, flash0_size,
229 2, flash1_base, 2, flash1_size);
230 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
231 g_free(nodename);
232 }
233
234 static void fdt_add_rtc_node(LoongArchMachineState *lams,
235 uint32_t *pch_pic_phandle)
236 {
237 char *nodename;
238 hwaddr base = VIRT_RTC_REG_BASE;
239 hwaddr size = VIRT_RTC_LEN;
240 MachineState *ms = MACHINE(lams);
241
242 nodename = g_strdup_printf("/rtc@%" PRIx64, base);
243 qemu_fdt_add_subnode(ms->fdt, nodename);
244 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
245 "loongson,ls7a-rtc");
246 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
247 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
248 VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4);
249 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
250 *pch_pic_phandle);
251 g_free(nodename);
252 }
253
254 static void fdt_add_uart_node(LoongArchMachineState *lams,
255 uint32_t *pch_pic_phandle)
256 {
257 char *nodename;
258 hwaddr base = VIRT_UART_BASE;
259 hwaddr size = VIRT_UART_SIZE;
260 MachineState *ms = MACHINE(lams);
261
262 nodename = g_strdup_printf("/serial@%" PRIx64, base);
263 qemu_fdt_add_subnode(ms->fdt, nodename);
264 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
265 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
266 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
267 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
268 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
269 VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4);
270 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
271 *pch_pic_phandle);
272 g_free(nodename);
273 }
274
275 static void create_fdt(LoongArchMachineState *lams)
276 {
277 MachineState *ms = MACHINE(lams);
278
279 ms->fdt = create_device_tree(&lams->fdt_size);
280 if (!ms->fdt) {
281 error_report("create_device_tree() failed");
282 exit(1);
283 }
284
285 /* Header */
286 qemu_fdt_setprop_string(ms->fdt, "/", "compatible",
287 "linux,dummy-loongson3");
288 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
289 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
290 qemu_fdt_add_subnode(ms->fdt, "/chosen");
291 }
292
293 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
294 {
295 int num;
296 const MachineState *ms = MACHINE(lams);
297 int smp_cpus = ms->smp.cpus;
298
299 qemu_fdt_add_subnode(ms->fdt, "/cpus");
300 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
301 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
302
303 /* cpu nodes */
304 for (num = smp_cpus - 1; num >= 0; num--) {
305 char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
306 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
307 CPUState *cs = CPU(cpu);
308
309 qemu_fdt_add_subnode(ms->fdt, nodename);
310 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
311 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
312 cpu->dtb_compatible);
313 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
314 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
315 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
316 }
317 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
318 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
319 qemu_fdt_alloc_phandle(ms->fdt));
320 g_free(nodename);
321 }
322
323 /*cpu map */
324 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
325
326 for (num = smp_cpus - 1; num >= 0; num--) {
327 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
328 char *map_path;
329
330 if (ms->smp.threads > 1) {
331 map_path = g_strdup_printf(
332 "/cpus/cpu-map/socket%d/core%d/thread%d",
333 num / (ms->smp.cores * ms->smp.threads),
334 (num / ms->smp.threads) % ms->smp.cores,
335 num % ms->smp.threads);
336 } else {
337 map_path = g_strdup_printf(
338 "/cpus/cpu-map/socket%d/core%d",
339 num / ms->smp.cores,
340 num % ms->smp.cores);
341 }
342 qemu_fdt_add_path(ms->fdt, map_path);
343 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
344
345 g_free(map_path);
346 g_free(cpu_path);
347 }
348 }
349
350 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
351 {
352 char *nodename;
353 hwaddr base = VIRT_FWCFG_BASE;
354 const MachineState *ms = MACHINE(lams);
355
356 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base);
357 qemu_fdt_add_subnode(ms->fdt, nodename);
358 qemu_fdt_setprop_string(ms->fdt, nodename,
359 "compatible", "qemu,fw-cfg-mmio");
360 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
361 2, base, 2, 0x18);
362 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
363 g_free(nodename);
364 }
365
366 static void fdt_add_pcie_irq_map_node(const LoongArchMachineState *lams,
367 char *nodename,
368 uint32_t *pch_pic_phandle)
369 {
370 int pin, dev;
371 uint32_t irq_map_stride = 0;
372 uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {};
373 uint32_t *irq_map = full_irq_map;
374 const MachineState *ms = MACHINE(lams);
375
376 /* This code creates a standard swizzle of interrupts such that
377 * each device's first interrupt is based on it's PCI_SLOT number.
378 * (See pci_swizzle_map_irq_fn())
379 *
380 * We only need one entry per interrupt in the table (not one per
381 * possible slot) seeing the interrupt-map-mask will allow the table
382 * to wrap to any number of devices.
383 */
384
385 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
386 int devfn = dev * 0x8;
387
388 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
389 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
390 int i = 0;
391
392 /* Fill PCI address cells */
393 irq_map[i] = cpu_to_be32(devfn << 8);
394 i += 3;
395
396 /* Fill PCI Interrupt cells */
397 irq_map[i] = cpu_to_be32(pin + 1);
398 i += 1;
399
400 /* Fill interrupt controller phandle and cells */
401 irq_map[i++] = cpu_to_be32(*pch_pic_phandle);
402 irq_map[i++] = cpu_to_be32(irq_nr);
403
404 if (!irq_map_stride) {
405 irq_map_stride = i;
406 }
407 irq_map += irq_map_stride;
408 }
409 }
410
411
412 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map,
413 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
414 irq_map_stride * sizeof(uint32_t));
415 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
416 0x1800, 0, 0, 0x7);
417 }
418
419 static void fdt_add_pcie_node(const LoongArchMachineState *lams,
420 uint32_t *pch_pic_phandle,
421 uint32_t *pch_msi_phandle)
422 {
423 char *nodename;
424 hwaddr base_mmio = VIRT_PCI_MEM_BASE;
425 hwaddr size_mmio = VIRT_PCI_MEM_SIZE;
426 hwaddr base_pio = VIRT_PCI_IO_BASE;
427 hwaddr size_pio = VIRT_PCI_IO_SIZE;
428 hwaddr base_pcie = VIRT_PCI_CFG_BASE;
429 hwaddr size_pcie = VIRT_PCI_CFG_SIZE;
430 hwaddr base = base_pcie;
431
432 const MachineState *ms = MACHINE(lams);
433
434 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
435 qemu_fdt_add_subnode(ms->fdt, nodename);
436 qemu_fdt_setprop_string(ms->fdt, nodename,
437 "compatible", "pci-host-ecam-generic");
438 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
439 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
440 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
441 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
442 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
443 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1));
444 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
445 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
446 2, base_pcie, 2, size_pcie);
447 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
448 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET,
449 2, base_pio, 2, size_pio,
450 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
451 2, base_mmio, 2, size_mmio);
452 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
453 0, *pch_msi_phandle, 0, 0x10000);
454
455 fdt_add_pcie_irq_map_node(lams, nodename, pch_pic_phandle);
456
457 g_free(nodename);
458 }
459
460 static void fdt_add_memory_node(MachineState *ms,
461 uint64_t base, uint64_t size, int node_id)
462 {
463 char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
464
465 qemu_fdt_add_subnode(ms->fdt, nodename);
466 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size);
467 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
468
469 if (ms->numa_state && ms->numa_state->num_nodes) {
470 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id);
471 }
472
473 g_free(nodename);
474 }
475
476 static void virt_build_smbios(LoongArchMachineState *lams)
477 {
478 MachineState *ms = MACHINE(lams);
479 MachineClass *mc = MACHINE_GET_CLASS(lams);
480 uint8_t *smbios_tables, *smbios_anchor;
481 size_t smbios_tables_len, smbios_anchor_len;
482 const char *product = "QEMU Virtual Machine";
483
484 if (!lams->fw_cfg) {
485 return;
486 }
487
488 smbios_set_defaults("QEMU", product, mc->name, true);
489
490 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64,
491 NULL, 0,
492 &smbios_tables, &smbios_tables_len,
493 &smbios_anchor, &smbios_anchor_len, &error_fatal);
494
495 if (smbios_anchor) {
496 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables",
497 smbios_tables, smbios_tables_len);
498 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor",
499 smbios_anchor, smbios_anchor_len);
500 }
501 }
502
503 static void virt_machine_done(Notifier *notifier, void *data)
504 {
505 LoongArchMachineState *lams = container_of(notifier,
506 LoongArchMachineState, machine_done);
507 virt_build_smbios(lams);
508 loongarch_acpi_setup(lams);
509 }
510
511 static void virt_powerdown_req(Notifier *notifier, void *opaque)
512 {
513 LoongArchMachineState *s = container_of(notifier,
514 LoongArchMachineState, powerdown_notifier);
515
516 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS);
517 }
518
519 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
520 {
521 /* Ensure there are no duplicate entries. */
522 for (unsigned i = 0; i < memmap_entries; i++) {
523 assert(memmap_table[i].address != address);
524 }
525
526 memmap_table = g_renew(struct memmap_entry, memmap_table,
527 memmap_entries + 1);
528 memmap_table[memmap_entries].address = cpu_to_le64(address);
529 memmap_table[memmap_entries].length = cpu_to_le64(length);
530 memmap_table[memmap_entries].type = cpu_to_le32(type);
531 memmap_table[memmap_entries].reserved = 0;
532 memmap_entries++;
533 }
534
535 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams)
536 {
537 DeviceState *dev;
538 MachineState *ms = MACHINE(lams);
539 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
540
541 if (ms->ram_slots) {
542 event |= ACPI_GED_MEM_HOTPLUG_EVT;
543 }
544 dev = qdev_new(TYPE_ACPI_GED);
545 qdev_prop_set_uint32(dev, "ged-event", event);
546 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
547
548 /* ged event */
549 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR);
550 /* memory hotplug */
551 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR);
552 /* ged regs used for reset and power down */
553 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
554
555 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
556 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE));
557 return dev;
558 }
559
560 static DeviceState *create_platform_bus(DeviceState *pch_pic)
561 {
562 DeviceState *dev;
563 SysBusDevice *sysbus;
564 int i, irq;
565 MemoryRegion *sysmem = get_system_memory();
566
567 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
568 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
569 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
570 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE);
571 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
572
573 sysbus = SYS_BUS_DEVICE(dev);
574 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
575 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i;
576 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq));
577 }
578
579 memory_region_add_subregion(sysmem,
580 VIRT_PLATFORM_BUS_BASEADDRESS,
581 sysbus_mmio_get_region(sysbus, 0));
582 return dev;
583 }
584
585 static void loongarch_devices_init(DeviceState *pch_pic,
586 LoongArchMachineState *lams,
587 uint32_t *pch_pic_phandle,
588 uint32_t *pch_msi_phandle)
589 {
590 MachineClass *mc = MACHINE_GET_CLASS(lams);
591 DeviceState *gpex_dev;
592 SysBusDevice *d;
593 PCIBus *pci_bus;
594 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
595 MemoryRegion *mmio_alias, *mmio_reg;
596 int i;
597
598 gpex_dev = qdev_new(TYPE_GPEX_HOST);
599 d = SYS_BUS_DEVICE(gpex_dev);
600 sysbus_realize_and_unref(d, &error_fatal);
601 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
602 lams->pci_bus = pci_bus;
603
604 /* Map only part size_ecam bytes of ECAM space */
605 ecam_alias = g_new0(MemoryRegion, 1);
606 ecam_reg = sysbus_mmio_get_region(d, 0);
607 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
608 ecam_reg, 0, VIRT_PCI_CFG_SIZE);
609 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE,
610 ecam_alias);
611
612 /* Map PCI mem space */
613 mmio_alias = g_new0(MemoryRegion, 1);
614 mmio_reg = sysbus_mmio_get_region(d, 1);
615 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
616 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE);
617 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE,
618 mmio_alias);
619
620 /* Map PCI IO port space. */
621 pio_alias = g_new0(MemoryRegion, 1);
622 pio_reg = sysbus_mmio_get_region(d, 2);
623 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
624 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE);
625 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE,
626 pio_alias);
627
628 for (i = 0; i < GPEX_NUM_IRQS; i++) {
629 sysbus_connect_irq(d, i,
630 qdev_get_gpio_in(pch_pic, 16 + i));
631 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
632 }
633
634 /* Add pcie node */
635 fdt_add_pcie_node(lams, pch_pic_phandle, pch_msi_phandle);
636
637 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
638 qdev_get_gpio_in(pch_pic,
639 VIRT_UART_IRQ - VIRT_GSI_BASE),
640 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
641 fdt_add_uart_node(lams, pch_pic_phandle);
642
643 /* Network init */
644 pci_init_nic_devices(pci_bus, mc->default_nic);
645
646 /*
647 * There are some invalid guest memory access.
648 * Create some unimplemented devices to emulate this.
649 */
650 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
651 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
652 qdev_get_gpio_in(pch_pic,
653 VIRT_RTC_IRQ - VIRT_GSI_BASE));
654 fdt_add_rtc_node(lams, pch_pic_phandle);
655
656 /* acpi ged */
657 lams->acpi_ged = create_acpi_ged(pch_pic, lams);
658 /* platform bus */
659 lams->platform_bus_dev = create_platform_bus(pch_pic);
660 }
661
662 static void loongarch_irq_init(LoongArchMachineState *lams)
663 {
664 MachineState *ms = MACHINE(lams);
665 DeviceState *pch_pic, *pch_msi, *cpudev;
666 DeviceState *ipi, *extioi;
667 SysBusDevice *d;
668 LoongArchCPU *lacpu;
669 CPULoongArchState *env;
670 CPUState *cpu_state;
671 int cpu, pin, i, start, num;
672 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
673
674 /*
675 * The connection of interrupts:
676 * +-----+ +---------+ +-------+
677 * | IPI |--> | CPUINTC | <-- | Timer |
678 * +-----+ +---------+ +-------+
679 * ^
680 * |
681 * +---------+
682 * | EIOINTC |
683 * +---------+
684 * ^ ^
685 * | |
686 * +---------+ +---------+
687 * | PCH-PIC | | PCH-MSI |
688 * +---------+ +---------+
689 * ^ ^ ^
690 * | | |
691 * +--------+ +---------+ +---------+
692 * | UARTs | | Devices | | Devices |
693 * +--------+ +---------+ +---------+
694 */
695
696 /* Create IPI device */
697 ipi = qdev_new(TYPE_LOONGARCH_IPI);
698 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus);
699 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
700
701 /* IPI iocsr memory region */
702 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX,
703 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
704 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR,
705 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
706
707 /* Add cpu interrupt-controller */
708 fdt_add_cpuic_node(lams, &cpuintc_phandle);
709
710 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
711 cpu_state = qemu_get_cpu(cpu);
712 cpudev = DEVICE(cpu_state);
713 lacpu = LOONGARCH_CPU(cpu_state);
714 env = &(lacpu->env);
715 env->address_space_iocsr = &lams->as_iocsr;
716
717 /* connect ipi irq to cpu irq */
718 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
719 env->ipistate = ipi;
720 }
721
722 /* Create EXTIOI device */
723 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
724 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus);
725 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
726 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE,
727 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0));
728
729 /*
730 * connect ext irq to the cpu irq
731 * cpu_pin[9:2] <= intc_pin[7:0]
732 */
733 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
734 cpudev = DEVICE(qemu_get_cpu(cpu));
735 for (pin = 0; pin < LS3A_INTC_IP; pin++) {
736 qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
737 qdev_get_gpio_in(cpudev, pin + 2));
738 }
739 }
740
741 /* Add Extend I/O Interrupt Controller node */
742 fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle);
743
744 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
745 num = VIRT_PCH_PIC_IRQ_NUM;
746 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
747 d = SYS_BUS_DEVICE(pch_pic);
748 sysbus_realize_and_unref(d, &error_fatal);
749 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
750 sysbus_mmio_get_region(d, 0));
751 memory_region_add_subregion(get_system_memory(),
752 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
753 sysbus_mmio_get_region(d, 1));
754 memory_region_add_subregion(get_system_memory(),
755 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
756 sysbus_mmio_get_region(d, 2));
757
758 /* Connect pch_pic irqs to extioi */
759 for (i = 0; i < num; i++) {
760 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
761 }
762
763 /* Add PCH PIC node */
764 fdt_add_pch_pic_node(lams, &eiointc_phandle, &pch_pic_phandle);
765
766 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
767 start = num;
768 num = EXTIOI_IRQS - start;
769 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
770 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
771 d = SYS_BUS_DEVICE(pch_msi);
772 sysbus_realize_and_unref(d, &error_fatal);
773 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
774 for (i = 0; i < num; i++) {
775 /* Connect pch_msi irqs to extioi */
776 qdev_connect_gpio_out(DEVICE(d), i,
777 qdev_get_gpio_in(extioi, i + start));
778 }
779
780 /* Add PCH MSI node */
781 fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle);
782
783 loongarch_devices_init(pch_pic, lams, &pch_pic_phandle, &pch_msi_phandle);
784 }
785
786 static void loongarch_firmware_init(LoongArchMachineState *lams)
787 {
788 char *filename = MACHINE(lams)->firmware;
789 char *bios_name = NULL;
790 int bios_size, i;
791 BlockBackend *pflash_blk0;
792 MemoryRegion *mr;
793
794 lams->bios_loaded = false;
795
796 /* Map legacy -drive if=pflash to machine properties */
797 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) {
798 pflash_cfi01_legacy_drive(lams->flash[i],
799 drive_get(IF_PFLASH, 0, i));
800 }
801
802 virt_flash_map(lams, get_system_memory());
803
804 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]);
805
806 if (pflash_blk0) {
807 if (filename) {
808 error_report("cannot use both '-bios' and '-drive if=pflash'"
809 "options at once");
810 exit(1);
811 }
812 lams->bios_loaded = true;
813 return;
814 }
815
816 if (filename) {
817 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename);
818 if (!bios_name) {
819 error_report("Could not find ROM image '%s'", filename);
820 exit(1);
821 }
822
823 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0);
824 bios_size = load_image_mr(bios_name, mr);
825 if (bios_size < 0) {
826 error_report("Could not load ROM image '%s'", bios_name);
827 exit(1);
828 }
829 g_free(bios_name);
830 lams->bios_loaded = true;
831 }
832 }
833
834
835 static void loongarch_qemu_write(void *opaque, hwaddr addr,
836 uint64_t val, unsigned size)
837 {
838 }
839
840 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
841 {
842 switch (addr) {
843 case VERSION_REG:
844 return 0x11ULL;
845 case FEATURE_REG:
846 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
847 1ULL << IOCSRF_CSRIPI;
848 case VENDOR_REG:
849 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */
850 case CPUNAME_REG:
851 return 0x303030354133ULL; /* "3A5000" */
852 case MISC_FUNC_REG:
853 return 1ULL << IOCSRM_EXTIOI_EN;
854 }
855 return 0ULL;
856 }
857
858 static const MemoryRegionOps loongarch_qemu_ops = {
859 .read = loongarch_qemu_read,
860 .write = loongarch_qemu_write,
861 .endianness = DEVICE_LITTLE_ENDIAN,
862 .valid = {
863 .min_access_size = 4,
864 .max_access_size = 8,
865 },
866 .impl = {
867 .min_access_size = 8,
868 .max_access_size = 8,
869 },
870 };
871
872 static void loongarch_init(MachineState *machine)
873 {
874 LoongArchCPU *lacpu;
875 const char *cpu_model = machine->cpu_type;
876 ram_addr_t offset = 0;
877 ram_addr_t ram_size = machine->ram_size;
878 uint64_t highram_size = 0, phyAddr = 0;
879 MemoryRegion *address_space_mem = get_system_memory();
880 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
881 int nb_numa_nodes = machine->numa_state->num_nodes;
882 NodeInfo *numa_info = machine->numa_state->nodes;
883 int i;
884 const CPUArchIdList *possible_cpus;
885 MachineClass *mc = MACHINE_GET_CLASS(machine);
886 CPUState *cpu;
887
888 if (!cpu_model) {
889 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
890 }
891
892 if (ram_size < 1 * GiB) {
893 error_report("ram_size must be greater than 1G.");
894 exit(1);
895 }
896 create_fdt(lams);
897
898 /* Create IOCSR space */
899 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL,
900 machine, "iocsr", UINT64_MAX);
901 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR");
902 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine),
903 &loongarch_qemu_ops,
904 machine, "iocsr_misc", 0x428);
905 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem);
906
907 /* Init CPUs */
908 possible_cpus = mc->possible_cpu_arch_ids(machine);
909 for (i = 0; i < possible_cpus->len; i++) {
910 cpu = cpu_create(machine->cpu_type);
911 cpu->cpu_index = i;
912 machine->possible_cpus->cpus[i].cpu = cpu;
913 lacpu = LOONGARCH_CPU(cpu);
914 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
915 }
916 fdt_add_cpu_nodes(lams);
917
918 /* Node0 memory */
919 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
920 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
921 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram",
922 machine->ram, offset, VIRT_LOWMEM_SIZE);
923 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem);
924
925 offset += VIRT_LOWMEM_SIZE;
926 if (nb_numa_nodes > 0) {
927 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
928 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
929 } else {
930 highram_size = ram_size - VIRT_LOWMEM_SIZE;
931 }
932 phyAddr = VIRT_HIGHMEM_BASE;
933 memmap_add_entry(phyAddr, highram_size, 1);
934 fdt_add_memory_node(machine, phyAddr, highram_size, 0);
935 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram",
936 machine->ram, offset, highram_size);
937 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem);
938
939 /* Node1 - Nodemax memory */
940 offset += highram_size;
941 phyAddr += highram_size;
942
943 for (i = 1; i < nb_numa_nodes; i++) {
944 MemoryRegion *nodemem = g_new(MemoryRegion, 1);
945 g_autofree char *ramName = g_strdup_printf("loongarch.node%d.ram", i);
946 memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
947 offset, numa_info[i].node_mem);
948 memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
949 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
950 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
951 offset += numa_info[i].node_mem;
952 phyAddr += numa_info[i].node_mem;
953 }
954
955 /* initialize device memory address space */
956 if (machine->ram_size < machine->maxram_size) {
957 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
958 hwaddr device_mem_base;
959
960 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
961 error_report("unsupported amount of memory slots: %"PRIu64,
962 machine->ram_slots);
963 exit(EXIT_FAILURE);
964 }
965
966 if (QEMU_ALIGN_UP(machine->maxram_size,
967 TARGET_PAGE_SIZE) != machine->maxram_size) {
968 error_report("maximum memory size must by aligned to multiple of "
969 "%d bytes", TARGET_PAGE_SIZE);
970 exit(EXIT_FAILURE);
971 }
972 /* device memory base is the top of high memory address. */
973 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB);
974 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
975 }
976
977 /* load the BIOS image. */
978 loongarch_firmware_init(lams);
979
980 /* fw_cfg init */
981 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine);
982 rom_set_fw(lams->fw_cfg);
983 if (lams->fw_cfg != NULL) {
984 fw_cfg_add_file(lams->fw_cfg, "etc/memmap",
985 memmap_table,
986 sizeof(struct memmap_entry) * (memmap_entries));
987 }
988 fdt_add_fw_cfg_node(lams);
989 fdt_add_flash_node(lams);
990
991 /* Initialize the IO interrupt subsystem */
992 loongarch_irq_init(lams);
993 platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
994 VIRT_PLATFORM_BUS_BASEADDRESS,
995 VIRT_PLATFORM_BUS_SIZE,
996 VIRT_PLATFORM_BUS_IRQ);
997 lams->machine_done.notify = virt_machine_done;
998 qemu_add_machine_init_done_notifier(&lams->machine_done);
999 /* connect powerdown request */
1000 lams->powerdown_notifier.notify = virt_powerdown_req;
1001 qemu_register_powerdown_notifier(&lams->powerdown_notifier);
1002
1003 /*
1004 * Since lowmem region starts from 0 and Linux kernel legacy start address
1005 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
1006 * access. FDT size limit with 1 MiB.
1007 * Put the FDT into the memory map as a ROM image: this will ensure
1008 * the FDT is copied again upon reset, even if addr points into RAM.
1009 */
1010 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
1011 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE,
1012 &address_space_memory);
1013 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
1014 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size));
1015
1016 lams->bootinfo.ram_size = ram_size;
1017 loongarch_load_kernel(machine, &lams->bootinfo);
1018 }
1019
1020 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
1021 {
1022 if (lams->acpi == ON_OFF_AUTO_OFF) {
1023 return false;
1024 }
1025 return true;
1026 }
1027
1028 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name,
1029 void *opaque, Error **errp)
1030 {
1031 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
1032 OnOffAuto acpi = lams->acpi;
1033
1034 visit_type_OnOffAuto(v, name, &acpi, errp);
1035 }
1036
1037 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name,
1038 void *opaque, Error **errp)
1039 {
1040 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
1041
1042 visit_type_OnOffAuto(v, name, &lams->acpi, errp);
1043 }
1044
1045 static void loongarch_machine_initfn(Object *obj)
1046 {
1047 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
1048
1049 lams->acpi = ON_OFF_AUTO_AUTO;
1050 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
1051 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
1052 virt_flash_create(lams);
1053 }
1054
1055 static bool memhp_type_supported(DeviceState *dev)
1056 {
1057 /* we only support pc dimm now */
1058 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
1059 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1060 }
1061
1062 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1063 Error **errp)
1064 {
1065 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
1066 }
1067
1068 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev,
1069 DeviceState *dev, Error **errp)
1070 {
1071 if (memhp_type_supported(dev)) {
1072 virt_mem_pre_plug(hotplug_dev, dev, errp);
1073 }
1074 }
1075
1076 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev,
1077 DeviceState *dev, Error **errp)
1078 {
1079 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
1080
1081 /* the acpi ged is always exist */
1082 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev,
1083 errp);
1084 }
1085
1086 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev,
1087 DeviceState *dev, Error **errp)
1088 {
1089 if (memhp_type_supported(dev)) {
1090 virt_mem_unplug_request(hotplug_dev, dev, errp);
1091 }
1092 }
1093
1094 static void virt_mem_unplug(HotplugHandler *hotplug_dev,
1095 DeviceState *dev, Error **errp)
1096 {
1097 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
1098
1099 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp);
1100 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams));
1101 qdev_unrealize(dev);
1102 }
1103
1104 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev,
1105 DeviceState *dev, Error **errp)
1106 {
1107 if (memhp_type_supported(dev)) {
1108 virt_mem_unplug(hotplug_dev, dev, errp);
1109 }
1110 }
1111
1112 static void virt_mem_plug(HotplugHandler *hotplug_dev,
1113 DeviceState *dev, Error **errp)
1114 {
1115 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
1116
1117 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams));
1118 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged),
1119 dev, &error_abort);
1120 }
1121
1122 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1123 DeviceState *dev, Error **errp)
1124 {
1125 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
1126 MachineClass *mc = MACHINE_GET_CLASS(lams);
1127
1128 if (device_is_dynamic_sysbus(mc, dev)) {
1129 if (lams->platform_bus_dev) {
1130 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev),
1131 SYS_BUS_DEVICE(dev));
1132 }
1133 } else if (memhp_type_supported(dev)) {
1134 virt_mem_plug(hotplug_dev, dev, errp);
1135 }
1136 }
1137
1138 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1139 DeviceState *dev)
1140 {
1141 MachineClass *mc = MACHINE_GET_CLASS(machine);
1142
1143 if (device_is_dynamic_sysbus(mc, dev) ||
1144 memhp_type_supported(dev)) {
1145 return HOTPLUG_HANDLER(machine);
1146 }
1147 return NULL;
1148 }
1149
1150 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1151 {
1152 int n;
1153 unsigned int max_cpus = ms->smp.max_cpus;
1154
1155 if (ms->possible_cpus) {
1156 assert(ms->possible_cpus->len == max_cpus);
1157 return ms->possible_cpus;
1158 }
1159
1160 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1161 sizeof(CPUArchId) * max_cpus);
1162 ms->possible_cpus->len = max_cpus;
1163 for (n = 0; n < ms->possible_cpus->len; n++) {
1164 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1165 ms->possible_cpus->cpus[n].arch_id = n;
1166
1167 ms->possible_cpus->cpus[n].props.has_socket_id = true;
1168 ms->possible_cpus->cpus[n].props.socket_id =
1169 n / (ms->smp.cores * ms->smp.threads);
1170 ms->possible_cpus->cpus[n].props.has_core_id = true;
1171 ms->possible_cpus->cpus[n].props.core_id =
1172 n / ms->smp.threads % ms->smp.cores;
1173 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1174 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
1175 }
1176 return ms->possible_cpus;
1177 }
1178
1179 static CpuInstanceProperties
1180 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1181 {
1182 MachineClass *mc = MACHINE_GET_CLASS(ms);
1183 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1184
1185 assert(cpu_index < possible_cpus->len);
1186 return possible_cpus->cpus[cpu_index].props;
1187 }
1188
1189 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1190 {
1191 int64_t nidx = 0;
1192
1193 if (ms->numa_state->num_nodes) {
1194 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
1195 if (ms->numa_state->num_nodes <= nidx) {
1196 nidx = ms->numa_state->num_nodes - 1;
1197 }
1198 }
1199 return nidx;
1200 }
1201
1202 static void loongarch_class_init(ObjectClass *oc, void *data)
1203 {
1204 MachineClass *mc = MACHINE_CLASS(oc);
1205 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1206
1207 mc->desc = "Loongson-3A5000 LS7A1000 machine";
1208 mc->init = loongarch_init;
1209 mc->default_ram_size = 1 * GiB;
1210 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
1211 mc->default_ram_id = "loongarch.ram";
1212 mc->max_cpus = LOONGARCH_MAX_CPUS;
1213 mc->is_default = 1;
1214 mc->default_kernel_irqchip_split = false;
1215 mc->block_default_type = IF_VIRTIO;
1216 mc->default_boot_order = "c";
1217 mc->no_cdrom = 1;
1218 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1219 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1220 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1221 mc->numa_mem_supported = true;
1222 mc->auto_enable_numa_with_memhp = true;
1223 mc->auto_enable_numa_with_memdev = true;
1224 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1225 mc->default_nic = "virtio-net-pci";
1226 hc->plug = loongarch_machine_device_plug_cb;
1227 hc->pre_plug = virt_machine_device_pre_plug;
1228 hc->unplug_request = virt_machine_device_unplug_request;
1229 hc->unplug = virt_machine_device_unplug;
1230
1231 object_class_property_add(oc, "acpi", "OnOffAuto",
1232 loongarch_get_acpi, loongarch_set_acpi,
1233 NULL, NULL);
1234 object_class_property_set_description(oc, "acpi",
1235 "Enable ACPI");
1236 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1237 #ifdef CONFIG_TPM
1238 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1239 #endif
1240 }
1241
1242 static const TypeInfo loongarch_machine_types[] = {
1243 {
1244 .name = TYPE_LOONGARCH_MACHINE,
1245 .parent = TYPE_MACHINE,
1246 .instance_size = sizeof(LoongArchMachineState),
1247 .class_init = loongarch_class_init,
1248 .instance_init = loongarch_machine_initfn,
1249 .interfaces = (InterfaceInfo[]) {
1250 { TYPE_HOTPLUG_HANDLER },
1251 { }
1252 },
1253 }
1254 };
1255
1256 DEFINE_TYPES(loongarch_machine_types)
AR7 emulation for QEMU