cpu-exec.c

   1 /*
   2  *  emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas.h"
  22 #include "tcg.h"
  23 #include "qemu-barrier.h"
  24 #include "qtest.h"
  25
  26 int tb_invalidated_flag;
  27
  28 //#define CONFIG_DEBUG_EXEC
  29
  30 bool qemu_cpu_has_work(CPUArchState *env)
  31 {
  32     return cpu_has_work(env);
  33 }
  34
  35 void cpu_loop_exit(CPUArchState *env)
  36 {
  37     env->current_tb = NULL;
  38     longjmp(env->jmp_env, 1);
  39 }
  40
  41 /* exit the current TB from a signal handler. The host registers are
  42    restored in a state compatible with the CPU emulator
  43  */
  44 #if defined(CONFIG_SOFTMMU)
  45 void cpu_resume_from_signal(CPUArchState *env, void *puc)
  46 {
  47     /* XXX: restore cpu registers saved in host registers */
  48
  49     env->exception_index = -1;
  50     longjmp(env->jmp_env, 1);
  51 }
  52 #endif
  53
  54 /* Execute the code without caching the generated code. An interpreter
  55    could be used if available. */
  56 static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
  57                              TranslationBlock *orig_tb)
  58 {
  59     tcg_target_ulong next_tb;
  60     TranslationBlock *tb;
  61
  62     /* Should never happen.
  63        We only end up here when an existing TB is too long.  */
  64     if (max_cycles > CF_COUNT_MASK)
  65         max_cycles = CF_COUNT_MASK;
  66
  67     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
  68                      max_cycles);
  69     env->current_tb = tb;
  70     /* execute the generated code */
  71     next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr);
  72     env->current_tb = NULL;
  73
  74     if ((next_tb & 3) == 2) {
  75         /* Restore PC.  This may happen if async event occurs before
  76            the TB starts executing.  */
  77         cpu_pc_from_tb(env, tb);
  78     }
  79     tb_phys_invalidate(tb, -1);
  80     tb_free(tb);
  81 }
  82
  83 static TranslationBlock *tb_find_slow(CPUArchState *env,
  84                                       target_ulong pc,
  85                                       target_ulong cs_base,
  86                                       uint64_t flags)
  87 {
  88     TranslationBlock *tb, **ptb1;
  89     unsigned int h;
  90     tb_page_addr_t phys_pc, phys_page1;
  91     target_ulong virt_page2;
  92
  93     tb_invalidated_flag = 0;
  94
  95     /* find translated block using physical mappings */
  96     phys_pc = get_page_addr_code(env, pc);
  97     phys_page1 = phys_pc & TARGET_PAGE_MASK;
  98     h = tb_phys_hash_func(phys_pc);
  99     ptb1 = &tb_phys_hash[h];
 100     for(;;) {
 101         tb = *ptb1;
 102         if (!tb)
 103             goto not_found;
 104         if (tb->pc == pc &&
 105             tb->page_addr[0] == phys_page1 &&
 106             tb->cs_base == cs_base &&
 107             tb->flags == flags) {
 108             /* check next page if needed */
 109             if (tb->page_addr[1] != -1) {
 110                 tb_page_addr_t phys_page2;
 111
 112                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 113                     TARGET_PAGE_SIZE;
 114                 phys_page2 = get_page_addr_code(env, virt_page2);
 115                 if (tb->page_addr[1] == phys_page2)
 116                     goto found;
 117             } else {
 118                 goto found;
 119             }
 120         }
 121         ptb1 = &tb->phys_hash_next;
 122     }
 123  not_found:
 124    /* if no translated code available, then translate it now */
 125     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 126
 127  found:
 128     /* Move the last found TB to the head of the list */
 129     if (likely(*ptb1)) {
 130         *ptb1 = tb->phys_hash_next;
 131         tb->phys_hash_next = tb_phys_hash[h];
 132         tb_phys_hash[h] = tb;
 133     }
 134     /* we add the TB in the virtual pc hash table */
 135     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 136     return tb;
 137 }
 138
 139 static inline TranslationBlock *tb_find_fast(CPUArchState *env)
 140 {
 141     TranslationBlock *tb;
 142     target_ulong cs_base, pc;
 143     int flags;
 144
 145     /* we record a subset of the CPU state. It will
 146        always be the same before a given translated block
 147        is executed. */
 148     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 149     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 150     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 151                  tb->flags != flags)) {
 152         tb = tb_find_slow(env, pc, cs_base, flags);
 153     }
 154     return tb;
 155 }
 156
 157 static CPUDebugExcpHandler *debug_excp_handler;
 158
 159 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
 160 {
 161     CPUDebugExcpHandler *old_handler = debug_excp_handler;
 162
 163     debug_excp_handler = handler;
 164     return old_handler;
 165 }
 166
 167 static void cpu_handle_debug_exception(CPUArchState *env)
 168 {
 169     CPUWatchpoint *wp;
 170
 171     if (!env->watchpoint_hit) {
 172         QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 173             wp->flags &= ~BP_WATCHPOINT_HIT;
 174         }
 175     }
 176     if (debug_excp_handler) {
 177         debug_excp_handler(env);
 178     }
 179 }
 180
 181 /* main execution loop */
 182
 183 volatile sig_atomic_t exit_request;
 184
 185 int cpu_exec(CPUArchState *env)
 186 {
 187 #ifdef TARGET_PPC
 188     CPUState *cpu = ENV_GET_CPU(env);
 189 #endif
 190     int ret, interrupt_request;
 191     TranslationBlock *tb;
 192     uint8_t *tc_ptr;
 193     tcg_target_ulong next_tb;
 194
 195     if (env->halted) {
 196         if (!cpu_has_work(env)) {
 197             return EXCP_HALTED;
 198         }
 199
 200         env->halted = 0;
 201     }
 202
 203     cpu_single_env = env;
 204
 205     if (unlikely(exit_request)) {
 206         env->exit_request = 1;
 207     }
 208
 209 #if defined(TARGET_I386)
 210     /* put eflags in CPU temporary format */
 211     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 212     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 213     CC_OP = CC_OP_EFLAGS;
 214     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 215 #elif defined(TARGET_SPARC)
 216 #elif defined(TARGET_M68K)
 217     env->cc_op = CC_OP_FLAGS;
 218     env->cc_dest = env->sr & 0xf;
 219     env->cc_x = (env->sr >> 4) & 1;
 220 #elif defined(TARGET_ALPHA)
 221 #elif defined(TARGET_ARM)
 222 #elif defined(TARGET_UNICORE32)
 223 #elif defined(TARGET_PPC)
 224     env->reserve_addr = -1;
 225 #elif defined(TARGET_LM32)
 226 #elif defined(TARGET_MICROBLAZE)
 227 #elif defined(TARGET_MIPS)
 228 #elif defined(TARGET_OPENRISC)
 229 #elif defined(TARGET_SH4)
 230 #elif defined(TARGET_CRIS)
 231 #elif defined(TARGET_S390X)
 232 #elif defined(TARGET_XTENSA)
 233     /* XXXXX */
 234 #else
 235 #error unsupported target CPU
 236 #endif
 237     env->exception_index = -1;
 238
 239     /* prepare setjmp context for exception handling */
 240     for(;;) {
 241         if (setjmp(env->jmp_env) == 0) {
 242             /* if an exception is pending, we execute it here */
 243             if (env->exception_index >= 0) {
 244                 if (env->exception_index >= EXCP_INTERRUPT) {
 245                     /* exit request from the cpu execution loop */
 246                     ret = env->exception_index;
 247                     if (ret == EXCP_DEBUG) {
 248                         cpu_handle_debug_exception(env);
 249                     }
 250                     break;
 251                 } else {
 252 #if defined(CONFIG_USER_ONLY)
 253                     /* if user mode only, we simulate a fake exception
 254                        which will be handled outside the cpu execution
 255                        loop */
 256 #if defined(TARGET_I386)
 257                     do_interrupt(env);
 258 #endif
 259                     ret = env->exception_index;
 260                     break;
 261 #else
 262                     do_interrupt(env);
 263                     env->exception_index = -1;
 264 #endif
 265                 }
 266             }
 267
 268             next_tb = 0; /* force lookup of first TB */
 269             for(;;) {
 270                 interrupt_request = env->interrupt_request;
 271                 if (unlikely(interrupt_request)) {
 272                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
 273                         /* Mask out external interrupts for this step. */
 274                         interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
 275                     }
 276                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 277                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 278                         env->exception_index = EXCP_DEBUG;
 279                         cpu_loop_exit(env);
 280                     }
 281 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 282     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
 283     defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
 284                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 285                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 286                         env->halted = 1;
 287                         env->exception_index = EXCP_HLT;
 288                         cpu_loop_exit(env);
 289                     }
 290 #endif
 291 #if defined(TARGET_I386)
 292 #if !defined(CONFIG_USER_ONLY)
 293                     if (interrupt_request & CPU_INTERRUPT_POLL) {
 294                         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
 295                         apic_poll_irq(env->apic_state);
 296                     }
 297 #endif
 298                     if (interrupt_request & CPU_INTERRUPT_INIT) {
 299                             cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
 300                                                           0);
 301                             do_cpu_init(x86_env_get_cpu(env));
 302                             env->exception_index = EXCP_HALTED;
 303                             cpu_loop_exit(env);
 304                     } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
 305                             do_cpu_sipi(x86_env_get_cpu(env));
 306                     } else if (env->hflags2 & HF2_GIF_MASK) {
 307                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 308                             !(env->hflags & HF_SMM_MASK)) {
 309                             cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
 310                                                           0);
 311                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 312                             do_smm_enter(env);
 313                             next_tb = 0;
 314                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 315                                    !(env->hflags2 & HF2_NMI_MASK)) {
 316                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 317                             env->hflags2 |= HF2_NMI_MASK;
 318                             do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
 319                             next_tb = 0;
 320                         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
 321                             env->interrupt_request &= ~CPU_INTERRUPT_MCE;
 322                             do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
 323                             next_tb = 0;
 324                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 325                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 326                                      (env->hflags2 & HF2_HIF_MASK)) ||
 327                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 328                                      (env->eflags & IF_MASK &&
 329                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 330                             int intno;
 331                             cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
 332                                                           0);
 333                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 334                             intno = cpu_get_pic_interrupt(env);
 335                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
 336                             do_interrupt_x86_hardirq(env, intno, 1);
 337                             /* ensure that no TB jump will be modified as
 338                                the program flow was changed */
 339                             next_tb = 0;
 340 #if !defined(CONFIG_USER_ONLY)
 341                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 342                                    (env->eflags & IF_MASK) &&
 343                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 344                             int intno;
 345                             /* FIXME: this should respect TPR */
 346                             cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
 347                                                           0);
 348                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 349                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
 350                             do_interrupt_x86_hardirq(env, intno, 1);
 351                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 352                             next_tb = 0;
 353 #endif
 354                         }
 355                     }
 356 #elif defined(TARGET_PPC)
 357                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 358                         cpu_reset(cpu);
 359                     }
 360                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 361                         ppc_hw_interrupt(env);
 362                         if (env->pending_interrupts == 0)
 363                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 364                         next_tb = 0;
 365                     }
 366 #elif defined(TARGET_LM32)
 367                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 368                         && (env->ie & IE_IE)) {
 369                         env->exception_index = EXCP_IRQ;
 370                         do_interrupt(env);
 371                         next_tb = 0;
 372                     }
 373 #elif defined(TARGET_MICROBLAZE)
 374                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 375                         && (env->sregs[SR_MSR] & MSR_IE)
 376                         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 377                         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 378                         env->exception_index = EXCP_IRQ;
 379                         do_interrupt(env);
 380                         next_tb = 0;
 381                     }
 382 #elif defined(TARGET_MIPS)
 383                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 384                         cpu_mips_hw_interrupts_pending(env)) {
 385                         /* Raise it */
 386                         env->exception_index = EXCP_EXT_INTERRUPT;
 387                         env->error_code = 0;
 388                         do_interrupt(env);
 389                         next_tb = 0;
 390                     }
 391 #elif defined(TARGET_OPENRISC)
 392                     {
 393                         int idx = -1;
 394                         if ((interrupt_request & CPU_INTERRUPT_HARD)
 395                             && (env->sr & SR_IEE)) {
 396                             idx = EXCP_INT;
 397                         }
 398                         if ((interrupt_request & CPU_INTERRUPT_TIMER)
 399                             && (env->sr & SR_TEE)) {
 400                             idx = EXCP_TICK;
 401                         }
 402                         if (idx >= 0) {
 403                             env->exception_index = idx;
 404                             do_interrupt(env);
 405                             next_tb = 0;
 406                         }
 407                     }
 408 #elif defined(TARGET_SPARC)
 409                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 410                         if (cpu_interrupts_enabled(env) &&
 411                             env->interrupt_index > 0) {
 412                             int pil = env->interrupt_index & 0xf;
 413                             int type = env->interrupt_index & 0xf0;
 414
 415                             if (((type == TT_EXTINT) &&
 416                                   cpu_pil_allowed(env, pil)) ||
 417                                   type != TT_EXTINT) {
 418                                 env->exception_index = env->interrupt_index;
 419                                 do_interrupt(env);
 420                                 next_tb = 0;
 421                             }
 422                         }
 423                     }
 424 #elif defined(TARGET_ARM)
 425                     if (interrupt_request & CPU_INTERRUPT_FIQ
 426                         && !(env->uncached_cpsr & CPSR_F)) {
 427                         env->exception_index = EXCP_FIQ;
 428                         do_interrupt(env);
 429                         next_tb = 0;
 430                     }
 431                     /* ARMv7-M interrupt return works by loading a magic value
 432                        into the PC.  On real hardware the load causes the
 433                        return to occur.  The qemu implementation performs the
 434                        jump normally, then does the exception return when the
 435                        CPU tries to execute code at the magic address.
 436                        This will cause the magic PC value to be pushed to
 437                        the stack if an interrupt occurred at the wrong time.
 438                        We avoid this by disabling interrupts when
 439                        pc contains a magic address.  */
 440                     if (interrupt_request & CPU_INTERRUPT_HARD
 441                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 442                             || !(env->uncached_cpsr & CPSR_I))) {
 443                         env->exception_index = EXCP_IRQ;
 444                         do_interrupt(env);
 445                         next_tb = 0;
 446                     }
 447 #elif defined(TARGET_UNICORE32)
 448                     if (interrupt_request & CPU_INTERRUPT_HARD
 449                         && !(env->uncached_asr & ASR_I)) {
 450                         do_interrupt(env);
 451                         next_tb = 0;
 452                     }
 453 #elif defined(TARGET_SH4)
 454                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 455                         do_interrupt(env);
 456                         next_tb = 0;
 457                     }
 458 #elif defined(TARGET_ALPHA)
 459                     {
 460                         int idx = -1;
 461                         /* ??? This hard-codes the OSF/1 interrupt levels.  */
 462                         switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
 463                         case 0 ... 3:
 464                             if (interrupt_request & CPU_INTERRUPT_HARD) {
 465                                 idx = EXCP_DEV_INTERRUPT;
 466                             }
 467                             /* FALLTHRU */
 468                         case 4:
 469                             if (interrupt_request & CPU_INTERRUPT_TIMER) {
 470                                 idx = EXCP_CLK_INTERRUPT;
 471                             }
 472                             /* FALLTHRU */
 473                         case 5:
 474                             if (interrupt_request & CPU_INTERRUPT_SMP) {
 475                                 idx = EXCP_SMP_INTERRUPT;
 476                             }
 477                             /* FALLTHRU */
 478                         case 6:
 479                             if (interrupt_request & CPU_INTERRUPT_MCHK) {
 480                                 idx = EXCP_MCHK;
 481                             }
 482                         }
 483                         if (idx >= 0) {
 484                             env->exception_index = idx;
 485                             env->error_code = 0;
 486                             do_interrupt(env);
 487                             next_tb = 0;
 488                         }
 489                     }
 490 #elif defined(TARGET_CRIS)
 491                     if (interrupt_request & CPU_INTERRUPT_HARD
 492                         && (env->pregs[PR_CCS] & I_FLAG)
 493                         && !env->locked_irq) {
 494                         env->exception_index = EXCP_IRQ;
 495                         do_interrupt(env);
 496                         next_tb = 0;
 497                     }
 498                     if (interrupt_request & CPU_INTERRUPT_NMI) {
 499                         unsigned int m_flag_archval;
 500                         if (env->pregs[PR_VR] < 32) {
 501                             m_flag_archval = M_FLAG_V10;
 502                         } else {
 503                             m_flag_archval = M_FLAG_V32;
 504                         }
 505                         if ((env->pregs[PR_CCS] & m_flag_archval)) {
 506                             env->exception_index = EXCP_NMI;
 507                             do_interrupt(env);
 508                             next_tb = 0;
 509                         }
 510                     }
 511 #elif defined(TARGET_M68K)
 512                     if (interrupt_request & CPU_INTERRUPT_HARD
 513                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 514                             < env->pending_level) {
 515                         /* Real hardware gets the interrupt vector via an
 516                            IACK cycle at this point.  Current emulated
 517                            hardware doesn't rely on this, so we
 518                            provide/save the vector when the interrupt is
 519                            first signalled.  */
 520                         env->exception_index = env->pending_vector;
 521                         do_interrupt_m68k_hardirq(env);
 522                         next_tb = 0;
 523                     }
 524 #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
 525                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 526                         (env->psw.mask & PSW_MASK_EXT)) {
 527                         do_interrupt(env);
 528                         next_tb = 0;
 529                     }
 530 #elif defined(TARGET_XTENSA)
 531                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 532                         env->exception_index = EXC_IRQ;
 533                         do_interrupt(env);
 534                         next_tb = 0;
 535                     }
 536 #endif
 537                    /* Don't use the cached interrupt_request value,
 538                       do_interrupt may have updated the EXITTB flag. */
 539                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 540                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 541                         /* ensure that no TB jump will be modified as
 542                            the program flow was changed */
 543                         next_tb = 0;
 544                     }
 545                 }
 546                 if (unlikely(env->exit_request)) {
 547                     env->exit_request = 0;
 548                     env->exception_index = EXCP_INTERRUPT;
 549                     cpu_loop_exit(env);
 550                 }
 551 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
 552                 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 553                     /* restore flags in standard format */
 554 #if defined(TARGET_I386)
 555                     env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
 556                         | (DF & DF_MASK);
 557                     log_cpu_state(env, X86_DUMP_CCOP);
 558                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 559 #elif defined(TARGET_M68K)
 560                     cpu_m68k_flush_flags(env, env->cc_op);
 561                     env->cc_op = CC_OP_FLAGS;
 562                     env->sr = (env->sr & 0xffe0)
 563                               | env->cc_dest | (env->cc_x << 4);
 564                     log_cpu_state(env, 0);
 565 #else
 566                     log_cpu_state(env, 0);
 567 #endif
 568                 }
 569 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
 570                 spin_lock(&tb_lock);
 571                 tb = tb_find_fast(env);
 572                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 573                    doing it in tb_find_slow */
 574                 if (tb_invalidated_flag) {
 575                     /* as some TB could have been invalidated because
 576                        of memory exceptions while generating the code, we
 577                        must recompute the hash index here */
 578                     next_tb = 0;
 579                     tb_invalidated_flag = 0;
 580                 }
 581 #ifdef CONFIG_DEBUG_EXEC
 582                 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
 583                              tb->tc_ptr, tb->pc,
 584                              lookup_symbol(tb->pc));
 585 #endif
 586                 /* see if we can patch the calling TB. When the TB
 587                    spans two pages, we cannot safely do a direct
 588                    jump. */
 589                 if (next_tb != 0 && tb->page_addr[1] == -1) {
 590                     tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
 591                 }
 592                 spin_unlock(&tb_lock);
 593
 594                 /* cpu_interrupt might be called while translating the
 595                    TB, but before it is linked into a potentially
 596                    infinite loop and becomes env->current_tb. Avoid
 597                    starting execution if there is a pending interrupt. */
 598                 env->current_tb = tb;
 599                 barrier();
 600                 if (likely(!env->exit_request)) {
 601                     tc_ptr = tb->tc_ptr;
 602                     /* execute the generated code */
 603                     next_tb = tcg_qemu_tb_exec(env, tc_ptr);
 604                     if ((next_tb & 3) == 2) {
 605                         /* Instruction counter expired.  */
 606                         int insns_left;
 607                         tb = (TranslationBlock *)(next_tb & ~3);
 608                         /* Restore PC.  */
 609                         cpu_pc_from_tb(env, tb);
 610                         insns_left = env->icount_decr.u32;
 611                         if (env->icount_extra && insns_left >= 0) {
 612                             /* Refill decrementer and continue execution.  */
 613                             env->icount_extra += insns_left;
 614                             if (env->icount_extra > 0xffff) {
 615                                 insns_left = 0xffff;
 616                             } else {
 617                                 insns_left = env->icount_extra;
 618                             }
 619                             env->icount_extra -= insns_left;
 620                             env->icount_decr.u16.low = insns_left;
 621                         } else {
 622                             if (insns_left > 0) {
 623                                 /* Execute remaining instructions.  */
 624                                 cpu_exec_nocache(env, insns_left, tb);
 625                             }
 626                             env->exception_index = EXCP_INTERRUPT;
 627                             next_tb = 0;
 628                             cpu_loop_exit(env);
 629                         }
 630                     }
 631                 }
 632                 env->current_tb = NULL;
 633                 /* reset soft MMU for next block (it can currently
 634                    only be set by a memory fault) */
 635             } /* for(;;) */
 636         } else {
 637             /* Reload env after longjmp - the compiler may have smashed all
 638              * local variables as longjmp is marked 'noreturn'. */
 639             env = cpu_single_env;
 640         }
 641     } /* for(;;) */
 642
 643
 644 #if defined(TARGET_I386)
 645     /* restore flags in standard format */
 646     env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
 647         | (DF & DF_MASK);
 648 #elif defined(TARGET_ARM)
 649     /* XXX: Save/restore host fpu exception state?.  */
 650 #elif defined(TARGET_UNICORE32)
 651 #elif defined(TARGET_SPARC)
 652 #elif defined(TARGET_PPC)
 653 #elif defined(TARGET_LM32)
 654 #elif defined(TARGET_M68K)
 655     cpu_m68k_flush_flags(env, env->cc_op);
 656     env->cc_op = CC_OP_FLAGS;
 657     env->sr = (env->sr & 0xffe0)
 658               | env->cc_dest | (env->cc_x << 4);
 659 #elif defined(TARGET_MICROBLAZE)
 660 #elif defined(TARGET_MIPS)
 661 #elif defined(TARGET_OPENRISC)
 662 #elif defined(TARGET_SH4)
 663 #elif defined(TARGET_ALPHA)
 664 #elif defined(TARGET_CRIS)
 665 #elif defined(TARGET_S390X)
 666 #elif defined(TARGET_XTENSA)
 667     /* XXXXX */
 668 #else
 669 #error unsupported target CPU
 670 #endif
 671
 672     /* fail safe : never use cpu_single_env outside cpu_exec() */
 673     cpu_single_env = NULL;
 674     return ret;
 675 }