2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/char/serial.h"
28 #include "chardev/char-serial.h"
29 #include "qapi/error.h"
30 #include "qemu/timer.h"
31 #include "qemu/error-report.h"
34 //#define DEBUG_SERIAL
36 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
38 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
39 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
40 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
41 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
43 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
44 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
46 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
47 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
48 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
49 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
50 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
52 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
53 #define UART_IIR_FE 0xC0 /* Fifo enabled */
56 * These are the definitions for the Modem Control Register
58 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
59 #define UART_MCR_OUT2 0x08 /* Out2 complement */
60 #define UART_MCR_OUT1 0x04 /* Out1 complement */
61 #define UART_MCR_RTS 0x02 /* RTS complement */
62 #define UART_MCR_DTR 0x01 /* DTR complement */
65 * These are the definitions for the Modem Status Register
67 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
68 #define UART_MSR_RI 0x40 /* Ring Indicator */
69 #define UART_MSR_DSR 0x20 /* Data Set Ready */
70 #define UART_MSR_CTS 0x10 /* Clear to Send */
71 #define UART_MSR_DDCD 0x08 /* Delta DCD */
72 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
73 #define UART_MSR_DDSR 0x02 /* Delta DSR */
74 #define UART_MSR_DCTS 0x01 /* Delta CTS */
75 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
77 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
78 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
79 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
80 #define UART_LSR_FE 0x08 /* Frame error indicator */
81 #define UART_LSR_PE 0x04 /* Parity error indicator */
82 #define UART_LSR_OE 0x02 /* Overrun error indicator */
83 #define UART_LSR_DR 0x01 /* Receiver data ready */
84 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
86 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
88 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
89 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
90 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
91 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
93 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
94 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
95 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
96 #define UART_FCR_FE 0x01 /* FIFO Enable */
98 #define MAX_XMIT_RETRY 4
101 #define DPRINTF(fmt, ...) \
102 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
104 #define DPRINTF(fmt, ...) \
108 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
);
109 static void serial_xmit(SerialState
*s
);
111 static inline void recv_fifo_put(SerialState
*s
, uint8_t chr
)
113 /* Receive overruns do not overwrite FIFO contents. */
114 if (!fifo8_is_full(&s
->recv_fifo
)) {
115 fifo8_push(&s
->recv_fifo
, chr
);
117 s
->lsr
|= UART_LSR_OE
;
121 static void serial_update_irq(SerialState
*s
)
123 uint8_t tmp_iir
= UART_IIR_NO_INT
;
125 if ((s
->ier
& UART_IER_RLSI
) && (s
->lsr
& UART_LSR_INT_ANY
)) {
126 tmp_iir
= UART_IIR_RLSI
;
127 } else if ((s
->ier
& UART_IER_RDI
) && s
->timeout_ipending
) {
128 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
129 * this is not in the specification but is observed on existing
131 tmp_iir
= UART_IIR_CTI
;
132 } else if ((s
->ier
& UART_IER_RDI
) && (s
->lsr
& UART_LSR_DR
) &&
133 (!(s
->fcr
& UART_FCR_FE
) ||
134 s
->recv_fifo
.num
>= s
->recv_fifo_itl
)) {
135 tmp_iir
= UART_IIR_RDI
;
136 } else if ((s
->ier
& UART_IER_THRI
) && s
->thr_ipending
) {
137 tmp_iir
= UART_IIR_THRI
;
138 } else if ((s
->ier
& UART_IER_MSI
) && (s
->msr
& UART_MSR_ANY_DELTA
)) {
139 tmp_iir
= UART_IIR_MSI
;
142 s
->iir
= tmp_iir
| (s
->iir
& 0xF0);
144 if (tmp_iir
!= UART_IIR_NO_INT
) {
145 qemu_irq_raise(s
->irq
);
147 qemu_irq_lower(s
->irq
);
151 static void serial_update_parameters(SerialState
*s
)
154 int parity
, data_bits
, stop_bits
, frame_size
;
155 QEMUSerialSetParams ssp
;
175 data_bits
= (s
->lcr
& 0x03) + 5;
176 frame_size
+= data_bits
+ stop_bits
;
177 /* Zero divisor should give about 3500 baud */
178 speed
= (s
->divider
== 0) ? 3500 : (float) s
->baudbase
/ s
->divider
;
181 ssp
.data_bits
= data_bits
;
182 ssp
.stop_bits
= stop_bits
;
183 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
184 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
186 DPRINTF("speed=%.2f parity=%c data=%d stop=%d\n",
187 speed
, parity
, data_bits
, stop_bits
);
190 static void serial_update_msl(SerialState
*s
)
195 timer_del(s
->modem_status_poll
);
197 if (qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
,
198 &flags
) == -ENOTSUP
) {
205 s
->msr
= (flags
& CHR_TIOCM_CTS
) ? s
->msr
| UART_MSR_CTS
: s
->msr
& ~UART_MSR_CTS
;
206 s
->msr
= (flags
& CHR_TIOCM_DSR
) ? s
->msr
| UART_MSR_DSR
: s
->msr
& ~UART_MSR_DSR
;
207 s
->msr
= (flags
& CHR_TIOCM_CAR
) ? s
->msr
| UART_MSR_DCD
: s
->msr
& ~UART_MSR_DCD
;
208 s
->msr
= (flags
& CHR_TIOCM_RI
) ? s
->msr
| UART_MSR_RI
: s
->msr
& ~UART_MSR_RI
;
210 if (s
->msr
!= omsr
) {
212 s
->msr
= s
->msr
| ((s
->msr
>> 4) ^ (omsr
>> 4));
213 /* UART_MSR_TERI only if change was from 1 -> 0 */
214 if ((s
->msr
& UART_MSR_TERI
) && !(omsr
& UART_MSR_RI
))
215 s
->msr
&= ~UART_MSR_TERI
;
216 serial_update_irq(s
);
219 /* The real 16550A apparently has a 250ns response latency to line status changes.
220 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
223 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
224 NANOSECONDS_PER_SECOND
/ 100);
228 static gboolean
serial_watch_cb(GIOChannel
*chan
, GIOCondition cond
,
231 SerialState
*s
= opaque
;
237 static void serial_xmit(SerialState
*s
)
240 assert(!(s
->lsr
& UART_LSR_TEMT
));
241 if (s
->tsr_retry
== 0) {
242 assert(!(s
->lsr
& UART_LSR_THRE
));
244 if (s
->fcr
& UART_FCR_FE
) {
245 assert(!fifo8_is_empty(&s
->xmit_fifo
));
246 s
->tsr
= fifo8_pop(&s
->xmit_fifo
);
247 if (!s
->xmit_fifo
.num
) {
248 s
->lsr
|= UART_LSR_THRE
;
252 s
->lsr
|= UART_LSR_THRE
;
254 if ((s
->lsr
& UART_LSR_THRE
) && !s
->thr_ipending
) {
256 serial_update_irq(s
);
260 if (s
->mcr
& UART_MCR_LOOP
) {
261 /* in loopback mode, say that we just received a char */
262 serial_receive1(s
, &s
->tsr
, 1);
264 int rc
= qemu_chr_fe_write(&s
->chr
, &s
->tsr
, 1);
267 (rc
== -1 && errno
== EAGAIN
)) &&
268 s
->tsr_retry
< MAX_XMIT_RETRY
) {
269 assert(s
->watch_tag
== 0);
271 qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
273 if (s
->watch_tag
> 0) {
281 /* Transmit another byte if it is already available. It is only
282 possible when FIFO is enabled and not empty. */
283 } while (!(s
->lsr
& UART_LSR_THRE
));
285 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
286 s
->lsr
|= UART_LSR_TEMT
;
290 is_load flag means, that value is set while loading VM state
291 and interrupt should not be invoked */
292 static void serial_write_fcr(SerialState
*s
, uint8_t val
)
294 /* Set fcr - val only has the bits that are supposed to "stick" */
297 if (val
& UART_FCR_FE
) {
298 s
->iir
|= UART_IIR_FE
;
299 /* Set recv_fifo trigger Level */
300 switch (val
& 0xC0) {
302 s
->recv_fifo_itl
= 1;
305 s
->recv_fifo_itl
= 4;
308 s
->recv_fifo_itl
= 8;
311 s
->recv_fifo_itl
= 14;
315 s
->iir
&= ~UART_IIR_FE
;
319 static void serial_update_tiocm(SerialState
*s
)
323 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
, &flags
);
325 flags
&= ~(CHR_TIOCM_RTS
| CHR_TIOCM_DTR
);
327 if (s
->mcr
& UART_MCR_RTS
) {
328 flags
|= CHR_TIOCM_RTS
;
330 if (s
->mcr
& UART_MCR_DTR
) {
331 flags
|= CHR_TIOCM_DTR
;
334 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_TIOCM
, &flags
);
337 static void serial_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
340 SerialState
*s
= opaque
;
345 trace_serial_ioport_write(addr
, val
);
349 if (s
->lcr
& UART_LCR_DLAB
) {
351 s
->divider
= (s
->divider
& 0xff00) | val
;
355 serial_update_parameters(s
);
357 s
->thr
= (uint8_t) val
;
358 if(s
->fcr
& UART_FCR_FE
) {
359 /* xmit overruns overwrite data, so make space if needed */
360 if (fifo8_is_full(&s
->xmit_fifo
)) {
361 fifo8_pop(&s
->xmit_fifo
);
363 fifo8_push(&s
->xmit_fifo
, s
->thr
);
366 s
->lsr
&= ~UART_LSR_THRE
;
367 s
->lsr
&= ~UART_LSR_TEMT
;
368 serial_update_irq(s
);
369 if (s
->tsr_retry
== 0) {
375 if (s
->lcr
& UART_LCR_DLAB
) {
376 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
377 serial_update_parameters(s
);
379 uint8_t changed
= (s
->ier
^ val
) & 0x0f;
381 /* If the backend device is a real serial port, turn polling of the modem
382 * status lines on physical port on or off depending on UART_IER_MSI state.
384 if ((changed
& UART_IER_MSI
) && s
->poll_msl
>= 0) {
385 if (s
->ier
& UART_IER_MSI
) {
387 serial_update_msl(s
);
389 timer_del(s
->modem_status_poll
);
394 /* Turning on the THRE interrupt on IER can trigger the interrupt
395 * if LSR.THRE=1, even if it had been masked before by reading IIR.
396 * This is not in the datasheet, but Windows relies on it. It is
397 * unclear if THRE has to be resampled every time THRI becomes
398 * 1, or only on the rising edge. Bochs does the latter, and Windows
399 * always toggles IER to all zeroes and back to all ones, so do the
402 * If IER.THRI is zero, thr_ipending is not used. Set it to zero
403 * so that the thr_ipending subsection is not migrated.
405 if (changed
& UART_IER_THRI
) {
406 if ((s
->ier
& UART_IER_THRI
) && (s
->lsr
& UART_LSR_THRE
)) {
414 serial_update_irq(s
);
419 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
420 if ((val
^ s
->fcr
) & UART_FCR_FE
) {
421 val
|= UART_FCR_XFR
| UART_FCR_RFR
;
426 if (val
& UART_FCR_RFR
) {
427 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
428 timer_del(s
->fifo_timeout_timer
);
429 s
->timeout_ipending
= 0;
430 fifo8_reset(&s
->recv_fifo
);
433 if (val
& UART_FCR_XFR
) {
434 s
->lsr
|= UART_LSR_THRE
;
436 fifo8_reset(&s
->xmit_fifo
);
439 serial_write_fcr(s
, val
& 0xC9);
440 serial_update_irq(s
);
446 serial_update_parameters(s
);
447 break_enable
= (val
>> 6) & 1;
448 if (break_enable
!= s
->last_break_enable
) {
449 s
->last_break_enable
= break_enable
;
450 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
457 int old_mcr
= s
->mcr
;
459 if (val
& UART_MCR_LOOP
)
462 if (s
->poll_msl
>= 0 && old_mcr
!= s
->mcr
) {
463 serial_update_tiocm(s
);
464 /* Update the modem status after a one-character-send wait-time, since there may be a response
465 from the device/computer at the other end of the serial line */
466 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
);
480 static uint64_t serial_ioport_read(void *opaque
, hwaddr addr
, unsigned size
)
482 SerialState
*s
= opaque
;
488 //~ fprintf(stderr, "%s(%p,0x%08x)\n", __func__, opaque, addr);
493 if (s
->lcr
& UART_LCR_DLAB
) {
494 ret
= s
->divider
& 0xff;
496 if(s
->fcr
& UART_FCR_FE
) {
497 ret
= fifo8_is_empty(&s
->recv_fifo
) ?
498 0 : fifo8_pop(&s
->recv_fifo
);
499 if (s
->recv_fifo
.num
== 0) {
500 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
502 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
504 s
->timeout_ipending
= 0;
507 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
509 serial_update_irq(s
);
510 if (!(s
->mcr
& UART_MCR_LOOP
)) {
511 /* in loopback mode, don't receive any data */
512 qemu_chr_fe_accept_input(&s
->chr
);
517 if (s
->lcr
& UART_LCR_DLAB
) {
518 ret
= (s
->divider
>> 8) & 0xff;
525 if ((ret
& UART_IIR_ID
) == UART_IIR_THRI
) {
527 serial_update_irq(s
);
538 /* Clear break and overrun interrupts */
539 if (s
->lsr
& (UART_LSR_BI
|UART_LSR_OE
)) {
540 s
->lsr
&= ~(UART_LSR_BI
|UART_LSR_OE
);
541 serial_update_irq(s
);
545 if (s
->mcr
& UART_MCR_LOOP
) {
546 /* in loopback, the modem output pins are connected to the
548 ret
= (s
->mcr
& 0x0c) << 4;
549 ret
|= (s
->mcr
& 0x02) << 3;
550 ret
|= (s
->mcr
& 0x01) << 5;
552 if (s
->poll_msl
>= 0)
553 serial_update_msl(s
);
555 /* Clear delta bits & msr int after read, if they were set */
556 if (s
->msr
& UART_MSR_ANY_DELTA
) {
558 serial_update_irq(s
);
566 trace_serial_ioport_read(addr
, ret
);
570 static int serial_can_receive(SerialState
*s
)
572 //~ fprintf(stderr, "%s:%u\n", __FILE__, __LINE__);
573 if(s
->fcr
& UART_FCR_FE
) {
574 if (s
->recv_fifo
.num
< UART_FIFO_LENGTH
) {
576 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
577 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
578 * effect will be to almost always fill the fifo completely before
579 * the guest has a chance to respond, effectively overriding the ITL
580 * that the guest has set.
582 return (s
->recv_fifo
.num
<= s
->recv_fifo_itl
) ?
583 s
->recv_fifo_itl
- s
->recv_fifo
.num
: 1;
588 return !(s
->lsr
& UART_LSR_DR
);
592 static void serial_receive_break(SerialState
*s
)
595 /* When the LSR_DR is set a null byte is pushed into the fifo */
596 recv_fifo_put(s
, '\0');
597 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
598 serial_update_irq(s
);
601 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
602 static void fifo_timeout_int (void *opaque
) {
603 SerialState
*s
= opaque
;
604 if (s
->recv_fifo
.num
) {
605 s
->timeout_ipending
= 1;
606 serial_update_irq(s
);
610 static int serial_can_receive1(void *opaque
)
612 SerialState
*s
= opaque
;
613 return serial_can_receive(s
);
616 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
618 SerialState
*s
= opaque
;
621 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER
);
623 if(s
->fcr
& UART_FCR_FE
) {
625 for (i
= 0; i
< size
; i
++) {
626 recv_fifo_put(s
, buf
[i
]);
628 s
->lsr
|= UART_LSR_DR
;
629 /* call the timeout receive callback in 4 char transmit time */
630 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
632 if (s
->lsr
& UART_LSR_DR
)
633 s
->lsr
|= UART_LSR_OE
;
635 s
->lsr
|= UART_LSR_DR
;
637 serial_update_irq(s
);
640 static void serial_event(void *opaque
, int event
)
642 SerialState
*s
= opaque
;
643 DPRINTF("event %x\n", event
);
644 if (event
== CHR_EVENT_BREAK
)
645 serial_receive_break(s
);
648 static int serial_pre_save(void *opaque
)
650 SerialState
*s
= opaque
;
651 s
->fcr_vmstate
= s
->fcr
;
656 static int serial_pre_load(void *opaque
)
658 SerialState
*s
= opaque
;
659 s
->thr_ipending
= -1;
664 static int serial_post_load(void *opaque
, int version_id
)
666 SerialState
*s
= opaque
;
668 if (version_id
< 3) {
671 if (s
->thr_ipending
== -1) {
672 s
->thr_ipending
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
675 if (s
->tsr_retry
> 0) {
676 /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */
677 if (s
->lsr
& UART_LSR_TEMT
) {
678 error_report("inconsistent state in serial device "
679 "(tsr empty, tsr_retry=%d", s
->tsr_retry
);
683 if (s
->tsr_retry
> MAX_XMIT_RETRY
) {
684 s
->tsr_retry
= MAX_XMIT_RETRY
;
687 assert(s
->watch_tag
== 0);
688 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
691 /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */
692 if (!(s
->lsr
& UART_LSR_TEMT
)) {
693 error_report("inconsistent state in serial device "
694 "(tsr not empty, tsr_retry=0");
699 s
->last_break_enable
= (s
->lcr
>> 6) & 1;
700 /* Initialize fcr via setter to perform essential side-effects */
701 serial_write_fcr(s
, s
->fcr_vmstate
);
702 serial_update_parameters(s
);
706 static bool serial_thr_ipending_needed(void *opaque
)
708 SerialState
*s
= opaque
;
710 if (s
->ier
& UART_IER_THRI
) {
711 bool expected_value
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
712 return s
->thr_ipending
!= expected_value
;
714 /* LSR.THRE will be sampled again when the interrupt is
715 * enabled. thr_ipending is not used in this case, do
722 static const VMStateDescription vmstate_serial_thr_ipending
= {
723 .name
= "serial/thr_ipending",
725 .minimum_version_id
= 1,
726 .needed
= serial_thr_ipending_needed
,
727 .fields
= (VMStateField
[]) {
728 VMSTATE_INT32(thr_ipending
, SerialState
),
729 VMSTATE_END_OF_LIST()
733 static bool serial_tsr_needed(void *opaque
)
735 SerialState
*s
= (SerialState
*)opaque
;
736 return s
->tsr_retry
!= 0;
739 static const VMStateDescription vmstate_serial_tsr
= {
740 .name
= "serial/tsr",
742 .minimum_version_id
= 1,
743 .needed
= serial_tsr_needed
,
744 .fields
= (VMStateField
[]) {
745 VMSTATE_UINT32(tsr_retry
, SerialState
),
746 VMSTATE_UINT8(thr
, SerialState
),
747 VMSTATE_UINT8(tsr
, SerialState
),
748 VMSTATE_END_OF_LIST()
752 static bool serial_recv_fifo_needed(void *opaque
)
754 SerialState
*s
= (SerialState
*)opaque
;
755 return !fifo8_is_empty(&s
->recv_fifo
);
759 static const VMStateDescription vmstate_serial_recv_fifo
= {
760 .name
= "serial/recv_fifo",
762 .minimum_version_id
= 1,
763 .needed
= serial_recv_fifo_needed
,
764 .fields
= (VMStateField
[]) {
765 VMSTATE_STRUCT(recv_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
766 VMSTATE_END_OF_LIST()
770 static bool serial_xmit_fifo_needed(void *opaque
)
772 SerialState
*s
= (SerialState
*)opaque
;
773 return !fifo8_is_empty(&s
->xmit_fifo
);
776 static const VMStateDescription vmstate_serial_xmit_fifo
= {
777 .name
= "serial/xmit_fifo",
779 .minimum_version_id
= 1,
780 .needed
= serial_xmit_fifo_needed
,
781 .fields
= (VMStateField
[]) {
782 VMSTATE_STRUCT(xmit_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
783 VMSTATE_END_OF_LIST()
787 static bool serial_fifo_timeout_timer_needed(void *opaque
)
789 SerialState
*s
= (SerialState
*)opaque
;
790 return timer_pending(s
->fifo_timeout_timer
);
793 static const VMStateDescription vmstate_serial_fifo_timeout_timer
= {
794 .name
= "serial/fifo_timeout_timer",
796 .minimum_version_id
= 1,
797 .needed
= serial_fifo_timeout_timer_needed
,
798 .fields
= (VMStateField
[]) {
799 VMSTATE_TIMER_PTR(fifo_timeout_timer
, SerialState
),
800 VMSTATE_END_OF_LIST()
804 static bool serial_timeout_ipending_needed(void *opaque
)
806 SerialState
*s
= (SerialState
*)opaque
;
807 return s
->timeout_ipending
!= 0;
810 static const VMStateDescription vmstate_serial_timeout_ipending
= {
811 .name
= "serial/timeout_ipending",
813 .minimum_version_id
= 1,
814 .needed
= serial_timeout_ipending_needed
,
815 .fields
= (VMStateField
[]) {
816 VMSTATE_INT32(timeout_ipending
, SerialState
),
817 VMSTATE_END_OF_LIST()
821 static bool serial_poll_needed(void *opaque
)
823 SerialState
*s
= (SerialState
*)opaque
;
824 return s
->poll_msl
>= 0;
827 static const VMStateDescription vmstate_serial_poll
= {
828 .name
= "serial/poll",
830 .needed
= serial_poll_needed
,
831 .minimum_version_id
= 1,
832 .fields
= (VMStateField
[]) {
833 VMSTATE_INT32(poll_msl
, SerialState
),
834 VMSTATE_TIMER_PTR(modem_status_poll
, SerialState
),
835 VMSTATE_END_OF_LIST()
839 const VMStateDescription vmstate_serial
= {
842 .minimum_version_id
= 2,
843 .pre_save
= serial_pre_save
,
844 .pre_load
= serial_pre_load
,
845 .post_load
= serial_post_load
,
846 .fields
= (VMStateField
[]) {
847 VMSTATE_UINT16_V(divider
, SerialState
, 2),
848 VMSTATE_UINT8(rbr
, SerialState
),
849 VMSTATE_UINT8(ier
, SerialState
),
850 VMSTATE_UINT8(iir
, SerialState
),
851 VMSTATE_UINT8(lcr
, SerialState
),
852 VMSTATE_UINT8(mcr
, SerialState
),
853 VMSTATE_UINT8(lsr
, SerialState
),
854 VMSTATE_UINT8(msr
, SerialState
),
855 VMSTATE_UINT8(scr
, SerialState
),
856 VMSTATE_UINT8_V(fcr_vmstate
, SerialState
, 3),
857 VMSTATE_END_OF_LIST()
859 .subsections
= (const VMStateDescription
*[]) {
860 &vmstate_serial_thr_ipending
,
862 &vmstate_serial_recv_fifo
,
863 &vmstate_serial_xmit_fifo
,
864 &vmstate_serial_fifo_timeout_timer
,
865 &vmstate_serial_timeout_ipending
,
866 &vmstate_serial_poll
,
871 static void serial_reset(void *opaque
)
873 SerialState
*s
= opaque
;
875 if (s
->watch_tag
> 0) {
876 g_source_remove(s
->watch_tag
);
882 s
->iir
= UART_IIR_NO_INT
;
884 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
885 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
887 s
->mcr
= UART_MCR_OUT2
;
890 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ 9600) * 10;
892 serial_update_parameters(s
);
894 s
->timeout_ipending
= 0;
895 timer_del(s
->fifo_timeout_timer
);
896 timer_del(s
->modem_status_poll
);
898 fifo8_reset(&s
->recv_fifo
);
899 fifo8_reset(&s
->xmit_fifo
);
901 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
904 s
->last_break_enable
= 0;
905 qemu_irq_lower(s
->irq
);
907 serial_update_msl(s
);
908 s
->msr
&= ~UART_MSR_ANY_DELTA
;
911 static int serial_be_change(void *opaque
)
913 SerialState
*s
= opaque
;
915 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
916 serial_event
, serial_be_change
, s
, NULL
, true);
918 serial_update_parameters(s
);
920 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
921 &s
->last_break_enable
);
923 s
->poll_msl
= (s
->ier
& UART_IER_MSI
) ? 1 : 0;
924 serial_update_msl(s
);
926 if (s
->poll_msl
>= 0 && !(s
->mcr
& UART_MCR_LOOP
)) {
927 serial_update_tiocm(s
);
930 if (s
->watch_tag
> 0) {
931 g_source_remove(s
->watch_tag
);
932 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
939 void serial_realize_core(SerialState
*s
, Error
**errp
)
941 s
->modem_status_poll
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) serial_update_msl
, s
);
943 s
->fifo_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) fifo_timeout_int
, s
);
944 qemu_register_reset(serial_reset
, s
);
946 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
947 serial_event
, serial_be_change
, s
, NULL
, true);
948 fifo8_create(&s
->recv_fifo
, UART_FIFO_LENGTH
);
949 fifo8_create(&s
->xmit_fifo
, UART_FIFO_LENGTH
);
953 void serial_exit_core(SerialState
*s
)
955 qemu_chr_fe_deinit(&s
->chr
, false);
957 timer_del(s
->modem_status_poll
);
958 timer_free(s
->modem_status_poll
);
960 timer_del(s
->fifo_timeout_timer
);
961 timer_free(s
->fifo_timeout_timer
);
963 fifo8_destroy(&s
->recv_fifo
);
964 fifo8_destroy(&s
->xmit_fifo
);
966 qemu_unregister_reset(serial_reset
, s
);
969 /* Change the main reference oscillator frequency. */
970 void serial_set_frequency(SerialState
*s
, uint32_t frequency
)
972 s
->baudbase
= frequency
;
973 serial_update_parameters(s
);
976 const MemoryRegionOps serial_io_ops
= {
977 .read
= serial_ioport_read
,
978 .write
= serial_ioport_write
,
980 .min_access_size
= 1,
981 .max_access_size
= 1,
983 .endianness
= DEVICE_LITTLE_ENDIAN
,
986 SerialState
*serial_init(int base
, qemu_irq irq
, int baudbase
,
987 Chardev
*chr
, MemoryRegion
*system_io
)
991 s
= g_malloc0(sizeof(SerialState
));
996 s
->baudbase
= baudbase
;
997 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
998 serial_realize_core(s
, &error_fatal
);
1000 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
1002 memory_region_init_io(&s
->io
, NULL
, &serial_io_ops
, s
, "serial", 8);
1003 memory_region_add_subregion(system_io
, base
, &s
->io
);
1008 /* Memory mapped interface */
1009 uint64_t serial_mm_read(void *opaque
, hwaddr addr
,
1012 SerialState
*s
= opaque
;
1013 return serial_ioport_read(s
, (addr
- s
->base
) >> s
->it_shift
, 1);
1016 void serial_mm_write(void *opaque
, hwaddr addr
,
1017 uint64_t value
, unsigned size
)
1019 SerialState
*s
= opaque
;
1021 serial_ioport_write(s
, (addr
- s
->base
) >> s
->it_shift
, value
, 1);
1024 static const MemoryRegionOps serial_mm_ops
[3] = {
1025 [DEVICE_NATIVE_ENDIAN
] = {
1026 .read
= serial_mm_read
,
1027 .write
= serial_mm_write
,
1028 .endianness
= DEVICE_NATIVE_ENDIAN
,
1029 .valid
.max_access_size
= 8,
1030 .impl
.max_access_size
= 8,
1032 [DEVICE_LITTLE_ENDIAN
] = {
1033 .read
= serial_mm_read
,
1034 .write
= serial_mm_write
,
1035 .endianness
= DEVICE_LITTLE_ENDIAN
,
1036 .valid
.max_access_size
= 8,
1037 .impl
.max_access_size
= 8,
1039 [DEVICE_BIG_ENDIAN
] = {
1040 .read
= serial_mm_read
,
1041 .write
= serial_mm_write
,
1042 .endianness
= DEVICE_BIG_ENDIAN
,
1043 .valid
.max_access_size
= 8,
1044 .impl
.max_access_size
= 8,
1048 SerialState
*serial_mm_init(MemoryRegion
*address_space
,
1049 hwaddr base
, int it_shift
,
1050 qemu_irq irq
, int baudbase
,
1051 Chardev
*chr
, enum device_endian end
)
1055 s
= g_malloc0(sizeof(SerialState
));
1058 s
->it_shift
= it_shift
;
1060 s
->baudbase
= baudbase
;
1061 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
1063 serial_realize_core(s
, &error_fatal
);
1064 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
1066 memory_region_init_io(&s
->io
, NULL
, &serial_mm_ops
[end
], s
,
1067 "serial", 8 << it_shift
);
1068 memory_region_add_subregion(address_space
, base
, &s
->io
);