2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31 #include "qemu-timer.h"
42 #define DPRINTF printf
47 /* internal processing - reset HC to try and recover */
48 #define USB_RET_PROCERR (-99)
50 #define MMIO_SIZE 0x1000
52 /* Capability Registers Base Address - section 2.2 */
53 #define CAPREGBASE 0x0000
54 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
55 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
56 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
57 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
58 #define EECP HCCPARAMS + 1
59 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
60 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
62 #define OPREGBASE 0x0020 // Operational Registers Base Address
64 #define USBCMD OPREGBASE + 0x0000
65 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
66 #define USBCMD_HCRESET (1 << 1) // HC Reset
67 #define USBCMD_FLS (3 << 2) // Frame List Size
68 #define USBCMD_FLS_SH 2 // Frame List Size Shift
69 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
70 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
71 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
72 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
73 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
74 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
75 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
76 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
78 #define USBSTS OPREGBASE + 0x0004
79 #define USBSTS_RO_MASK 0x0000003f
80 #define USBSTS_INT (1 << 0) // USB Interrupt
81 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
82 #define USBSTS_PCD (1 << 2) // Port Change Detect
83 #define USBSTS_FLR (1 << 3) // Frame List Rollover
84 #define USBSTS_HSE (1 << 4) // Host System Error
85 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
86 #define USBSTS_HALT (1 << 12) // HC Halted
87 #define USBSTS_REC (1 << 13) // Reclamation
88 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
89 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
92 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
93 * so no need to redefine here.
95 #define USBINTR OPREGBASE + 0x0008
96 #define USBINTR_MASK 0x0000003f
98 #define FRINDEX OPREGBASE + 0x000c
99 #define CTRLDSSEGMENT OPREGBASE + 0x0010
100 #define PERIODICLISTBASE OPREGBASE + 0x0014
101 #define ASYNCLISTADDR OPREGBASE + 0x0018
102 #define ASYNCLISTADDR_MASK 0xffffffe0
104 #define CONFIGFLAG OPREGBASE + 0x0040
106 #define PORTSC (OPREGBASE + 0x0044)
107 #define PORTSC_BEGIN PORTSC
108 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
110 * Bits that are reserved or are read-only are masked out of values
111 * written to us by software
113 #define PORTSC_RO_MASK 0x007001c0
114 #define PORTSC_RWC_MASK 0x0000002a
115 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
116 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
117 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
118 #define PORTSC_PTC (15 << 16) // Port Test Control
119 #define PORTSC_PTC_SH 16 // Port Test Control shift
120 #define PORTSC_PIC (3 << 14) // Port Indicator Control
121 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
122 #define PORTSC_POWNER (1 << 13) // Port Owner
123 #define PORTSC_PPOWER (1 << 12) // Port Power
124 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
125 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
126 #define PORTSC_PRESET (1 << 8) // Port Reset
127 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
128 #define PORTSC_FPRES (1 << 6) // Force Port Resume
129 #define PORTSC_OCC (1 << 5) // Over Current Change
130 #define PORTSC_OCA (1 << 4) // Over Current Active
131 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
132 #define PORTSC_PED (1 << 2) // Port Enable/Disable
133 #define PORTSC_CSC (1 << 1) // Connect Status Change
134 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
136 #define FRAME_TIMER_FREQ 1000
137 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
139 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
140 #define NB_PORTS 6 // Number of downstream ports
141 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
142 #define MAX_QH 100 // Max allowable queue heads in a chain
143 #define MIN_FR_PER_TICK 3 // Min frames to process when catching up
145 /* Internal periodic / asynchronous schedule state machine states
152 /* The following states are internal to the state machine function
166 /* macros for accessing fields within next link pointer entry */
167 #define NLPTR_GET(x) ((x) & 0xffffffe0)
168 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
169 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
171 /* link pointer types */
172 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
173 #define NLPTR_TYPE_QH 1 // queue head
174 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
175 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
178 /* EHCI spec version 1.0 Section 3.3
180 typedef struct EHCIitd
{
183 uint32_t transact
[8];
184 #define ITD_XACT_ACTIVE (1 << 31)
185 #define ITD_XACT_DBERROR (1 << 30)
186 #define ITD_XACT_BABBLE (1 << 29)
187 #define ITD_XACT_XACTERR (1 << 28)
188 #define ITD_XACT_LENGTH_MASK 0x0fff0000
189 #define ITD_XACT_LENGTH_SH 16
190 #define ITD_XACT_IOC (1 << 15)
191 #define ITD_XACT_PGSEL_MASK 0x00007000
192 #define ITD_XACT_PGSEL_SH 12
193 #define ITD_XACT_OFFSET_MASK 0x00000fff
196 #define ITD_BUFPTR_MASK 0xfffff000
197 #define ITD_BUFPTR_SH 12
198 #define ITD_BUFPTR_EP_MASK 0x00000f00
199 #define ITD_BUFPTR_EP_SH 8
200 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
201 #define ITD_BUFPTR_DEVADDR_SH 0
202 #define ITD_BUFPTR_DIRECTION (1 << 11)
203 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
204 #define ITD_BUFPTR_MAXPKT_SH 0
205 #define ITD_BUFPTR_MULT_MASK 0x00000003
206 #define ITD_BUFPTR_MULT_SH 0
209 /* EHCI spec version 1.0 Section 3.4
211 typedef struct EHCIsitd
{
212 uint32_t next
; // Standard next link pointer
214 #define SITD_EPCHAR_IO (1 << 31)
215 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
216 #define SITD_EPCHAR_PORTNUM_SH 24
217 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
218 #define SITD_EPCHAR_HUBADDR_SH 16
219 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
220 #define SITD_EPCHAR_EPNUM_SH 8
221 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
224 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
225 #define SITD_UFRAME_CMASK_SH 8
226 #define SITD_UFRAME_SMASK_MASK 0x000000ff
229 #define SITD_RESULTS_IOC (1 << 31)
230 #define SITD_RESULTS_PGSEL (1 << 30)
231 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
232 #define SITD_RESULTS_TYBYTES_SH 16
233 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
234 #define SITD_RESULTS_CPROGMASK_SH 8
235 #define SITD_RESULTS_ACTIVE (1 << 7)
236 #define SITD_RESULTS_ERR (1 << 6)
237 #define SITD_RESULTS_DBERR (1 << 5)
238 #define SITD_RESULTS_BABBLE (1 << 4)
239 #define SITD_RESULTS_XACTERR (1 << 3)
240 #define SITD_RESULTS_MISSEDUF (1 << 2)
241 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
244 #define SITD_BUFPTR_MASK 0xfffff000
245 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
246 #define SITD_BUFPTR_TPOS_MASK 0x00000018
247 #define SITD_BUFPTR_TPOS_SH 3
248 #define SITD_BUFPTR_TCNT_MASK 0x00000007
250 uint32_t backptr
; // Standard next link pointer
253 /* EHCI spec version 1.0 Section 3.5
255 typedef struct EHCIqtd
{
256 uint32_t next
; // Standard next link pointer
257 uint32_t altnext
; // Standard next link pointer
259 #define QTD_TOKEN_DTOGGLE (1 << 31)
260 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
261 #define QTD_TOKEN_TBYTES_SH 16
262 #define QTD_TOKEN_IOC (1 << 15)
263 #define QTD_TOKEN_CPAGE_MASK 0x00007000
264 #define QTD_TOKEN_CPAGE_SH 12
265 #define QTD_TOKEN_CERR_MASK 0x00000c00
266 #define QTD_TOKEN_CERR_SH 10
267 #define QTD_TOKEN_PID_MASK 0x00000300
268 #define QTD_TOKEN_PID_SH 8
269 #define QTD_TOKEN_ACTIVE (1 << 7)
270 #define QTD_TOKEN_HALT (1 << 6)
271 #define QTD_TOKEN_DBERR (1 << 5)
272 #define QTD_TOKEN_BABBLE (1 << 4)
273 #define QTD_TOKEN_XACTERR (1 << 3)
274 #define QTD_TOKEN_MISSEDUF (1 << 2)
275 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
276 #define QTD_TOKEN_PING (1 << 0)
278 uint32_t bufptr
[5]; // Standard buffer pointer
279 #define QTD_BUFPTR_MASK 0xfffff000
280 #define QTD_BUFPTR_SH 12
283 /* EHCI spec version 1.0 Section 3.6
285 typedef struct EHCIqh
{
286 uint32_t next
; // Standard next link pointer
288 /* endpoint characteristics */
290 #define QH_EPCHAR_RL_MASK 0xf0000000
291 #define QH_EPCHAR_RL_SH 28
292 #define QH_EPCHAR_C (1 << 27)
293 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
294 #define QH_EPCHAR_MPLEN_SH 16
295 #define QH_EPCHAR_H (1 << 15)
296 #define QH_EPCHAR_DTC (1 << 14)
297 #define QH_EPCHAR_EPS_MASK 0x00003000
298 #define QH_EPCHAR_EPS_SH 12
299 #define EHCI_QH_EPS_FULL 0
300 #define EHCI_QH_EPS_LOW 1
301 #define EHCI_QH_EPS_HIGH 2
302 #define EHCI_QH_EPS_RESERVED 3
304 #define QH_EPCHAR_EP_MASK 0x00000f00
305 #define QH_EPCHAR_EP_SH 8
306 #define QH_EPCHAR_I (1 << 7)
307 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
308 #define QH_EPCHAR_DEVADDR_SH 0
310 /* endpoint capabilities */
312 #define QH_EPCAP_MULT_MASK 0xc0000000
313 #define QH_EPCAP_MULT_SH 30
314 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
315 #define QH_EPCAP_PORTNUM_SH 23
316 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
317 #define QH_EPCAP_HUBADDR_SH 16
318 #define QH_EPCAP_CMASK_MASK 0x0000ff00
319 #define QH_EPCAP_CMASK_SH 8
320 #define QH_EPCAP_SMASK_MASK 0x000000ff
321 #define QH_EPCAP_SMASK_SH 0
323 uint32_t current_qtd
; // Standard next link pointer
324 uint32_t next_qtd
; // Standard next link pointer
325 uint32_t altnext_qtd
;
326 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
327 #define QH_ALTNEXT_NAKCNT_SH 1
329 uint32_t token
; // Same as QTD token
330 uint32_t bufptr
[5]; // Standard buffer pointer
331 #define BUFPTR_CPROGMASK_MASK 0x000000ff
332 #define BUFPTR_FRAMETAG_MASK 0x0000001f
333 #define BUFPTR_SBYTES_MASK 0x00000fe0
334 #define BUFPTR_SBYTES_SH 5
337 /* EHCI spec version 1.0 Section 3.7
339 typedef struct EHCIfstn
{
340 uint32_t next
; // Standard next link pointer
341 uint32_t backptr
; // Standard next link pointer
344 typedef struct EHCIPacket EHCIPacket
;
345 typedef struct EHCIQueue EHCIQueue
;
346 typedef struct EHCIState EHCIState
;
350 EHCI_ASYNC_INITIALIZED
,
357 QTAILQ_ENTRY(EHCIPacket
) next
;
359 EHCIqtd qtd
; /* copy of current QTD (being worked on) */
360 uint32_t qtdaddr
; /* address QTD read from */
365 enum async_state async
;
371 QTAILQ_ENTRY(EHCIQueue
) next
;
377 /* cached data from guest - needs to be flushed
378 * when guest removes an entry (doorbell, handshake sequence)
380 EHCIqh qh
; /* copy of current QH (being worked on) */
381 uint32_t qhaddr
; /* address QH read from */
382 uint32_t qtdaddr
; /* address QTD read from */
384 QTAILQ_HEAD(, EHCIPacket
) packets
;
387 typedef QTAILQ_HEAD(EHCIQueueHead
, EHCIQueue
) EHCIQueueHead
;
394 MemoryRegion mem_caps
;
395 MemoryRegion mem_opreg
;
396 MemoryRegion mem_ports
;
403 * EHCI spec version 1.0 Section 2.3
404 * Host Controller Operational Registers
406 uint8_t caps
[OPREGBASE
];
408 uint32_t opreg
[(PORTSC_BEGIN
-OPREGBASE
)/sizeof(uint32_t)];
414 uint32_t ctrldssegment
;
415 uint32_t periodiclistbase
;
416 uint32_t asynclistaddr
;
421 uint32_t portsc
[NB_PORTS
];
424 * Internal states, shadow registers, etc
426 QEMUTimer
*frame_timer
;
428 uint32_t astate
; /* Current state in asynchronous schedule */
429 uint32_t pstate
; /* Current state in periodic schedule */
430 USBPort ports
[NB_PORTS
];
431 USBPort
*companion_ports
[NB_PORTS
];
432 uint32_t usbsts_pending
;
433 uint32_t usbsts_frindex
;
434 EHCIQueueHead aqueues
;
435 EHCIQueueHead pqueues
;
437 /* which address to look at next */
438 uint32_t a_fetch_addr
;
439 uint32_t p_fetch_addr
;
444 uint64_t last_run_ns
;
445 uint32_t async_stepdown
;
448 #define SET_LAST_RUN_CLOCK(s) \
449 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
451 /* nifty macros from Arnon's EHCI version */
452 #define get_field(data, field) \
453 (((data) & field##_MASK) >> field##_SH)
455 #define set_field(data, newval, field) do { \
456 uint32_t val = *data; \
457 val &= ~ field##_MASK; \
458 val |= ((newval) << field##_SH) & field##_MASK; \
462 static const char *ehci_state_names
[] = {
463 [EST_INACTIVE
] = "INACTIVE",
464 [EST_ACTIVE
] = "ACTIVE",
465 [EST_EXECUTING
] = "EXECUTING",
466 [EST_SLEEPING
] = "SLEEPING",
467 [EST_WAITLISTHEAD
] = "WAITLISTHEAD",
468 [EST_FETCHENTRY
] = "FETCH ENTRY",
469 [EST_FETCHQH
] = "FETCH QH",
470 [EST_FETCHITD
] = "FETCH ITD",
471 [EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
472 [EST_FETCHQTD
] = "FETCH QTD",
473 [EST_EXECUTE
] = "EXECUTE",
474 [EST_WRITEBACK
] = "WRITEBACK",
475 [EST_HORIZONTALQH
] = "HORIZONTALQH",
478 static const char *ehci_mmio_names
[] = {
481 [USBINTR
] = "USBINTR",
482 [FRINDEX
] = "FRINDEX",
483 [PERIODICLISTBASE
] = "P-LIST BASE",
484 [ASYNCLISTADDR
] = "A-LIST ADDR",
485 [CONFIGFLAG
] = "CONFIGFLAG",
488 static int ehci_state_executing(EHCIQueue
*q
);
489 static int ehci_state_writeback(EHCIQueue
*q
);
491 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
493 if (nr
< len
&& n
[nr
] != NULL
) {
500 static const char *state2str(uint32_t state
)
502 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
505 static const char *addr2str(hwaddr addr
)
507 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
),
511 static void ehci_trace_usbsts(uint32_t mask
, int state
)
514 if (mask
& USBSTS_INT
) {
515 trace_usb_ehci_usbsts("INT", state
);
517 if (mask
& USBSTS_ERRINT
) {
518 trace_usb_ehci_usbsts("ERRINT", state
);
520 if (mask
& USBSTS_PCD
) {
521 trace_usb_ehci_usbsts("PCD", state
);
523 if (mask
& USBSTS_FLR
) {
524 trace_usb_ehci_usbsts("FLR", state
);
526 if (mask
& USBSTS_HSE
) {
527 trace_usb_ehci_usbsts("HSE", state
);
529 if (mask
& USBSTS_IAA
) {
530 trace_usb_ehci_usbsts("IAA", state
);
534 if (mask
& USBSTS_HALT
) {
535 trace_usb_ehci_usbsts("HALT", state
);
537 if (mask
& USBSTS_REC
) {
538 trace_usb_ehci_usbsts("REC", state
);
540 if (mask
& USBSTS_PSS
) {
541 trace_usb_ehci_usbsts("PSS", state
);
543 if (mask
& USBSTS_ASS
) {
544 trace_usb_ehci_usbsts("ASS", state
);
548 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
550 if ((s
->usbsts
& mask
) == mask
) {
553 ehci_trace_usbsts(mask
, 1);
557 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
559 if ((s
->usbsts
& mask
) == 0) {
562 ehci_trace_usbsts(mask
, 0);
566 /* update irq line */
567 static inline void ehci_update_irq(EHCIState
*s
)
571 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
575 trace_usb_ehci_irq(level
, s
->frindex
, s
->usbsts
, s
->usbintr
);
576 qemu_set_irq(s
->irq
, level
);
579 /* flag interrupt condition */
580 static inline void ehci_raise_irq(EHCIState
*s
, int intr
)
582 if (intr
& (USBSTS_PCD
| USBSTS_FLR
| USBSTS_HSE
)) {
586 s
->usbsts_pending
|= intr
;
591 * Commit pending interrupts (added via ehci_raise_irq),
592 * at the rate allowed by "Interrupt Threshold Control".
594 static inline void ehci_commit_irq(EHCIState
*s
)
598 if (!s
->usbsts_pending
) {
601 if (s
->usbsts_frindex
> s
->frindex
) {
605 itc
= (s
->usbcmd
>> 16) & 0xff;
606 s
->usbsts
|= s
->usbsts_pending
;
607 s
->usbsts_pending
= 0;
608 s
->usbsts_frindex
= s
->frindex
+ itc
;
612 static void ehci_update_halt(EHCIState
*s
)
614 if (s
->usbcmd
& USBCMD_RUNSTOP
) {
615 ehci_clear_usbsts(s
, USBSTS_HALT
);
617 if (s
->astate
== EST_INACTIVE
&& s
->pstate
== EST_INACTIVE
) {
618 ehci_set_usbsts(s
, USBSTS_HALT
);
623 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
626 trace_usb_ehci_state("async", state2str(state
));
628 if (s
->astate
== EST_INACTIVE
) {
629 ehci_clear_usbsts(s
, USBSTS_ASS
);
632 ehci_set_usbsts(s
, USBSTS_ASS
);
635 trace_usb_ehci_state("periodic", state2str(state
));
637 if (s
->pstate
== EST_INACTIVE
) {
638 ehci_clear_usbsts(s
, USBSTS_PSS
);
641 ehci_set_usbsts(s
, USBSTS_PSS
);
646 static int ehci_get_state(EHCIState
*s
, int async
)
648 return async
? s
->astate
: s
->pstate
;
651 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
654 s
->a_fetch_addr
= addr
;
656 s
->p_fetch_addr
= addr
;
660 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
662 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
665 static void ehci_trace_qh(EHCIQueue
*q
, hwaddr addr
, EHCIqh
*qh
)
667 /* need three here due to argument count limits */
668 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
669 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
670 trace_usb_ehci_qh_fields(addr
,
671 get_field(qh
->epchar
, QH_EPCHAR_RL
),
672 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
673 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
674 get_field(qh
->epchar
, QH_EPCHAR_EP
),
675 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
676 trace_usb_ehci_qh_bits(addr
,
677 (bool)(qh
->epchar
& QH_EPCHAR_C
),
678 (bool)(qh
->epchar
& QH_EPCHAR_H
),
679 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
680 (bool)(qh
->epchar
& QH_EPCHAR_I
));
683 static void ehci_trace_qtd(EHCIQueue
*q
, hwaddr addr
, EHCIqtd
*qtd
)
685 /* need three here due to argument count limits */
686 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
687 trace_usb_ehci_qtd_fields(addr
,
688 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
689 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
690 get_field(qtd
->token
, QTD_TOKEN_CERR
),
691 get_field(qtd
->token
, QTD_TOKEN_PID
));
692 trace_usb_ehci_qtd_bits(addr
,
693 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
694 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
695 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
696 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
697 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
700 static void ehci_trace_itd(EHCIState
*s
, hwaddr addr
, EHCIitd
*itd
)
702 trace_usb_ehci_itd(addr
, itd
->next
,
703 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
704 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
705 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
706 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
709 static void ehci_trace_sitd(EHCIState
*s
, hwaddr addr
,
712 trace_usb_ehci_sitd(addr
, sitd
->next
,
713 (bool)(sitd
->results
& SITD_RESULTS_ACTIVE
));
716 static void ehci_trace_guest_bug(EHCIState
*s
, const char *message
)
718 trace_usb_ehci_guest_bug(message
);
719 fprintf(stderr
, "ehci warning: %s\n", message
);
722 static inline bool ehci_enabled(EHCIState
*s
)
724 return s
->usbcmd
& USBCMD_RUNSTOP
;
727 static inline bool ehci_async_enabled(EHCIState
*s
)
729 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_ASE
);
732 static inline bool ehci_periodic_enabled(EHCIState
*s
)
734 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_PSE
);
737 /* packet management */
739 static EHCIPacket
*ehci_alloc_packet(EHCIQueue
*q
)
743 p
= g_new0(EHCIPacket
, 1);
745 usb_packet_init(&p
->packet
);
746 QTAILQ_INSERT_TAIL(&q
->packets
, p
, next
);
747 trace_usb_ehci_packet_action(p
->queue
, p
, "alloc");
751 static void ehci_free_packet(EHCIPacket
*p
)
753 if (p
->async
== EHCI_ASYNC_FINISHED
) {
754 int state
= ehci_get_state(p
->queue
->ehci
, p
->queue
->async
);
755 /* This is a normal, but rare condition (cancel racing completion) */
756 fprintf(stderr
, "EHCI: Warning packet completed but not processed\n");
757 ehci_state_executing(p
->queue
);
758 ehci_state_writeback(p
->queue
);
759 ehci_set_state(p
->queue
->ehci
, p
->queue
->async
, state
);
760 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
763 trace_usb_ehci_packet_action(p
->queue
, p
, "free");
764 if (p
->async
== EHCI_ASYNC_INITIALIZED
) {
765 usb_packet_unmap(&p
->packet
, &p
->sgl
);
766 qemu_sglist_destroy(&p
->sgl
);
768 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
769 usb_cancel_packet(&p
->packet
);
770 usb_packet_unmap(&p
->packet
, &p
->sgl
);
771 qemu_sglist_destroy(&p
->sgl
);
773 QTAILQ_REMOVE(&p
->queue
->packets
, p
, next
);
774 usb_packet_cleanup(&p
->packet
);
778 /* queue management */
780 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, uint32_t addr
, int async
)
782 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
785 q
= g_malloc0(sizeof(*q
));
789 QTAILQ_INIT(&q
->packets
);
790 QTAILQ_INSERT_HEAD(head
, q
, next
);
791 trace_usb_ehci_queue_action(q
, "alloc");
795 static int ehci_cancel_queue(EHCIQueue
*q
)
800 p
= QTAILQ_FIRST(&q
->packets
);
805 trace_usb_ehci_queue_action(q
, "cancel");
809 } while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
);
813 static int ehci_reset_queue(EHCIQueue
*q
)
817 trace_usb_ehci_queue_action(q
, "reset");
818 packets
= ehci_cancel_queue(q
);
824 static void ehci_free_queue(EHCIQueue
*q
, const char *warn
)
826 EHCIQueueHead
*head
= q
->async
? &q
->ehci
->aqueues
: &q
->ehci
->pqueues
;
829 trace_usb_ehci_queue_action(q
, "free");
830 cancelled
= ehci_cancel_queue(q
);
831 if (warn
&& cancelled
> 0) {
832 ehci_trace_guest_bug(q
->ehci
, warn
);
834 QTAILQ_REMOVE(head
, q
, next
);
838 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
,
841 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
844 QTAILQ_FOREACH(q
, head
, next
) {
845 if (addr
== q
->qhaddr
) {
852 static void ehci_queues_rip_unused(EHCIState
*ehci
, int async
)
854 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
855 const char *warn
= async
? "guest unlinked busy QH" : NULL
;
856 uint64_t maxage
= FRAME_TIMER_NS
* ehci
->maxframes
* 4;
859 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
862 q
->ts
= ehci
->last_run_ns
;
865 if (ehci
->last_run_ns
< q
->ts
+ maxage
) {
868 ehci_free_queue(q
, warn
);
872 static void ehci_queues_rip_unseen(EHCIState
*ehci
, int async
)
874 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
877 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
879 ehci_free_queue(q
, NULL
);
884 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
, int async
)
886 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
889 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
893 ehci_free_queue(q
, NULL
);
897 static void ehci_queues_rip_all(EHCIState
*ehci
, int async
)
899 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
900 const char *warn
= async
? "guest stopped busy async schedule" : NULL
;
903 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
904 ehci_free_queue(q
, warn
);
908 /* Attach or detach a device on root hub */
910 static void ehci_attach(USBPort
*port
)
912 EHCIState
*s
= port
->opaque
;
913 uint32_t *portsc
= &s
->portsc
[port
->index
];
914 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
916 trace_usb_ehci_port_attach(port
->index
, owner
, port
->dev
->product_desc
);
918 if (*portsc
& PORTSC_POWNER
) {
919 USBPort
*companion
= s
->companion_ports
[port
->index
];
920 companion
->dev
= port
->dev
;
921 companion
->ops
->attach(companion
);
925 *portsc
|= PORTSC_CONNECT
;
926 *portsc
|= PORTSC_CSC
;
928 ehci_raise_irq(s
, USBSTS_PCD
);
932 static void ehci_detach(USBPort
*port
)
934 EHCIState
*s
= port
->opaque
;
935 uint32_t *portsc
= &s
->portsc
[port
->index
];
936 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
938 trace_usb_ehci_port_detach(port
->index
, owner
);
940 if (*portsc
& PORTSC_POWNER
) {
941 USBPort
*companion
= s
->companion_ports
[port
->index
];
942 companion
->ops
->detach(companion
);
943 companion
->dev
= NULL
;
945 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
946 * the port ownership is returned immediately to the EHCI controller."
948 *portsc
&= ~PORTSC_POWNER
;
952 ehci_queues_rip_device(s
, port
->dev
, 0);
953 ehci_queues_rip_device(s
, port
->dev
, 1);
955 *portsc
&= ~(PORTSC_CONNECT
|PORTSC_PED
);
956 *portsc
|= PORTSC_CSC
;
958 ehci_raise_irq(s
, USBSTS_PCD
);
962 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
964 EHCIState
*s
= port
->opaque
;
965 uint32_t portsc
= s
->portsc
[port
->index
];
967 if (portsc
& PORTSC_POWNER
) {
968 USBPort
*companion
= s
->companion_ports
[port
->index
];
969 companion
->ops
->child_detach(companion
, child
);
973 ehci_queues_rip_device(s
, child
, 0);
974 ehci_queues_rip_device(s
, child
, 1);
977 static void ehci_wakeup(USBPort
*port
)
979 EHCIState
*s
= port
->opaque
;
980 uint32_t portsc
= s
->portsc
[port
->index
];
982 if (portsc
& PORTSC_POWNER
) {
983 USBPort
*companion
= s
->companion_ports
[port
->index
];
984 if (companion
->ops
->wakeup
) {
985 companion
->ops
->wakeup(companion
);
990 qemu_bh_schedule(s
->async_bh
);
993 static int ehci_register_companion(USBBus
*bus
, USBPort
*ports
[],
994 uint32_t portcount
, uint32_t firstport
)
996 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
999 if (firstport
+ portcount
> NB_PORTS
) {
1000 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "firstport",
1001 "firstport on masterbus");
1002 error_printf_unless_qmp(
1003 "firstport value of %u makes companion take ports %u - %u, which "
1004 "is outside of the valid range of 0 - %u\n", firstport
, firstport
,
1005 firstport
+ portcount
- 1, NB_PORTS
- 1);
1009 for (i
= 0; i
< portcount
; i
++) {
1010 if (s
->companion_ports
[firstport
+ i
]) {
1011 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "masterbus",
1012 "an USB masterbus");
1013 error_printf_unless_qmp(
1014 "port %u on masterbus %s already has a companion assigned\n",
1015 firstport
+ i
, bus
->qbus
.name
);
1020 for (i
= 0; i
< portcount
; i
++) {
1021 s
->companion_ports
[firstport
+ i
] = ports
[i
];
1022 s
->ports
[firstport
+ i
].speedmask
|=
1023 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
;
1024 /* Ensure devs attached before the initial reset go to the companion */
1025 s
->portsc
[firstport
+ i
] = PORTSC_POWNER
;
1028 s
->companion_count
++;
1029 s
->caps
[0x05] = (s
->companion_count
<< 4) | portcount
;
1034 static USBDevice
*ehci_find_device(EHCIState
*ehci
, uint8_t addr
)
1040 for (i
= 0; i
< NB_PORTS
; i
++) {
1041 port
= &ehci
->ports
[i
];
1042 if (!(ehci
->portsc
[i
] & PORTSC_PED
)) {
1043 DPRINTF("Port %d not enabled\n", i
);
1046 dev
= usb_find_device(port
, addr
);
1054 /* 4.1 host controller initialization */
1055 static void ehci_reset(void *opaque
)
1057 EHCIState
*s
= opaque
;
1059 USBDevice
*devs
[NB_PORTS
];
1061 trace_usb_ehci_reset();
1064 * Do the detach before touching portsc, so that it correctly gets send to
1065 * us or to our companion based on PORTSC_POWNER before the reset.
1067 for(i
= 0; i
< NB_PORTS
; i
++) {
1068 devs
[i
] = s
->ports
[i
].dev
;
1069 if (devs
[i
] && devs
[i
]->attached
) {
1070 usb_detach(&s
->ports
[i
]);
1074 memset(&s
->opreg
, 0x00, sizeof(s
->opreg
));
1075 memset(&s
->portsc
, 0x00, sizeof(s
->portsc
));
1077 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
1078 s
->usbsts
= USBSTS_HALT
;
1079 s
->usbsts_pending
= 0;
1080 s
->usbsts_frindex
= 0;
1082 s
->astate
= EST_INACTIVE
;
1083 s
->pstate
= EST_INACTIVE
;
1085 for(i
= 0; i
< NB_PORTS
; i
++) {
1086 if (s
->companion_ports
[i
]) {
1087 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
1089 s
->portsc
[i
] = PORTSC_PPOWER
;
1091 if (devs
[i
] && devs
[i
]->attached
) {
1092 usb_attach(&s
->ports
[i
]);
1093 usb_device_reset(devs
[i
]);
1096 ehci_queues_rip_all(s
, 0);
1097 ehci_queues_rip_all(s
, 1);
1098 qemu_del_timer(s
->frame_timer
);
1099 qemu_bh_cancel(s
->async_bh
);
1102 static uint64_t ehci_caps_read(void *ptr
, hwaddr addr
,
1106 return s
->caps
[addr
];
1109 static uint64_t ehci_opreg_read(void *ptr
, hwaddr addr
,
1115 val
= s
->opreg
[addr
>> 2];
1116 trace_usb_ehci_opreg_read(addr
+ OPREGBASE
, addr2str(addr
), val
);
1120 static uint64_t ehci_port_read(void *ptr
, hwaddr addr
,
1126 val
= s
->portsc
[addr
>> 2];
1127 trace_usb_ehci_portsc_read(addr
+ PORTSC_BEGIN
, addr
>> 2, val
);
1131 static void handle_port_owner_write(EHCIState
*s
, int port
, uint32_t owner
)
1133 USBDevice
*dev
= s
->ports
[port
].dev
;
1134 uint32_t *portsc
= &s
->portsc
[port
];
1137 if (s
->companion_ports
[port
] == NULL
)
1140 owner
= owner
& PORTSC_POWNER
;
1141 orig
= *portsc
& PORTSC_POWNER
;
1143 if (!(owner
^ orig
)) {
1147 if (dev
&& dev
->attached
) {
1148 usb_detach(&s
->ports
[port
]);
1151 *portsc
&= ~PORTSC_POWNER
;
1154 if (dev
&& dev
->attached
) {
1155 usb_attach(&s
->ports
[port
]);
1159 static void ehci_port_write(void *ptr
, hwaddr addr
,
1160 uint64_t val
, unsigned size
)
1163 int port
= addr
>> 2;
1164 uint32_t *portsc
= &s
->portsc
[port
];
1165 uint32_t old
= *portsc
;
1166 USBDevice
*dev
= s
->ports
[port
].dev
;
1168 trace_usb_ehci_portsc_write(addr
+ PORTSC_BEGIN
, addr
>> 2, val
);
1170 /* Clear rwc bits */
1171 *portsc
&= ~(val
& PORTSC_RWC_MASK
);
1172 /* The guest may clear, but not set the PED bit */
1173 *portsc
&= val
| ~PORTSC_PED
;
1174 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1175 handle_port_owner_write(s
, port
, val
);
1176 /* And finally apply RO_MASK */
1177 val
&= PORTSC_RO_MASK
;
1179 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
1180 trace_usb_ehci_port_reset(port
, 1);
1183 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
1184 trace_usb_ehci_port_reset(port
, 0);
1185 if (dev
&& dev
->attached
) {
1186 usb_port_reset(&s
->ports
[port
]);
1187 *portsc
&= ~PORTSC_CSC
;
1191 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1192 * to SW that this port has a high speed device attached
1194 if (dev
&& dev
->attached
&& (dev
->speedmask
& USB_SPEED_MASK_HIGH
)) {
1199 *portsc
&= ~PORTSC_RO_MASK
;
1201 trace_usb_ehci_portsc_change(addr
+ PORTSC_BEGIN
, addr
>> 2, *portsc
, old
);
1204 static void ehci_opreg_write(void *ptr
, hwaddr addr
,
1205 uint64_t val
, unsigned size
)
1208 uint32_t *mmio
= s
->opreg
+ (addr
>> 2);
1209 uint32_t old
= *mmio
;
1212 trace_usb_ehci_opreg_write(addr
+ OPREGBASE
, addr2str(addr
), val
);
1214 switch (addr
+ OPREGBASE
) {
1216 if (val
& USBCMD_HCRESET
) {
1222 /* not supporting dynamic frame list size at the moment */
1223 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
1224 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
1225 (int)val
& USBCMD_FLS
);
1229 if (val
& USBCMD_IAAD
) {
1231 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1232 * trigger and re-use a qh without us seeing the unlink.
1234 s
->async_stepdown
= 0;
1235 qemu_bh_schedule(s
->async_bh
);
1236 trace_usb_ehci_doorbell_ring();
1239 if (((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & val
) !=
1240 ((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & s
->usbcmd
)) {
1241 if (s
->pstate
== EST_INACTIVE
) {
1242 SET_LAST_RUN_CLOCK(s
);
1244 s
->usbcmd
= val
; /* Set usbcmd for ehci_update_halt() */
1245 ehci_update_halt(s
);
1246 s
->async_stepdown
= 0;
1247 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
1252 val
&= USBSTS_RO_MASK
; // bits 6 through 31 are RO
1253 ehci_clear_usbsts(s
, val
); // bits 0 through 5 are R/WC
1259 val
&= USBINTR_MASK
;
1263 val
&= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1269 for(i
= 0; i
< NB_PORTS
; i
++)
1270 handle_port_owner_write(s
, i
, 0);
1274 case PERIODICLISTBASE
:
1275 if (ehci_periodic_enabled(s
)) {
1277 "ehci: PERIODIC list base register set while periodic schedule\n"
1278 " is enabled and HC is enabled\n");
1283 if (ehci_async_enabled(s
)) {
1285 "ehci: ASYNC list address register set while async schedule\n"
1286 " is enabled and HC is enabled\n");
1292 trace_usb_ehci_opreg_change(addr
+ OPREGBASE
, addr2str(addr
), *mmio
, old
);
1296 // TODO : Put in common header file, duplication from usb-ohci.c
1298 /* Get an array of dwords from main memory */
1299 static inline int get_dwords(EHCIState
*ehci
, uint32_t addr
,
1300 uint32_t *buf
, int num
)
1304 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1305 pci_dma_read(&ehci
->dev
, addr
, buf
, sizeof(*buf
));
1306 *buf
= le32_to_cpu(*buf
);
1312 /* Put an array of dwords in to main memory */
1313 static inline int put_dwords(EHCIState
*ehci
, uint32_t addr
,
1314 uint32_t *buf
, int num
)
1318 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1319 uint32_t tmp
= cpu_to_le32(*buf
);
1320 pci_dma_write(&ehci
->dev
, addr
, &tmp
, sizeof(tmp
));
1327 * Write the qh back to guest physical memory. This step isn't
1328 * in the EHCI spec but we need to do it since we don't share
1329 * physical memory with our guest VM.
1331 * The first three dwords are read-only for the EHCI, so skip them
1332 * when writing back the qh.
1334 static void ehci_flush_qh(EHCIQueue
*q
)
1336 uint32_t *qh
= (uint32_t *) &q
->qh
;
1337 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1338 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1340 put_dwords(q
->ehci
, addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1345 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1347 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1355 assert(p
->qtdaddr
== q
->qtdaddr
);
1357 // remember values in fields to preserve in qh after overlay
1359 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1360 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1362 q
->qh
.current_qtd
= p
->qtdaddr
;
1363 q
->qh
.next_qtd
= p
->qtd
.next
;
1364 q
->qh
.altnext_qtd
= p
->qtd
.altnext
;
1365 q
->qh
.token
= p
->qtd
.token
;
1368 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1369 if (eps
== EHCI_QH_EPS_HIGH
) {
1370 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1371 q
->qh
.token
|= ping
;
1374 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1375 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1377 for (i
= 0; i
< 5; i
++) {
1378 q
->qh
.bufptr
[i
] = p
->qtd
.bufptr
[i
];
1381 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1382 // preserve QH DT bit
1383 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1384 q
->qh
.token
|= dtoggle
;
1387 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1388 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1395 static int ehci_init_transfer(EHCIPacket
*p
)
1397 uint32_t cpage
, offset
, bytes
, plen
;
1400 cpage
= get_field(p
->qtd
.token
, QTD_TOKEN_CPAGE
);
1401 bytes
= get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
);
1402 offset
= p
->qtd
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1403 pci_dma_sglist_init(&p
->sgl
, &p
->queue
->ehci
->dev
, 5);
1407 fprintf(stderr
, "cpage out of range (%d)\n", cpage
);
1408 return USB_RET_PROCERR
;
1411 page
= p
->qtd
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1414 if (plen
> 4096 - offset
) {
1415 plen
= 4096 - offset
;
1420 qemu_sglist_add(&p
->sgl
, page
, plen
);
1426 static void ehci_finish_transfer(EHCIQueue
*q
, int status
)
1428 uint32_t cpage
, offset
;
1431 /* update cpage & offset */
1432 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1433 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1436 cpage
+= offset
>> QTD_BUFPTR_SH
;
1437 offset
&= ~QTD_BUFPTR_MASK
;
1439 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1440 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1441 q
->qh
.bufptr
[0] |= offset
;
1445 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1448 EHCIState
*s
= port
->opaque
;
1449 uint32_t portsc
= s
->portsc
[port
->index
];
1451 if (portsc
& PORTSC_POWNER
) {
1452 USBPort
*companion
= s
->companion_ports
[port
->index
];
1453 companion
->ops
->complete(companion
, packet
);
1457 p
= container_of(packet
, EHCIPacket
, packet
);
1458 trace_usb_ehci_packet_action(p
->queue
, p
, "wakeup");
1459 assert(p
->async
== EHCI_ASYNC_INFLIGHT
);
1460 p
->async
= EHCI_ASYNC_FINISHED
;
1461 p
->usb_status
= packet
->result
;
1463 if (p
->queue
->async
) {
1464 qemu_bh_schedule(p
->queue
->ehci
->async_bh
);
1468 static void ehci_execute_complete(EHCIQueue
*q
)
1470 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1473 assert(p
->qtdaddr
== q
->qtdaddr
);
1474 assert(p
->async
== EHCI_ASYNC_INITIALIZED
||
1475 p
->async
== EHCI_ASYNC_FINISHED
);
1477 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1478 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->usb_status
);
1480 if (p
->usb_status
< 0) {
1481 switch (p
->usb_status
) {
1482 case USB_RET_IOERROR
:
1484 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1485 set_field(&q
->qh
.token
, 0, QTD_TOKEN_CERR
);
1486 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1489 q
->qh
.token
|= QTD_TOKEN_HALT
;
1490 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1493 set_field(&q
->qh
.altnext_qtd
, 0, QH_ALTNEXT_NAKCNT
);
1494 return; /* We're not done yet with this transaction */
1495 case USB_RET_BABBLE
:
1496 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1497 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1500 /* should not be triggerable */
1501 fprintf(stderr
, "USB invalid response %d\n", p
->usb_status
);
1506 // TODO check 4.12 for splits
1507 uint32_t tbytes
= get_field(q
->qh
.token
, QTD_TOKEN_TBYTES
);
1509 if (tbytes
&& p
->pid
== USB_TOKEN_IN
) {
1510 tbytes
-= p
->usb_status
;
1515 DPRINTF("updating tbytes to %d\n", tbytes
);
1516 set_field(&q
->qh
.token
, tbytes
, QTD_TOKEN_TBYTES
);
1518 ehci_finish_transfer(q
, p
->usb_status
);
1519 usb_packet_unmap(&p
->packet
, &p
->sgl
);
1520 qemu_sglist_destroy(&p
->sgl
);
1521 p
->async
= EHCI_ASYNC_NONE
;
1523 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1524 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1526 if (q
->qh
.token
& QTD_TOKEN_IOC
) {
1527 ehci_raise_irq(q
->ehci
, USBSTS_INT
);
1533 static int ehci_execute(EHCIPacket
*p
, const char *action
)
1539 assert(p
->async
== EHCI_ASYNC_NONE
||
1540 p
->async
== EHCI_ASYNC_INITIALIZED
);
1542 if (!(p
->qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1543 fprintf(stderr
, "Attempting to execute inactive qtd\n");
1544 return USB_RET_PROCERR
;
1547 if (get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
) > BUFF_SIZE
) {
1548 ehci_trace_guest_bug(p
->queue
->ehci
,
1549 "guest requested more bytes than allowed");
1550 return USB_RET_PROCERR
;
1553 p
->pid
= (p
->qtd
.token
& QTD_TOKEN_PID_MASK
) >> QTD_TOKEN_PID_SH
;
1556 p
->pid
= USB_TOKEN_OUT
;
1559 p
->pid
= USB_TOKEN_IN
;
1562 p
->pid
= USB_TOKEN_SETUP
;
1565 fprintf(stderr
, "bad token\n");
1569 endp
= get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
);
1570 ep
= usb_ep_get(p
->queue
->dev
, p
->pid
, endp
);
1572 if (p
->async
== EHCI_ASYNC_NONE
) {
1573 if (ehci_init_transfer(p
) != 0) {
1574 return USB_RET_PROCERR
;
1577 usb_packet_setup(&p
->packet
, p
->pid
, ep
, p
->qtdaddr
);
1578 usb_packet_map(&p
->packet
, &p
->sgl
);
1579 p
->async
= EHCI_ASYNC_INITIALIZED
;
1582 trace_usb_ehci_packet_action(p
->queue
, p
, action
);
1583 ret
= usb_handle_packet(p
->queue
->dev
, &p
->packet
);
1584 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd endp %x ret %d\n",
1585 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->pid
,
1586 q
->packet
.iov
.size
, endp
, ret
);
1588 if (ret
> BUFF_SIZE
) {
1589 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1590 return USB_RET_PROCERR
;
1599 static int ehci_process_itd(EHCIState
*ehci
,
1606 uint32_t i
, len
, pid
, dir
, devaddr
, endp
;
1607 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1609 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1610 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1611 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1612 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1613 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1615 for(i
= 0; i
< 8; i
++) {
1616 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1617 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1618 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1619 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1620 ptr2
= (itd
->bufptr
[pg
+1] & ITD_BUFPTR_MASK
);
1621 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1623 if (len
> max
* mult
) {
1627 if (len
> BUFF_SIZE
) {
1628 return USB_RET_PROCERR
;
1631 pci_dma_sglist_init(&ehci
->isgl
, &ehci
->dev
, 2);
1632 if (off
+ len
> 4096) {
1633 /* transfer crosses page border */
1634 uint32_t len2
= off
+ len
- 4096;
1635 uint32_t len1
= len
- len2
;
1636 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len1
);
1637 qemu_sglist_add(&ehci
->isgl
, ptr2
, len2
);
1639 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len
);
1642 pid
= dir
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1644 dev
= ehci_find_device(ehci
, devaddr
);
1645 ep
= usb_ep_get(dev
, pid
, endp
);
1646 if (ep
&& ep
->type
== USB_ENDPOINT_XFER_ISOC
) {
1647 usb_packet_setup(&ehci
->ipacket
, pid
, ep
, addr
);
1648 usb_packet_map(&ehci
->ipacket
, &ehci
->isgl
);
1649 ret
= usb_handle_packet(dev
, &ehci
->ipacket
);
1650 assert(ret
!= USB_RET_ASYNC
);
1651 usb_packet_unmap(&ehci
->ipacket
, &ehci
->isgl
);
1653 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1656 qemu_sglist_destroy(&ehci
->isgl
);
1661 fprintf(stderr
, "Unexpected iso usb result: %d\n", ret
);
1663 case USB_RET_IOERROR
:
1665 /* 3.3.2: XACTERR is only allowed on IN transactions */
1667 itd
->transact
[i
] |= ITD_XACT_XACTERR
;
1668 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1671 case USB_RET_BABBLE
:
1672 itd
->transact
[i
] |= ITD_XACT_BABBLE
;
1673 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1676 /* no data for us, so do a zero-length transfer */
1684 set_field(&itd
->transact
[i
], len
- ret
, ITD_XACT_LENGTH
);
1687 set_field(&itd
->transact
[i
], ret
, ITD_XACT_LENGTH
);
1690 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1691 ehci_raise_irq(ehci
, USBSTS_INT
);
1693 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1700 /* This state is the entry point for asynchronous schedule
1701 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1703 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1708 uint32_t entry
= ehci
->asynclistaddr
;
1710 /* set reclamation flag at start event (4.8.6) */
1712 ehci_set_usbsts(ehci
, USBSTS_REC
);
1715 ehci_queues_rip_unused(ehci
, async
);
1717 /* Find the head of the list (4.9.1.1) */
1718 for(i
= 0; i
< MAX_QH
; i
++) {
1719 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &qh
,
1720 sizeof(EHCIqh
) >> 2);
1721 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1723 if (qh
.epchar
& QH_EPCHAR_H
) {
1725 entry
|= (NLPTR_TYPE_QH
<< 1);
1728 ehci_set_fetch_addr(ehci
, async
, entry
);
1729 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1735 if (entry
== ehci
->asynclistaddr
) {
1740 /* no head found for list. */
1742 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1749 /* This state is the entry point for periodic schedule processing as
1750 * well as being a continuation state for async processing.
1752 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1755 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1757 if (NLPTR_TBIT(entry
)) {
1758 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1762 /* section 4.8, only QH in async schedule */
1763 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1764 fprintf(stderr
, "non queue head request in async schedule\n");
1768 switch (NLPTR_TYPE_GET(entry
)) {
1770 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1774 case NLPTR_TYPE_ITD
:
1775 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1779 case NLPTR_TYPE_STITD
:
1780 ehci_set_state(ehci
, async
, EST_FETCHSITD
);
1785 /* TODO: handle FSTN type */
1786 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %d "
1787 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1795 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1798 uint32_t entry
, devaddr
, endp
;
1802 entry
= ehci_get_fetch_addr(ehci
, async
);
1803 q
= ehci_find_queue_by_qh(ehci
, entry
, async
);
1805 q
= ehci_alloc_queue(ehci
, entry
, async
);
1807 p
= QTAILQ_FIRST(&q
->packets
);
1811 /* we are going in circles -- stop processing */
1812 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1817 get_dwords(ehci
, NLPTR_GET(q
->qhaddr
),
1818 (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2);
1819 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &qh
);
1822 * The overlay area of the qh should never be changed by the guest,
1823 * except when idle, in which case the reset is a nop.
1825 devaddr
= get_field(qh
.epchar
, QH_EPCHAR_DEVADDR
);
1826 endp
= get_field(qh
.epchar
, QH_EPCHAR_EP
);
1827 if ((devaddr
!= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
)) ||
1828 (endp
!= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
)) ||
1829 (memcmp(&qh
.current_qtd
, &q
->qh
.current_qtd
,
1830 9 * sizeof(uint32_t)) != 0) ||
1831 (q
->dev
!= NULL
&& q
->dev
->addr
!= devaddr
)) {
1832 if (ehci_reset_queue(q
) > 0) {
1833 ehci_trace_guest_bug(ehci
, "guest updated active QH");
1839 q
->transact_ctr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
1840 if (q
->transact_ctr
== 0) { /* Guest bug in some versions of windows */
1841 q
->transact_ctr
= 4;
1844 if (q
->dev
== NULL
) {
1845 q
->dev
= ehci_find_device(q
->ehci
, devaddr
);
1848 if (p
&& p
->async
== EHCI_ASYNC_FINISHED
) {
1849 /* I/O finished -- continue processing queue */
1850 trace_usb_ehci_packet_action(p
->queue
, p
, "complete");
1851 ehci_set_state(ehci
, async
, EST_EXECUTING
);
1855 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1857 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1858 if (ehci
->usbsts
& USBSTS_REC
) {
1859 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1861 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1862 " - done processing\n", q
->qhaddr
);
1863 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1870 if (q
->qhaddr
!= q
->qh
.next
) {
1871 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1873 q
->qh
.epchar
& QH_EPCHAR_H
,
1874 q
->qh
.token
& QTD_TOKEN_HALT
,
1875 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1880 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1881 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1883 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) &&
1884 (NLPTR_TBIT(q
->qh
.current_qtd
) == 0)) {
1885 q
->qtdaddr
= q
->qh
.current_qtd
;
1886 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1889 /* EHCI spec version 1.0 Section 4.10.2 */
1890 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1897 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1903 entry
= ehci_get_fetch_addr(ehci
, async
);
1905 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1906 sizeof(EHCIitd
) >> 2);
1907 ehci_trace_itd(ehci
, entry
, &itd
);
1909 if (ehci_process_itd(ehci
, &itd
, entry
) != 0) {
1913 put_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1914 sizeof(EHCIitd
) >> 2);
1915 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1916 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1921 static int ehci_state_fetchsitd(EHCIState
*ehci
, int async
)
1927 entry
= ehci_get_fetch_addr(ehci
, async
);
1929 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *)&sitd
,
1930 sizeof(EHCIsitd
) >> 2);
1931 ehci_trace_sitd(ehci
, entry
, &sitd
);
1933 if (!(sitd
.results
& SITD_RESULTS_ACTIVE
)) {
1934 /* siTD is not active, nothing to do */;
1936 /* TODO: split transfers are not implemented */
1937 fprintf(stderr
, "WARNING: Skipping active siTD\n");
1940 ehci_set_fetch_addr(ehci
, async
, sitd
.next
);
1941 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1945 /* Section 4.10.2 - paragraph 3 */
1946 static int ehci_state_advqueue(EHCIQueue
*q
)
1949 /* TO-DO: 4.10.2 - paragraph 2
1950 * if I-bit is set to 1 and QH is not active
1951 * go to horizontal QH
1954 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1960 * want data and alt-next qTD is valid
1962 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1963 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1964 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1965 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1970 } else if (NLPTR_TBIT(q
->qh
.next_qtd
) == 0) {
1971 q
->qtdaddr
= q
->qh
.next_qtd
;
1972 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1975 * no valid qTD, try next QH
1978 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1984 /* Section 4.10.2 - paragraph 4 */
1985 static int ehci_state_fetchqtd(EHCIQueue
*q
)
1991 get_dwords(q
->ehci
, NLPTR_GET(q
->qtdaddr
), (uint32_t *) &qtd
,
1992 sizeof(EHCIqtd
) >> 2);
1993 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &qtd
);
1995 p
= QTAILQ_FIRST(&q
->packets
);
1997 if (p
->qtdaddr
!= q
->qtdaddr
||
1998 (!NLPTR_TBIT(p
->qtd
.next
) && (p
->qtd
.next
!= qtd
.next
)) ||
1999 (!NLPTR_TBIT(p
->qtd
.altnext
) && (p
->qtd
.altnext
!= qtd
.altnext
)) ||
2000 p
->qtd
.bufptr
[0] != qtd
.bufptr
[0]) {
2001 ehci_cancel_queue(q
);
2002 ehci_trace_guest_bug(q
->ehci
, "guest updated active QH or qTD");
2006 ehci_qh_do_overlay(q
);
2010 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
2012 /* transfer canceled by guest (clear active) */
2013 ehci_cancel_queue(q
);
2016 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2018 } else if (p
!= NULL
) {
2020 case EHCI_ASYNC_NONE
:
2021 case EHCI_ASYNC_INITIALIZED
:
2022 /* Not yet executed (MULT), or previously nacked (int) packet */
2023 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
2025 case EHCI_ASYNC_INFLIGHT
:
2026 /* Unfinished async handled packet, go horizontal */
2027 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2029 case EHCI_ASYNC_FINISHED
:
2031 * We get here when advqueue moves to a packet which is already
2032 * finished, which can happen with packets queued up by fill_queue
2034 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2039 p
= ehci_alloc_packet(q
);
2040 p
->qtdaddr
= q
->qtdaddr
;
2042 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
2049 static int ehci_state_horizqh(EHCIQueue
*q
)
2053 if (ehci_get_fetch_addr(q
->ehci
, q
->async
) != q
->qh
.next
) {
2054 ehci_set_fetch_addr(q
->ehci
, q
->async
, q
->qh
.next
);
2055 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHENTRY
);
2058 ehci_set_state(q
->ehci
, q
->async
, EST_ACTIVE
);
2064 static int ehci_fill_queue(EHCIPacket
*p
)
2066 EHCIQueue
*q
= p
->queue
;
2067 EHCIqtd qtd
= p
->qtd
;
2071 if (NLPTR_TBIT(qtd
.altnext
) == 0) {
2074 if (NLPTR_TBIT(qtd
.next
) != 0) {
2078 get_dwords(q
->ehci
, NLPTR_GET(qtdaddr
),
2079 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2);
2080 ehci_trace_qtd(q
, NLPTR_GET(qtdaddr
), &qtd
);
2081 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
2084 p
= ehci_alloc_packet(q
);
2085 p
->qtdaddr
= qtdaddr
;
2087 p
->usb_status
= ehci_execute(p
, "queue");
2088 if (p
->usb_status
== USB_RET_PROCERR
) {
2091 assert(p
->usb_status
== USB_RET_ASYNC
);
2092 p
->async
= EHCI_ASYNC_INFLIGHT
;
2094 return p
->usb_status
;
2097 static int ehci_state_execute(EHCIQueue
*q
)
2099 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2103 assert(p
->qtdaddr
== q
->qtdaddr
);
2105 if (ehci_qh_do_overlay(q
) != 0) {
2109 // TODO verify enough time remains in the uframe as in 4.4.1.1
2110 // TODO write back ptr to async list when done or out of time
2112 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
2113 if (!q
->async
&& q
->transact_ctr
== 0) {
2114 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2120 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
2123 p
->usb_status
= ehci_execute(p
, "process");
2124 if (p
->usb_status
== USB_RET_PROCERR
) {
2128 if (p
->usb_status
== USB_RET_ASYNC
) {
2130 trace_usb_ehci_packet_action(p
->queue
, p
, "async");
2131 p
->async
= EHCI_ASYNC_INFLIGHT
;
2132 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2134 again
= (ehci_fill_queue(p
) == USB_RET_PROCERR
) ? -1 : 1;
2141 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2148 static int ehci_state_executing(EHCIQueue
*q
)
2150 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2153 assert(p
->qtdaddr
== q
->qtdaddr
);
2155 ehci_execute_complete(q
);
2158 if (!q
->async
&& q
->transact_ctr
> 0) {
2163 if (p
->usb_status
== USB_RET_NAK
) {
2164 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2166 ehci_set_state(q
->ehci
, q
->async
, EST_WRITEBACK
);
2174 static int ehci_state_writeback(EHCIQueue
*q
)
2176 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2177 uint32_t *qtd
, addr
;
2180 /* Write back the QTD from the QH area */
2182 assert(p
->qtdaddr
== q
->qtdaddr
);
2184 ehci_trace_qtd(q
, NLPTR_GET(p
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
2185 qtd
= (uint32_t *) &q
->qh
.next_qtd
;
2186 addr
= NLPTR_GET(p
->qtdaddr
);
2187 put_dwords(q
->ehci
, addr
+ 2 * sizeof(uint32_t), qtd
+ 2, 2);
2188 ehci_free_packet(p
);
2191 * EHCI specs say go horizontal here.
2193 * We can also advance the queue here for performance reasons. We
2194 * need to take care to only take that shortcut in case we've
2195 * processed the qtd just written back without errors, i.e. halt
2198 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
2200 * We should not do any further processing on a halted queue!
2201 * This is esp. important for bulk endpoints with pipelining enabled
2202 * (redirection to a real USB device), where we must cancel all the
2203 * transfers after this one so that:
2204 * 1) If they've completed already, they are not processed further
2205 * causing more stalls, originating from the same failed transfer
2206 * 2) If still in flight, they are cancelled before the guest does
2207 * a clear stall, otherwise the guest and device can loose sync!
2209 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
2210 ehci_free_packet(p
);
2212 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2215 ehci_set_state(q
->ehci
, q
->async
, EST_ADVANCEQUEUE
);
2222 * This is the state machine that is common to both async and periodic
2225 static void ehci_advance_state(EHCIState
*ehci
, int async
)
2227 EHCIQueue
*q
= NULL
;
2231 switch(ehci_get_state(ehci
, async
)) {
2232 case EST_WAITLISTHEAD
:
2233 again
= ehci_state_waitlisthead(ehci
, async
);
2236 case EST_FETCHENTRY
:
2237 again
= ehci_state_fetchentry(ehci
, async
);
2241 q
= ehci_state_fetchqh(ehci
, async
);
2243 assert(q
->async
== async
);
2251 again
= ehci_state_fetchitd(ehci
, async
);
2255 again
= ehci_state_fetchsitd(ehci
, async
);
2258 case EST_ADVANCEQUEUE
:
2259 again
= ehci_state_advqueue(q
);
2263 again
= ehci_state_fetchqtd(q
);
2266 case EST_HORIZONTALQH
:
2267 again
= ehci_state_horizqh(q
);
2271 again
= ehci_state_execute(q
);
2273 ehci
->async_stepdown
= 0;
2280 ehci
->async_stepdown
= 0;
2282 again
= ehci_state_executing(q
);
2287 again
= ehci_state_writeback(q
);
2291 fprintf(stderr
, "Bad state!\n");
2298 fprintf(stderr
, "processing error - resetting ehci HC\n");
2306 static void ehci_advance_async_state(EHCIState
*ehci
)
2308 const int async
= 1;
2310 switch(ehci_get_state(ehci
, async
)) {
2312 if (!ehci_async_enabled(ehci
)) {
2315 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2316 // No break, fall through to ACTIVE
2319 if (!ehci_async_enabled(ehci
)) {
2320 ehci_queues_rip_all(ehci
, async
);
2321 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2325 /* make sure guest has acknowledged the doorbell interrupt */
2326 /* TO-DO: is this really needed? */
2327 if (ehci
->usbsts
& USBSTS_IAA
) {
2328 DPRINTF("IAA status bit still set.\n");
2332 /* check that address register has been set */
2333 if (ehci
->asynclistaddr
== 0) {
2337 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
2338 ehci_advance_state(ehci
, async
);
2340 /* If the doorbell is set, the guest wants to make a change to the
2341 * schedule. The host controller needs to release cached data.
2344 if (ehci
->usbcmd
& USBCMD_IAAD
) {
2345 /* Remove all unseen qhs from the async qhs queue */
2346 ehci_queues_rip_unseen(ehci
, async
);
2347 trace_usb_ehci_doorbell_ack();
2348 ehci
->usbcmd
&= ~USBCMD_IAAD
;
2349 ehci_raise_irq(ehci
, USBSTS_IAA
);
2354 /* this should only be due to a developer mistake */
2355 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
2356 "Resetting to active\n", ehci
->astate
);
2361 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2365 const int async
= 0;
2369 switch(ehci_get_state(ehci
, async
)) {
2371 if (!(ehci
->frindex
& 7) && ehci_periodic_enabled(ehci
)) {
2372 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2373 // No break, fall through to ACTIVE
2378 if (!(ehci
->frindex
& 7) && !ehci_periodic_enabled(ehci
)) {
2379 ehci_queues_rip_all(ehci
, async
);
2380 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2384 list
= ehci
->periodiclistbase
& 0xfffff000;
2385 /* check that register has been set */
2389 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2391 pci_dma_read(&ehci
->dev
, list
, &entry
, sizeof entry
);
2392 entry
= le32_to_cpu(entry
);
2394 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2395 ehci
->frindex
/ 8, list
, entry
);
2396 ehci_set_fetch_addr(ehci
, async
,entry
);
2397 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2398 ehci_advance_state(ehci
, async
);
2399 ehci_queues_rip_unused(ehci
, async
);
2403 /* this should only be due to a developer mistake */
2404 fprintf(stderr
, "ehci: Bad periodic state %d. "
2405 "Resetting to active\n", ehci
->pstate
);
2410 static void ehci_update_frindex(EHCIState
*ehci
, int frames
)
2414 if (!ehci_enabled(ehci
)) {
2418 for (i
= 0; i
< frames
; i
++) {
2421 if (ehci
->frindex
== 0x00002000) {
2422 ehci_raise_irq(ehci
, USBSTS_FLR
);
2425 if (ehci
->frindex
== 0x00004000) {
2426 ehci_raise_irq(ehci
, USBSTS_FLR
);
2428 if (ehci
->usbsts_frindex
>= 0x00004000) {
2429 ehci
->usbsts_frindex
-= 0x00004000;
2431 ehci
->usbsts_frindex
= 0;
2437 static void ehci_frame_timer(void *opaque
)
2439 EHCIState
*ehci
= opaque
;
2441 int64_t expire_time
, t_now
;
2442 uint64_t ns_elapsed
;
2443 int frames
, skipped_frames
;
2446 t_now
= qemu_get_clock_ns(vm_clock
);
2447 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2448 frames
= ns_elapsed
/ FRAME_TIMER_NS
;
2450 if (ehci_periodic_enabled(ehci
) || ehci
->pstate
!= EST_INACTIVE
) {
2452 ehci
->async_stepdown
= 0;
2454 if (frames
> ehci
->maxframes
) {
2455 skipped_frames
= frames
- ehci
->maxframes
;
2456 ehci_update_frindex(ehci
, skipped_frames
);
2457 ehci
->last_run_ns
+= FRAME_TIMER_NS
* skipped_frames
;
2458 frames
-= skipped_frames
;
2459 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames
);
2462 for (i
= 0; i
< frames
; i
++) {
2464 * If we're running behind schedule, we should not catch up
2465 * too fast, as that will make some guests unhappy:
2466 * 1) We must process a minimum of MIN_FR_PER_TICK frames,
2467 * otherwise we will never catch up
2468 * 2) Process frames until the guest has requested an irq (IOC)
2470 if (i
>= MIN_FR_PER_TICK
) {
2471 ehci_commit_irq(ehci
);
2472 if ((ehci
->usbsts
& USBINTR_MASK
) & ehci
->usbintr
) {
2476 ehci_update_frindex(ehci
, 1);
2477 ehci_advance_periodic_state(ehci
);
2478 ehci
->last_run_ns
+= FRAME_TIMER_NS
;
2481 if (ehci
->async_stepdown
< ehci
->maxframes
/ 2) {
2482 ehci
->async_stepdown
++;
2484 ehci_update_frindex(ehci
, frames
);
2485 ehci
->last_run_ns
+= FRAME_TIMER_NS
* frames
;
2488 /* Async is not inside loop since it executes everything it can once
2491 if (ehci_async_enabled(ehci
) || ehci
->astate
!= EST_INACTIVE
) {
2493 ehci_advance_async_state(ehci
);
2496 ehci_commit_irq(ehci
);
2497 if (ehci
->usbsts_pending
) {
2499 ehci
->async_stepdown
= 0;
2503 expire_time
= t_now
+ (get_ticks_per_sec()
2504 * (ehci
->async_stepdown
+1) / FRAME_TIMER_FREQ
);
2505 qemu_mod_timer(ehci
->frame_timer
, expire_time
);
2509 static void ehci_async_bh(void *opaque
)
2511 EHCIState
*ehci
= opaque
;
2512 ehci_advance_async_state(ehci
);
2515 static const MemoryRegionOps ehci_mmio_caps_ops
= {
2516 .read
= ehci_caps_read
,
2517 .valid
.min_access_size
= 1,
2518 .valid
.max_access_size
= 4,
2519 .impl
.min_access_size
= 1,
2520 .impl
.max_access_size
= 1,
2521 .endianness
= DEVICE_LITTLE_ENDIAN
,
2524 static const MemoryRegionOps ehci_mmio_opreg_ops
= {
2525 .read
= ehci_opreg_read
,
2526 .write
= ehci_opreg_write
,
2527 .valid
.min_access_size
= 4,
2528 .valid
.max_access_size
= 4,
2529 .endianness
= DEVICE_LITTLE_ENDIAN
,
2532 static const MemoryRegionOps ehci_mmio_port_ops
= {
2533 .read
= ehci_port_read
,
2534 .write
= ehci_port_write
,
2535 .valid
.min_access_size
= 4,
2536 .valid
.max_access_size
= 4,
2537 .endianness
= DEVICE_LITTLE_ENDIAN
,
2540 static int usb_ehci_initfn(PCIDevice
*dev
);
2542 static USBPortOps ehci_port_ops
= {
2543 .attach
= ehci_attach
,
2544 .detach
= ehci_detach
,
2545 .child_detach
= ehci_child_detach
,
2546 .wakeup
= ehci_wakeup
,
2547 .complete
= ehci_async_complete_packet
,
2550 static USBBusOps ehci_bus_ops
= {
2551 .register_companion
= ehci_register_companion
,
2554 static int usb_ehci_post_load(void *opaque
, int version_id
)
2556 EHCIState
*s
= opaque
;
2559 for (i
= 0; i
< NB_PORTS
; i
++) {
2560 USBPort
*companion
= s
->companion_ports
[i
];
2561 if (companion
== NULL
) {
2564 if (s
->portsc
[i
] & PORTSC_POWNER
) {
2565 companion
->dev
= s
->ports
[i
].dev
;
2567 companion
->dev
= NULL
;
2574 static void usb_ehci_vm_state_change(void *opaque
, int running
, RunState state
)
2576 EHCIState
*ehci
= opaque
;
2579 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2580 * schedule in guest memory. We must do the rebuilt ASAP, so that
2581 * USB-devices which have async handled packages have a packet in the
2582 * ep queue to match the completion with.
2584 if (state
== RUN_STATE_RUNNING
) {
2585 ehci_advance_async_state(ehci
);
2589 * The schedule rebuilt from guest memory could cause the migration dest
2590 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2591 * will never have existed on the destination. Therefor we must flush the
2592 * async schedule on savevm to catch any not yet noticed unlinks.
2594 if (state
== RUN_STATE_SAVE_VM
) {
2595 ehci_advance_async_state(ehci
);
2596 ehci_queues_rip_unseen(ehci
, 1);
2600 static const VMStateDescription vmstate_ehci
= {
2603 .minimum_version_id
= 1,
2604 .post_load
= usb_ehci_post_load
,
2605 .fields
= (VMStateField
[]) {
2606 VMSTATE_PCI_DEVICE(dev
, EHCIState
),
2607 /* mmio registers */
2608 VMSTATE_UINT32(usbcmd
, EHCIState
),
2609 VMSTATE_UINT32(usbsts
, EHCIState
),
2610 VMSTATE_UINT32_V(usbsts_pending
, EHCIState
, 2),
2611 VMSTATE_UINT32_V(usbsts_frindex
, EHCIState
, 2),
2612 VMSTATE_UINT32(usbintr
, EHCIState
),
2613 VMSTATE_UINT32(frindex
, EHCIState
),
2614 VMSTATE_UINT32(ctrldssegment
, EHCIState
),
2615 VMSTATE_UINT32(periodiclistbase
, EHCIState
),
2616 VMSTATE_UINT32(asynclistaddr
, EHCIState
),
2617 VMSTATE_UINT32(configflag
, EHCIState
),
2618 VMSTATE_UINT32(portsc
[0], EHCIState
),
2619 VMSTATE_UINT32(portsc
[1], EHCIState
),
2620 VMSTATE_UINT32(portsc
[2], EHCIState
),
2621 VMSTATE_UINT32(portsc
[3], EHCIState
),
2622 VMSTATE_UINT32(portsc
[4], EHCIState
),
2623 VMSTATE_UINT32(portsc
[5], EHCIState
),
2625 VMSTATE_TIMER(frame_timer
, EHCIState
),
2626 VMSTATE_UINT64(last_run_ns
, EHCIState
),
2627 VMSTATE_UINT32(async_stepdown
, EHCIState
),
2628 /* schedule state */
2629 VMSTATE_UINT32(astate
, EHCIState
),
2630 VMSTATE_UINT32(pstate
, EHCIState
),
2631 VMSTATE_UINT32(a_fetch_addr
, EHCIState
),
2632 VMSTATE_UINT32(p_fetch_addr
, EHCIState
),
2633 VMSTATE_END_OF_LIST()
2637 static Property ehci_properties
[] = {
2638 DEFINE_PROP_UINT32("maxframes", EHCIState
, maxframes
, 128),
2639 DEFINE_PROP_END_OF_LIST(),
2642 static void ehci_class_init(ObjectClass
*klass
, void *data
)
2644 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2645 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2647 k
->init
= usb_ehci_initfn
;
2648 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2649 k
->device_id
= PCI_DEVICE_ID_INTEL_82801D
; /* ich4 */
2651 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2652 dc
->vmsd
= &vmstate_ehci
;
2653 dc
->props
= ehci_properties
;
2656 static TypeInfo ehci_info
= {
2658 .parent
= TYPE_PCI_DEVICE
,
2659 .instance_size
= sizeof(EHCIState
),
2660 .class_init
= ehci_class_init
,
2663 static void ich9_ehci_class_init(ObjectClass
*klass
, void *data
)
2665 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2666 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2668 k
->init
= usb_ehci_initfn
;
2669 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2670 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_EHCI1
;
2672 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2673 dc
->vmsd
= &vmstate_ehci
;
2674 dc
->props
= ehci_properties
;
2677 static TypeInfo ich9_ehci_info
= {
2678 .name
= "ich9-usb-ehci1",
2679 .parent
= TYPE_PCI_DEVICE
,
2680 .instance_size
= sizeof(EHCIState
),
2681 .class_init
= ich9_ehci_class_init
,
2684 static int usb_ehci_initfn(PCIDevice
*dev
)
2686 EHCIState
*s
= DO_UPCAST(EHCIState
, dev
, dev
);
2687 uint8_t *pci_conf
= s
->dev
.config
;
2690 pci_set_byte(&pci_conf
[PCI_CLASS_PROG
], 0x20);
2692 /* capabilities pointer */
2693 pci_set_byte(&pci_conf
[PCI_CAPABILITY_LIST
], 0x00);
2694 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2696 pci_set_byte(&pci_conf
[PCI_INTERRUPT_PIN
], 4); /* interrupt pin D */
2697 pci_set_byte(&pci_conf
[PCI_MIN_GNT
], 0);
2698 pci_set_byte(&pci_conf
[PCI_MAX_LAT
], 0);
2700 // pci_conf[0x50] = 0x01; // power management caps
2702 pci_set_byte(&pci_conf
[USB_SBRN
], USB_RELEASE_2
); // release number (2.1.4)
2703 pci_set_byte(&pci_conf
[0x61], 0x20); // frame length adjustment (2.1.5)
2704 pci_set_word(&pci_conf
[0x62], 0x00); // port wake up capability (2.1.6)
2706 pci_conf
[0x64] = 0x00;
2707 pci_conf
[0x65] = 0x00;
2708 pci_conf
[0x66] = 0x00;
2709 pci_conf
[0x67] = 0x00;
2710 pci_conf
[0x68] = 0x01;
2711 pci_conf
[0x69] = 0x00;
2712 pci_conf
[0x6a] = 0x00;
2713 pci_conf
[0x6b] = 0x00; // USBLEGSUP
2714 pci_conf
[0x6c] = 0x00;
2715 pci_conf
[0x6d] = 0x00;
2716 pci_conf
[0x6e] = 0x00;
2717 pci_conf
[0x6f] = 0xc0; // USBLEFCTLSTS
2719 /* 2.2 host controller interface version */
2720 s
->caps
[0x00] = (uint8_t) OPREGBASE
;
2721 s
->caps
[0x01] = 0x00;
2722 s
->caps
[0x02] = 0x00;
2723 s
->caps
[0x03] = 0x01; /* HC version */
2724 s
->caps
[0x04] = NB_PORTS
; /* Number of downstream ports */
2725 s
->caps
[0x05] = 0x00; /* No companion ports at present */
2726 s
->caps
[0x06] = 0x00;
2727 s
->caps
[0x07] = 0x00;
2728 s
->caps
[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2729 s
->caps
[0x09] = 0x68; /* EECP */
2730 s
->caps
[0x0a] = 0x00;
2731 s
->caps
[0x0b] = 0x00;
2733 s
->irq
= s
->dev
.irq
[3];
2735 usb_bus_new(&s
->bus
, &ehci_bus_ops
, &s
->dev
.qdev
);
2736 for(i
= 0; i
< NB_PORTS
; i
++) {
2737 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2738 USB_SPEED_MASK_HIGH
);
2739 s
->ports
[i
].dev
= 0;
2742 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, ehci_frame_timer
, s
);
2743 s
->async_bh
= qemu_bh_new(ehci_async_bh
, s
);
2744 QTAILQ_INIT(&s
->aqueues
);
2745 QTAILQ_INIT(&s
->pqueues
);
2746 usb_packet_init(&s
->ipacket
);
2748 qemu_register_reset(ehci_reset
, s
);
2749 qemu_add_vm_change_state_handler(usb_ehci_vm_state_change
, s
);
2751 memory_region_init(&s
->mem
, "ehci", MMIO_SIZE
);
2752 memory_region_init_io(&s
->mem_caps
, &ehci_mmio_caps_ops
, s
,
2753 "capabilities", OPREGBASE
);
2754 memory_region_init_io(&s
->mem_opreg
, &ehci_mmio_opreg_ops
, s
,
2755 "operational", PORTSC_BEGIN
- OPREGBASE
);
2756 memory_region_init_io(&s
->mem_ports
, &ehci_mmio_port_ops
, s
,
2757 "ports", PORTSC_END
- PORTSC_BEGIN
);
2759 memory_region_add_subregion(&s
->mem
, 0, &s
->mem_caps
);
2760 memory_region_add_subregion(&s
->mem
, OPREGBASE
, &s
->mem_opreg
);
2761 memory_region_add_subregion(&s
->mem
, PORTSC_BEGIN
, &s
->mem_ports
);
2763 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mem
);
2768 static void ehci_register_types(void)
2770 type_register_static(&ehci_info
);
2771 type_register_static(&ich9_ehci_info
);
2774 type_init(ehci_register_types
)
2777 * vim: expandtab ts=4