2 * High Precisition Event Timer emulation
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
7 * Authors: Beth Kon <bkon@us.ibm.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * *****************************************************************
24 * This driver attempts to emulate an HPET device in software.
28 #include "hw/i386/pc.h"
29 #include "ui/console.h"
30 #include "qemu/timer.h"
31 #include "hw/timer/hpet.h"
32 #include "hw/sysbus.h"
33 #include "hw/timer/mc146818rtc.h"
34 #include "hw/timer/i8254.h"
38 #define DPRINTF printf
43 #define HPET_MSI_SUPPORT 0
45 #define TYPE_HPET "hpet"
46 #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET)
49 typedef struct HPETTimer
{ /* timers */
50 uint8_t tn
; /*timer number*/
51 QEMUTimer
*qemu_timer
;
52 struct HPETState
*state
;
53 /* Memory-mapped, software visible timer registers */
54 uint64_t config
; /* configuration/cap */
55 uint64_t cmp
; /* comparator */
56 uint64_t fsb
; /* FSB route */
57 /* Hidden register state */
58 uint64_t period
; /* Last value written to comparator */
59 uint8_t wrap_flag
; /* timer pop will indicate wrap for one-shot 32-bit
60 * mode. Next pop will be actual timer expiration.
64 typedef struct HPETState
{
66 SysBusDevice parent_obj
;
71 qemu_irq irqs
[HPET_NUM_IRQ_ROUTES
];
73 uint8_t rtc_irq_level
;
76 HPETTimer timer
[HPET_MAX_TIMERS
];
78 /* Memory-mapped, software visible registers */
79 uint64_t capability
; /* capabilities */
80 uint64_t config
; /* configuration */
81 uint64_t isr
; /* interrupt status reg */
82 uint64_t hpet_counter
; /* main counter */
83 uint8_t hpet_id
; /* instance id */
86 static uint32_t hpet_in_legacy_mode(HPETState
*s
)
88 return s
->config
& HPET_CFG_LEGACY
;
91 static uint32_t timer_int_route(struct HPETTimer
*timer
)
93 return (timer
->config
& HPET_TN_INT_ROUTE_MASK
) >> HPET_TN_INT_ROUTE_SHIFT
;
96 static uint32_t timer_fsb_route(HPETTimer
*t
)
98 return t
->config
& HPET_TN_FSB_ENABLE
;
101 static uint32_t hpet_enabled(HPETState
*s
)
103 return s
->config
& HPET_CFG_ENABLE
;
106 static uint32_t timer_is_periodic(HPETTimer
*t
)
108 return t
->config
& HPET_TN_PERIODIC
;
111 static uint32_t timer_enabled(HPETTimer
*t
)
113 return t
->config
& HPET_TN_ENABLE
;
116 static uint32_t hpet_time_after(uint64_t a
, uint64_t b
)
118 return ((int32_t)(b
) - (int32_t)(a
) < 0);
121 static uint32_t hpet_time_after64(uint64_t a
, uint64_t b
)
123 return ((int64_t)(b
) - (int64_t)(a
) < 0);
126 static uint64_t ticks_to_ns(uint64_t value
)
128 return (muldiv64(value
, HPET_CLK_PERIOD
, FS_PER_NS
));
131 static uint64_t ns_to_ticks(uint64_t value
)
133 return (muldiv64(value
, FS_PER_NS
, HPET_CLK_PERIOD
));
136 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old
, uint64_t mask
)
143 static int activating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
145 return (!(old
& mask
) && (new & mask
));
148 static int deactivating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
150 return ((old
& mask
) && !(new & mask
));
153 static uint64_t hpet_get_ticks(HPETState
*s
)
155 return ns_to_ticks(qemu_get_clock_ns(vm_clock
) + s
->hpet_offset
);
159 * calculate diff between comparator value and current ticks
161 static inline uint64_t hpet_calculate_diff(HPETTimer
*t
, uint64_t current
)
164 if (t
->config
& HPET_TN_32BIT
) {
167 cmp
= (uint32_t)t
->cmp
;
168 diff
= cmp
- (uint32_t)current
;
169 diff
= (int32_t)diff
> 0 ? diff
: (uint32_t)1;
170 return (uint64_t)diff
;
175 diff
= cmp
- current
;
176 diff
= (int64_t)diff
> 0 ? diff
: (uint64_t)1;
181 static void update_irq(struct HPETTimer
*timer
, int set
)
187 if (timer
->tn
<= 1 && hpet_in_legacy_mode(timer
->state
)) {
188 /* if LegacyReplacementRoute bit is set, HPET specification requires
189 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
190 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
192 route
= (timer
->tn
== 0) ? 0 : RTC_ISA_IRQ
;
194 route
= timer_int_route(timer
);
197 mask
= 1 << timer
->tn
;
198 if (!set
|| !timer_enabled(timer
) || !hpet_enabled(timer
->state
)) {
200 if (!timer_fsb_route(timer
)) {
201 qemu_irq_lower(s
->irqs
[route
]);
203 } else if (timer_fsb_route(timer
)) {
204 stl_le_phys(timer
->fsb
>> 32, timer
->fsb
& 0xffffffff);
205 } else if (timer
->config
& HPET_TN_TYPE_LEVEL
) {
207 qemu_irq_raise(s
->irqs
[route
]);
210 qemu_irq_pulse(s
->irqs
[route
]);
214 static void hpet_pre_save(void *opaque
)
216 HPETState
*s
= opaque
;
218 /* save current counter value */
219 s
->hpet_counter
= hpet_get_ticks(s
);
222 static int hpet_pre_load(void *opaque
)
224 HPETState
*s
= opaque
;
226 /* version 1 only supports 3, later versions will load the actual value */
227 s
->num_timers
= HPET_MIN_TIMERS
;
231 static int hpet_post_load(void *opaque
, int version_id
)
233 HPETState
*s
= opaque
;
235 /* Recalculate the offset between the main counter and guest time */
236 s
->hpet_offset
= ticks_to_ns(s
->hpet_counter
) - qemu_get_clock_ns(vm_clock
);
238 /* Push number of timers into capability returned via HPET_ID */
239 s
->capability
&= ~HPET_ID_NUM_TIM_MASK
;
240 s
->capability
|= (s
->num_timers
- 1) << HPET_ID_NUM_TIM_SHIFT
;
241 hpet_cfg
.hpet
[s
->hpet_id
].event_timer_block_id
= (uint32_t)s
->capability
;
243 /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
244 s
->flags
&= ~(1 << HPET_MSI_SUPPORT
);
245 if (s
->timer
[0].config
& HPET_TN_FSB_CAP
) {
246 s
->flags
|= 1 << HPET_MSI_SUPPORT
;
251 static bool hpet_rtc_irq_level_needed(void *opaque
)
253 HPETState
*s
= opaque
;
255 return s
->rtc_irq_level
!= 0;
258 static const VMStateDescription vmstate_hpet_rtc_irq_level
= {
259 .name
= "hpet/rtc_irq_level",
261 .minimum_version_id
= 1,
262 .minimum_version_id_old
= 1,
263 .fields
= (VMStateField
[]) {
264 VMSTATE_UINT8(rtc_irq_level
, HPETState
),
265 VMSTATE_END_OF_LIST()
269 static const VMStateDescription vmstate_hpet_timer
= {
270 .name
= "hpet_timer",
272 .minimum_version_id
= 1,
273 .minimum_version_id_old
= 1,
274 .fields
= (VMStateField
[]) {
275 VMSTATE_UINT8(tn
, HPETTimer
),
276 VMSTATE_UINT64(config
, HPETTimer
),
277 VMSTATE_UINT64(cmp
, HPETTimer
),
278 VMSTATE_UINT64(fsb
, HPETTimer
),
279 VMSTATE_UINT64(period
, HPETTimer
),
280 VMSTATE_UINT8(wrap_flag
, HPETTimer
),
281 VMSTATE_TIMER(qemu_timer
, HPETTimer
),
282 VMSTATE_END_OF_LIST()
286 static const VMStateDescription vmstate_hpet
= {
289 .minimum_version_id
= 1,
290 .minimum_version_id_old
= 1,
291 .pre_save
= hpet_pre_save
,
292 .pre_load
= hpet_pre_load
,
293 .post_load
= hpet_post_load
,
294 .fields
= (VMStateField
[]) {
295 VMSTATE_UINT64(config
, HPETState
),
296 VMSTATE_UINT64(isr
, HPETState
),
297 VMSTATE_UINT64(hpet_counter
, HPETState
),
298 VMSTATE_UINT8_V(num_timers
, HPETState
, 2),
299 VMSTATE_STRUCT_VARRAY_UINT8(timer
, HPETState
, num_timers
, 0,
300 vmstate_hpet_timer
, HPETTimer
),
301 VMSTATE_END_OF_LIST()
303 .subsections
= (VMStateSubsection
[]) {
305 .vmsd
= &vmstate_hpet_rtc_irq_level
,
306 .needed
= hpet_rtc_irq_level_needed
,
314 * timer expiration callback
316 static void hpet_timer(void *opaque
)
318 HPETTimer
*t
= opaque
;
321 uint64_t period
= t
->period
;
322 uint64_t cur_tick
= hpet_get_ticks(t
->state
);
324 if (timer_is_periodic(t
) && period
!= 0) {
325 if (t
->config
& HPET_TN_32BIT
) {
326 while (hpet_time_after(cur_tick
, t
->cmp
)) {
327 t
->cmp
= (uint32_t)(t
->cmp
+ t
->period
);
330 while (hpet_time_after64(cur_tick
, t
->cmp
)) {
334 diff
= hpet_calculate_diff(t
, cur_tick
);
335 qemu_mod_timer(t
->qemu_timer
,
336 qemu_get_clock_ns(vm_clock
) + (int64_t)ticks_to_ns(diff
));
337 } else if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
339 diff
= hpet_calculate_diff(t
, cur_tick
);
340 qemu_mod_timer(t
->qemu_timer
, qemu_get_clock_ns(vm_clock
) +
341 (int64_t)ticks_to_ns(diff
));
348 static void hpet_set_timer(HPETTimer
*t
)
351 uint32_t wrap_diff
; /* how many ticks until we wrap? */
352 uint64_t cur_tick
= hpet_get_ticks(t
->state
);
354 /* whenever new timer is being set up, make sure wrap_flag is 0 */
356 diff
= hpet_calculate_diff(t
, cur_tick
);
358 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
359 * counter wraps in addition to an interrupt with comparator match.
361 if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
362 wrap_diff
= 0xffffffff - (uint32_t)cur_tick
;
363 if (wrap_diff
< (uint32_t)diff
) {
368 qemu_mod_timer(t
->qemu_timer
,
369 qemu_get_clock_ns(vm_clock
) + (int64_t)ticks_to_ns(diff
));
372 static void hpet_del_timer(HPETTimer
*t
)
374 qemu_del_timer(t
->qemu_timer
);
379 static uint32_t hpet_ram_readb(void *opaque
, hwaddr addr
)
381 printf("qemu: hpet_read b at %" PRIx64
"\n", addr
);
385 static uint32_t hpet_ram_readw(void *opaque
, hwaddr addr
)
387 printf("qemu: hpet_read w at %" PRIx64
"\n", addr
);
392 static uint64_t hpet_ram_read(void *opaque
, hwaddr addr
,
395 HPETState
*s
= opaque
;
396 uint64_t cur_tick
, index
;
398 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64
"\n", addr
);
400 /*address range of all TN regs*/
401 if (index
>= 0x100 && index
<= 0x3ff) {
402 uint8_t timer_id
= (addr
- 0x100) / 0x20;
403 HPETTimer
*timer
= &s
->timer
[timer_id
];
405 if (timer_id
> s
->num_timers
) {
406 DPRINTF("qemu: timer id out of range\n");
410 switch ((addr
- 0x100) % 0x20) {
412 return timer
->config
;
413 case HPET_TN_CFG
+ 4: // Interrupt capabilities
414 return timer
->config
>> 32;
415 case HPET_TN_CMP
: // comparator register
417 case HPET_TN_CMP
+ 4:
418 return timer
->cmp
>> 32;
421 case HPET_TN_ROUTE
+ 4:
422 return timer
->fsb
>> 32;
424 DPRINTF("qemu: invalid hpet_ram_readl\n");
430 return s
->capability
;
432 return s
->capability
>> 32;
436 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
439 if (hpet_enabled(s
)) {
440 cur_tick
= hpet_get_ticks(s
);
442 cur_tick
= s
->hpet_counter
;
444 DPRINTF("qemu: reading counter = %" PRIx64
"\n", cur_tick
);
446 case HPET_COUNTER
+ 4:
447 if (hpet_enabled(s
)) {
448 cur_tick
= hpet_get_ticks(s
);
450 cur_tick
= s
->hpet_counter
;
452 DPRINTF("qemu: reading counter + 4 = %" PRIx64
"\n", cur_tick
);
453 return cur_tick
>> 32;
457 DPRINTF("qemu: invalid hpet_ram_readl\n");
464 static void hpet_ram_write(void *opaque
, hwaddr addr
,
465 uint64_t value
, unsigned size
)
468 HPETState
*s
= opaque
;
469 uint64_t old_val
, new_val
, val
, index
;
471 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64
" = %#x\n", addr
, value
);
473 old_val
= hpet_ram_read(opaque
, addr
, 4);
476 /*address range of all TN regs*/
477 if (index
>= 0x100 && index
<= 0x3ff) {
478 uint8_t timer_id
= (addr
- 0x100) / 0x20;
479 HPETTimer
*timer
= &s
->timer
[timer_id
];
481 DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id
);
482 if (timer_id
> s
->num_timers
) {
483 DPRINTF("qemu: timer id out of range\n");
486 switch ((addr
- 0x100) % 0x20) {
488 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
489 if (activating_bit(old_val
, new_val
, HPET_TN_FSB_ENABLE
)) {
490 update_irq(timer
, 0);
492 val
= hpet_fixup_reg(new_val
, old_val
, HPET_TN_CFG_WRITE_MASK
);
493 timer
->config
= (timer
->config
& 0xffffffff00000000ULL
) | val
;
494 if (new_val
& HPET_TN_32BIT
) {
495 timer
->cmp
= (uint32_t)timer
->cmp
;
496 timer
->period
= (uint32_t)timer
->period
;
498 if (activating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
499 hpet_set_timer(timer
);
500 } else if (deactivating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
501 hpet_del_timer(timer
);
504 case HPET_TN_CFG
+ 4: // Interrupt capabilities
505 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
507 case HPET_TN_CMP
: // comparator register
508 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
509 if (timer
->config
& HPET_TN_32BIT
) {
510 new_val
= (uint32_t)new_val
;
512 if (!timer_is_periodic(timer
)
513 || (timer
->config
& HPET_TN_SETVAL
)) {
514 timer
->cmp
= (timer
->cmp
& 0xffffffff00000000ULL
) | new_val
;
516 if (timer_is_periodic(timer
)) {
518 * FIXME: Clamp period to reasonable min value?
519 * Clamp period to reasonable max value
521 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
523 (timer
->period
& 0xffffffff00000000ULL
) | new_val
;
525 timer
->config
&= ~HPET_TN_SETVAL
;
526 if (hpet_enabled(s
)) {
527 hpet_set_timer(timer
);
530 case HPET_TN_CMP
+ 4: // comparator register high order
531 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
532 if (!timer_is_periodic(timer
)
533 || (timer
->config
& HPET_TN_SETVAL
)) {
534 timer
->cmp
= (timer
->cmp
& 0xffffffffULL
) | new_val
<< 32;
537 * FIXME: Clamp period to reasonable min value?
538 * Clamp period to reasonable max value
540 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
542 (timer
->period
& 0xffffffffULL
) | new_val
<< 32;
544 timer
->config
&= ~HPET_TN_SETVAL
;
545 if (hpet_enabled(s
)) {
546 hpet_set_timer(timer
);
550 timer
->fsb
= (timer
->fsb
& 0xffffffff00000000ULL
) | new_val
;
552 case HPET_TN_ROUTE
+ 4:
553 timer
->fsb
= (new_val
<< 32) | (timer
->fsb
& 0xffffffff);
556 DPRINTF("qemu: invalid hpet_ram_writel\n");
565 val
= hpet_fixup_reg(new_val
, old_val
, HPET_CFG_WRITE_MASK
);
566 s
->config
= (s
->config
& 0xffffffff00000000ULL
) | val
;
567 if (activating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
568 /* Enable main counter and interrupt generation. */
570 ticks_to_ns(s
->hpet_counter
) - qemu_get_clock_ns(vm_clock
);
571 for (i
= 0; i
< s
->num_timers
; i
++) {
572 if ((&s
->timer
[i
])->cmp
!= ~0ULL) {
573 hpet_set_timer(&s
->timer
[i
]);
576 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
577 /* Halt main counter and disable interrupt generation. */
578 s
->hpet_counter
= hpet_get_ticks(s
);
579 for (i
= 0; i
< s
->num_timers
; i
++) {
580 hpet_del_timer(&s
->timer
[i
]);
583 /* i8254 and RTC output pins are disabled
584 * when HPET is in legacy mode */
585 if (activating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
586 qemu_set_irq(s
->pit_enabled
, 0);
587 qemu_irq_lower(s
->irqs
[0]);
588 qemu_irq_lower(s
->irqs
[RTC_ISA_IRQ
]);
589 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
590 qemu_irq_lower(s
->irqs
[0]);
591 qemu_set_irq(s
->pit_enabled
, 1);
592 qemu_set_irq(s
->irqs
[RTC_ISA_IRQ
], s
->rtc_irq_level
);
596 DPRINTF("qemu: invalid HPET_CFG+4 write\n");
599 val
= new_val
& s
->isr
;
600 for (i
= 0; i
< s
->num_timers
; i
++) {
601 if (val
& (1 << i
)) {
602 update_irq(&s
->timer
[i
], 0);
607 if (hpet_enabled(s
)) {
608 DPRINTF("qemu: Writing counter while HPET enabled!\n");
611 (s
->hpet_counter
& 0xffffffff00000000ULL
) | value
;
612 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64
"\n",
613 value
, s
->hpet_counter
);
615 case HPET_COUNTER
+ 4:
616 if (hpet_enabled(s
)) {
617 DPRINTF("qemu: Writing counter while HPET enabled!\n");
620 (s
->hpet_counter
& 0xffffffffULL
) | (((uint64_t)value
) << 32);
621 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64
"\n",
622 value
, s
->hpet_counter
);
625 DPRINTF("qemu: invalid hpet_ram_writel\n");
631 static const MemoryRegionOps hpet_ram_ops
= {
632 .read
= hpet_ram_read
,
633 .write
= hpet_ram_write
,
635 .min_access_size
= 4,
636 .max_access_size
= 4,
638 .endianness
= DEVICE_NATIVE_ENDIAN
,
641 static void hpet_reset(DeviceState
*d
)
643 HPETState
*s
= HPET(d
);
644 SysBusDevice
*sbd
= SYS_BUS_DEVICE(d
);
647 for (i
= 0; i
< s
->num_timers
; i
++) {
648 HPETTimer
*timer
= &s
->timer
[i
];
650 hpet_del_timer(timer
);
652 timer
->config
= HPET_TN_PERIODIC_CAP
| HPET_TN_SIZE_CAP
;
653 if (s
->flags
& (1 << HPET_MSI_SUPPORT
)) {
654 timer
->config
|= HPET_TN_FSB_CAP
;
656 /* advertise availability of ioapic inti2 */
657 timer
->config
|= 0x00000004ULL
<< 32;
658 timer
->period
= 0ULL;
659 timer
->wrap_flag
= 0;
662 qemu_set_irq(s
->pit_enabled
, 1);
663 s
->hpet_counter
= 0ULL;
664 s
->hpet_offset
= 0ULL;
666 hpet_cfg
.hpet
[s
->hpet_id
].event_timer_block_id
= (uint32_t)s
->capability
;
667 hpet_cfg
.hpet
[s
->hpet_id
].address
= sbd
->mmio
[0].addr
;
669 /* to document that the RTC lowers its output on reset as well */
670 s
->rtc_irq_level
= 0;
673 static void hpet_handle_legacy_irq(void *opaque
, int n
, int level
)
675 HPETState
*s
= HPET(opaque
);
677 if (n
== HPET_LEGACY_PIT_INT
) {
678 if (!hpet_in_legacy_mode(s
)) {
679 qemu_set_irq(s
->irqs
[0], level
);
682 s
->rtc_irq_level
= level
;
683 if (!hpet_in_legacy_mode(s
)) {
684 qemu_set_irq(s
->irqs
[RTC_ISA_IRQ
], level
);
689 static void hpet_init(Object
*obj
)
691 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
692 HPETState
*s
= HPET(obj
);
695 memory_region_init_io(&s
->iomem
, obj
, &hpet_ram_ops
, s
, "hpet", 0x400);
696 sysbus_init_mmio(sbd
, &s
->iomem
);
699 static void hpet_realize(DeviceState
*dev
, Error
**errp
)
701 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
702 HPETState
*s
= HPET(dev
);
706 if (hpet_cfg
.count
== UINT8_MAX
) {
711 if (hpet_cfg
.count
== 8) {
712 error_setg(errp
, "Only 8 instances of HPET is allowed");
716 s
->hpet_id
= hpet_cfg
.count
++;
718 for (i
= 0; i
< HPET_NUM_IRQ_ROUTES
; i
++) {
719 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
722 if (s
->num_timers
< HPET_MIN_TIMERS
) {
723 s
->num_timers
= HPET_MIN_TIMERS
;
724 } else if (s
->num_timers
> HPET_MAX_TIMERS
) {
725 s
->num_timers
= HPET_MAX_TIMERS
;
727 for (i
= 0; i
< HPET_MAX_TIMERS
; i
++) {
728 timer
= &s
->timer
[i
];
729 timer
->qemu_timer
= qemu_new_timer_ns(vm_clock
, hpet_timer
, timer
);
734 /* 64-bit main counter; LegacyReplacementRoute. */
735 s
->capability
= 0x8086a001ULL
;
736 s
->capability
|= (s
->num_timers
- 1) << HPET_ID_NUM_TIM_SHIFT
;
737 s
->capability
|= ((HPET_CLK_PERIOD
) << 32);
739 qdev_init_gpio_in(dev
, hpet_handle_legacy_irq
, 2);
740 qdev_init_gpio_out(dev
, &s
->pit_enabled
, 1);
743 static Property hpet_device_properties
[] = {
744 DEFINE_PROP_UINT8("timers", HPETState
, num_timers
, HPET_MIN_TIMERS
),
745 DEFINE_PROP_BIT("msi", HPETState
, flags
, HPET_MSI_SUPPORT
, false),
746 DEFINE_PROP_END_OF_LIST(),
749 static void hpet_device_class_init(ObjectClass
*klass
, void *data
)
751 DeviceClass
*dc
= DEVICE_CLASS(klass
);
753 dc
->realize
= hpet_realize
;
755 dc
->reset
= hpet_reset
;
756 dc
->vmsd
= &vmstate_hpet
;
757 dc
->props
= hpet_device_properties
;
760 static const TypeInfo hpet_device_info
= {
762 .parent
= TYPE_SYS_BUS_DEVICE
,
763 .instance_size
= sizeof(HPETState
),
764 .instance_init
= hpet_init
,
765 .class_init
= hpet_device_class_init
,
768 static void hpet_register_types(void)
770 type_register_static(&hpet_device_info
);
773 type_init(hpet_register_types
)