2 * ARM PrimeCell Timer modules.
4 * Copyright (c) 2005-2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "hw/sysbus.h"
11 #include "qemu/timer.h"
12 #include "qemu-common.h"
14 #include "hw/ptimer.h"
16 /* Common timer implementation. */
18 #define TIMER_CTRL_ONESHOT (1 << 0)
19 #define TIMER_CTRL_32BIT (1 << 1)
20 #define TIMER_CTRL_DIV1 (0 << 2)
21 #define TIMER_CTRL_DIV16 (1 << 2)
22 #define TIMER_CTRL_DIV256 (2 << 2)
23 #define TIMER_CTRL_IE (1 << 5)
24 #define TIMER_CTRL_PERIODIC (1 << 6)
25 #define TIMER_CTRL_ENABLE (1 << 7)
36 /* Check all active timers, and schedule the next timer interrupt. */
38 static void arm_timer_update(arm_timer_state
*s
)
40 /* Update interrupts. */
41 if (s
->int_level
&& (s
->control
& TIMER_CTRL_IE
)) {
42 qemu_irq_raise(s
->irq
);
44 qemu_irq_lower(s
->irq
);
48 static uint32_t arm_timer_read(void *opaque
, hwaddr offset
)
50 arm_timer_state
*s
= (arm_timer_state
*)opaque
;
52 switch (offset
>> 2) {
53 case 0: /* TimerLoad */
54 case 6: /* TimerBGLoad */
56 case 1: /* TimerValue */
57 return ptimer_get_count(s
->timer
);
58 case 2: /* TimerControl */
60 case 4: /* TimerRIS */
62 case 5: /* TimerMIS */
63 if ((s
->control
& TIMER_CTRL_IE
) == 0)
67 qemu_log_mask(LOG_GUEST_ERROR
,
68 "%s: Bad offset %x\n", __func__
, (int)offset
);
73 /* Reset the timer limit after settings have changed. */
74 static void arm_timer_recalibrate(arm_timer_state
*s
, int reload
)
78 if ((s
->control
& (TIMER_CTRL_PERIODIC
| TIMER_CTRL_ONESHOT
)) == 0) {
80 if (s
->control
& TIMER_CTRL_32BIT
)
88 ptimer_set_limit(s
->timer
, limit
, reload
);
91 static void arm_timer_write(void *opaque
, hwaddr offset
,
94 arm_timer_state
*s
= (arm_timer_state
*)opaque
;
97 switch (offset
>> 2) {
98 case 0: /* TimerLoad */
100 arm_timer_recalibrate(s
, 1);
102 case 1: /* TimerValue */
103 /* ??? Linux seems to want to write to this readonly register.
106 case 2: /* TimerControl */
107 if (s
->control
& TIMER_CTRL_ENABLE
) {
108 /* Pause the timer if it is running. This may cause some
109 inaccuracy dure to rounding, but avoids a whole lot of other
111 ptimer_stop(s
->timer
);
115 /* ??? Need to recalculate expiry time after changing divisor. */
116 switch ((value
>> 2) & 3) {
117 case 1: freq
>>= 4; break;
118 case 2: freq
>>= 8; break;
120 arm_timer_recalibrate(s
, s
->control
& TIMER_CTRL_ENABLE
);
121 ptimer_set_freq(s
->timer
, freq
);
122 if (s
->control
& TIMER_CTRL_ENABLE
) {
123 /* Restart the timer if still enabled. */
124 ptimer_run(s
->timer
, (s
->control
& TIMER_CTRL_ONESHOT
) != 0);
127 case 3: /* TimerIntClr */
130 case 6: /* TimerBGLoad */
132 arm_timer_recalibrate(s
, 0);
135 qemu_log_mask(LOG_GUEST_ERROR
,
136 "%s: Bad offset %x\n", __func__
, (int)offset
);
141 static void arm_timer_tick(void *opaque
)
143 arm_timer_state
*s
= (arm_timer_state
*)opaque
;
148 static const VMStateDescription vmstate_arm_timer
= {
151 .minimum_version_id
= 1,
152 .minimum_version_id_old
= 1,
153 .fields
= (VMStateField
[]) {
154 VMSTATE_UINT32(control
, arm_timer_state
),
155 VMSTATE_UINT32(limit
, arm_timer_state
),
156 VMSTATE_INT32(int_level
, arm_timer_state
),
157 VMSTATE_PTIMER(timer
, arm_timer_state
),
158 VMSTATE_END_OF_LIST()
162 static arm_timer_state
*arm_timer_init(uint32_t freq
)
167 s
= (arm_timer_state
*)g_malloc0(sizeof(arm_timer_state
));
169 s
->control
= TIMER_CTRL_IE
;
171 bh
= qemu_bh_new(arm_timer_tick
, s
);
172 s
->timer
= ptimer_init(bh
);
173 vmstate_register(NULL
, -1, &vmstate_arm_timer
, s
);
177 /* ARM PrimeCell SP804 dual timer module.
179 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
185 arm_timer_state
*timer
[2];
186 uint32_t freq0
, freq1
;
191 static const uint8_t sp804_ids
[] = {
195 0xd, 0xf0, 0x05, 0xb1
198 /* Merge the IRQs from the two component devices. */
199 static void sp804_set_irq(void *opaque
, int irq
, int level
)
201 sp804_state
*s
= (sp804_state
*)opaque
;
203 s
->level
[irq
] = level
;
204 qemu_set_irq(s
->irq
, s
->level
[0] || s
->level
[1]);
207 static uint64_t sp804_read(void *opaque
, hwaddr offset
,
210 sp804_state
*s
= (sp804_state
*)opaque
;
213 return arm_timer_read(s
->timer
[0], offset
);
216 return arm_timer_read(s
->timer
[1], offset
- 0x20);
220 if (offset
>= 0xfe0 && offset
<= 0xffc) {
221 return sp804_ids
[(offset
- 0xfe0) >> 2];
225 /* Integration Test control registers, which we won't support */
226 case 0xf00: /* TimerITCR */
227 case 0xf04: /* TimerITOP (strictly write only but..) */
228 qemu_log_mask(LOG_UNIMP
,
229 "%s: integration test registers unimplemented\n",
234 qemu_log_mask(LOG_GUEST_ERROR
,
235 "%s: Bad offset %x\n", __func__
, (int)offset
);
239 static void sp804_write(void *opaque
, hwaddr offset
,
240 uint64_t value
, unsigned size
)
242 sp804_state
*s
= (sp804_state
*)opaque
;
245 arm_timer_write(s
->timer
[0], offset
, value
);
250 arm_timer_write(s
->timer
[1], offset
- 0x20, value
);
254 /* Technically we could be writing to the Test Registers, but not likely */
255 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset %x\n",
256 __func__
, (int)offset
);
259 static const MemoryRegionOps sp804_ops
= {
261 .write
= sp804_write
,
262 .endianness
= DEVICE_NATIVE_ENDIAN
,
265 static const VMStateDescription vmstate_sp804
= {
268 .minimum_version_id
= 1,
269 .minimum_version_id_old
= 1,
270 .fields
= (VMStateField
[]) {
271 VMSTATE_INT32_ARRAY(level
, sp804_state
, 2),
272 VMSTATE_END_OF_LIST()
276 static int sp804_init(SysBusDevice
*dev
)
278 sp804_state
*s
= FROM_SYSBUS(sp804_state
, dev
);
281 qi
= qemu_allocate_irqs(sp804_set_irq
, s
, 2);
282 sysbus_init_irq(dev
, &s
->irq
);
283 s
->timer
[0] = arm_timer_init(s
->freq0
);
284 s
->timer
[1] = arm_timer_init(s
->freq1
);
285 s
->timer
[0]->irq
= qi
[0];
286 s
->timer
[1]->irq
= qi
[1];
287 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sp804_ops
, s
,
289 sysbus_init_mmio(dev
, &s
->iomem
);
290 vmstate_register(&dev
->qdev
, -1, &vmstate_sp804
, s
);
294 /* Integrator/CP timer module. */
299 arm_timer_state
*timer
[3];
302 static uint64_t icp_pit_read(void *opaque
, hwaddr offset
,
305 icp_pit_state
*s
= (icp_pit_state
*)opaque
;
308 /* ??? Don't know the PrimeCell ID for this device. */
311 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad timer %d\n", __func__
, n
);
314 return arm_timer_read(s
->timer
[n
], offset
& 0xff);
317 static void icp_pit_write(void *opaque
, hwaddr offset
,
318 uint64_t value
, unsigned size
)
320 icp_pit_state
*s
= (icp_pit_state
*)opaque
;
325 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad timer %d\n", __func__
, n
);
328 arm_timer_write(s
->timer
[n
], offset
& 0xff, value
);
331 static const MemoryRegionOps icp_pit_ops
= {
332 .read
= icp_pit_read
,
333 .write
= icp_pit_write
,
334 .endianness
= DEVICE_NATIVE_ENDIAN
,
337 static int icp_pit_init(SysBusDevice
*dev
)
339 icp_pit_state
*s
= FROM_SYSBUS(icp_pit_state
, dev
);
341 /* Timer 0 runs at the system clock speed (40MHz). */
342 s
->timer
[0] = arm_timer_init(40000000);
343 /* The other two timers run at 1MHz. */
344 s
->timer
[1] = arm_timer_init(1000000);
345 s
->timer
[2] = arm_timer_init(1000000);
347 sysbus_init_irq(dev
, &s
->timer
[0]->irq
);
348 sysbus_init_irq(dev
, &s
->timer
[1]->irq
);
349 sysbus_init_irq(dev
, &s
->timer
[2]->irq
);
351 memory_region_init_io(&s
->iomem
, OBJECT(s
), &icp_pit_ops
, s
,
353 sysbus_init_mmio(dev
, &s
->iomem
);
354 /* This device has no state to save/restore. The component timers will
359 static void icp_pit_class_init(ObjectClass
*klass
, void *data
)
361 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
363 sdc
->init
= icp_pit_init
;
366 static const TypeInfo icp_pit_info
= {
367 .name
= "integrator_pit",
368 .parent
= TYPE_SYS_BUS_DEVICE
,
369 .instance_size
= sizeof(icp_pit_state
),
370 .class_init
= icp_pit_class_init
,
373 static Property sp804_properties
[] = {
374 DEFINE_PROP_UINT32("freq0", sp804_state
, freq0
, 1000000),
375 DEFINE_PROP_UINT32("freq1", sp804_state
, freq1
, 1000000),
376 DEFINE_PROP_END_OF_LIST(),
379 static void sp804_class_init(ObjectClass
*klass
, void *data
)
381 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
382 DeviceClass
*k
= DEVICE_CLASS(klass
);
384 sdc
->init
= sp804_init
;
385 k
->props
= sp804_properties
;
388 static const TypeInfo sp804_info
= {
390 .parent
= TYPE_SYS_BUS_DEVICE
,
391 .instance_size
= sizeof(sp804_state
),
392 .class_init
= sp804_class_init
,
395 static void arm_timer_register_types(void)
397 type_register_static(&icp_pit_info
);
398 type_register_static(&sp804_info
);
401 type_init(arm_timer_register_types
)