target-arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 /* internal defines */
   5 typedef struct DisasContext {
   6     target_ulong pc;
   7     uint32_t insn;
   8     int is_jmp;
   9     /* Nonzero if this instruction has been conditionally skipped.  */
  10     int condjmp;
  11     /* The label that will be jumped to when the instruction is skipped.  */
  12     TCGLabel *condlabel;
  13     /* Thumb-2 conditional execution bits.  */
  14     int condexec_mask;
  15     int condexec_cond;
  16     struct TranslationBlock *tb;
  17     int singlestep_enabled;
  18     int thumb;
  19     int bswap_code;
  20 #if !defined(CONFIG_USER_ONLY)
  21     int user;
  22 #endif
  23     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  24     bool ns;        /* Use non-secure CPREG bank on access */
  25     int fp_excp_el; /* FP exception EL or 0 if enabled */
  26     bool el3_is_aa64;  /* Flag indicating whether EL3 is AArch64 or not */
  27     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  28     int vec_len;
  29     int vec_stride;
  30     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  31      * so that top level loop can generate correct syndrome information.
  32      */
  33     uint32_t svc_imm;
  34     int aarch64;
  35     int current_el;
  36     GHashTable *cp_regs;
  37     uint64_t features; /* CPU features bits */
  38     /* Because unallocated encodings generate different exception syndrome
  39      * information from traps due to FP being disabled, we can't do a single
  40      * "is fp access disabled" check at a high level in the decode tree.
  41      * To help in catching bugs where the access check was forgotten in some
  42      * code path, we set this flag when the access check is done, and assert
  43      * that it is set at the point where we actually touch the FP regs.
  44      */
  45     bool fp_access_checked;
  46     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  47      * single-step support).
  48      */
  49     bool ss_active;
  50     bool pstate_ss;
  51     /* True if the insn just emitted was a load-exclusive instruction
  52      * (necessary for syndrome information for single step exceptions),
  53      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  54      */
  55     bool is_ldex;
  56     /* True if a single-step exception will be taken to the current EL */
  57     bool ss_same_el;
  58     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  59     int c15_cpar;
  60 #define TMP_A64_MAX 16
  61     int tmp_a64_count;
  62     TCGv_i64 tmp_a64[TMP_A64_MAX];
  63 } DisasContext;
  64
  65 extern TCGv_ptr cpu_env;
  66
  67 static inline int arm_dc_feature(DisasContext *dc, int feature)
  68 {
  69     return (dc->features & (1ULL << feature)) != 0;
  70 }
  71
  72 static inline int get_mem_index(DisasContext *s)
  73 {
  74     return s->mmu_idx;
  75 }
  76
  77 /* Function used to determine the target exception EL when otherwise not known
  78  * or default.
  79  */
  80 static inline int default_exception_el(DisasContext *s)
  81 {
  82     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
  83      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
  84      * exceptions can only be routed to ELs above 1, so we target the higher of
  85      * 1 or the current EL.
  86      */
  87     return (s->mmu_idx == ARMMMUIdx_S1SE0 && !s->el3_is_aa64)
  88             ? 3 : MAX(1, s->current_el);
  89 }
  90
  91 /* target-specific extra values for is_jmp */
  92 /* These instructions trap after executing, so the A32/T32 decoder must
  93  * defer them until after the conditional execution state has been updated.
  94  * WFI also needs special handling when single-stepping.
  95  */
  96 #define DISAS_WFI 4
  97 #define DISAS_SWI 5
  98 /* For instructions which unconditionally cause an exception we can skip
  99  * emitting unreachable code at the end of the TB in the A64 decoder
 100  */
 101 #define DISAS_EXC 6
 102 /* WFE */
 103 #define DISAS_WFE 7
 104 #define DISAS_HVC 8
 105 #define DISAS_SMC 9
 106
 107 #ifdef TARGET_AARCH64
 108 void a64_translate_init(void);
 109 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
 110                                         TranslationBlock *tb,
 111                                         bool search_pc);
 112 void gen_a64_set_pc_im(uint64_t val);
 113 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 114                             fprintf_function cpu_fprintf, int flags);
 115 #else
 116 static inline void a64_translate_init(void)
 117 {
 118 }
 119
 120 static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
 121                                                       TranslationBlock *tb,
 122                                                       bool search_pc)
 123 {
 124 }
 125
 126 static inline void gen_a64_set_pc_im(uint64_t val)
 127 {
 128 }
 129
 130 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 131                                           fprintf_function cpu_fprintf,
 132                                           int flags)
 133 {
 134 }
 135 #endif
 136
 137 void arm_gen_test_cc(int cc, TCGLabel *label);
 138
 139 #endif /* TARGET_ARM_TRANSLATE_H */