hw/cpu/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/cpu/a15mpcore.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_arm.h"
  24
  25 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  26 {
  27     A15MPPrivState *s = (A15MPPrivState *)opaque;
  28
  29     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  30 }
  31
  32 static void a15mp_priv_initfn(Object *obj)
  33 {
  34     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  35     A15MPPrivState *s = A15MPCORE_PRIV(obj);
  36     DeviceState *gicdev;
  37
  38     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  39     sysbus_init_mmio(sbd, &s->container);
  40
  41     object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
  42     gicdev = DEVICE(&s->gic);
  43     qdev_set_parent_bus(gicdev, sysbus_get_default());
  44     qdev_prop_set_uint32(gicdev, "revision", 2);
  45 }
  46
  47 static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  48 {
  49     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  50     A15MPPrivState *s = A15MPCORE_PRIV(dev);
  51     DeviceState *gicdev;
  52     SysBusDevice *busdev;
  53     int i;
  54     Error *err = NULL;
  55     bool has_el3;
  56     Object *cpuobj;
  57
  58     gicdev = DEVICE(&s->gic);
  59     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  60     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  61
  62     if (!kvm_irqchip_in_kernel()) {
  63         /* Make the GIC's TZ support match the CPUs. We assume that
  64          * either all the CPUs have TZ, or none do.
  65          */
  66         cpuobj = OBJECT(qemu_get_cpu(0));
  67         has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  68             object_property_get_bool(cpuobj, "has_el3", &error_abort);
  69         qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  70     }
  71
  72     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  73     if (err != NULL) {
  74         error_propagate(errp, err);
  75         return;
  76     }
  77     busdev = SYS_BUS_DEVICE(&s->gic);
  78
  79     /* Pass through outbound IRQ lines from the GIC */
  80     sysbus_pass_irq(sbd, busdev);
  81
  82     /* Pass through inbound GPIO lines to the GIC */
  83     qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  84
  85     /* Wire the outputs from each CPU's generic timer to the
  86      * appropriate GIC PPI inputs
  87      */
  88     for (i = 0; i < s->num_cpu; i++) {
  89         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  90         int ppibase = s->num_irq - 32 + i * 32;
  91         int irq;
  92         /* Mapping from the output timer irq lines from the CPU to the
  93          * GIC PPI inputs used on the A15:
  94          */
  95         const int timer_irq[] = {
  96             [GTIMER_PHYS] = 30,
  97             [GTIMER_VIRT] = 27,
  98             [GTIMER_HYP]  = 26,
  99             [GTIMER_SEC]  = 29,
 100         };
 101         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 102             qdev_connect_gpio_out(cpudev, irq,
 103                                   qdev_get_gpio_in(gicdev,
 104                                                    ppibase + timer_irq[irq]));
 105         }
 106     }
 107
 108     /* Memory map (addresses are offsets from PERIPHBASE):
 109      *  0x0000-0x0fff -- reserved
 110      *  0x1000-0x1fff -- GIC Distributor
 111      *  0x2000-0x2fff -- GIC CPU interface
 112      *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
 113      *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
 114      *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
 115      */
 116     memory_region_add_subregion(&s->container, 0x1000,
 117                                 sysbus_mmio_get_region(busdev, 0));
 118     memory_region_add_subregion(&s->container, 0x2000,
 119                                 sysbus_mmio_get_region(busdev, 1));
 120 }
 121
 122 static Property a15mp_priv_properties[] = {
 123     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 124     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 125      * IRQ lines (with another 32 internal). We default to 128+32, which
 126      * is the number provided by the Cortex-A15MP test chip in the
 127      * Versatile Express A15 development board.
 128      * Other boards may differ and should set this property appropriately.
 129      */
 130     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 131     DEFINE_PROP_END_OF_LIST(),
 132 };
 133
 134 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 135 {
 136     DeviceClass *dc = DEVICE_CLASS(klass);
 137
 138     dc->realize = a15mp_priv_realize;
 139     dc->props = a15mp_priv_properties;
 140     /* We currently have no savable state */
 141 }
 142
 143 static const TypeInfo a15mp_priv_info = {
 144     .name  = TYPE_A15MPCORE_PRIV,
 145     .parent = TYPE_SYS_BUS_DEVICE,
 146     .instance_size  = sizeof(A15MPPrivState),
 147     .instance_init = a15mp_priv_initfn,
 148     .class_init = a15mp_priv_class_init,
 149 };
 150
 151 static void a15mp_register_types(void)
 152 {
 153     type_register_static(&a15mp_priv_info);
 154 }
 155
 156 type_init(a15mp_register_types)